2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
40 #include "uvd/uvd_4_2_d.h"
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
45 /* Firmware versions for VI */
46 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8))
47 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8))
48 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8))
49 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8))
51 /* Polaris10/11 firmware version */
52 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
55 #ifdef CONFIG_DRM_AMDGPU_CIK
56 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
57 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
58 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
59 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
60 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
62 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
63 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
64 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
65 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
66 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin"
67 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
70 * amdgpu_uvd_cs_ctx - Command submission parser context
72 * Used for emulating virtual memory support on UVD 4.2.
74 struct amdgpu_uvd_cs_ctx
{
75 struct amdgpu_cs_parser
*parser
;
77 unsigned data0
, data1
;
81 /* does the IB has a msg command */
84 /* minimum buffer sizes */
88 #ifdef CONFIG_DRM_AMDGPU_CIK
89 MODULE_FIRMWARE(FIRMWARE_BONAIRE
);
90 MODULE_FIRMWARE(FIRMWARE_KABINI
);
91 MODULE_FIRMWARE(FIRMWARE_KAVERI
);
92 MODULE_FIRMWARE(FIRMWARE_HAWAII
);
93 MODULE_FIRMWARE(FIRMWARE_MULLINS
);
95 MODULE_FIRMWARE(FIRMWARE_TONGA
);
96 MODULE_FIRMWARE(FIRMWARE_CARRIZO
);
97 MODULE_FIRMWARE(FIRMWARE_FIJI
);
98 MODULE_FIRMWARE(FIRMWARE_STONEY
);
99 MODULE_FIRMWARE(FIRMWARE_POLARIS10
);
100 MODULE_FIRMWARE(FIRMWARE_POLARIS11
);
102 static void amdgpu_uvd_idle_work_handler(struct work_struct
*work
);
104 int amdgpu_uvd_sw_init(struct amdgpu_device
*adev
)
106 struct amdgpu_ring
*ring
;
107 struct amd_sched_rq
*rq
;
108 unsigned long bo_size
;
110 const struct common_firmware_header
*hdr
;
111 unsigned version_major
, version_minor
, family_id
;
114 INIT_DELAYED_WORK(&adev
->uvd
.idle_work
, amdgpu_uvd_idle_work_handler
);
116 switch (adev
->asic_type
) {
117 #ifdef CONFIG_DRM_AMDGPU_CIK
119 fw_name
= FIRMWARE_BONAIRE
;
122 fw_name
= FIRMWARE_KABINI
;
125 fw_name
= FIRMWARE_KAVERI
;
128 fw_name
= FIRMWARE_HAWAII
;
131 fw_name
= FIRMWARE_MULLINS
;
135 fw_name
= FIRMWARE_TONGA
;
138 fw_name
= FIRMWARE_FIJI
;
141 fw_name
= FIRMWARE_CARRIZO
;
144 fw_name
= FIRMWARE_STONEY
;
147 fw_name
= FIRMWARE_POLARIS10
;
150 fw_name
= FIRMWARE_POLARIS11
;
156 r
= request_firmware(&adev
->uvd
.fw
, fw_name
, adev
->dev
);
158 dev_err(adev
->dev
, "amdgpu_uvd: Can't load firmware \"%s\"\n",
163 r
= amdgpu_ucode_validate(adev
->uvd
.fw
);
165 dev_err(adev
->dev
, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
167 release_firmware(adev
->uvd
.fw
);
172 /* Set the default UVD handles that the firmware can handle */
173 adev
->uvd
.max_handles
= AMDGPU_DEFAULT_UVD_HANDLES
;
175 hdr
= (const struct common_firmware_header
*)adev
->uvd
.fw
->data
;
176 family_id
= le32_to_cpu(hdr
->ucode_version
) & 0xff;
177 version_major
= (le32_to_cpu(hdr
->ucode_version
) >> 24) & 0xff;
178 version_minor
= (le32_to_cpu(hdr
->ucode_version
) >> 8) & 0xff;
179 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
180 version_major
, version_minor
, family_id
);
183 * Limit the number of UVD handles depending on microcode major
184 * and minor versions. The firmware version which has 40 UVD
185 * instances support is 1.80. So all subsequent versions should
186 * also have the same support.
188 if ((version_major
> 0x01) ||
189 ((version_major
== 0x01) && (version_minor
>= 0x50)))
190 adev
->uvd
.max_handles
= AMDGPU_MAX_UVD_HANDLES
;
192 adev
->uvd
.fw_version
= ((version_major
<< 24) | (version_minor
<< 16) |
195 if ((adev
->asic_type
== CHIP_POLARIS10
||
196 adev
->asic_type
== CHIP_POLARIS11
) &&
197 (adev
->uvd
.fw_version
< FW_1_66_16
))
198 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
199 version_major
, version_minor
);
201 bo_size
= AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr
->ucode_size_bytes
) + 8)
202 + AMDGPU_UVD_STACK_SIZE
+ AMDGPU_UVD_HEAP_SIZE
203 + AMDGPU_UVD_SESSION_SIZE
* adev
->uvd
.max_handles
;
204 r
= amdgpu_bo_create(adev
, bo_size
, PAGE_SIZE
, true,
205 AMDGPU_GEM_DOMAIN_VRAM
,
206 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
207 NULL
, NULL
, &adev
->uvd
.vcpu_bo
);
209 dev_err(adev
->dev
, "(%d) failed to allocate UVD bo\n", r
);
213 r
= amdgpu_bo_reserve(adev
->uvd
.vcpu_bo
, false);
215 amdgpu_bo_unref(&adev
->uvd
.vcpu_bo
);
216 dev_err(adev
->dev
, "(%d) failed to reserve UVD bo\n", r
);
220 r
= amdgpu_bo_pin(adev
->uvd
.vcpu_bo
, AMDGPU_GEM_DOMAIN_VRAM
,
221 &adev
->uvd
.gpu_addr
);
223 amdgpu_bo_unreserve(adev
->uvd
.vcpu_bo
);
224 amdgpu_bo_unref(&adev
->uvd
.vcpu_bo
);
225 dev_err(adev
->dev
, "(%d) UVD bo pin failed\n", r
);
229 r
= amdgpu_bo_kmap(adev
->uvd
.vcpu_bo
, &adev
->uvd
.cpu_addr
);
231 dev_err(adev
->dev
, "(%d) UVD map failed\n", r
);
235 amdgpu_bo_unreserve(adev
->uvd
.vcpu_bo
);
237 ring
= &adev
->uvd
.ring
;
238 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_NORMAL
];
239 r
= amd_sched_entity_init(&ring
->sched
, &adev
->uvd
.entity
,
240 rq
, amdgpu_sched_jobs
);
242 DRM_ERROR("Failed setting up UVD run queue.\n");
246 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
) {
247 atomic_set(&adev
->uvd
.handles
[i
], 0);
248 adev
->uvd
.filp
[i
] = NULL
;
251 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
252 if (!amdgpu_ip_block_version_cmp(adev
, AMD_IP_BLOCK_TYPE_UVD
, 5, 0))
253 adev
->uvd
.address_64_bit
= true;
255 switch (adev
->asic_type
) {
257 adev
->uvd
.use_ctx_buf
= adev
->uvd
.fw_version
>= FW_1_65_10
;
260 adev
->uvd
.use_ctx_buf
= adev
->uvd
.fw_version
>= FW_1_87_11
;
263 adev
->uvd
.use_ctx_buf
= adev
->uvd
.fw_version
>= FW_1_87_12
;
266 adev
->uvd
.use_ctx_buf
= adev
->uvd
.fw_version
>= FW_1_37_15
;
269 adev
->uvd
.use_ctx_buf
= adev
->asic_type
>= CHIP_POLARIS10
;
275 int amdgpu_uvd_sw_fini(struct amdgpu_device
*adev
)
279 kfree(adev
->uvd
.saved_bo
);
281 amd_sched_entity_fini(&adev
->uvd
.ring
.sched
, &adev
->uvd
.entity
);
283 if (adev
->uvd
.vcpu_bo
) {
284 r
= amdgpu_bo_reserve(adev
->uvd
.vcpu_bo
, false);
286 amdgpu_bo_kunmap(adev
->uvd
.vcpu_bo
);
287 amdgpu_bo_unpin(adev
->uvd
.vcpu_bo
);
288 amdgpu_bo_unreserve(adev
->uvd
.vcpu_bo
);
291 amdgpu_bo_unref(&adev
->uvd
.vcpu_bo
);
294 amdgpu_ring_fini(&adev
->uvd
.ring
);
296 release_firmware(adev
->uvd
.fw
);
301 int amdgpu_uvd_suspend(struct amdgpu_device
*adev
)
307 if (adev
->uvd
.vcpu_bo
== NULL
)
310 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
)
311 if (atomic_read(&adev
->uvd
.handles
[i
]))
314 if (i
== AMDGPU_MAX_UVD_HANDLES
)
317 cancel_delayed_work_sync(&adev
->uvd
.idle_work
);
319 size
= amdgpu_bo_size(adev
->uvd
.vcpu_bo
);
320 ptr
= adev
->uvd
.cpu_addr
;
322 adev
->uvd
.saved_bo
= kmalloc(size
, GFP_KERNEL
);
323 if (!adev
->uvd
.saved_bo
)
326 memcpy(adev
->uvd
.saved_bo
, ptr
, size
);
331 int amdgpu_uvd_resume(struct amdgpu_device
*adev
)
336 if (adev
->uvd
.vcpu_bo
== NULL
)
339 size
= amdgpu_bo_size(adev
->uvd
.vcpu_bo
);
340 ptr
= adev
->uvd
.cpu_addr
;
342 if (adev
->uvd
.saved_bo
!= NULL
) {
343 memcpy(ptr
, adev
->uvd
.saved_bo
, size
);
344 kfree(adev
->uvd
.saved_bo
);
345 adev
->uvd
.saved_bo
= NULL
;
347 const struct common_firmware_header
*hdr
;
350 hdr
= (const struct common_firmware_header
*)adev
->uvd
.fw
->data
;
351 offset
= le32_to_cpu(hdr
->ucode_array_offset_bytes
);
352 memcpy(adev
->uvd
.cpu_addr
, (adev
->uvd
.fw
->data
) + offset
,
353 (adev
->uvd
.fw
->size
) - offset
);
354 size
-= le32_to_cpu(hdr
->ucode_size_bytes
);
355 ptr
+= le32_to_cpu(hdr
->ucode_size_bytes
);
356 memset(ptr
, 0, size
);
362 void amdgpu_uvd_free_handles(struct amdgpu_device
*adev
, struct drm_file
*filp
)
364 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
367 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
) {
368 uint32_t handle
= atomic_read(&adev
->uvd
.handles
[i
]);
369 if (handle
!= 0 && adev
->uvd
.filp
[i
] == filp
) {
372 r
= amdgpu_uvd_get_destroy_msg(ring
, handle
,
375 DRM_ERROR("Error destroying UVD (%d)!\n", r
);
379 fence_wait(fence
, false);
382 adev
->uvd
.filp
[i
] = NULL
;
383 atomic_set(&adev
->uvd
.handles
[i
], 0);
388 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo
*rbo
)
391 for (i
= 0; i
< rbo
->placement
.num_placement
; ++i
) {
392 rbo
->placements
[i
].fpfn
= 0 >> PAGE_SHIFT
;
393 rbo
->placements
[i
].lpfn
= (256 * 1024 * 1024) >> PAGE_SHIFT
;
398 * amdgpu_uvd_cs_pass1 - first parsing round
400 * @ctx: UVD parser context
402 * Make sure UVD message and feedback buffers are in VRAM and
403 * nobody is violating an 256MB boundary.
405 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx
*ctx
)
407 struct amdgpu_bo_va_mapping
*mapping
;
408 struct amdgpu_bo
*bo
;
409 uint32_t cmd
, lo
, hi
;
413 lo
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data0
);
414 hi
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data1
);
415 addr
= ((uint64_t)lo
) | (((uint64_t)hi
) << 32);
417 mapping
= amdgpu_cs_find_mapping(ctx
->parser
, addr
, &bo
);
418 if (mapping
== NULL
) {
419 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr
);
423 if (!ctx
->parser
->adev
->uvd
.address_64_bit
) {
424 /* check if it's a message or feedback command */
425 cmd
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->idx
) >> 1;
426 if (cmd
== 0x0 || cmd
== 0x3) {
427 /* yes, force it into VRAM */
428 uint32_t domain
= AMDGPU_GEM_DOMAIN_VRAM
;
429 amdgpu_ttm_placement_from_domain(bo
, domain
);
431 amdgpu_uvd_force_into_uvd_segment(bo
);
433 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);
440 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
442 * @msg: pointer to message structure
443 * @buf_sizes: returned buffer sizes
445 * Peek into the decode message and calculate the necessary buffer sizes.
447 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device
*adev
, uint32_t *msg
,
448 unsigned buf_sizes
[])
450 unsigned stream_type
= msg
[4];
451 unsigned width
= msg
[6];
452 unsigned height
= msg
[7];
453 unsigned dpb_size
= msg
[9];
454 unsigned pitch
= msg
[28];
455 unsigned level
= msg
[57];
457 unsigned width_in_mb
= width
/ 16;
458 unsigned height_in_mb
= ALIGN(height
/ 16, 2);
459 unsigned fs_in_mb
= width_in_mb
* height_in_mb
;
461 unsigned image_size
, tmp
, min_dpb_size
, num_dpb_buffer
;
462 unsigned min_ctx_size
= ~0;
464 image_size
= width
* height
;
465 image_size
+= image_size
/ 2;
466 image_size
= ALIGN(image_size
, 1024);
468 switch (stream_type
) {
472 num_dpb_buffer
= 8100 / fs_in_mb
;
475 num_dpb_buffer
= 18000 / fs_in_mb
;
478 num_dpb_buffer
= 20480 / fs_in_mb
;
481 num_dpb_buffer
= 32768 / fs_in_mb
;
484 num_dpb_buffer
= 34816 / fs_in_mb
;
487 num_dpb_buffer
= 110400 / fs_in_mb
;
490 num_dpb_buffer
= 184320 / fs_in_mb
;
493 num_dpb_buffer
= 184320 / fs_in_mb
;
497 if (num_dpb_buffer
> 17)
500 /* reference picture buffer */
501 min_dpb_size
= image_size
* num_dpb_buffer
;
503 /* macroblock context buffer */
504 min_dpb_size
+= width_in_mb
* height_in_mb
* num_dpb_buffer
* 192;
506 /* IT surface buffer */
507 min_dpb_size
+= width_in_mb
* height_in_mb
* 32;
512 /* reference picture buffer */
513 min_dpb_size
= image_size
* 3;
516 min_dpb_size
+= width_in_mb
* height_in_mb
* 128;
518 /* IT surface buffer */
519 min_dpb_size
+= width_in_mb
* 64;
521 /* DB surface buffer */
522 min_dpb_size
+= width_in_mb
* 128;
525 tmp
= max(width_in_mb
, height_in_mb
);
526 min_dpb_size
+= ALIGN(tmp
* 7 * 16, 64);
531 /* reference picture buffer */
532 min_dpb_size
= image_size
* 3;
537 /* reference picture buffer */
538 min_dpb_size
= image_size
* 3;
541 min_dpb_size
+= width_in_mb
* height_in_mb
* 64;
543 /* IT surface buffer */
544 min_dpb_size
+= ALIGN(width_in_mb
* height_in_mb
* 32, 64);
547 case 7: /* H264 Perf */
550 num_dpb_buffer
= 8100 / fs_in_mb
;
553 num_dpb_buffer
= 18000 / fs_in_mb
;
556 num_dpb_buffer
= 20480 / fs_in_mb
;
559 num_dpb_buffer
= 32768 / fs_in_mb
;
562 num_dpb_buffer
= 34816 / fs_in_mb
;
565 num_dpb_buffer
= 110400 / fs_in_mb
;
568 num_dpb_buffer
= 184320 / fs_in_mb
;
571 num_dpb_buffer
= 184320 / fs_in_mb
;
575 if (num_dpb_buffer
> 17)
578 /* reference picture buffer */
579 min_dpb_size
= image_size
* num_dpb_buffer
;
581 if (!adev
->uvd
.use_ctx_buf
){
582 /* macroblock context buffer */
584 width_in_mb
* height_in_mb
* num_dpb_buffer
* 192;
586 /* IT surface buffer */
587 min_dpb_size
+= width_in_mb
* height_in_mb
* 32;
589 /* macroblock context buffer */
591 width_in_mb
* height_in_mb
* num_dpb_buffer
* 192;
596 image_size
= (ALIGN(width
, 16) * ALIGN(height
, 16) * 3) / 2;
597 image_size
= ALIGN(image_size
, 256);
599 num_dpb_buffer
= (le32_to_cpu(msg
[59]) & 0xff) + 2;
600 min_dpb_size
= image_size
* num_dpb_buffer
;
601 min_ctx_size
= ((width
+ 255) / 16) * ((height
+ 255) / 16)
602 * 16 * num_dpb_buffer
+ 52 * 1024;
606 DRM_ERROR("UVD codec not handled %d!\n", stream_type
);
611 DRM_ERROR("Invalid UVD decoding target pitch!\n");
615 if (dpb_size
< min_dpb_size
) {
616 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
617 dpb_size
, min_dpb_size
);
621 buf_sizes
[0x1] = dpb_size
;
622 buf_sizes
[0x2] = image_size
;
623 buf_sizes
[0x4] = min_ctx_size
;
628 * amdgpu_uvd_cs_msg - handle UVD message
630 * @ctx: UVD parser context
631 * @bo: buffer object containing the message
632 * @offset: offset into the buffer object
634 * Peek into the UVD message and extract the session id.
635 * Make sure that we don't open up to many sessions.
637 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx
*ctx
,
638 struct amdgpu_bo
*bo
, unsigned offset
)
640 struct amdgpu_device
*adev
= ctx
->parser
->adev
;
641 int32_t *msg
, msg_type
, handle
;
647 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
651 r
= amdgpu_bo_kmap(bo
, &ptr
);
653 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r
);
663 DRM_ERROR("Invalid UVD handle!\n");
669 /* it's a create msg, calc image size (width * height) */
670 amdgpu_bo_kunmap(bo
);
672 /* try to alloc a new handle */
673 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
) {
674 if (atomic_read(&adev
->uvd
.handles
[i
]) == handle
) {
675 DRM_ERROR("Handle 0x%x already in use!\n", handle
);
679 if (!atomic_cmpxchg(&adev
->uvd
.handles
[i
], 0, handle
)) {
680 adev
->uvd
.filp
[i
] = ctx
->parser
->filp
;
685 DRM_ERROR("No more free UVD handles!\n");
689 /* it's a decode msg, calc buffer sizes */
690 r
= amdgpu_uvd_cs_msg_decode(adev
, msg
, ctx
->buf_sizes
);
691 amdgpu_bo_kunmap(bo
);
695 /* validate the handle */
696 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
) {
697 if (atomic_read(&adev
->uvd
.handles
[i
]) == handle
) {
698 if (adev
->uvd
.filp
[i
] != ctx
->parser
->filp
) {
699 DRM_ERROR("UVD handle collision detected!\n");
706 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle
);
710 /* it's a destroy msg, free the handle */
711 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
)
712 atomic_cmpxchg(&adev
->uvd
.handles
[i
], handle
, 0);
713 amdgpu_bo_kunmap(bo
);
717 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type
);
725 * amdgpu_uvd_cs_pass2 - second parsing round
727 * @ctx: UVD parser context
729 * Patch buffer addresses, make sure buffer sizes are correct.
731 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx
*ctx
)
733 struct amdgpu_bo_va_mapping
*mapping
;
734 struct amdgpu_bo
*bo
;
735 uint32_t cmd
, lo
, hi
;
740 lo
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data0
);
741 hi
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data1
);
742 addr
= ((uint64_t)lo
) | (((uint64_t)hi
) << 32);
744 mapping
= amdgpu_cs_find_mapping(ctx
->parser
, addr
, &bo
);
748 start
= amdgpu_bo_gpu_offset(bo
);
750 end
= (mapping
->it
.last
+ 1 - mapping
->it
.start
);
751 end
= end
* AMDGPU_GPU_PAGE_SIZE
+ start
;
753 addr
-= ((uint64_t)mapping
->it
.start
) * AMDGPU_GPU_PAGE_SIZE
;
756 amdgpu_set_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data0
,
757 lower_32_bits(start
));
758 amdgpu_set_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data1
,
759 upper_32_bits(start
));
761 cmd
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->idx
) >> 1;
763 if ((end
- start
) < ctx
->buf_sizes
[cmd
]) {
764 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd
,
765 (unsigned)(end
- start
),
766 ctx
->buf_sizes
[cmd
]);
770 } else if (cmd
== 0x206) {
771 if ((end
- start
) < ctx
->buf_sizes
[4]) {
772 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd
,
773 (unsigned)(end
- start
),
777 } else if ((cmd
!= 0x100) && (cmd
!= 0x204)) {
778 DRM_ERROR("invalid UVD command %X!\n", cmd
);
782 if (!ctx
->parser
->adev
->uvd
.address_64_bit
) {
783 if ((start
>> 28) != ((end
- 1) >> 28)) {
784 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
789 if ((cmd
== 0 || cmd
== 0x3) &&
790 (start
>> 28) != (ctx
->parser
->adev
->uvd
.gpu_addr
>> 28)) {
791 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
798 ctx
->has_msg_cmd
= true;
799 r
= amdgpu_uvd_cs_msg(ctx
, bo
, addr
);
802 } else if (!ctx
->has_msg_cmd
) {
803 DRM_ERROR("Message needed before other commands are send!\n");
811 * amdgpu_uvd_cs_reg - parse register writes
813 * @ctx: UVD parser context
814 * @cb: callback function
816 * Parse the register writes, call cb on each complete command.
818 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx
*ctx
,
819 int (*cb
)(struct amdgpu_uvd_cs_ctx
*ctx
))
821 struct amdgpu_ib
*ib
= &ctx
->parser
->job
->ibs
[ctx
->ib_idx
];
825 for (i
= 0; i
<= ctx
->count
; ++i
) {
826 unsigned reg
= ctx
->reg
+ i
;
828 if (ctx
->idx
>= ib
->length_dw
) {
829 DRM_ERROR("Register command after end of CS!\n");
834 case mmUVD_GPCOM_VCPU_DATA0
:
835 ctx
->data0
= ctx
->idx
;
837 case mmUVD_GPCOM_VCPU_DATA1
:
838 ctx
->data1
= ctx
->idx
;
840 case mmUVD_GPCOM_VCPU_CMD
:
845 case mmUVD_ENGINE_CNTL
:
848 DRM_ERROR("Invalid reg 0x%X!\n", reg
);
857 * amdgpu_uvd_cs_packets - parse UVD packets
859 * @ctx: UVD parser context
860 * @cb: callback function
862 * Parse the command stream packets.
864 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx
*ctx
,
865 int (*cb
)(struct amdgpu_uvd_cs_ctx
*ctx
))
867 struct amdgpu_ib
*ib
= &ctx
->parser
->job
->ibs
[ctx
->ib_idx
];
870 for (ctx
->idx
= 0 ; ctx
->idx
< ib
->length_dw
; ) {
871 uint32_t cmd
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->idx
);
872 unsigned type
= CP_PACKET_GET_TYPE(cmd
);
875 ctx
->reg
= CP_PACKET0_GET_REG(cmd
);
876 ctx
->count
= CP_PACKET_GET_COUNT(cmd
);
877 r
= amdgpu_uvd_cs_reg(ctx
, cb
);
885 DRM_ERROR("Unknown packet type %d !\n", type
);
893 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
895 * @parser: Command submission parser context
897 * Parse the command stream, patch in addresses as necessary.
899 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser
*parser
, uint32_t ib_idx
)
901 struct amdgpu_uvd_cs_ctx ctx
= {};
902 unsigned buf_sizes
[] = {
904 [0x00000001] = 0xFFFFFFFF,
905 [0x00000002] = 0xFFFFFFFF,
907 [0x00000004] = 0xFFFFFFFF,
909 struct amdgpu_ib
*ib
= &parser
->job
->ibs
[ib_idx
];
912 if (ib
->length_dw
% 16) {
913 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
919 ctx
.buf_sizes
= buf_sizes
;
922 /* first round, make sure the buffers are actually in the UVD segment */
923 r
= amdgpu_uvd_cs_packets(&ctx
, amdgpu_uvd_cs_pass1
);
927 /* second round, patch buffer addresses into the command stream */
928 r
= amdgpu_uvd_cs_packets(&ctx
, amdgpu_uvd_cs_pass2
);
932 if (!ctx
.has_msg_cmd
) {
933 DRM_ERROR("UVD-IBs need a msg command!\n");
940 static int amdgpu_uvd_send_msg(struct amdgpu_ring
*ring
, struct amdgpu_bo
*bo
,
941 bool direct
, struct fence
**fence
)
943 struct ttm_validate_buffer tv
;
944 struct ww_acquire_ctx ticket
;
945 struct list_head head
;
946 struct amdgpu_job
*job
;
947 struct amdgpu_ib
*ib
;
948 struct fence
*f
= NULL
;
949 struct amdgpu_device
*adev
= ring
->adev
;
953 memset(&tv
, 0, sizeof(tv
));
956 INIT_LIST_HEAD(&head
);
957 list_add(&tv
.head
, &head
);
959 r
= ttm_eu_reserve_buffers(&ticket
, &head
, true, NULL
);
963 if (!bo
->adev
->uvd
.address_64_bit
) {
964 amdgpu_ttm_placement_from_domain(bo
, AMDGPU_GEM_DOMAIN_VRAM
);
965 amdgpu_uvd_force_into_uvd_segment(bo
);
968 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
972 r
= amdgpu_job_alloc_with_ib(adev
, 64, &job
);
977 addr
= amdgpu_bo_gpu_offset(bo
);
978 ib
->ptr
[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0
, 0);
980 ib
->ptr
[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1
, 0);
981 ib
->ptr
[3] = addr
>> 32;
982 ib
->ptr
[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD
, 0);
984 for (i
= 6; i
< 16; ++i
)
985 ib
->ptr
[i
] = PACKET2(0);
989 r
= amdgpu_ib_schedule(ring
, 1, ib
, NULL
, NULL
, &f
);
990 job
->fence
= fence_get(f
);
994 amdgpu_job_free(job
);
996 r
= amdgpu_job_submit(job
, ring
, &adev
->uvd
.entity
,
997 AMDGPU_FENCE_OWNER_UNDEFINED
, &f
);
1002 ttm_eu_fence_buffer_objects(&ticket
, &head
, f
);
1005 *fence
= fence_get(f
);
1006 amdgpu_bo_unref(&bo
);
1012 amdgpu_job_free(job
);
1015 ttm_eu_backoff_reservation(&ticket
, &head
);
1019 /* multiple fence commands without any stream commands in between can
1020 crash the vcpu so just try to emmit a dummy create/destroy msg to
1022 int amdgpu_uvd_get_create_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
1023 struct fence
**fence
)
1025 struct amdgpu_device
*adev
= ring
->adev
;
1026 struct amdgpu_bo
*bo
;
1030 r
= amdgpu_bo_create(adev
, 1024, PAGE_SIZE
, true,
1031 AMDGPU_GEM_DOMAIN_VRAM
,
1032 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
1037 r
= amdgpu_bo_reserve(bo
, false);
1039 amdgpu_bo_unref(&bo
);
1043 r
= amdgpu_bo_kmap(bo
, (void **)&msg
);
1045 amdgpu_bo_unreserve(bo
);
1046 amdgpu_bo_unref(&bo
);
1050 /* stitch together an UVD create msg */
1051 msg
[0] = cpu_to_le32(0x00000de4);
1052 msg
[1] = cpu_to_le32(0x00000000);
1053 msg
[2] = cpu_to_le32(handle
);
1054 msg
[3] = cpu_to_le32(0x00000000);
1055 msg
[4] = cpu_to_le32(0x00000000);
1056 msg
[5] = cpu_to_le32(0x00000000);
1057 msg
[6] = cpu_to_le32(0x00000000);
1058 msg
[7] = cpu_to_le32(0x00000780);
1059 msg
[8] = cpu_to_le32(0x00000440);
1060 msg
[9] = cpu_to_le32(0x00000000);
1061 msg
[10] = cpu_to_le32(0x01b37000);
1062 for (i
= 11; i
< 1024; ++i
)
1063 msg
[i
] = cpu_to_le32(0x0);
1065 amdgpu_bo_kunmap(bo
);
1066 amdgpu_bo_unreserve(bo
);
1068 return amdgpu_uvd_send_msg(ring
, bo
, true, fence
);
1071 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
1072 bool direct
, struct fence
**fence
)
1074 struct amdgpu_device
*adev
= ring
->adev
;
1075 struct amdgpu_bo
*bo
;
1079 r
= amdgpu_bo_create(adev
, 1024, PAGE_SIZE
, true,
1080 AMDGPU_GEM_DOMAIN_VRAM
,
1081 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
1086 r
= amdgpu_bo_reserve(bo
, false);
1088 amdgpu_bo_unref(&bo
);
1092 r
= amdgpu_bo_kmap(bo
, (void **)&msg
);
1094 amdgpu_bo_unreserve(bo
);
1095 amdgpu_bo_unref(&bo
);
1099 /* stitch together an UVD destroy msg */
1100 msg
[0] = cpu_to_le32(0x00000de4);
1101 msg
[1] = cpu_to_le32(0x00000002);
1102 msg
[2] = cpu_to_le32(handle
);
1103 msg
[3] = cpu_to_le32(0x00000000);
1104 for (i
= 4; i
< 1024; ++i
)
1105 msg
[i
] = cpu_to_le32(0x0);
1107 amdgpu_bo_kunmap(bo
);
1108 amdgpu_bo_unreserve(bo
);
1110 return amdgpu_uvd_send_msg(ring
, bo
, direct
, fence
);
1113 static void amdgpu_uvd_idle_work_handler(struct work_struct
*work
)
1115 struct amdgpu_device
*adev
=
1116 container_of(work
, struct amdgpu_device
, uvd
.idle_work
.work
);
1117 unsigned i
, fences
, handles
= 0;
1119 fences
= amdgpu_fence_count_emitted(&adev
->uvd
.ring
);
1121 for (i
= 0; i
< adev
->uvd
.max_handles
; ++i
)
1122 if (atomic_read(&adev
->uvd
.handles
[i
]))
1125 if (fences
== 0 && handles
== 0) {
1126 if (adev
->pm
.dpm_enabled
) {
1127 amdgpu_dpm_enable_uvd(adev
, false);
1129 amdgpu_asic_set_uvd_clocks(adev
, 0, 0);
1132 schedule_delayed_work(&adev
->uvd
.idle_work
, UVD_IDLE_TIMEOUT
);
1136 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring
*ring
)
1138 struct amdgpu_device
*adev
= ring
->adev
;
1139 bool set_clocks
= !cancel_delayed_work_sync(&adev
->uvd
.idle_work
);
1142 if (adev
->pm
.dpm_enabled
) {
1143 amdgpu_dpm_enable_uvd(adev
, true);
1145 amdgpu_asic_set_uvd_clocks(adev
, 53300, 40000);
1150 void amdgpu_uvd_ring_end_use(struct amdgpu_ring
*ring
)
1152 schedule_delayed_work(&ring
->adev
->uvd
.idle_work
, UVD_IDLE_TIMEOUT
);
1156 * amdgpu_uvd_ring_test_ib - test ib execution
1158 * @ring: amdgpu_ring pointer
1160 * Test if we can successfully execute an IB
1162 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
1164 struct fence
*fence
;
1167 r
= amdgpu_uvd_get_create_msg(ring
, 1, NULL
);
1169 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r
);
1173 r
= amdgpu_uvd_get_destroy_msg(ring
, 1, true, &fence
);
1175 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r
);
1179 r
= fence_wait_timeout(fence
, false, timeout
);
1181 DRM_ERROR("amdgpu: IB test timed out.\n");
1184 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
1186 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);