2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/fence-array.h>
30 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_trace.h"
36 * GPUVM is similar to the legacy gart on older asics, however
37 * rather than there being a single global gart table
38 * for the entire GPU, there are multiple VM page tables active
39 * at any given time. The VM page tables can contain a mix
40 * vram pages and system memory pages and system memory pages
41 * can be mapped as snooped (cached system pages) or unsnooped
42 * (uncached system pages).
43 * Each VM has an ID associated with it and there is a page table
44 * associated with each VMID. When execting a command buffer,
45 * the kernel tells the the ring what VMID to use for that command
46 * buffer. VMIDs are allocated dynamically as commands are submitted.
47 * The userspace drivers maintain their own address space and the kernel
48 * sets up their pages tables accordingly when they submit their
49 * command buffers and a VMID is assigned.
50 * Cayman/Trinity support up to 8 active VMs at any given time;
54 /* Special value that no flush is necessary */
55 #define AMDGPU_VM_NO_FLUSH (~0ll)
57 /* Local structure. Encapsulate some VM table update parameters to reduce
58 * the number of function parameters
60 struct amdgpu_pte_update_params
{
61 /* amdgpu device we do this update for */
62 struct amdgpu_device
*adev
;
63 /* address where to copy page table entries from */
65 /* indirect buffer to fill with commands */
70 * amdgpu_vm_num_pde - return the number of page directory entries
72 * @adev: amdgpu_device pointer
74 * Calculate the number of page directory entries.
76 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device
*adev
)
78 return adev
->vm_manager
.max_pfn
>> amdgpu_vm_block_size
;
82 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
84 * @adev: amdgpu_device pointer
86 * Calculate the size of the page directory in bytes.
88 static unsigned amdgpu_vm_directory_size(struct amdgpu_device
*adev
)
90 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev
) * 8);
94 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
96 * @vm: vm providing the BOs
97 * @validated: head of validation list
98 * @entry: entry to add
100 * Add the page directory to the list of BOs to
101 * validate for command submission.
103 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
104 struct list_head
*validated
,
105 struct amdgpu_bo_list_entry
*entry
)
107 entry
->robj
= vm
->page_directory
;
109 entry
->tv
.bo
= &vm
->page_directory
->tbo
;
110 entry
->tv
.shared
= true;
111 entry
->user_pages
= NULL
;
112 list_add(&entry
->tv
.head
, validated
);
116 * amdgpu_vm_get_bos - add the vm BOs to a duplicates list
118 * @adev: amdgpu device pointer
119 * @vm: vm providing the BOs
120 * @duplicates: head of duplicates list
122 * Add the page directory to the BO duplicates list
123 * for command submission.
125 void amdgpu_vm_get_pt_bos(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
126 struct list_head
*duplicates
)
128 uint64_t num_evictions
;
131 /* We only need to validate the page tables
132 * if they aren't already valid.
134 num_evictions
= atomic64_read(&adev
->num_evictions
);
135 if (num_evictions
== vm
->last_eviction_counter
)
138 /* add the vm page table to the list */
139 for (i
= 0; i
<= vm
->max_pde_used
; ++i
) {
140 struct amdgpu_bo_list_entry
*entry
= &vm
->page_tables
[i
].entry
;
145 list_add(&entry
->tv
.head
, duplicates
);
151 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
153 * @adev: amdgpu device instance
154 * @vm: vm providing the BOs
156 * Move the PT BOs to the tail of the LRU.
158 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device
*adev
,
159 struct amdgpu_vm
*vm
)
161 struct ttm_bo_global
*glob
= adev
->mman
.bdev
.glob
;
164 spin_lock(&glob
->lru_lock
);
165 for (i
= 0; i
<= vm
->max_pde_used
; ++i
) {
166 struct amdgpu_bo_list_entry
*entry
= &vm
->page_tables
[i
].entry
;
171 ttm_bo_move_to_lru_tail(&entry
->robj
->tbo
);
173 spin_unlock(&glob
->lru_lock
);
176 static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device
*adev
,
177 struct amdgpu_vm_id
*id
)
179 return id
->current_gpu_reset_count
!=
180 atomic_read(&adev
->gpu_reset_counter
) ? true : false;
184 * amdgpu_vm_grab_id - allocate the next free VMID
186 * @vm: vm to allocate id for
187 * @ring: ring we want to submit job to
188 * @sync: sync object where we add dependencies
189 * @fence: fence protecting ID from reuse
191 * Allocate an id for the vm, adding fences to the sync obj as necessary.
193 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
194 struct amdgpu_sync
*sync
, struct fence
*fence
,
195 struct amdgpu_job
*job
)
197 struct amdgpu_device
*adev
= ring
->adev
;
198 uint64_t fence_context
= adev
->fence_context
+ ring
->idx
;
199 struct fence
*updates
= sync
->last_vm_update
;
200 struct amdgpu_vm_id
*id
, *idle
;
201 struct fence
**fences
;
205 fences
= kmalloc_array(sizeof(void *), adev
->vm_manager
.num_ids
,
210 mutex_lock(&adev
->vm_manager
.lock
);
212 /* Check if we have an idle VMID */
214 list_for_each_entry(idle
, &adev
->vm_manager
.ids_lru
, list
) {
215 fences
[i
] = amdgpu_sync_peek_fence(&idle
->active
, ring
);
221 /* If we can't find a idle VMID to use, wait till one becomes available */
222 if (&idle
->list
== &adev
->vm_manager
.ids_lru
) {
223 u64 fence_context
= adev
->vm_manager
.fence_context
+ ring
->idx
;
224 unsigned seqno
= ++adev
->vm_manager
.seqno
[ring
->idx
];
225 struct fence_array
*array
;
228 for (j
= 0; j
< i
; ++j
)
229 fence_get(fences
[j
]);
231 array
= fence_array_create(i
, fences
, fence_context
,
234 for (j
= 0; j
< i
; ++j
)
235 fence_put(fences
[j
]);
242 r
= amdgpu_sync_fence(ring
->adev
, sync
, &array
->base
);
243 fence_put(&array
->base
);
247 mutex_unlock(&adev
->vm_manager
.lock
);
253 job
->vm_needs_flush
= true;
254 /* Check if we can use a VMID already assigned to this VM */
257 struct fence
*flushed
;
260 if (i
== AMDGPU_MAX_RINGS
)
263 /* Check all the prerequisites to using this VMID */
266 if (amdgpu_vm_is_gpu_reset(adev
, id
))
269 if (atomic64_read(&id
->owner
) != vm
->client_id
)
272 if (job
->vm_pd_addr
!= id
->pd_gpu_addr
)
278 if (id
->last_flush
->context
!= fence_context
&&
279 !fence_is_signaled(id
->last_flush
))
282 flushed
= id
->flushed_updates
;
284 (!flushed
|| fence_is_later(updates
, flushed
)))
287 /* Good we can use this VMID. Remember this submission as
290 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
294 id
->current_gpu_reset_count
= atomic_read(&adev
->gpu_reset_counter
);
295 list_move_tail(&id
->list
, &adev
->vm_manager
.ids_lru
);
296 vm
->ids
[ring
->idx
] = id
;
298 job
->vm_id
= id
- adev
->vm_manager
.ids
;
299 job
->vm_needs_flush
= false;
300 trace_amdgpu_vm_grab_id(vm
, ring
->idx
, job
);
302 mutex_unlock(&adev
->vm_manager
.lock
);
305 } while (i
!= ring
->idx
);
307 /* Still no ID to use? Then use the idle one found earlier */
310 /* Remember this submission as user of the VMID */
311 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
315 fence_put(id
->first
);
316 id
->first
= fence_get(fence
);
318 fence_put(id
->last_flush
);
319 id
->last_flush
= NULL
;
321 fence_put(id
->flushed_updates
);
322 id
->flushed_updates
= fence_get(updates
);
324 id
->pd_gpu_addr
= job
->vm_pd_addr
;
325 id
->current_gpu_reset_count
= atomic_read(&adev
->gpu_reset_counter
);
326 list_move_tail(&id
->list
, &adev
->vm_manager
.ids_lru
);
327 atomic64_set(&id
->owner
, vm
->client_id
);
328 vm
->ids
[ring
->idx
] = id
;
330 job
->vm_id
= id
- adev
->vm_manager
.ids
;
331 trace_amdgpu_vm_grab_id(vm
, ring
->idx
, job
);
334 mutex_unlock(&adev
->vm_manager
.lock
);
338 static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring
*ring
)
340 struct amdgpu_device
*adev
= ring
->adev
;
341 const struct amdgpu_ip_block_version
*ip_block
;
343 if (ring
->type
!= AMDGPU_RING_TYPE_COMPUTE
)
344 /* only compute rings */
347 ip_block
= amdgpu_get_ip_block(adev
, AMD_IP_BLOCK_TYPE_GFX
);
351 if (ip_block
->major
<= 7) {
352 /* gfx7 has no workaround */
354 } else if (ip_block
->major
== 8) {
355 if (adev
->gfx
.mec_fw_version
>= 673)
356 /* gfx8 is fixed in MEC firmware 673 */
365 * amdgpu_vm_flush - hardware flush the vm
367 * @ring: ring to use for flush
368 * @vm_id: vmid number to use
369 * @pd_addr: address of the page directory
371 * Emit a VM flush when it is necessary.
373 int amdgpu_vm_flush(struct amdgpu_ring
*ring
, struct amdgpu_job
*job
)
375 struct amdgpu_device
*adev
= ring
->adev
;
376 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[job
->vm_id
];
377 bool gds_switch_needed
= ring
->funcs
->emit_gds_switch
&& (
378 id
->gds_base
!= job
->gds_base
||
379 id
->gds_size
!= job
->gds_size
||
380 id
->gws_base
!= job
->gws_base
||
381 id
->gws_size
!= job
->gws_size
||
382 id
->oa_base
!= job
->oa_base
||
383 id
->oa_size
!= job
->oa_size
);
386 if (ring
->funcs
->emit_pipeline_sync
&& (
387 job
->vm_needs_flush
|| gds_switch_needed
||
388 amdgpu_vm_ring_has_compute_vm_bug(ring
)))
389 amdgpu_ring_emit_pipeline_sync(ring
);
391 if (ring
->funcs
->emit_vm_flush
&& (job
->vm_needs_flush
||
392 amdgpu_vm_is_gpu_reset(adev
, id
))) {
395 trace_amdgpu_vm_flush(job
->vm_pd_addr
, ring
->idx
, job
->vm_id
);
396 amdgpu_ring_emit_vm_flush(ring
, job
->vm_id
, job
->vm_pd_addr
);
398 r
= amdgpu_fence_emit(ring
, &fence
);
402 mutex_lock(&adev
->vm_manager
.lock
);
403 fence_put(id
->last_flush
);
404 id
->last_flush
= fence
;
405 mutex_unlock(&adev
->vm_manager
.lock
);
408 if (gds_switch_needed
) {
409 id
->gds_base
= job
->gds_base
;
410 id
->gds_size
= job
->gds_size
;
411 id
->gws_base
= job
->gws_base
;
412 id
->gws_size
= job
->gws_size
;
413 id
->oa_base
= job
->oa_base
;
414 id
->oa_size
= job
->oa_size
;
415 amdgpu_ring_emit_gds_switch(ring
, job
->vm_id
,
416 job
->gds_base
, job
->gds_size
,
417 job
->gws_base
, job
->gws_size
,
418 job
->oa_base
, job
->oa_size
);
425 * amdgpu_vm_reset_id - reset VMID to zero
427 * @adev: amdgpu device structure
428 * @vm_id: vmid number to use
430 * Reset saved GDW, GWS and OA to force switch on next flush.
432 void amdgpu_vm_reset_id(struct amdgpu_device
*adev
, unsigned vm_id
)
434 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[vm_id
];
445 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
448 * @bo: requested buffer object
450 * Find @bo inside the requested vm.
451 * Search inside the @bos vm list for the requested vm
452 * Returns the found bo_va or NULL if none is found
454 * Object has to be reserved!
456 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
457 struct amdgpu_bo
*bo
)
459 struct amdgpu_bo_va
*bo_va
;
461 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
462 if (bo_va
->vm
== vm
) {
470 * amdgpu_vm_update_pages - helper to call the right asic function
472 * @params: see amdgpu_pte_update_params definition
473 * @pe: addr of the page entry
474 * @addr: dst addr to write into pe
475 * @count: number of page entries to update
476 * @incr: increase next addr by incr bytes
477 * @flags: hw access flags
479 * Traces the parameters and calls the right asic functions
480 * to setup the page table using the DMA.
482 static void amdgpu_vm_update_pages(struct amdgpu_pte_update_params
*params
,
483 uint64_t pe
, uint64_t addr
,
484 unsigned count
, uint32_t incr
,
487 trace_amdgpu_vm_set_page(pe
, addr
, count
, incr
, flags
);
490 amdgpu_vm_copy_pte(params
->adev
, params
->ib
,
491 pe
, (params
->src
+ (addr
>> 12) * 8), count
);
493 } else if (count
< 3) {
494 amdgpu_vm_write_pte(params
->adev
, params
->ib
, NULL
, pe
, addr
,
498 amdgpu_vm_set_pte_pde(params
->adev
, params
->ib
, pe
, addr
,
504 * amdgpu_vm_clear_bo - initially clear the page dir/table
506 * @adev: amdgpu_device pointer
509 * need to reserve bo first before calling it.
511 static int amdgpu_vm_clear_bo(struct amdgpu_device
*adev
,
512 struct amdgpu_vm
*vm
,
513 struct amdgpu_bo
*bo
)
515 struct amdgpu_ring
*ring
;
516 struct fence
*fence
= NULL
;
517 struct amdgpu_job
*job
;
518 struct amdgpu_pte_update_params params
;
523 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
525 r
= reservation_object_reserve_shared(bo
->tbo
.resv
);
529 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
533 addr
= amdgpu_bo_gpu_offset(bo
);
534 entries
= amdgpu_bo_size(bo
) / 8;
536 r
= amdgpu_job_alloc_with_ib(adev
, 64, &job
);
540 memset(¶ms
, 0, sizeof(params
));
542 params
.ib
= &job
->ibs
[0];
543 amdgpu_vm_update_pages(¶ms
, addr
, 0, entries
, 0, 0);
544 amdgpu_ring_pad_ib(ring
, &job
->ibs
[0]);
546 WARN_ON(job
->ibs
[0].length_dw
> 64);
547 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
548 AMDGPU_FENCE_OWNER_VM
, &fence
);
552 amdgpu_bo_fence(bo
, fence
, true);
557 amdgpu_job_free(job
);
564 * amdgpu_vm_map_gart - Resolve gart mapping of addr
566 * @pages_addr: optional DMA address to use for lookup
567 * @addr: the unmapped addr
569 * Look up the physical address of the page that the pte resolves
570 * to and return the pointer for the page table entry.
572 uint64_t amdgpu_vm_map_gart(const dma_addr_t
*pages_addr
, uint64_t addr
)
577 /* page table offset */
578 result
= pages_addr
[addr
>> PAGE_SHIFT
];
580 /* in case cpu page size != gpu page size*/
581 result
|= addr
& (~PAGE_MASK
);
584 /* No mapping required */
588 result
&= 0xFFFFFFFFFFFFF000ULL
;
594 * amdgpu_vm_update_pdes - make sure that page directory is valid
596 * @adev: amdgpu_device pointer
598 * @start: start of GPU address range
599 * @end: end of GPU address range
601 * Allocates new page tables if necessary
602 * and updates the page directory.
603 * Returns 0 for success, error for failure.
605 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
606 struct amdgpu_vm
*vm
)
608 struct amdgpu_ring
*ring
;
609 struct amdgpu_bo
*pd
= vm
->page_directory
;
610 uint64_t pd_addr
= amdgpu_bo_gpu_offset(pd
);
611 uint32_t incr
= AMDGPU_VM_PTE_COUNT
* 8;
612 uint64_t last_pde
= ~0, last_pt
= ~0;
613 unsigned count
= 0, pt_idx
, ndw
;
614 struct amdgpu_job
*job
;
615 struct amdgpu_pte_update_params params
;
616 struct fence
*fence
= NULL
;
620 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
625 /* assume the worst case */
626 ndw
+= vm
->max_pde_used
* 6;
628 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
632 memset(¶ms
, 0, sizeof(params
));
634 params
.ib
= &job
->ibs
[0];
636 /* walk over the address space and update the page directory */
637 for (pt_idx
= 0; pt_idx
<= vm
->max_pde_used
; ++pt_idx
) {
638 struct amdgpu_bo
*bo
= vm
->page_tables
[pt_idx
].entry
.robj
;
644 pt
= amdgpu_bo_gpu_offset(bo
);
645 if (vm
->page_tables
[pt_idx
].addr
== pt
)
647 vm
->page_tables
[pt_idx
].addr
= pt
;
649 pde
= pd_addr
+ pt_idx
* 8;
650 if (((last_pde
+ 8 * count
) != pde
) ||
651 ((last_pt
+ incr
* count
) != pt
)) {
654 amdgpu_vm_update_pages(¶ms
, last_pde
,
655 last_pt
, count
, incr
,
668 amdgpu_vm_update_pages(¶ms
, last_pde
, last_pt
,
669 count
, incr
, AMDGPU_PTE_VALID
);
671 if (params
.ib
->length_dw
!= 0) {
672 amdgpu_ring_pad_ib(ring
, params
.ib
);
673 amdgpu_sync_resv(adev
, &job
->sync
, pd
->tbo
.resv
,
674 AMDGPU_FENCE_OWNER_VM
);
675 WARN_ON(params
.ib
->length_dw
> ndw
);
676 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
677 AMDGPU_FENCE_OWNER_VM
, &fence
);
681 amdgpu_bo_fence(pd
, fence
, true);
682 fence_put(vm
->page_directory_fence
);
683 vm
->page_directory_fence
= fence_get(fence
);
687 amdgpu_job_free(job
);
693 amdgpu_job_free(job
);
698 * amdgpu_vm_update_ptes - make sure that page tables are valid
700 * @params: see amdgpu_pte_update_params definition
702 * @start: start of GPU address range
703 * @end: end of GPU address range
704 * @dst: destination address to map to, the next dst inside the function
705 * @flags: mapping flags
707 * Update the page tables in the range @start - @end.
709 static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params
*params
,
710 struct amdgpu_vm
*vm
,
711 uint64_t start
, uint64_t end
,
712 uint64_t dst
, uint32_t flags
)
714 const uint64_t mask
= AMDGPU_VM_PTE_COUNT
- 1;
716 uint64_t cur_pe_start
, cur_nptes
, cur_dst
;
717 uint64_t addr
; /* next GPU address to be updated */
719 struct amdgpu_bo
*pt
;
720 unsigned nptes
; /* next number of ptes to be updated */
721 uint64_t next_pe_start
;
723 /* initialize the variables */
725 pt_idx
= addr
>> amdgpu_vm_block_size
;
726 pt
= vm
->page_tables
[pt_idx
].entry
.robj
;
728 if ((addr
& ~mask
) == (end
& ~mask
))
731 nptes
= AMDGPU_VM_PTE_COUNT
- (addr
& mask
);
733 cur_pe_start
= amdgpu_bo_gpu_offset(pt
);
734 cur_pe_start
+= (addr
& mask
) * 8;
740 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
;
742 /* walk over the address space and update the page tables */
744 pt_idx
= addr
>> amdgpu_vm_block_size
;
745 pt
= vm
->page_tables
[pt_idx
].entry
.robj
;
747 if ((addr
& ~mask
) == (end
& ~mask
))
750 nptes
= AMDGPU_VM_PTE_COUNT
- (addr
& mask
);
752 next_pe_start
= amdgpu_bo_gpu_offset(pt
);
753 next_pe_start
+= (addr
& mask
) * 8;
755 if ((cur_pe_start
+ 8 * cur_nptes
) == next_pe_start
) {
756 /* The next ptb is consecutive to current ptb.
757 * Don't call amdgpu_vm_update_pages now.
758 * Will update two ptbs together in future.
762 amdgpu_vm_update_pages(params
, cur_pe_start
, cur_dst
,
763 cur_nptes
, AMDGPU_GPU_PAGE_SIZE
,
766 cur_pe_start
= next_pe_start
;
773 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
;
776 amdgpu_vm_update_pages(params
, cur_pe_start
, cur_dst
, cur_nptes
,
777 AMDGPU_GPU_PAGE_SIZE
, flags
);
781 * amdgpu_vm_frag_ptes - add fragment information to PTEs
783 * @params: see amdgpu_pte_update_params definition
785 * @start: first PTE to handle
786 * @end: last PTE to handle
787 * @dst: addr those PTEs should point to
788 * @flags: hw mapping flags
790 static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params
*params
,
791 struct amdgpu_vm
*vm
,
792 uint64_t start
, uint64_t end
,
793 uint64_t dst
, uint32_t flags
)
796 * The MC L1 TLB supports variable sized pages, based on a fragment
797 * field in the PTE. When this field is set to a non-zero value, page
798 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
799 * flags are considered valid for all PTEs within the fragment range
800 * and corresponding mappings are assumed to be physically contiguous.
802 * The L1 TLB can store a single PTE for the whole fragment,
803 * significantly increasing the space available for translation
804 * caching. This leads to large improvements in throughput when the
805 * TLB is under pressure.
807 * The L2 TLB distributes small and large fragments into two
808 * asymmetric partitions. The large fragment cache is significantly
809 * larger. Thus, we try to use large fragments wherever possible.
810 * Userspace can support this by aligning virtual base address and
811 * allocation size to the fragment size.
814 const uint64_t frag_align
= 1 << AMDGPU_LOG2_PAGES_PER_FRAG
;
816 uint64_t frag_start
= ALIGN(start
, frag_align
);
817 uint64_t frag_end
= end
& ~(frag_align
- 1);
821 /* system pages are non continuously */
822 if (params
->src
|| !(flags
& AMDGPU_PTE_VALID
) ||
823 (frag_start
>= frag_end
)) {
825 amdgpu_vm_update_ptes(params
, vm
, start
, end
, dst
, flags
);
829 /* use more than 64KB fragment size if possible */
830 frag
= lower_32_bits(frag_start
| frag_end
);
831 frag
= likely(frag
) ? __ffs(frag
) : 31;
833 /* handle the 4K area at the beginning */
834 if (start
!= frag_start
) {
835 amdgpu_vm_update_ptes(params
, vm
, start
, frag_start
,
837 dst
+= (frag_start
- start
) * AMDGPU_GPU_PAGE_SIZE
;
840 /* handle the area in the middle */
841 amdgpu_vm_update_ptes(params
, vm
, frag_start
, frag_end
, dst
,
842 flags
| AMDGPU_PTE_FRAG(frag
));
844 /* handle the 4K area at the end */
845 if (frag_end
!= end
) {
846 dst
+= (frag_end
- frag_start
) * AMDGPU_GPU_PAGE_SIZE
;
847 amdgpu_vm_update_ptes(params
, vm
, frag_end
, end
, dst
, flags
);
852 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
854 * @adev: amdgpu_device pointer
855 * @exclusive: fence we need to sync to
856 * @src: address where to copy page table entries from
857 * @pages_addr: DMA addresses to use for mapping
859 * @start: start of mapped range
860 * @last: last mapped entry
861 * @flags: flags for the entries
862 * @addr: addr to set the area to
863 * @fence: optional resulting fence
865 * Fill in the page table entries between @start and @last.
866 * Returns 0 for success, -EINVAL for failure.
868 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device
*adev
,
869 struct fence
*exclusive
,
871 dma_addr_t
*pages_addr
,
872 struct amdgpu_vm
*vm
,
873 uint64_t start
, uint64_t last
,
874 uint32_t flags
, uint64_t addr
,
875 struct fence
**fence
)
877 struct amdgpu_ring
*ring
;
878 void *owner
= AMDGPU_FENCE_OWNER_VM
;
879 unsigned nptes
, ncmds
, ndw
;
880 struct amdgpu_job
*job
;
881 struct amdgpu_pte_update_params params
;
882 struct fence
*f
= NULL
;
885 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
887 memset(¶ms
, 0, sizeof(params
));
891 /* sync to everything on unmapping */
892 if (!(flags
& AMDGPU_PTE_VALID
))
893 owner
= AMDGPU_FENCE_OWNER_UNDEFINED
;
895 nptes
= last
- start
+ 1;
898 * reserve space for one command every (1 << BLOCK_SIZE)
899 * entries or 2k dwords (whatever is smaller)
901 ncmds
= (nptes
>> min(amdgpu_vm_block_size
, 11)) + 1;
907 /* only copy commands needed */
910 } else if (pages_addr
) {
911 /* copy commands needed */
918 /* set page commands needed */
921 /* two extra commands for begin/end of fragment */
925 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
929 params
.ib
= &job
->ibs
[0];
931 if (!src
&& pages_addr
) {
935 /* Put the PTEs at the end of the IB. */
937 pte
= (uint64_t *)&(job
->ibs
->ptr
[i
]);
938 params
.src
= job
->ibs
->gpu_addr
+ i
* 4;
940 for (i
= 0; i
< nptes
; ++i
) {
941 pte
[i
] = amdgpu_vm_map_gart(pages_addr
, addr
+ i
*
942 AMDGPU_GPU_PAGE_SIZE
);
947 r
= amdgpu_sync_fence(adev
, &job
->sync
, exclusive
);
951 r
= amdgpu_sync_resv(adev
, &job
->sync
, vm
->page_directory
->tbo
.resv
,
956 r
= reservation_object_reserve_shared(vm
->page_directory
->tbo
.resv
);
960 amdgpu_vm_frag_ptes(¶ms
, vm
, start
, last
+ 1, addr
, flags
);
962 amdgpu_ring_pad_ib(ring
, params
.ib
);
963 WARN_ON(params
.ib
->length_dw
> ndw
);
964 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
965 AMDGPU_FENCE_OWNER_VM
, &f
);
969 amdgpu_bo_fence(vm
->page_directory
, f
, true);
972 *fence
= fence_get(f
);
978 amdgpu_job_free(job
);
983 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
985 * @adev: amdgpu_device pointer
986 * @exclusive: fence we need to sync to
987 * @gtt_flags: flags as they are used for GTT
988 * @pages_addr: DMA addresses to use for mapping
990 * @mapping: mapped range and flags to use for the update
991 * @addr: addr to set the area to
992 * @flags: HW flags for the mapping
993 * @fence: optional resulting fence
995 * Split the mapping into smaller chunks so that each update fits
997 * Returns 0 for success, -EINVAL for failure.
999 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device
*adev
,
1000 struct fence
*exclusive
,
1002 dma_addr_t
*pages_addr
,
1003 struct amdgpu_vm
*vm
,
1004 struct amdgpu_bo_va_mapping
*mapping
,
1005 uint32_t flags
, uint64_t addr
,
1006 struct fence
**fence
)
1008 const uint64_t max_size
= 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE
;
1010 uint64_t src
= 0, start
= mapping
->it
.start
;
1013 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1014 * but in case of something, we filter the flags in first place
1016 if (!(mapping
->flags
& AMDGPU_PTE_READABLE
))
1017 flags
&= ~AMDGPU_PTE_READABLE
;
1018 if (!(mapping
->flags
& AMDGPU_PTE_WRITEABLE
))
1019 flags
&= ~AMDGPU_PTE_WRITEABLE
;
1021 trace_amdgpu_vm_bo_update(mapping
);
1024 if (flags
== gtt_flags
)
1025 src
= adev
->gart
.table_addr
+ (addr
>> 12) * 8;
1028 addr
+= mapping
->offset
;
1030 if (!pages_addr
|| src
)
1031 return amdgpu_vm_bo_update_mapping(adev
, exclusive
,
1032 src
, pages_addr
, vm
,
1033 start
, mapping
->it
.last
,
1034 flags
, addr
, fence
);
1036 while (start
!= mapping
->it
.last
+ 1) {
1039 last
= min((uint64_t)mapping
->it
.last
, start
+ max_size
- 1);
1040 r
= amdgpu_vm_bo_update_mapping(adev
, exclusive
,
1041 src
, pages_addr
, vm
,
1042 start
, last
, flags
, addr
,
1048 addr
+= max_size
* AMDGPU_GPU_PAGE_SIZE
;
1055 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1057 * @adev: amdgpu_device pointer
1058 * @bo_va: requested BO and VM object
1061 * Fill in the page table entries for @bo_va.
1062 * Returns 0 for success, -EINVAL for failure.
1064 * Object have to be reserved and mutex must be locked!
1066 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
1067 struct amdgpu_bo_va
*bo_va
,
1068 struct ttm_mem_reg
*mem
)
1070 struct amdgpu_vm
*vm
= bo_va
->vm
;
1071 struct amdgpu_bo_va_mapping
*mapping
;
1072 dma_addr_t
*pages_addr
= NULL
;
1073 uint32_t gtt_flags
, flags
;
1074 struct fence
*exclusive
;
1079 struct ttm_dma_tt
*ttm
;
1081 addr
= (u64
)mem
->start
<< PAGE_SHIFT
;
1082 switch (mem
->mem_type
) {
1084 ttm
= container_of(bo_va
->bo
->tbo
.ttm
, struct
1086 pages_addr
= ttm
->dma_address
;
1090 addr
+= adev
->vm_manager
.vram_base_offset
;
1097 exclusive
= reservation_object_get_excl(bo_va
->bo
->tbo
.resv
);
1103 flags
= amdgpu_ttm_tt_pte_flags(adev
, bo_va
->bo
->tbo
.ttm
, mem
);
1104 gtt_flags
= (adev
== bo_va
->bo
->adev
) ? flags
: 0;
1106 spin_lock(&vm
->status_lock
);
1107 if (!list_empty(&bo_va
->vm_status
))
1108 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
1109 spin_unlock(&vm
->status_lock
);
1111 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1112 r
= amdgpu_vm_bo_split_mapping(adev
, exclusive
,
1113 gtt_flags
, pages_addr
, vm
,
1114 mapping
, flags
, addr
,
1115 &bo_va
->last_pt_update
);
1120 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1121 list_for_each_entry(mapping
, &bo_va
->valids
, list
)
1122 trace_amdgpu_vm_bo_mapping(mapping
);
1124 list_for_each_entry(mapping
, &bo_va
->invalids
, list
)
1125 trace_amdgpu_vm_bo_mapping(mapping
);
1128 spin_lock(&vm
->status_lock
);
1129 list_splice_init(&bo_va
->invalids
, &bo_va
->valids
);
1130 list_del_init(&bo_va
->vm_status
);
1132 list_add(&bo_va
->vm_status
, &vm
->cleared
);
1133 spin_unlock(&vm
->status_lock
);
1139 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1141 * @adev: amdgpu_device pointer
1144 * Make sure all freed BOs are cleared in the PT.
1145 * Returns 0 for success.
1147 * PTs have to be reserved and mutex must be locked!
1149 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
1150 struct amdgpu_vm
*vm
)
1152 struct amdgpu_bo_va_mapping
*mapping
;
1155 while (!list_empty(&vm
->freed
)) {
1156 mapping
= list_first_entry(&vm
->freed
,
1157 struct amdgpu_bo_va_mapping
, list
);
1158 list_del(&mapping
->list
);
1160 r
= amdgpu_vm_bo_split_mapping(adev
, NULL
, 0, NULL
, vm
, mapping
,
1172 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1174 * @adev: amdgpu_device pointer
1177 * Make sure all invalidated BOs are cleared in the PT.
1178 * Returns 0 for success.
1180 * PTs have to be reserved and mutex must be locked!
1182 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
,
1183 struct amdgpu_vm
*vm
, struct amdgpu_sync
*sync
)
1185 struct amdgpu_bo_va
*bo_va
= NULL
;
1188 spin_lock(&vm
->status_lock
);
1189 while (!list_empty(&vm
->invalidated
)) {
1190 bo_va
= list_first_entry(&vm
->invalidated
,
1191 struct amdgpu_bo_va
, vm_status
);
1192 spin_unlock(&vm
->status_lock
);
1194 r
= amdgpu_vm_bo_update(adev
, bo_va
, NULL
);
1198 spin_lock(&vm
->status_lock
);
1200 spin_unlock(&vm
->status_lock
);
1203 r
= amdgpu_sync_fence(adev
, sync
, bo_va
->last_pt_update
);
1209 * amdgpu_vm_bo_add - add a bo to a specific vm
1211 * @adev: amdgpu_device pointer
1213 * @bo: amdgpu buffer object
1215 * Add @bo into the requested vm.
1216 * Add @bo to the list of bos associated with the vm
1217 * Returns newly added bo_va or NULL for failure
1219 * Object has to be reserved!
1221 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
1222 struct amdgpu_vm
*vm
,
1223 struct amdgpu_bo
*bo
)
1225 struct amdgpu_bo_va
*bo_va
;
1227 bo_va
= kzalloc(sizeof(struct amdgpu_bo_va
), GFP_KERNEL
);
1228 if (bo_va
== NULL
) {
1233 bo_va
->ref_count
= 1;
1234 INIT_LIST_HEAD(&bo_va
->bo_list
);
1235 INIT_LIST_HEAD(&bo_va
->valids
);
1236 INIT_LIST_HEAD(&bo_va
->invalids
);
1237 INIT_LIST_HEAD(&bo_va
->vm_status
);
1239 list_add_tail(&bo_va
->bo_list
, &bo
->va
);
1245 * amdgpu_vm_bo_map - map bo inside a vm
1247 * @adev: amdgpu_device pointer
1248 * @bo_va: bo_va to store the address
1249 * @saddr: where to map the BO
1250 * @offset: requested offset in the BO
1251 * @flags: attributes of pages (read/write/valid/etc.)
1253 * Add a mapping of the BO at the specefied addr into the VM.
1254 * Returns 0 for success, error for failure.
1256 * Object has to be reserved and unreserved outside!
1258 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
1259 struct amdgpu_bo_va
*bo_va
,
1260 uint64_t saddr
, uint64_t offset
,
1261 uint64_t size
, uint32_t flags
)
1263 struct amdgpu_bo_va_mapping
*mapping
;
1264 struct amdgpu_vm
*vm
= bo_va
->vm
;
1265 struct interval_tree_node
*it
;
1266 unsigned last_pfn
, pt_idx
;
1270 /* validate the parameters */
1271 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
1272 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
)
1275 /* make sure object fit at this offset */
1276 eaddr
= saddr
+ size
- 1;
1277 if ((saddr
>= eaddr
) || (offset
+ size
> amdgpu_bo_size(bo_va
->bo
)))
1280 last_pfn
= eaddr
/ AMDGPU_GPU_PAGE_SIZE
;
1281 if (last_pfn
>= adev
->vm_manager
.max_pfn
) {
1282 dev_err(adev
->dev
, "va above limit (0x%08X >= 0x%08X)\n",
1283 last_pfn
, adev
->vm_manager
.max_pfn
);
1287 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1288 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
1290 it
= interval_tree_iter_first(&vm
->va
, saddr
, eaddr
);
1292 struct amdgpu_bo_va_mapping
*tmp
;
1293 tmp
= container_of(it
, struct amdgpu_bo_va_mapping
, it
);
1294 /* bo and tmp overlap, invalid addr */
1295 dev_err(adev
->dev
, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1296 "0x%010lx-0x%010lx\n", bo_va
->bo
, saddr
, eaddr
,
1297 tmp
->it
.start
, tmp
->it
.last
+ 1);
1302 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
1308 INIT_LIST_HEAD(&mapping
->list
);
1309 mapping
->it
.start
= saddr
;
1310 mapping
->it
.last
= eaddr
;
1311 mapping
->offset
= offset
;
1312 mapping
->flags
= flags
;
1314 list_add(&mapping
->list
, &bo_va
->invalids
);
1315 interval_tree_insert(&mapping
->it
, &vm
->va
);
1317 /* Make sure the page tables are allocated */
1318 saddr
>>= amdgpu_vm_block_size
;
1319 eaddr
>>= amdgpu_vm_block_size
;
1321 BUG_ON(eaddr
>= amdgpu_vm_num_pdes(adev
));
1323 if (eaddr
> vm
->max_pde_used
)
1324 vm
->max_pde_used
= eaddr
;
1326 /* walk over the address space and allocate the page tables */
1327 for (pt_idx
= saddr
; pt_idx
<= eaddr
; ++pt_idx
) {
1328 struct reservation_object
*resv
= vm
->page_directory
->tbo
.resv
;
1329 struct amdgpu_bo_list_entry
*entry
;
1330 struct amdgpu_bo
*pt
;
1332 entry
= &vm
->page_tables
[pt_idx
].entry
;
1336 r
= amdgpu_bo_create(adev
, AMDGPU_VM_PTE_COUNT
* 8,
1337 AMDGPU_GPU_PAGE_SIZE
, true,
1338 AMDGPU_GEM_DOMAIN_VRAM
,
1339 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
|
1340 AMDGPU_GEM_CREATE_SHADOW
,
1345 /* Keep a reference to the page table to avoid freeing
1346 * them up in the wrong order.
1348 pt
->parent
= amdgpu_bo_ref(vm
->page_directory
);
1350 r
= amdgpu_vm_clear_bo(adev
, vm
, pt
);
1352 amdgpu_bo_unref(&pt
);
1357 entry
->priority
= 0;
1358 entry
->tv
.bo
= &entry
->robj
->tbo
;
1359 entry
->tv
.shared
= true;
1360 entry
->user_pages
= NULL
;
1361 vm
->page_tables
[pt_idx
].addr
= 0;
1367 list_del(&mapping
->list
);
1368 interval_tree_remove(&mapping
->it
, &vm
->va
);
1369 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1377 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1379 * @adev: amdgpu_device pointer
1380 * @bo_va: bo_va to remove the address from
1381 * @saddr: where to the BO is mapped
1383 * Remove a mapping of the BO at the specefied addr from the VM.
1384 * Returns 0 for success, error for failure.
1386 * Object has to be reserved and unreserved outside!
1388 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
1389 struct amdgpu_bo_va
*bo_va
,
1392 struct amdgpu_bo_va_mapping
*mapping
;
1393 struct amdgpu_vm
*vm
= bo_va
->vm
;
1396 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1398 list_for_each_entry(mapping
, &bo_va
->valids
, list
) {
1399 if (mapping
->it
.start
== saddr
)
1403 if (&mapping
->list
== &bo_va
->valids
) {
1406 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1407 if (mapping
->it
.start
== saddr
)
1411 if (&mapping
->list
== &bo_va
->invalids
)
1415 list_del(&mapping
->list
);
1416 interval_tree_remove(&mapping
->it
, &vm
->va
);
1417 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1420 list_add(&mapping
->list
, &vm
->freed
);
1428 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1430 * @adev: amdgpu_device pointer
1431 * @bo_va: requested bo_va
1433 * Remove @bo_va->bo from the requested vm.
1435 * Object have to be reserved!
1437 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
1438 struct amdgpu_bo_va
*bo_va
)
1440 struct amdgpu_bo_va_mapping
*mapping
, *next
;
1441 struct amdgpu_vm
*vm
= bo_va
->vm
;
1443 list_del(&bo_va
->bo_list
);
1445 spin_lock(&vm
->status_lock
);
1446 list_del(&bo_va
->vm_status
);
1447 spin_unlock(&vm
->status_lock
);
1449 list_for_each_entry_safe(mapping
, next
, &bo_va
->valids
, list
) {
1450 list_del(&mapping
->list
);
1451 interval_tree_remove(&mapping
->it
, &vm
->va
);
1452 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1453 list_add(&mapping
->list
, &vm
->freed
);
1455 list_for_each_entry_safe(mapping
, next
, &bo_va
->invalids
, list
) {
1456 list_del(&mapping
->list
);
1457 interval_tree_remove(&mapping
->it
, &vm
->va
);
1461 fence_put(bo_va
->last_pt_update
);
1466 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1468 * @adev: amdgpu_device pointer
1470 * @bo: amdgpu buffer object
1472 * Mark @bo as invalid.
1474 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
1475 struct amdgpu_bo
*bo
)
1477 struct amdgpu_bo_va
*bo_va
;
1479 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
1480 spin_lock(&bo_va
->vm
->status_lock
);
1481 if (list_empty(&bo_va
->vm_status
))
1482 list_add(&bo_va
->vm_status
, &bo_va
->vm
->invalidated
);
1483 spin_unlock(&bo_va
->vm
->status_lock
);
1488 * amdgpu_vm_init - initialize a vm instance
1490 * @adev: amdgpu_device pointer
1495 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1497 const unsigned align
= min(AMDGPU_VM_PTB_ALIGN_SIZE
,
1498 AMDGPU_VM_PTE_COUNT
* 8);
1499 unsigned pd_size
, pd_entries
;
1500 unsigned ring_instance
;
1501 struct amdgpu_ring
*ring
;
1502 struct amd_sched_rq
*rq
;
1505 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
1508 vm
->client_id
= atomic64_inc_return(&adev
->vm_manager
.client_counter
);
1509 spin_lock_init(&vm
->status_lock
);
1510 INIT_LIST_HEAD(&vm
->invalidated
);
1511 INIT_LIST_HEAD(&vm
->cleared
);
1512 INIT_LIST_HEAD(&vm
->freed
);
1514 pd_size
= amdgpu_vm_directory_size(adev
);
1515 pd_entries
= amdgpu_vm_num_pdes(adev
);
1517 /* allocate page table array */
1518 vm
->page_tables
= drm_calloc_large(pd_entries
, sizeof(struct amdgpu_vm_pt
));
1519 if (vm
->page_tables
== NULL
) {
1520 DRM_ERROR("Cannot allocate memory for page table array\n");
1524 /* create scheduler entity for page table updates */
1526 ring_instance
= atomic_inc_return(&adev
->vm_manager
.vm_pte_next_ring
);
1527 ring_instance
%= adev
->vm_manager
.vm_pte_num_rings
;
1528 ring
= adev
->vm_manager
.vm_pte_rings
[ring_instance
];
1529 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_KERNEL
];
1530 r
= amd_sched_entity_init(&ring
->sched
, &vm
->entity
,
1531 rq
, amdgpu_sched_jobs
);
1535 vm
->page_directory_fence
= NULL
;
1537 r
= amdgpu_bo_create(adev
, pd_size
, align
, true,
1538 AMDGPU_GEM_DOMAIN_VRAM
,
1539 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
|
1540 AMDGPU_GEM_CREATE_SHADOW
,
1541 NULL
, NULL
, &vm
->page_directory
);
1543 goto error_free_sched_entity
;
1545 r
= amdgpu_bo_reserve(vm
->page_directory
, false);
1547 goto error_free_page_directory
;
1549 r
= amdgpu_vm_clear_bo(adev
, vm
, vm
->page_directory
);
1550 amdgpu_bo_unreserve(vm
->page_directory
);
1552 goto error_free_page_directory
;
1553 vm
->last_eviction_counter
= atomic64_read(&adev
->num_evictions
);
1557 error_free_page_directory
:
1558 amdgpu_bo_unref(&vm
->page_directory
);
1559 vm
->page_directory
= NULL
;
1561 error_free_sched_entity
:
1562 amd_sched_entity_fini(&ring
->sched
, &vm
->entity
);
1568 * amdgpu_vm_fini - tear down a vm instance
1570 * @adev: amdgpu_device pointer
1574 * Unbind the VM and remove all bos from the vm bo list
1576 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1578 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
1581 amd_sched_entity_fini(vm
->entity
.sched
, &vm
->entity
);
1583 if (!RB_EMPTY_ROOT(&vm
->va
)) {
1584 dev_err(adev
->dev
, "still active bo inside vm\n");
1586 rbtree_postorder_for_each_entry_safe(mapping
, tmp
, &vm
->va
, it
.rb
) {
1587 list_del(&mapping
->list
);
1588 interval_tree_remove(&mapping
->it
, &vm
->va
);
1591 list_for_each_entry_safe(mapping
, tmp
, &vm
->freed
, list
) {
1592 list_del(&mapping
->list
);
1596 for (i
= 0; i
< amdgpu_vm_num_pdes(adev
); i
++) {
1597 if (vm
->page_tables
[i
].entry
.robj
&&
1598 vm
->page_tables
[i
].entry
.robj
->shadow
)
1599 amdgpu_bo_unref(&vm
->page_tables
[i
].entry
.robj
->shadow
);
1600 amdgpu_bo_unref(&vm
->page_tables
[i
].entry
.robj
);
1602 drm_free_large(vm
->page_tables
);
1604 if (vm
->page_directory
->shadow
)
1605 amdgpu_bo_unref(&vm
->page_directory
->shadow
);
1606 amdgpu_bo_unref(&vm
->page_directory
);
1607 fence_put(vm
->page_directory_fence
);
1611 * amdgpu_vm_manager_init - init the VM manager
1613 * @adev: amdgpu_device pointer
1615 * Initialize the VM manager structures
1617 void amdgpu_vm_manager_init(struct amdgpu_device
*adev
)
1621 INIT_LIST_HEAD(&adev
->vm_manager
.ids_lru
);
1623 /* skip over VMID 0, since it is the system VM */
1624 for (i
= 1; i
< adev
->vm_manager
.num_ids
; ++i
) {
1625 amdgpu_vm_reset_id(adev
, i
);
1626 amdgpu_sync_create(&adev
->vm_manager
.ids
[i
].active
);
1627 list_add_tail(&adev
->vm_manager
.ids
[i
].list
,
1628 &adev
->vm_manager
.ids_lru
);
1631 adev
->vm_manager
.fence_context
= fence_context_alloc(AMDGPU_MAX_RINGS
);
1632 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
1633 adev
->vm_manager
.seqno
[i
] = 0;
1635 atomic_set(&adev
->vm_manager
.vm_pte_next_ring
, 0);
1636 atomic64_set(&adev
->vm_manager
.client_counter
, 0);
1640 * amdgpu_vm_manager_fini - cleanup VM manager
1642 * @adev: amdgpu_device pointer
1644 * Cleanup the VM manager and free resources.
1646 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
)
1650 for (i
= 0; i
< AMDGPU_NUM_VM
; ++i
) {
1651 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[i
];
1653 fence_put(adev
->vm_manager
.ids
[i
].first
);
1654 amdgpu_sync_free(&adev
->vm_manager
.ids
[i
].active
);
1655 fence_put(id
->flushed_updates
);