2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * amdgpu_vm_num_pde - return the number of page directory entries
56 * @adev: amdgpu_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device
*adev
)
62 return adev
->vm_manager
.max_pfn
>> amdgpu_vm_block_size
;
66 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
68 * @adev: amdgpu_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned amdgpu_vm_directory_size(struct amdgpu_device
*adev
)
74 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev
) * 8);
78 * amdgpu_vm_get_bos - add the vm BOs to a validation list
80 * @vm: vm providing the BOs
81 * @head: head of validation list
83 * Add the page directory to the list of BOs to
84 * validate for command submission (cayman+).
86 struct amdgpu_bo_list_entry
*amdgpu_vm_get_bos(struct amdgpu_device
*adev
,
88 struct list_head
*head
)
90 struct amdgpu_bo_list_entry
*list
;
93 mutex_lock(&vm
->mutex
);
94 list
= drm_malloc_ab(vm
->max_pde_used
+ 2,
95 sizeof(struct amdgpu_bo_list_entry
));
97 mutex_unlock(&vm
->mutex
);
101 /* add the vm page table to the list */
102 list
[0].robj
= vm
->page_directory
;
103 list
[0].prefered_domains
= AMDGPU_GEM_DOMAIN_VRAM
;
104 list
[0].allowed_domains
= AMDGPU_GEM_DOMAIN_VRAM
;
105 list
[0].priority
= 0;
106 list
[0].tv
.bo
= &vm
->page_directory
->tbo
;
107 list
[0].tv
.shared
= true;
108 list_add(&list
[0].tv
.head
, head
);
110 for (i
= 0, idx
= 1; i
<= vm
->max_pde_used
; i
++) {
111 if (!vm
->page_tables
[i
].bo
)
114 list
[idx
].robj
= vm
->page_tables
[i
].bo
;
115 list
[idx
].prefered_domains
= AMDGPU_GEM_DOMAIN_VRAM
;
116 list
[idx
].allowed_domains
= AMDGPU_GEM_DOMAIN_VRAM
;
117 list
[idx
].priority
= 0;
118 list
[idx
].tv
.bo
= &list
[idx
].robj
->tbo
;
119 list
[idx
].tv
.shared
= true;
120 list_add(&list
[idx
++].tv
.head
, head
);
122 mutex_unlock(&vm
->mutex
);
128 * amdgpu_vm_grab_id - allocate the next free VMID
130 * @vm: vm to allocate id for
131 * @ring: ring we want to submit job to
132 * @sync: sync object where we add dependencies
134 * Allocate an id for the vm, adding fences to the sync obj as necessary.
136 * Global mutex must be locked!
138 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
139 struct amdgpu_sync
*sync
)
141 struct amdgpu_fence
*best
[AMDGPU_MAX_RINGS
] = {};
142 struct amdgpu_vm_id
*vm_id
= &vm
->ids
[ring
->idx
];
143 struct amdgpu_device
*adev
= ring
->adev
;
145 unsigned choices
[2] = {};
148 /* check if the id is still valid */
149 if (vm_id
->id
&& vm_id
->last_id_use
&&
150 vm_id
->last_id_use
== adev
->vm_manager
.active
[vm_id
->id
])
153 /* we definately need to flush */
154 vm_id
->pd_gpu_addr
= ~0ll;
156 /* skip over VMID 0, since it is the system VM */
157 for (i
= 1; i
< adev
->vm_manager
.nvm
; ++i
) {
158 struct amdgpu_fence
*fence
= adev
->vm_manager
.active
[i
];
161 /* found a free one */
163 trace_amdgpu_vm_grab_id(i
, ring
->idx
);
167 if (amdgpu_fence_is_earlier(fence
, best
[fence
->ring
->idx
])) {
168 best
[fence
->ring
->idx
] = fence
;
169 choices
[fence
->ring
== ring
? 0 : 1] = i
;
173 for (i
= 0; i
< 2; ++i
) {
175 struct amdgpu_fence
*fence
;
177 fence
= adev
->vm_manager
.active
[choices
[i
]];
178 vm_id
->id
= choices
[i
];
180 trace_amdgpu_vm_grab_id(choices
[i
], ring
->idx
);
181 return amdgpu_sync_fence(ring
->adev
, sync
, &fence
->base
);
185 /* should never happen */
191 * amdgpu_vm_flush - hardware flush the vm
193 * @ring: ring to use for flush
194 * @vm: vm we want to flush
195 * @updates: last vm update that we waited for
197 * Flush the vm (cayman+).
199 * Global and local mutex must be locked!
201 void amdgpu_vm_flush(struct amdgpu_ring
*ring
,
202 struct amdgpu_vm
*vm
,
203 struct fence
*updates
)
205 uint64_t pd_addr
= amdgpu_bo_gpu_offset(vm
->page_directory
);
206 struct amdgpu_vm_id
*vm_id
= &vm
->ids
[ring
->idx
];
207 struct fence
*flushed_updates
= vm_id
->flushed_updates
;
208 bool is_earlier
= false;
210 if (flushed_updates
&& updates
) {
211 BUG_ON(flushed_updates
->context
!= updates
->context
);
212 is_earlier
= (updates
->seqno
- flushed_updates
->seqno
<=
213 INT_MAX
) ? true : false;
216 if (pd_addr
!= vm_id
->pd_gpu_addr
|| !flushed_updates
||
219 trace_amdgpu_vm_flush(pd_addr
, ring
->idx
, vm_id
->id
);
221 vm_id
->flushed_updates
= fence_get(updates
);
222 fence_put(flushed_updates
);
224 if (!flushed_updates
)
225 vm_id
->flushed_updates
= fence_get(updates
);
226 vm_id
->pd_gpu_addr
= pd_addr
;
227 amdgpu_ring_emit_vm_flush(ring
, vm_id
->id
, vm_id
->pd_gpu_addr
);
232 * amdgpu_vm_fence - remember fence for vm
234 * @adev: amdgpu_device pointer
235 * @vm: vm we want to fence
236 * @fence: fence to remember
238 * Fence the vm (cayman+).
239 * Set the fence used to protect page table and id.
241 * Global and local mutex must be locked!
243 void amdgpu_vm_fence(struct amdgpu_device
*adev
,
244 struct amdgpu_vm
*vm
,
245 struct amdgpu_fence
*fence
)
247 unsigned ridx
= fence
->ring
->idx
;
248 unsigned vm_id
= vm
->ids
[ridx
].id
;
250 amdgpu_fence_unref(&adev
->vm_manager
.active
[vm_id
]);
251 adev
->vm_manager
.active
[vm_id
] = amdgpu_fence_ref(fence
);
253 amdgpu_fence_unref(&vm
->ids
[ridx
].last_id_use
);
254 vm
->ids
[ridx
].last_id_use
= amdgpu_fence_ref(fence
);
258 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
261 * @bo: requested buffer object
263 * Find @bo inside the requested vm (cayman+).
264 * Search inside the @bos vm list for the requested vm
265 * Returns the found bo_va or NULL if none is found
267 * Object has to be reserved!
269 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
270 struct amdgpu_bo
*bo
)
272 struct amdgpu_bo_va
*bo_va
;
274 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
275 if (bo_va
->vm
== vm
) {
283 * amdgpu_vm_update_pages - helper to call the right asic function
285 * @adev: amdgpu_device pointer
286 * @ib: indirect buffer to fill with commands
287 * @pe: addr of the page entry
288 * @addr: dst addr to write into pe
289 * @count: number of page entries to update
290 * @incr: increase next addr by incr bytes
291 * @flags: hw access flags
292 * @gtt_flags: GTT hw access flags
294 * Traces the parameters and calls the right asic functions
295 * to setup the page table using the DMA.
297 static void amdgpu_vm_update_pages(struct amdgpu_device
*adev
,
298 struct amdgpu_ib
*ib
,
299 uint64_t pe
, uint64_t addr
,
300 unsigned count
, uint32_t incr
,
301 uint32_t flags
, uint32_t gtt_flags
)
303 trace_amdgpu_vm_set_page(pe
, addr
, count
, incr
, flags
);
305 if ((flags
& AMDGPU_PTE_SYSTEM
) && (flags
== gtt_flags
)) {
306 uint64_t src
= adev
->gart
.table_addr
+ (addr
>> 12) * 8;
307 amdgpu_vm_copy_pte(adev
, ib
, pe
, src
, count
);
309 } else if ((flags
& AMDGPU_PTE_SYSTEM
) || (count
< 3)) {
310 amdgpu_vm_write_pte(adev
, ib
, pe
, addr
,
314 amdgpu_vm_set_pte_pde(adev
, ib
, pe
, addr
,
319 int amdgpu_vm_free_job(struct amdgpu_job
*sched_job
)
322 for (i
= 0; i
< sched_job
->num_ibs
; i
++)
323 amdgpu_ib_free(sched_job
->adev
, &sched_job
->ibs
[i
]);
324 kfree(sched_job
->ibs
);
329 * amdgpu_vm_clear_bo - initially clear the page dir/table
331 * @adev: amdgpu_device pointer
334 static int amdgpu_vm_clear_bo(struct amdgpu_device
*adev
,
335 struct amdgpu_bo
*bo
)
337 struct amdgpu_ring
*ring
= adev
->vm_manager
.vm_pte_funcs_ring
;
338 struct fence
*fence
= NULL
;
339 struct amdgpu_ib
*ib
;
344 r
= amdgpu_bo_reserve(bo
, false);
348 r
= reservation_object_reserve_shared(bo
->tbo
.resv
);
352 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
354 goto error_unreserve
;
356 addr
= amdgpu_bo_gpu_offset(bo
);
357 entries
= amdgpu_bo_size(bo
) / 8;
359 ib
= kzalloc(sizeof(struct amdgpu_ib
), GFP_KERNEL
);
361 goto error_unreserve
;
363 r
= amdgpu_ib_get(ring
, NULL
, entries
* 2 + 64, ib
);
369 amdgpu_vm_update_pages(adev
, ib
, addr
, 0, entries
, 0, 0, 0);
370 amdgpu_vm_pad_ib(adev
, ib
);
371 WARN_ON(ib
->length_dw
> 64);
372 r
= amdgpu_sched_ib_submit_kernel_helper(adev
, ring
, ib
, 1,
374 AMDGPU_FENCE_OWNER_VM
,
377 amdgpu_bo_fence(bo
, fence
, true);
379 if (amdgpu_enable_scheduler
) {
380 amdgpu_bo_unreserve(bo
);
384 amdgpu_ib_free(adev
, ib
);
388 amdgpu_bo_unreserve(bo
);
393 * amdgpu_vm_map_gart - get the physical address of a gart page
395 * @adev: amdgpu_device pointer
396 * @addr: the unmapped addr
398 * Look up the physical address of the page that the pte resolves
400 * Returns the physical address of the page.
402 uint64_t amdgpu_vm_map_gart(struct amdgpu_device
*adev
, uint64_t addr
)
406 /* page table offset */
407 result
= adev
->gart
.pages_addr
[addr
>> PAGE_SHIFT
];
409 /* in case cpu page size != gpu page size*/
410 result
|= addr
& (~PAGE_MASK
);
416 * amdgpu_vm_update_pdes - make sure that page directory is valid
418 * @adev: amdgpu_device pointer
420 * @start: start of GPU address range
421 * @end: end of GPU address range
423 * Allocates new page tables if necessary
424 * and updates the page directory (cayman+).
425 * Returns 0 for success, error for failure.
427 * Global and local mutex must be locked!
429 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
430 struct amdgpu_vm
*vm
)
432 struct amdgpu_ring
*ring
= adev
->vm_manager
.vm_pte_funcs_ring
;
433 struct amdgpu_bo
*pd
= vm
->page_directory
;
434 uint64_t pd_addr
= amdgpu_bo_gpu_offset(pd
);
435 uint32_t incr
= AMDGPU_VM_PTE_COUNT
* 8;
436 uint64_t last_pde
= ~0, last_pt
= ~0;
437 unsigned count
= 0, pt_idx
, ndw
;
438 struct amdgpu_ib
*ib
;
439 struct fence
*fence
= NULL
;
446 /* assume the worst case */
447 ndw
+= vm
->max_pde_used
* 6;
449 /* update too big for an IB */
453 ib
= kzalloc(sizeof(struct amdgpu_ib
), GFP_KERNEL
);
457 r
= amdgpu_ib_get(ring
, NULL
, ndw
* 4, ib
);
462 /* walk over the address space and update the page directory */
463 for (pt_idx
= 0; pt_idx
<= vm
->max_pde_used
; ++pt_idx
) {
464 struct amdgpu_bo
*bo
= vm
->page_tables
[pt_idx
].bo
;
470 pt
= amdgpu_bo_gpu_offset(bo
);
471 if (vm
->page_tables
[pt_idx
].addr
== pt
)
473 vm
->page_tables
[pt_idx
].addr
= pt
;
475 pde
= pd_addr
+ pt_idx
* 8;
476 if (((last_pde
+ 8 * count
) != pde
) ||
477 ((last_pt
+ incr
* count
) != pt
)) {
480 amdgpu_vm_update_pages(adev
, ib
, last_pde
,
481 last_pt
, count
, incr
,
482 AMDGPU_PTE_VALID
, 0);
494 amdgpu_vm_update_pages(adev
, ib
, last_pde
, last_pt
, count
,
495 incr
, AMDGPU_PTE_VALID
, 0);
497 if (ib
->length_dw
!= 0) {
498 amdgpu_vm_pad_ib(adev
, ib
);
499 amdgpu_sync_resv(adev
, &ib
->sync
, pd
->tbo
.resv
, AMDGPU_FENCE_OWNER_VM
);
500 WARN_ON(ib
->length_dw
> ndw
);
501 r
= amdgpu_sched_ib_submit_kernel_helper(adev
, ring
, ib
, 1,
503 AMDGPU_FENCE_OWNER_VM
,
508 amdgpu_bo_fence(pd
, fence
, true);
509 fence_put(vm
->page_directory_fence
);
510 vm
->page_directory_fence
= fence_get(fence
);
514 if (!amdgpu_enable_scheduler
|| ib
->length_dw
== 0) {
515 amdgpu_ib_free(adev
, ib
);
522 amdgpu_ib_free(adev
, ib
);
528 * amdgpu_vm_frag_ptes - add fragment information to PTEs
530 * @adev: amdgpu_device pointer
531 * @ib: IB for the update
532 * @pe_start: first PTE to handle
533 * @pe_end: last PTE to handle
534 * @addr: addr those PTEs should point to
535 * @flags: hw mapping flags
536 * @gtt_flags: GTT hw mapping flags
538 * Global and local mutex must be locked!
540 static void amdgpu_vm_frag_ptes(struct amdgpu_device
*adev
,
541 struct amdgpu_ib
*ib
,
542 uint64_t pe_start
, uint64_t pe_end
,
543 uint64_t addr
, uint32_t flags
,
547 * The MC L1 TLB supports variable sized pages, based on a fragment
548 * field in the PTE. When this field is set to a non-zero value, page
549 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
550 * flags are considered valid for all PTEs within the fragment range
551 * and corresponding mappings are assumed to be physically contiguous.
553 * The L1 TLB can store a single PTE for the whole fragment,
554 * significantly increasing the space available for translation
555 * caching. This leads to large improvements in throughput when the
556 * TLB is under pressure.
558 * The L2 TLB distributes small and large fragments into two
559 * asymmetric partitions. The large fragment cache is significantly
560 * larger. Thus, we try to use large fragments wherever possible.
561 * Userspace can support this by aligning virtual base address and
562 * allocation size to the fragment size.
565 /* SI and newer are optimized for 64KB */
566 uint64_t frag_flags
= AMDGPU_PTE_FRAG_64KB
;
567 uint64_t frag_align
= 0x80;
569 uint64_t frag_start
= ALIGN(pe_start
, frag_align
);
570 uint64_t frag_end
= pe_end
& ~(frag_align
- 1);
574 /* system pages are non continuously */
575 if ((flags
& AMDGPU_PTE_SYSTEM
) || !(flags
& AMDGPU_PTE_VALID
) ||
576 (frag_start
>= frag_end
)) {
578 count
= (pe_end
- pe_start
) / 8;
579 amdgpu_vm_update_pages(adev
, ib
, pe_start
, addr
, count
,
580 AMDGPU_GPU_PAGE_SIZE
, flags
, gtt_flags
);
584 /* handle the 4K area at the beginning */
585 if (pe_start
!= frag_start
) {
586 count
= (frag_start
- pe_start
) / 8;
587 amdgpu_vm_update_pages(adev
, ib
, pe_start
, addr
, count
,
588 AMDGPU_GPU_PAGE_SIZE
, flags
, gtt_flags
);
589 addr
+= AMDGPU_GPU_PAGE_SIZE
* count
;
592 /* handle the area in the middle */
593 count
= (frag_end
- frag_start
) / 8;
594 amdgpu_vm_update_pages(adev
, ib
, frag_start
, addr
, count
,
595 AMDGPU_GPU_PAGE_SIZE
, flags
| frag_flags
,
598 /* handle the 4K area at the end */
599 if (frag_end
!= pe_end
) {
600 addr
+= AMDGPU_GPU_PAGE_SIZE
* count
;
601 count
= (pe_end
- frag_end
) / 8;
602 amdgpu_vm_update_pages(adev
, ib
, frag_end
, addr
, count
,
603 AMDGPU_GPU_PAGE_SIZE
, flags
, gtt_flags
);
608 * amdgpu_vm_update_ptes - make sure that page tables are valid
610 * @adev: amdgpu_device pointer
612 * @start: start of GPU address range
613 * @end: end of GPU address range
614 * @dst: destination address to map to
615 * @flags: mapping flags
617 * Update the page tables in the range @start - @end (cayman+).
619 * Global and local mutex must be locked!
621 static int amdgpu_vm_update_ptes(struct amdgpu_device
*adev
,
622 struct amdgpu_vm
*vm
,
623 struct amdgpu_ib
*ib
,
624 uint64_t start
, uint64_t end
,
625 uint64_t dst
, uint32_t flags
,
628 uint64_t mask
= AMDGPU_VM_PTE_COUNT
- 1;
629 uint64_t last_pte
= ~0, last_dst
= ~0;
630 void *owner
= AMDGPU_FENCE_OWNER_VM
;
634 /* sync to everything on unmapping */
635 if (!(flags
& AMDGPU_PTE_VALID
))
636 owner
= AMDGPU_FENCE_OWNER_UNDEFINED
;
638 /* walk over the address space and update the page tables */
639 for (addr
= start
; addr
< end
; ) {
640 uint64_t pt_idx
= addr
>> amdgpu_vm_block_size
;
641 struct amdgpu_bo
*pt
= vm
->page_tables
[pt_idx
].bo
;
646 amdgpu_sync_resv(adev
, &ib
->sync
, pt
->tbo
.resv
, owner
);
647 r
= reservation_object_reserve_shared(pt
->tbo
.resv
);
651 if ((addr
& ~mask
) == (end
& ~mask
))
654 nptes
= AMDGPU_VM_PTE_COUNT
- (addr
& mask
);
656 pte
= amdgpu_bo_gpu_offset(pt
);
657 pte
+= (addr
& mask
) * 8;
659 if ((last_pte
+ 8 * count
) != pte
) {
662 amdgpu_vm_frag_ptes(adev
, ib
, last_pte
,
663 last_pte
+ 8 * count
,
676 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
;
680 amdgpu_vm_frag_ptes(adev
, ib
, last_pte
,
681 last_pte
+ 8 * count
,
682 last_dst
, flags
, gtt_flags
);
689 * amdgpu_vm_fence_pts - fence page tables after an update
692 * @start: start of GPU address range
693 * @end: end of GPU address range
694 * @fence: fence to use
696 * Fence the page tables in the range @start - @end (cayman+).
698 * Global and local mutex must be locked!
700 static void amdgpu_vm_fence_pts(struct amdgpu_vm
*vm
,
701 uint64_t start
, uint64_t end
,
706 start
>>= amdgpu_vm_block_size
;
707 end
>>= amdgpu_vm_block_size
;
709 for (i
= start
; i
<= end
; ++i
)
710 amdgpu_bo_fence(vm
->page_tables
[i
].bo
, fence
, true);
714 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
716 * @adev: amdgpu_device pointer
718 * @mapping: mapped range and flags to use for the update
719 * @addr: addr to set the area to
720 * @gtt_flags: flags as they are used for GTT
721 * @fence: optional resulting fence
723 * Fill in the page table entries for @mapping.
724 * Returns 0 for success, -EINVAL for failure.
726 * Object have to be reserved and mutex must be locked!
728 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device
*adev
,
729 struct amdgpu_vm
*vm
,
730 struct amdgpu_bo_va_mapping
*mapping
,
731 uint64_t addr
, uint32_t gtt_flags
,
732 struct fence
**fence
)
734 struct amdgpu_ring
*ring
= adev
->vm_manager
.vm_pte_funcs_ring
;
735 unsigned nptes
, ncmds
, ndw
;
736 uint32_t flags
= gtt_flags
;
737 struct amdgpu_ib
*ib
;
738 struct fence
*f
= NULL
;
741 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
742 * but in case of something, we filter the flags in first place
744 if (!(mapping
->flags
& AMDGPU_PTE_READABLE
))
745 flags
&= ~AMDGPU_PTE_READABLE
;
746 if (!(mapping
->flags
& AMDGPU_PTE_WRITEABLE
))
747 flags
&= ~AMDGPU_PTE_WRITEABLE
;
749 trace_amdgpu_vm_bo_update(mapping
);
751 nptes
= mapping
->it
.last
- mapping
->it
.start
+ 1;
754 * reserve space for one command every (1 << BLOCK_SIZE)
755 * entries or 2k dwords (whatever is smaller)
757 ncmds
= (nptes
>> min(amdgpu_vm_block_size
, 11)) + 1;
762 if ((flags
& AMDGPU_PTE_SYSTEM
) && (flags
== gtt_flags
)) {
763 /* only copy commands needed */
766 } else if (flags
& AMDGPU_PTE_SYSTEM
) {
767 /* header for write data commands */
770 /* body of write data command */
774 /* set page commands needed */
777 /* two extra commands for begin/end of fragment */
781 /* update too big for an IB */
785 ib
= kzalloc(sizeof(struct amdgpu_ib
), GFP_KERNEL
);
789 r
= amdgpu_ib_get(ring
, NULL
, ndw
* 4, ib
);
797 r
= amdgpu_vm_update_ptes(adev
, vm
, ib
, mapping
->it
.start
,
798 mapping
->it
.last
+ 1, addr
+ mapping
->offset
,
802 amdgpu_ib_free(adev
, ib
);
807 amdgpu_vm_pad_ib(adev
, ib
);
808 WARN_ON(ib
->length_dw
> ndw
);
809 r
= amdgpu_sched_ib_submit_kernel_helper(adev
, ring
, ib
, 1,
811 AMDGPU_FENCE_OWNER_VM
,
816 amdgpu_vm_fence_pts(vm
, mapping
->it
.start
,
817 mapping
->it
.last
+ 1, f
);
820 *fence
= fence_get(f
);
823 if (!amdgpu_enable_scheduler
) {
824 amdgpu_ib_free(adev
, ib
);
830 amdgpu_ib_free(adev
, ib
);
836 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
838 * @adev: amdgpu_device pointer
839 * @bo_va: requested BO and VM object
842 * Fill in the page table entries for @bo_va.
843 * Returns 0 for success, -EINVAL for failure.
845 * Object have to be reserved and mutex must be locked!
847 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
848 struct amdgpu_bo_va
*bo_va
,
849 struct ttm_mem_reg
*mem
)
851 struct amdgpu_vm
*vm
= bo_va
->vm
;
852 struct amdgpu_bo_va_mapping
*mapping
;
858 addr
= mem
->start
<< PAGE_SHIFT
;
859 if (mem
->mem_type
!= TTM_PL_TT
)
860 addr
+= adev
->vm_manager
.vram_base_offset
;
865 flags
= amdgpu_ttm_tt_pte_flags(adev
, bo_va
->bo
->tbo
.ttm
, mem
);
867 spin_lock(&vm
->status_lock
);
868 if (!list_empty(&bo_va
->vm_status
))
869 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
870 spin_unlock(&vm
->status_lock
);
872 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
873 r
= amdgpu_vm_bo_update_mapping(adev
, vm
, mapping
, addr
,
874 flags
, &bo_va
->last_pt_update
);
879 spin_lock(&vm
->status_lock
);
880 list_splice_init(&bo_va
->invalids
, &bo_va
->valids
);
881 list_del_init(&bo_va
->vm_status
);
883 list_add(&bo_va
->vm_status
, &vm
->cleared
);
884 spin_unlock(&vm
->status_lock
);
890 * amdgpu_vm_clear_freed - clear freed BOs in the PT
892 * @adev: amdgpu_device pointer
895 * Make sure all freed BOs are cleared in the PT.
896 * Returns 0 for success.
898 * PTs have to be reserved and mutex must be locked!
900 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
901 struct amdgpu_vm
*vm
)
903 struct amdgpu_bo_va_mapping
*mapping
;
906 while (!list_empty(&vm
->freed
)) {
907 mapping
= list_first_entry(&vm
->freed
,
908 struct amdgpu_bo_va_mapping
, list
);
909 list_del(&mapping
->list
);
911 r
= amdgpu_vm_bo_update_mapping(adev
, vm
, mapping
, 0, 0, NULL
);
922 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
924 * @adev: amdgpu_device pointer
927 * Make sure all invalidated BOs are cleared in the PT.
928 * Returns 0 for success.
930 * PTs have to be reserved and mutex must be locked!
932 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
,
933 struct amdgpu_vm
*vm
, struct amdgpu_sync
*sync
)
935 struct amdgpu_bo_va
*bo_va
= NULL
;
938 spin_lock(&vm
->status_lock
);
939 while (!list_empty(&vm
->invalidated
)) {
940 bo_va
= list_first_entry(&vm
->invalidated
,
941 struct amdgpu_bo_va
, vm_status
);
942 spin_unlock(&vm
->status_lock
);
944 r
= amdgpu_vm_bo_update(adev
, bo_va
, NULL
);
948 spin_lock(&vm
->status_lock
);
950 spin_unlock(&vm
->status_lock
);
953 r
= amdgpu_sync_fence(adev
, sync
, bo_va
->last_pt_update
);
959 * amdgpu_vm_bo_add - add a bo to a specific vm
961 * @adev: amdgpu_device pointer
963 * @bo: amdgpu buffer object
965 * Add @bo into the requested vm (cayman+).
966 * Add @bo to the list of bos associated with the vm
967 * Returns newly added bo_va or NULL for failure
969 * Object has to be reserved!
971 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
972 struct amdgpu_vm
*vm
,
973 struct amdgpu_bo
*bo
)
975 struct amdgpu_bo_va
*bo_va
;
977 bo_va
= kzalloc(sizeof(struct amdgpu_bo_va
), GFP_KERNEL
);
983 bo_va
->ref_count
= 1;
984 INIT_LIST_HEAD(&bo_va
->bo_list
);
985 INIT_LIST_HEAD(&bo_va
->valids
);
986 INIT_LIST_HEAD(&bo_va
->invalids
);
987 INIT_LIST_HEAD(&bo_va
->vm_status
);
989 mutex_lock(&vm
->mutex
);
990 list_add_tail(&bo_va
->bo_list
, &bo
->va
);
991 mutex_unlock(&vm
->mutex
);
997 * amdgpu_vm_bo_map - map bo inside a vm
999 * @adev: amdgpu_device pointer
1000 * @bo_va: bo_va to store the address
1001 * @saddr: where to map the BO
1002 * @offset: requested offset in the BO
1003 * @flags: attributes of pages (read/write/valid/etc.)
1005 * Add a mapping of the BO at the specefied addr into the VM.
1006 * Returns 0 for success, error for failure.
1008 * Object has to be reserved and gets unreserved by this function!
1010 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
1011 struct amdgpu_bo_va
*bo_va
,
1012 uint64_t saddr
, uint64_t offset
,
1013 uint64_t size
, uint32_t flags
)
1015 struct amdgpu_bo_va_mapping
*mapping
;
1016 struct amdgpu_vm
*vm
= bo_va
->vm
;
1017 struct interval_tree_node
*it
;
1018 unsigned last_pfn
, pt_idx
;
1022 /* validate the parameters */
1023 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
1024 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
) {
1025 amdgpu_bo_unreserve(bo_va
->bo
);
1029 /* make sure object fit at this offset */
1030 eaddr
= saddr
+ size
;
1031 if ((saddr
>= eaddr
) || (offset
+ size
> amdgpu_bo_size(bo_va
->bo
))) {
1032 amdgpu_bo_unreserve(bo_va
->bo
);
1036 last_pfn
= eaddr
/ AMDGPU_GPU_PAGE_SIZE
;
1037 if (last_pfn
> adev
->vm_manager
.max_pfn
) {
1038 dev_err(adev
->dev
, "va above limit (0x%08X > 0x%08X)\n",
1039 last_pfn
, adev
->vm_manager
.max_pfn
);
1040 amdgpu_bo_unreserve(bo_va
->bo
);
1044 mutex_lock(&vm
->mutex
);
1046 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1047 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
1049 it
= interval_tree_iter_first(&vm
->va
, saddr
, eaddr
- 1);
1051 struct amdgpu_bo_va_mapping
*tmp
;
1052 tmp
= container_of(it
, struct amdgpu_bo_va_mapping
, it
);
1053 /* bo and tmp overlap, invalid addr */
1054 dev_err(adev
->dev
, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1055 "0x%010lx-0x%010lx\n", bo_va
->bo
, saddr
, eaddr
,
1056 tmp
->it
.start
, tmp
->it
.last
+ 1);
1057 amdgpu_bo_unreserve(bo_va
->bo
);
1062 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
1064 amdgpu_bo_unreserve(bo_va
->bo
);
1069 INIT_LIST_HEAD(&mapping
->list
);
1070 mapping
->it
.start
= saddr
;
1071 mapping
->it
.last
= eaddr
- 1;
1072 mapping
->offset
= offset
;
1073 mapping
->flags
= flags
;
1075 list_add(&mapping
->list
, &bo_va
->invalids
);
1076 interval_tree_insert(&mapping
->it
, &vm
->va
);
1077 trace_amdgpu_vm_bo_map(bo_va
, mapping
);
1079 /* Make sure the page tables are allocated */
1080 saddr
>>= amdgpu_vm_block_size
;
1081 eaddr
>>= amdgpu_vm_block_size
;
1083 BUG_ON(eaddr
>= amdgpu_vm_num_pdes(adev
));
1085 if (eaddr
> vm
->max_pde_used
)
1086 vm
->max_pde_used
= eaddr
;
1088 amdgpu_bo_unreserve(bo_va
->bo
);
1090 /* walk over the address space and allocate the page tables */
1091 for (pt_idx
= saddr
; pt_idx
<= eaddr
; ++pt_idx
) {
1092 struct amdgpu_bo
*pt
;
1094 if (vm
->page_tables
[pt_idx
].bo
)
1097 /* drop mutex to allocate and clear page table */
1098 mutex_unlock(&vm
->mutex
);
1100 r
= amdgpu_bo_create(adev
, AMDGPU_VM_PTE_COUNT
* 8,
1101 AMDGPU_GPU_PAGE_SIZE
, true,
1102 AMDGPU_GEM_DOMAIN_VRAM
,
1103 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
,
1108 r
= amdgpu_vm_clear_bo(adev
, pt
);
1110 amdgpu_bo_unref(&pt
);
1114 /* aquire mutex again */
1115 mutex_lock(&vm
->mutex
);
1116 if (vm
->page_tables
[pt_idx
].bo
) {
1117 /* someone else allocated the pt in the meantime */
1118 mutex_unlock(&vm
->mutex
);
1119 amdgpu_bo_unref(&pt
);
1120 mutex_lock(&vm
->mutex
);
1124 vm
->page_tables
[pt_idx
].addr
= 0;
1125 vm
->page_tables
[pt_idx
].bo
= pt
;
1128 mutex_unlock(&vm
->mutex
);
1132 mutex_lock(&vm
->mutex
);
1133 list_del(&mapping
->list
);
1134 interval_tree_remove(&mapping
->it
, &vm
->va
);
1135 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1139 mutex_unlock(&vm
->mutex
);
1144 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1146 * @adev: amdgpu_device pointer
1147 * @bo_va: bo_va to remove the address from
1148 * @saddr: where to the BO is mapped
1150 * Remove a mapping of the BO at the specefied addr from the VM.
1151 * Returns 0 for success, error for failure.
1153 * Object has to be reserved and gets unreserved by this function!
1155 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
1156 struct amdgpu_bo_va
*bo_va
,
1159 struct amdgpu_bo_va_mapping
*mapping
;
1160 struct amdgpu_vm
*vm
= bo_va
->vm
;
1163 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1165 list_for_each_entry(mapping
, &bo_va
->valids
, list
) {
1166 if (mapping
->it
.start
== saddr
)
1170 if (&mapping
->list
== &bo_va
->valids
) {
1173 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1174 if (mapping
->it
.start
== saddr
)
1178 if (&mapping
->list
== &bo_va
->invalids
) {
1179 amdgpu_bo_unreserve(bo_va
->bo
);
1184 mutex_lock(&vm
->mutex
);
1185 list_del(&mapping
->list
);
1186 interval_tree_remove(&mapping
->it
, &vm
->va
);
1187 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1190 list_add(&mapping
->list
, &vm
->freed
);
1193 mutex_unlock(&vm
->mutex
);
1194 amdgpu_bo_unreserve(bo_va
->bo
);
1200 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1202 * @adev: amdgpu_device pointer
1203 * @bo_va: requested bo_va
1205 * Remove @bo_va->bo from the requested vm (cayman+).
1207 * Object have to be reserved!
1209 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
1210 struct amdgpu_bo_va
*bo_va
)
1212 struct amdgpu_bo_va_mapping
*mapping
, *next
;
1213 struct amdgpu_vm
*vm
= bo_va
->vm
;
1215 list_del(&bo_va
->bo_list
);
1217 mutex_lock(&vm
->mutex
);
1219 spin_lock(&vm
->status_lock
);
1220 list_del(&bo_va
->vm_status
);
1221 spin_unlock(&vm
->status_lock
);
1223 list_for_each_entry_safe(mapping
, next
, &bo_va
->valids
, list
) {
1224 list_del(&mapping
->list
);
1225 interval_tree_remove(&mapping
->it
, &vm
->va
);
1226 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1227 list_add(&mapping
->list
, &vm
->freed
);
1229 list_for_each_entry_safe(mapping
, next
, &bo_va
->invalids
, list
) {
1230 list_del(&mapping
->list
);
1231 interval_tree_remove(&mapping
->it
, &vm
->va
);
1235 fence_put(bo_va
->last_pt_update
);
1238 mutex_unlock(&vm
->mutex
);
1242 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1244 * @adev: amdgpu_device pointer
1246 * @bo: amdgpu buffer object
1248 * Mark @bo as invalid (cayman+).
1250 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
1251 struct amdgpu_bo
*bo
)
1253 struct amdgpu_bo_va
*bo_va
;
1255 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
1256 spin_lock(&bo_va
->vm
->status_lock
);
1257 if (list_empty(&bo_va
->vm_status
))
1258 list_add(&bo_va
->vm_status
, &bo_va
->vm
->invalidated
);
1259 spin_unlock(&bo_va
->vm
->status_lock
);
1264 * amdgpu_vm_init - initialize a vm instance
1266 * @adev: amdgpu_device pointer
1269 * Init @vm fields (cayman+).
1271 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1273 const unsigned align
= min(AMDGPU_VM_PTB_ALIGN_SIZE
,
1274 AMDGPU_VM_PTE_COUNT
* 8);
1275 unsigned pd_size
, pd_entries
, pts_size
;
1278 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
1280 vm
->ids
[i
].flushed_updates
= NULL
;
1281 vm
->ids
[i
].last_id_use
= NULL
;
1283 mutex_init(&vm
->mutex
);
1285 spin_lock_init(&vm
->status_lock
);
1286 INIT_LIST_HEAD(&vm
->invalidated
);
1287 INIT_LIST_HEAD(&vm
->cleared
);
1288 INIT_LIST_HEAD(&vm
->freed
);
1290 pd_size
= amdgpu_vm_directory_size(adev
);
1291 pd_entries
= amdgpu_vm_num_pdes(adev
);
1293 /* allocate page table array */
1294 pts_size
= pd_entries
* sizeof(struct amdgpu_vm_pt
);
1295 vm
->page_tables
= kzalloc(pts_size
, GFP_KERNEL
);
1296 if (vm
->page_tables
== NULL
) {
1297 DRM_ERROR("Cannot allocate memory for page table array\n");
1301 vm
->page_directory_fence
= NULL
;
1303 r
= amdgpu_bo_create(adev
, pd_size
, align
, true,
1304 AMDGPU_GEM_DOMAIN_VRAM
,
1305 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
,
1306 NULL
, &vm
->page_directory
);
1310 r
= amdgpu_vm_clear_bo(adev
, vm
->page_directory
);
1312 amdgpu_bo_unref(&vm
->page_directory
);
1313 vm
->page_directory
= NULL
;
1321 * amdgpu_vm_fini - tear down a vm instance
1323 * @adev: amdgpu_device pointer
1326 * Tear down @vm (cayman+).
1327 * Unbind the VM and remove all bos from the vm bo list
1329 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1331 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
1334 if (!RB_EMPTY_ROOT(&vm
->va
)) {
1335 dev_err(adev
->dev
, "still active bo inside vm\n");
1337 rbtree_postorder_for_each_entry_safe(mapping
, tmp
, &vm
->va
, it
.rb
) {
1338 list_del(&mapping
->list
);
1339 interval_tree_remove(&mapping
->it
, &vm
->va
);
1342 list_for_each_entry_safe(mapping
, tmp
, &vm
->freed
, list
) {
1343 list_del(&mapping
->list
);
1347 for (i
= 0; i
< amdgpu_vm_num_pdes(adev
); i
++)
1348 amdgpu_bo_unref(&vm
->page_tables
[i
].bo
);
1349 kfree(vm
->page_tables
);
1351 amdgpu_bo_unref(&vm
->page_directory
);
1352 fence_put(vm
->page_directory_fence
);
1354 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
1355 fence_put(vm
->ids
[i
].flushed_updates
);
1356 amdgpu_fence_unref(&vm
->ids
[i
].last_id_use
);
1359 mutex_destroy(&vm
->mutex
);