2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/amdgpu_drm.h>
30 #include "amdgpu_connectors.h"
32 #include "atombios_encoders.h"
33 #include "atombios_dp.h"
34 #include <linux/backlight.h>
35 #include "bif/bif_4_1_d.h"
38 amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device
*adev
)
43 bios_2_scratch
= RREG32(mmBIOS_SCRATCH_2
);
45 backlight_level
= ((bios_2_scratch
& ATOM_S2_CURRENT_BL_LEVEL_MASK
) >>
46 ATOM_S2_CURRENT_BL_LEVEL_SHIFT
);
48 return backlight_level
;
52 amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device
*adev
,
57 bios_2_scratch
= RREG32(mmBIOS_SCRATCH_2
);
59 bios_2_scratch
&= ~ATOM_S2_CURRENT_BL_LEVEL_MASK
;
60 bios_2_scratch
|= ((backlight_level
<< ATOM_S2_CURRENT_BL_LEVEL_SHIFT
) &
61 ATOM_S2_CURRENT_BL_LEVEL_MASK
);
63 WREG32(mmBIOS_SCRATCH_2
, bios_2_scratch
);
67 amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder
*amdgpu_encoder
)
69 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
70 struct amdgpu_device
*adev
= dev
->dev_private
;
72 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
75 return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev
);
79 amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder
*amdgpu_encoder
,
82 struct drm_encoder
*encoder
= &amdgpu_encoder
->base
;
83 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
84 struct amdgpu_device
*adev
= dev
->dev_private
;
85 struct amdgpu_encoder_atom_dig
*dig
;
87 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
90 if ((amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) &&
91 amdgpu_encoder
->enc_priv
) {
92 dig
= amdgpu_encoder
->enc_priv
;
93 dig
->backlight_level
= level
;
94 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev
, dig
->backlight_level
);
96 switch (amdgpu_encoder
->encoder_id
) {
97 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
98 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
99 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
101 if (dig
->backlight_level
== 0)
102 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
103 ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
105 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
106 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
, 0, 0);
107 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
108 ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
117 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
119 static u8
amdgpu_atombios_encoder_backlight_level(struct backlight_device
*bd
)
123 /* Convert brightness to hardware level */
124 if (bd
->props
.brightness
< 0)
126 else if (bd
->props
.brightness
> AMDGPU_MAX_BL_LEVEL
)
127 level
= AMDGPU_MAX_BL_LEVEL
;
129 level
= bd
->props
.brightness
;
134 static int amdgpu_atombios_encoder_update_backlight_status(struct backlight_device
*bd
)
136 struct amdgpu_backlight_privdata
*pdata
= bl_get_data(bd
);
137 struct amdgpu_encoder
*amdgpu_encoder
= pdata
->encoder
;
139 amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder
,
140 amdgpu_atombios_encoder_backlight_level(bd
));
146 amdgpu_atombios_encoder_get_backlight_brightness(struct backlight_device
*bd
)
148 struct amdgpu_backlight_privdata
*pdata
= bl_get_data(bd
);
149 struct amdgpu_encoder
*amdgpu_encoder
= pdata
->encoder
;
150 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
151 struct amdgpu_device
*adev
= dev
->dev_private
;
153 return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev
);
156 static const struct backlight_ops amdgpu_atombios_encoder_backlight_ops
= {
157 .get_brightness
= amdgpu_atombios_encoder_get_backlight_brightness
,
158 .update_status
= amdgpu_atombios_encoder_update_backlight_status
,
161 void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder
*amdgpu_encoder
,
162 struct drm_connector
*drm_connector
)
164 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
165 struct amdgpu_device
*adev
= dev
->dev_private
;
166 struct backlight_device
*bd
;
167 struct backlight_properties props
;
168 struct amdgpu_backlight_privdata
*pdata
;
169 struct amdgpu_encoder_atom_dig
*dig
;
173 /* Mac laptops with multiple GPUs use the gmux driver for backlight
174 * so don't register a backlight device
176 if ((adev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
177 (adev
->pdev
->device
== 0x6741))
180 if (!amdgpu_encoder
->enc_priv
)
183 if (!adev
->is_atom_bios
)
186 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
189 pdata
= kmalloc(sizeof(struct amdgpu_backlight_privdata
), GFP_KERNEL
);
191 DRM_ERROR("Memory allocation failed\n");
195 memset(&props
, 0, sizeof(props
));
196 props
.max_brightness
= AMDGPU_MAX_BL_LEVEL
;
197 props
.type
= BACKLIGHT_RAW
;
198 snprintf(bl_name
, sizeof(bl_name
),
199 "amdgpu_bl%d", dev
->primary
->index
);
200 bd
= backlight_device_register(bl_name
, drm_connector
->kdev
,
201 pdata
, &amdgpu_atombios_encoder_backlight_ops
, &props
);
203 DRM_ERROR("Backlight registration failed\n");
207 pdata
->encoder
= amdgpu_encoder
;
209 backlight_level
= amdgpu_atombios_encoder_get_backlight_level_from_reg(adev
);
211 dig
= amdgpu_encoder
->enc_priv
;
214 bd
->props
.brightness
= amdgpu_atombios_encoder_get_backlight_brightness(bd
);
215 bd
->props
.power
= FB_BLANK_UNBLANK
;
216 backlight_update_status(bd
);
218 DRM_INFO("amdgpu atom DIG backlight initialized\n");
228 amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder
*amdgpu_encoder
)
230 struct drm_device
*dev
= amdgpu_encoder
->base
.dev
;
231 struct amdgpu_device
*adev
= dev
->dev_private
;
232 struct backlight_device
*bd
= NULL
;
233 struct amdgpu_encoder_atom_dig
*dig
;
235 if (!amdgpu_encoder
->enc_priv
)
238 if (!adev
->is_atom_bios
)
241 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
))
244 dig
= amdgpu_encoder
->enc_priv
;
249 struct amdgpu_legacy_backlight_privdata
*pdata
;
251 pdata
= bl_get_data(bd
);
252 backlight_device_unregister(bd
);
255 DRM_INFO("amdgpu atom LVDS backlight unloaded\n");
259 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
261 void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder
*encoder
)
265 void amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder
*encoder
)
271 bool amdgpu_atombios_encoder_is_digital(struct drm_encoder
*encoder
)
273 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
274 switch (amdgpu_encoder
->encoder_id
) {
275 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
276 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
277 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
278 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
279 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
286 bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder
*encoder
,
287 const struct drm_display_mode
*mode
,
288 struct drm_display_mode
*adjusted_mode
)
290 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
292 /* set the active encoder to connector routing */
293 amdgpu_encoder_set_active_device(encoder
);
294 drm_mode_set_crtcinfo(adjusted_mode
, 0);
297 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
298 && (mode
->crtc_vsync_start
< (mode
->crtc_vdisplay
+ 2)))
299 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ 2;
301 /* vertical FP must be at least 1 */
302 if (mode
->crtc_vsync_start
== mode
->crtc_vdisplay
)
303 adjusted_mode
->crtc_vsync_start
++;
305 /* get the native mode for scaling */
306 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_LCD_SUPPORT
))
307 amdgpu_panel_mode_fixup(encoder
, adjusted_mode
);
308 else if (amdgpu_encoder
->rmx_type
!= RMX_OFF
)
309 amdgpu_panel_mode_fixup(encoder
, adjusted_mode
);
311 if ((amdgpu_encoder
->active_device
& (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
312 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
)) {
313 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
314 amdgpu_atombios_dp_set_link_config(connector
, adjusted_mode
);
321 amdgpu_atombios_encoder_setup_dac(struct drm_encoder
*encoder
, int action
)
323 struct drm_device
*dev
= encoder
->dev
;
324 struct amdgpu_device
*adev
= dev
->dev_private
;
325 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
326 DAC_ENCODER_CONTROL_PS_ALLOCATION args
;
329 memset(&args
, 0, sizeof(args
));
331 switch (amdgpu_encoder
->encoder_id
) {
332 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
333 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
334 index
= GetIndexIntoMasterTable(COMMAND
, DAC1EncoderControl
);
336 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
337 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
338 index
= GetIndexIntoMasterTable(COMMAND
, DAC2EncoderControl
);
342 args
.ucAction
= action
;
343 args
.ucDacStandard
= ATOM_DAC1_PS2
;
344 args
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
346 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
350 static u8
amdgpu_atombios_encoder_get_bpc(struct drm_encoder
*encoder
)
355 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
356 bpc
= amdgpu_crtc
->bpc
;
361 return PANEL_BPC_UNDEFINE
;
363 return PANEL_6BIT_PER_COLOR
;
366 return PANEL_8BIT_PER_COLOR
;
368 return PANEL_10BIT_PER_COLOR
;
370 return PANEL_12BIT_PER_COLOR
;
372 return PANEL_16BIT_PER_COLOR
;
376 union dvo_encoder_control
{
377 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds
;
378 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo
;
379 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3
;
380 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4
;
384 amdgpu_atombios_encoder_setup_dvo(struct drm_encoder
*encoder
, int action
)
386 struct drm_device
*dev
= encoder
->dev
;
387 struct amdgpu_device
*adev
= dev
->dev_private
;
388 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
389 union dvo_encoder_control args
;
390 int index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
393 memset(&args
, 0, sizeof(args
));
395 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
403 args
.ext_tmds
.sXTmdsEncoder
.ucEnable
= action
;
405 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
406 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
408 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
412 args
.dvo
.sDVOEncoder
.ucAction
= action
;
413 args
.dvo
.sDVOEncoder
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
414 /* DFP1, CRT1, TV1 depending on the type of port */
415 args
.dvo
.sDVOEncoder
.ucDeviceType
= ATOM_DEVICE_DFP1_INDEX
;
417 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
418 args
.dvo
.sDVOEncoder
.usDevAttr
.sDigAttrib
.ucAttribute
|= PANEL_ENCODER_MISC_DUAL
;
422 args
.dvo_v3
.ucAction
= action
;
423 args
.dvo_v3
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
424 args
.dvo_v3
.ucDVOConfig
= 0; /* XXX */
428 args
.dvo_v4
.ucAction
= action
;
429 args
.dvo_v4
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
430 args
.dvo_v4
.ucDVOConfig
= 0; /* XXX */
431 args
.dvo_v4
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
434 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
439 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
443 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
446 int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder
*encoder
)
448 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
449 struct drm_connector
*connector
;
450 struct amdgpu_connector
*amdgpu_connector
;
451 struct amdgpu_connector_atom_dig
*dig_connector
;
453 /* dp bridges are always DP */
454 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
)
455 return ATOM_ENCODER_MODE_DP
;
457 /* DVO is always DVO */
458 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DVO1
) ||
459 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
))
460 return ATOM_ENCODER_MODE_DVO
;
462 connector
= amdgpu_get_connector_for_encoder(encoder
);
463 /* if we don't have an active device yet, just use one of
464 * the connectors tied to the encoder.
467 connector
= amdgpu_get_connector_for_encoder_init(encoder
);
468 amdgpu_connector
= to_amdgpu_connector(connector
);
470 switch (connector
->connector_type
) {
471 case DRM_MODE_CONNECTOR_DVII
:
472 case DRM_MODE_CONNECTOR_HDMIB
: /* HDMI-B is basically DL-DVI; analog works fine */
473 if (amdgpu_audio
!= 0) {
474 if (amdgpu_connector
->use_digital
&&
475 (amdgpu_connector
->audio
== AMDGPU_AUDIO_ENABLE
))
476 return ATOM_ENCODER_MODE_HDMI
;
477 else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector
)) &&
478 (amdgpu_connector
->audio
== AMDGPU_AUDIO_AUTO
))
479 return ATOM_ENCODER_MODE_HDMI
;
480 else if (amdgpu_connector
->use_digital
)
481 return ATOM_ENCODER_MODE_DVI
;
483 return ATOM_ENCODER_MODE_CRT
;
484 } else if (amdgpu_connector
->use_digital
) {
485 return ATOM_ENCODER_MODE_DVI
;
487 return ATOM_ENCODER_MODE_CRT
;
490 case DRM_MODE_CONNECTOR_DVID
:
491 case DRM_MODE_CONNECTOR_HDMIA
:
493 if (amdgpu_audio
!= 0) {
494 if (amdgpu_connector
->audio
== AMDGPU_AUDIO_ENABLE
)
495 return ATOM_ENCODER_MODE_HDMI
;
496 else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector
)) &&
497 (amdgpu_connector
->audio
== AMDGPU_AUDIO_AUTO
))
498 return ATOM_ENCODER_MODE_HDMI
;
500 return ATOM_ENCODER_MODE_DVI
;
502 return ATOM_ENCODER_MODE_DVI
;
505 case DRM_MODE_CONNECTOR_LVDS
:
506 return ATOM_ENCODER_MODE_LVDS
;
508 case DRM_MODE_CONNECTOR_DisplayPort
:
509 dig_connector
= amdgpu_connector
->con_priv
;
510 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
511 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
)) {
512 return ATOM_ENCODER_MODE_DP
;
513 } else if (amdgpu_audio
!= 0) {
514 if (amdgpu_connector
->audio
== AMDGPU_AUDIO_ENABLE
)
515 return ATOM_ENCODER_MODE_HDMI
;
516 else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector
)) &&
517 (amdgpu_connector
->audio
== AMDGPU_AUDIO_AUTO
))
518 return ATOM_ENCODER_MODE_HDMI
;
520 return ATOM_ENCODER_MODE_DVI
;
522 return ATOM_ENCODER_MODE_DVI
;
525 case DRM_MODE_CONNECTOR_eDP
:
526 return ATOM_ENCODER_MODE_DP
;
527 case DRM_MODE_CONNECTOR_DVIA
:
528 case DRM_MODE_CONNECTOR_VGA
:
529 return ATOM_ENCODER_MODE_CRT
;
531 case DRM_MODE_CONNECTOR_Composite
:
532 case DRM_MODE_CONNECTOR_SVIDEO
:
533 case DRM_MODE_CONNECTOR_9PinDIN
:
535 return ATOM_ENCODER_MODE_TV
;
536 /*return ATOM_ENCODER_MODE_CV;*/
542 * DIG Encoder/Transmitter Setup
545 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
546 * Supports up to 6 digital outputs
547 * - 6 DIG encoder blocks.
548 * - DIG to PHY mapping is hardcoded
549 * DIG1 drives UNIPHY0 link A, A+B
550 * DIG2 drives UNIPHY0 link B
551 * DIG3 drives UNIPHY1 link A, A+B
552 * DIG4 drives UNIPHY1 link B
553 * DIG5 drives UNIPHY2 link A, A+B
554 * DIG6 drives UNIPHY2 link B
557 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
559 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
560 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
561 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
562 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
565 union dig_encoder_control
{
566 DIG_ENCODER_CONTROL_PS_ALLOCATION v1
;
567 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2
;
568 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3
;
569 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4
;
570 DIG_ENCODER_CONTROL_PARAMETERS_V5 v5
;
574 amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder
*encoder
,
575 int action
, int panel_mode
)
577 struct drm_device
*dev
= encoder
->dev
;
578 struct amdgpu_device
*adev
= dev
->dev_private
;
579 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
580 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
581 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
582 union dig_encoder_control args
;
583 int index
= GetIndexIntoMasterTable(COMMAND
, DIGxEncoderControl
);
586 int dp_lane_count
= 0;
587 int hpd_id
= AMDGPU_HPD_NONE
;
590 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
591 struct amdgpu_connector_atom_dig
*dig_connector
=
592 amdgpu_connector
->con_priv
;
594 dp_clock
= dig_connector
->dp_clock
;
595 dp_lane_count
= dig_connector
->dp_lane_count
;
596 hpd_id
= amdgpu_connector
->hpd
.hpd
;
599 /* no dig encoder assigned */
600 if (dig
->dig_encoder
== -1)
603 memset(&args
, 0, sizeof(args
));
605 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
612 args
.v1
.ucAction
= action
;
613 args
.v1
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
614 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
615 args
.v3
.ucPanelMode
= panel_mode
;
617 args
.v1
.ucEncoderMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
619 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
))
620 args
.v1
.ucLaneNum
= dp_lane_count
;
621 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
622 args
.v1
.ucLaneNum
= 8;
624 args
.v1
.ucLaneNum
= 4;
626 if (ENCODER_MODE_IS_DP(args
.v1
.ucEncoderMode
) && (dp_clock
== 270000))
627 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
628 switch (amdgpu_encoder
->encoder_id
) {
629 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
630 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
;
632 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
633 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
634 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
;
636 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
637 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
;
641 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKB
;
643 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA
;
647 args
.v3
.ucAction
= action
;
648 args
.v3
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
649 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
650 args
.v3
.ucPanelMode
= panel_mode
;
652 args
.v3
.ucEncoderMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
654 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
))
655 args
.v3
.ucLaneNum
= dp_lane_count
;
656 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
657 args
.v3
.ucLaneNum
= 8;
659 args
.v3
.ucLaneNum
= 4;
661 if (ENCODER_MODE_IS_DP(args
.v3
.ucEncoderMode
) && (dp_clock
== 270000))
662 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
663 args
.v3
.acConfig
.ucDigSel
= dig
->dig_encoder
;
664 args
.v3
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
667 args
.v4
.ucAction
= action
;
668 args
.v4
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
669 if (action
== ATOM_ENCODER_CMD_SETUP_PANEL_MODE
)
670 args
.v4
.ucPanelMode
= panel_mode
;
672 args
.v4
.ucEncoderMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
674 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
))
675 args
.v4
.ucLaneNum
= dp_lane_count
;
676 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
677 args
.v4
.ucLaneNum
= 8;
679 args
.v4
.ucLaneNum
= 4;
681 if (ENCODER_MODE_IS_DP(args
.v4
.ucEncoderMode
)) {
682 if (dp_clock
== 540000)
683 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ
;
684 else if (dp_clock
== 324000)
685 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ
;
686 else if (dp_clock
== 270000)
687 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ
;
689 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ
;
691 args
.v4
.acConfig
.ucDigSel
= dig
->dig_encoder
;
692 args
.v4
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
693 if (hpd_id
== AMDGPU_HPD_NONE
)
694 args
.v4
.ucHPD_ID
= 0;
696 args
.v4
.ucHPD_ID
= hpd_id
+ 1;
700 case ATOM_ENCODER_CMD_SETUP_PANEL_MODE
:
701 args
.v5
.asDPPanelModeParam
.ucAction
= action
;
702 args
.v5
.asDPPanelModeParam
.ucPanelMode
= panel_mode
;
703 args
.v5
.asDPPanelModeParam
.ucDigId
= dig
->dig_encoder
;
705 case ATOM_ENCODER_CMD_STREAM_SETUP
:
706 args
.v5
.asStreamParam
.ucAction
= action
;
707 args
.v5
.asStreamParam
.ucDigId
= dig
->dig_encoder
;
708 args
.v5
.asStreamParam
.ucDigMode
=
709 amdgpu_atombios_encoder_get_encoder_mode(encoder
);
710 if (ENCODER_MODE_IS_DP(args
.v5
.asStreamParam
.ucDigMode
))
711 args
.v5
.asStreamParam
.ucLaneNum
= dp_lane_count
;
712 else if (amdgpu_dig_monitor_is_duallink(encoder
,
713 amdgpu_encoder
->pixel_clock
))
714 args
.v5
.asStreamParam
.ucLaneNum
= 8;
716 args
.v5
.asStreamParam
.ucLaneNum
= 4;
717 args
.v5
.asStreamParam
.ulPixelClock
=
718 cpu_to_le32(amdgpu_encoder
->pixel_clock
/ 10);
719 args
.v5
.asStreamParam
.ucBitPerColor
=
720 amdgpu_atombios_encoder_get_bpc(encoder
);
721 args
.v5
.asStreamParam
.ucLinkRateIn270Mhz
= dp_clock
/ 27000;
723 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_START
:
724 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1
:
725 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2
:
726 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3
:
727 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4
:
728 case ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE
:
729 case ATOM_ENCODER_CMD_DP_VIDEO_OFF
:
730 case ATOM_ENCODER_CMD_DP_VIDEO_ON
:
731 args
.v5
.asCmdParam
.ucAction
= action
;
732 args
.v5
.asCmdParam
.ucDigId
= dig
->dig_encoder
;
735 DRM_ERROR("Unsupported action 0x%x\n", action
);
740 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
745 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
749 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
753 union dig_transmitter_control
{
754 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1
;
755 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2
;
756 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3
;
757 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4
;
758 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5
;
759 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 v6
;
763 amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder
*encoder
, int action
,
764 uint8_t lane_num
, uint8_t lane_set
)
766 struct drm_device
*dev
= encoder
->dev
;
767 struct amdgpu_device
*adev
= dev
->dev_private
;
768 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
769 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
770 struct drm_connector
*connector
;
771 union dig_transmitter_control args
;
777 int dp_lane_count
= 0;
778 int connector_object_id
= 0;
779 int igp_lane_info
= 0;
780 int dig_encoder
= dig
->dig_encoder
;
781 int hpd_id
= AMDGPU_HPD_NONE
;
783 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
784 connector
= amdgpu_get_connector_for_encoder_init(encoder
);
785 /* just needed to avoid bailing in the encoder check. the encoder
786 * isn't used for init
790 connector
= amdgpu_get_connector_for_encoder(encoder
);
793 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
794 struct amdgpu_connector_atom_dig
*dig_connector
=
795 amdgpu_connector
->con_priv
;
797 hpd_id
= amdgpu_connector
->hpd
.hpd
;
798 dp_clock
= dig_connector
->dp_clock
;
799 dp_lane_count
= dig_connector
->dp_lane_count
;
800 connector_object_id
=
801 (amdgpu_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
805 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
806 pll_id
= amdgpu_crtc
->pll_id
;
809 /* no dig encoder assigned */
810 if (dig_encoder
== -1)
813 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)))
816 memset(&args
, 0, sizeof(args
));
818 switch (amdgpu_encoder
->encoder_id
) {
819 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
820 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
822 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
823 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
824 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
825 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
826 index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
828 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
829 index
= GetIndexIntoMasterTable(COMMAND
, LVTMATransmitterControl
);
833 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
840 args
.v1
.ucAction
= action
;
841 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
842 args
.v1
.usInitInfo
= cpu_to_le16(connector_object_id
);
843 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
844 args
.v1
.asMode
.ucLaneSel
= lane_num
;
845 args
.v1
.asMode
.ucLaneSet
= lane_set
;
848 args
.v1
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
849 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
850 args
.v1
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
852 args
.v1
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
855 args
.v1
.ucConfig
= ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
;
858 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
;
860 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
;
862 if ((adev
->flags
& AMD_IS_APU
) &&
863 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_UNIPHY
)) {
865 !amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
)) {
866 if (igp_lane_info
& 0x1)
867 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
868 else if (igp_lane_info
& 0x2)
869 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_4_7
;
870 else if (igp_lane_info
& 0x4)
871 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_11
;
872 else if (igp_lane_info
& 0x8)
873 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_12_15
;
875 if (igp_lane_info
& 0x3)
876 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_7
;
877 else if (igp_lane_info
& 0xc)
878 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_15
;
883 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
;
885 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
;
888 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
889 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
890 if (dig
->coherent_mode
)
891 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
892 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
893 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK
;
897 args
.v2
.ucAction
= action
;
898 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
899 args
.v2
.usInitInfo
= cpu_to_le16(connector_object_id
);
900 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
901 args
.v2
.asMode
.ucLaneSel
= lane_num
;
902 args
.v2
.asMode
.ucLaneSet
= lane_set
;
905 args
.v2
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
906 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
907 args
.v2
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
909 args
.v2
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
912 args
.v2
.acConfig
.ucEncoderSel
= dig_encoder
;
914 args
.v2
.acConfig
.ucLinkSel
= 1;
916 switch (amdgpu_encoder
->encoder_id
) {
917 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
918 args
.v2
.acConfig
.ucTransmitterSel
= 0;
920 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
921 args
.v2
.acConfig
.ucTransmitterSel
= 1;
923 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
924 args
.v2
.acConfig
.ucTransmitterSel
= 2;
929 args
.v2
.acConfig
.fCoherentMode
= 1;
930 args
.v2
.acConfig
.fDPConnector
= 1;
931 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
932 if (dig
->coherent_mode
)
933 args
.v2
.acConfig
.fCoherentMode
= 1;
934 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
935 args
.v2
.acConfig
.fDualLinkConnector
= 1;
939 args
.v3
.ucAction
= action
;
940 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
941 args
.v3
.usInitInfo
= cpu_to_le16(connector_object_id
);
942 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
943 args
.v3
.asMode
.ucLaneSel
= lane_num
;
944 args
.v3
.asMode
.ucLaneSet
= lane_set
;
947 args
.v3
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
948 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
949 args
.v3
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
951 args
.v3
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
955 args
.v3
.ucLaneNum
= dp_lane_count
;
956 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
957 args
.v3
.ucLaneNum
= 8;
959 args
.v3
.ucLaneNum
= 4;
962 args
.v3
.acConfig
.ucLinkSel
= 1;
964 args
.v3
.acConfig
.ucEncoderSel
= 1;
966 /* Select the PLL for the PHY
967 * DP PHY should be clocked from external src if there is
970 /* On DCE4, if there is an external clock, it generates the DP ref clock */
971 if (is_dp
&& adev
->clock
.dp_extclk
)
972 args
.v3
.acConfig
.ucRefClkSource
= 2; /* external src */
974 args
.v3
.acConfig
.ucRefClkSource
= pll_id
;
976 switch (amdgpu_encoder
->encoder_id
) {
977 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
978 args
.v3
.acConfig
.ucTransmitterSel
= 0;
980 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
981 args
.v3
.acConfig
.ucTransmitterSel
= 1;
983 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
984 args
.v3
.acConfig
.ucTransmitterSel
= 2;
989 args
.v3
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
990 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
991 if (dig
->coherent_mode
)
992 args
.v3
.acConfig
.fCoherentMode
= 1;
993 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
994 args
.v3
.acConfig
.fDualLinkConnector
= 1;
998 args
.v4
.ucAction
= action
;
999 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
1000 args
.v4
.usInitInfo
= cpu_to_le16(connector_object_id
);
1001 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
1002 args
.v4
.asMode
.ucLaneSel
= lane_num
;
1003 args
.v4
.asMode
.ucLaneSet
= lane_set
;
1006 args
.v4
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
1007 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1008 args
.v4
.usPixelClock
= cpu_to_le16((amdgpu_encoder
->pixel_clock
/ 2) / 10);
1010 args
.v4
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
1014 args
.v4
.ucLaneNum
= dp_lane_count
;
1015 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1016 args
.v4
.ucLaneNum
= 8;
1018 args
.v4
.ucLaneNum
= 4;
1021 args
.v4
.acConfig
.ucLinkSel
= 1;
1022 if (dig_encoder
& 1)
1023 args
.v4
.acConfig
.ucEncoderSel
= 1;
1025 /* Select the PLL for the PHY
1026 * DP PHY should be clocked from external src if there is
1029 /* On DCE5 DCPLL usually generates the DP ref clock */
1031 if (adev
->clock
.dp_extclk
)
1032 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_EXTCLK
;
1034 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_DCPLL
;
1036 args
.v4
.acConfig
.ucRefClkSource
= pll_id
;
1038 switch (amdgpu_encoder
->encoder_id
) {
1039 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1040 args
.v4
.acConfig
.ucTransmitterSel
= 0;
1042 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1043 args
.v4
.acConfig
.ucTransmitterSel
= 1;
1045 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1046 args
.v4
.acConfig
.ucTransmitterSel
= 2;
1051 args
.v4
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1052 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1053 if (dig
->coherent_mode
)
1054 args
.v4
.acConfig
.fCoherentMode
= 1;
1055 if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1056 args
.v4
.acConfig
.fDualLinkConnector
= 1;
1060 args
.v5
.ucAction
= action
;
1062 args
.v5
.usSymClock
= cpu_to_le16(dp_clock
/ 10);
1064 args
.v5
.usSymClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
1066 switch (amdgpu_encoder
->encoder_id
) {
1067 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1069 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYB
;
1071 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYA
;
1073 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1075 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYD
;
1077 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYC
;
1079 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1081 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYF
;
1083 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYE
;
1085 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1086 args
.v5
.ucPhyId
= ATOM_PHY_ID_UNIPHYG
;
1090 args
.v5
.ucLaneNum
= dp_lane_count
;
1091 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1092 args
.v5
.ucLaneNum
= 8;
1094 args
.v5
.ucLaneNum
= 4;
1095 args
.v5
.ucConnObjId
= connector_object_id
;
1096 args
.v5
.ucDigMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1098 if (is_dp
&& adev
->clock
.dp_extclk
)
1099 args
.v5
.asConfig
.ucPhyClkSrcId
= ENCODER_REFCLK_SRC_EXTCLK
;
1101 args
.v5
.asConfig
.ucPhyClkSrcId
= pll_id
;
1104 args
.v5
.asConfig
.ucCoherentMode
= 1; /* DP requires coherent */
1105 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1106 if (dig
->coherent_mode
)
1107 args
.v5
.asConfig
.ucCoherentMode
= 1;
1109 if (hpd_id
== AMDGPU_HPD_NONE
)
1110 args
.v5
.asConfig
.ucHPDSel
= 0;
1112 args
.v5
.asConfig
.ucHPDSel
= hpd_id
+ 1;
1113 args
.v5
.ucDigEncoderSel
= 1 << dig_encoder
;
1114 args
.v5
.ucDPLaneSet
= lane_set
;
1117 args
.v6
.ucAction
= action
;
1119 args
.v6
.ulSymClock
= cpu_to_le32(dp_clock
/ 10);
1121 args
.v6
.ulSymClock
= cpu_to_le32(amdgpu_encoder
->pixel_clock
/ 10);
1123 switch (amdgpu_encoder
->encoder_id
) {
1124 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1126 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYB
;
1128 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYA
;
1130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1132 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYD
;
1134 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYC
;
1136 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1138 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYF
;
1140 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYE
;
1142 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1143 args
.v6
.ucPhyId
= ATOM_PHY_ID_UNIPHYG
;
1147 args
.v6
.ucLaneNum
= dp_lane_count
;
1148 else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1149 args
.v6
.ucLaneNum
= 8;
1151 args
.v6
.ucLaneNum
= 4;
1152 args
.v6
.ucConnObjId
= connector_object_id
;
1153 if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
)
1154 args
.v6
.ucDPLaneSet
= lane_set
;
1156 args
.v6
.ucDigMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1158 if (hpd_id
== AMDGPU_HPD_NONE
)
1159 args
.v6
.ucHPDSel
= 0;
1161 args
.v6
.ucHPDSel
= hpd_id
+ 1;
1162 args
.v6
.ucDigEncoderSel
= 1 << dig_encoder
;
1165 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1170 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1174 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1178 amdgpu_atombios_encoder_set_edp_panel_power(struct drm_connector
*connector
,
1181 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1182 struct drm_device
*dev
= amdgpu_connector
->base
.dev
;
1183 struct amdgpu_device
*adev
= dev
->dev_private
;
1184 union dig_transmitter_control args
;
1185 int index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1188 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
1191 if ((action
!= ATOM_TRANSMITTER_ACTION_POWER_ON
) &&
1192 (action
!= ATOM_TRANSMITTER_ACTION_POWER_OFF
))
1195 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1198 memset(&args
, 0, sizeof(args
));
1200 args
.v1
.ucAction
= action
;
1202 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1204 /* wait for the panel to power up */
1205 if (action
== ATOM_TRANSMITTER_ACTION_POWER_ON
) {
1208 for (i
= 0; i
< 300; i
++) {
1209 if (amdgpu_display_hpd_sense(adev
, amdgpu_connector
->hpd
.hpd
))
1219 union external_encoder_control
{
1220 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1
;
1221 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3
;
1225 amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder
*encoder
,
1226 struct drm_encoder
*ext_encoder
,
1229 struct drm_device
*dev
= encoder
->dev
;
1230 struct amdgpu_device
*adev
= dev
->dev_private
;
1231 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1232 struct amdgpu_encoder
*ext_amdgpu_encoder
= to_amdgpu_encoder(ext_encoder
);
1233 union external_encoder_control args
;
1234 struct drm_connector
*connector
;
1235 int index
= GetIndexIntoMasterTable(COMMAND
, ExternalEncoderControl
);
1238 int dp_lane_count
= 0;
1239 int connector_object_id
= 0;
1240 u32 ext_enum
= (ext_amdgpu_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1242 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1243 connector
= amdgpu_get_connector_for_encoder_init(encoder
);
1245 connector
= amdgpu_get_connector_for_encoder(encoder
);
1248 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1249 struct amdgpu_connector_atom_dig
*dig_connector
=
1250 amdgpu_connector
->con_priv
;
1252 dp_clock
= dig_connector
->dp_clock
;
1253 dp_lane_count
= dig_connector
->dp_lane_count
;
1254 connector_object_id
=
1255 (amdgpu_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1258 memset(&args
, 0, sizeof(args
));
1260 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1265 /* no params on frev 1 */
1271 args
.v1
.sDigEncoder
.ucAction
= action
;
1272 args
.v1
.sDigEncoder
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
1273 args
.v1
.sDigEncoder
.ucEncoderMode
=
1274 amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1276 if (ENCODER_MODE_IS_DP(args
.v1
.sDigEncoder
.ucEncoderMode
)) {
1277 if (dp_clock
== 270000)
1278 args
.v1
.sDigEncoder
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
1279 args
.v1
.sDigEncoder
.ucLaneNum
= dp_lane_count
;
1280 } else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1281 args
.v1
.sDigEncoder
.ucLaneNum
= 8;
1283 args
.v1
.sDigEncoder
.ucLaneNum
= 4;
1286 args
.v3
.sExtEncoder
.ucAction
= action
;
1287 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1288 args
.v3
.sExtEncoder
.usConnectorId
= cpu_to_le16(connector_object_id
);
1290 args
.v3
.sExtEncoder
.usPixelClock
= cpu_to_le16(amdgpu_encoder
->pixel_clock
/ 10);
1291 args
.v3
.sExtEncoder
.ucEncoderMode
=
1292 amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1294 if (ENCODER_MODE_IS_DP(args
.v3
.sExtEncoder
.ucEncoderMode
)) {
1295 if (dp_clock
== 270000)
1296 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
1297 else if (dp_clock
== 540000)
1298 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ
;
1299 args
.v3
.sExtEncoder
.ucLaneNum
= dp_lane_count
;
1300 } else if (amdgpu_dig_monitor_is_duallink(encoder
, amdgpu_encoder
->pixel_clock
))
1301 args
.v3
.sExtEncoder
.ucLaneNum
= 8;
1303 args
.v3
.sExtEncoder
.ucLaneNum
= 4;
1305 case GRAPH_OBJECT_ENUM_ID1
:
1306 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1
;
1308 case GRAPH_OBJECT_ENUM_ID2
:
1309 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2
;
1311 case GRAPH_OBJECT_ENUM_ID3
:
1312 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3
;
1315 args
.v3
.sExtEncoder
.ucBitPerColor
= amdgpu_atombios_encoder_get_bpc(encoder
);
1318 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1323 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1326 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1330 amdgpu_atombios_encoder_setup_dig(struct drm_encoder
*encoder
, int action
)
1332 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1333 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1334 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1335 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1336 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1337 struct amdgpu_connector_atom_dig
*amdgpu_dig_connector
= NULL
;
1340 amdgpu_connector
= to_amdgpu_connector(connector
);
1341 amdgpu_dig_connector
= amdgpu_connector
->con_priv
;
1344 if (action
== ATOM_ENABLE
) {
1346 dig
->panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
1348 dig
->panel_mode
= amdgpu_atombios_dp_get_panel_mode(encoder
, connector
);
1350 /* setup and enable the encoder */
1351 amdgpu_atombios_encoder_setup_dig_encoder(encoder
, ATOM_ENCODER_CMD_SETUP
, 0);
1352 amdgpu_atombios_encoder_setup_dig_encoder(encoder
,
1353 ATOM_ENCODER_CMD_SETUP_PANEL_MODE
,
1356 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1357 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP
);
1358 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1360 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1361 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
1362 ATOM_TRANSMITTER_ACTION_POWER_ON
);
1363 amdgpu_dig_connector
->edp_on
= true;
1366 /* enable the transmitter */
1367 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
1368 ATOM_TRANSMITTER_ACTION_ENABLE
,
1370 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1372 /* DP_SET_POWER_D0 is set in amdgpu_atombios_dp_link_train */
1373 amdgpu_atombios_dp_link_train(encoder
, connector
);
1374 amdgpu_atombios_encoder_setup_dig_encoder(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_ON
, 0);
1376 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1377 amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder
, dig
->backlight_level
);
1379 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
, ATOM_ENABLE
);
1381 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1383 amdgpu_atombios_encoder_setup_dig_encoder(encoder
,
1384 ATOM_ENCODER_CMD_DP_VIDEO_OFF
, 0);
1386 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
, ATOM_DISABLE
);
1387 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1388 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
1389 ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
1391 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1393 amdgpu_atombios_dp_set_rx_power_state(connector
, DP_SET_POWER_D3
);
1394 /* disable the transmitter */
1395 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
,
1396 ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1397 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder
)) &&
1399 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1400 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
1401 ATOM_TRANSMITTER_ACTION_POWER_OFF
);
1402 amdgpu_dig_connector
->edp_on
= false;
1409 amdgpu_atombios_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
1411 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1413 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1414 amdgpu_encoder
->encoder_id
, mode
, amdgpu_encoder
->devices
,
1415 amdgpu_encoder
->active_device
);
1416 switch (amdgpu_encoder
->encoder_id
) {
1417 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1418 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1419 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1420 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1422 case DRM_MODE_DPMS_ON
:
1423 amdgpu_atombios_encoder_setup_dig(encoder
, ATOM_ENABLE
);
1425 case DRM_MODE_DPMS_STANDBY
:
1426 case DRM_MODE_DPMS_SUSPEND
:
1427 case DRM_MODE_DPMS_OFF
:
1428 amdgpu_atombios_encoder_setup_dig(encoder
, ATOM_DISABLE
);
1432 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1434 case DRM_MODE_DPMS_ON
:
1435 amdgpu_atombios_encoder_setup_dvo(encoder
, ATOM_ENABLE
);
1437 case DRM_MODE_DPMS_STANDBY
:
1438 case DRM_MODE_DPMS_SUSPEND
:
1439 case DRM_MODE_DPMS_OFF
:
1440 amdgpu_atombios_encoder_setup_dvo(encoder
, ATOM_DISABLE
);
1444 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1446 case DRM_MODE_DPMS_ON
:
1447 amdgpu_atombios_encoder_setup_dac(encoder
, ATOM_ENABLE
);
1449 case DRM_MODE_DPMS_STANDBY
:
1450 case DRM_MODE_DPMS_SUSPEND
:
1451 case DRM_MODE_DPMS_OFF
:
1452 amdgpu_atombios_encoder_setup_dac(encoder
, ATOM_DISABLE
);
1461 union crtc_source_param
{
1462 SELECT_CRTC_SOURCE_PS_ALLOCATION v1
;
1463 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2
;
1464 SELECT_CRTC_SOURCE_PARAMETERS_V3 v3
;
1468 amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder
*encoder
)
1470 struct drm_device
*dev
= encoder
->dev
;
1471 struct amdgpu_device
*adev
= dev
->dev_private
;
1472 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1473 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1474 union crtc_source_param args
;
1475 int index
= GetIndexIntoMasterTable(COMMAND
, SelectCRTC_Source
);
1477 struct amdgpu_encoder_atom_dig
*dig
;
1479 memset(&args
, 0, sizeof(args
));
1481 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1489 args
.v1
.ucCRTC
= amdgpu_crtc
->crtc_id
;
1490 switch (amdgpu_encoder
->encoder_id
) {
1491 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1492 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1493 args
.v1
.ucDevice
= ATOM_DEVICE_DFP1_INDEX
;
1495 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1496 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1497 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)
1498 args
.v1
.ucDevice
= ATOM_DEVICE_LCD1_INDEX
;
1500 args
.v1
.ucDevice
= ATOM_DEVICE_DFP3_INDEX
;
1502 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1503 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1504 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1505 args
.v1
.ucDevice
= ATOM_DEVICE_DFP2_INDEX
;
1507 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1508 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1509 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1510 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1511 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1512 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1514 args
.v1
.ucDevice
= ATOM_DEVICE_CRT1_INDEX
;
1516 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1517 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1518 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1519 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1520 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1521 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1523 args
.v1
.ucDevice
= ATOM_DEVICE_CRT2_INDEX
;
1528 args
.v2
.ucCRTC
= amdgpu_crtc
->crtc_id
;
1529 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
) {
1530 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1532 if (connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
)
1533 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1534 else if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
)
1535 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_CRT
;
1537 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1538 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1539 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1541 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1543 switch (amdgpu_encoder
->encoder_id
) {
1544 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1545 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1546 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1547 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1548 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1549 dig
= amdgpu_encoder
->enc_priv
;
1550 switch (dig
->dig_encoder
) {
1552 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1555 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1558 args
.v2
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1561 args
.v2
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1564 args
.v2
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1567 args
.v2
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1570 args
.v2
.ucEncoderID
= ASIC_INT_DIG7_ENCODER_ID
;
1574 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1575 args
.v2
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1578 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1579 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1580 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1581 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1583 args
.v2
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1585 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1586 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1587 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1588 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1589 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1591 args
.v2
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1596 args
.v3
.ucCRTC
= amdgpu_crtc
->crtc_id
;
1597 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) != ENCODER_OBJECT_ID_NONE
) {
1598 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1600 if (connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
)
1601 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1602 else if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
)
1603 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_CRT
;
1605 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1606 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1607 args
.v2
.ucEncodeMode
= ATOM_ENCODER_MODE_LVDS
;
1609 args
.v2
.ucEncodeMode
= amdgpu_atombios_encoder_get_encoder_mode(encoder
);
1611 args
.v3
.ucDstBpc
= amdgpu_atombios_encoder_get_bpc(encoder
);
1612 switch (amdgpu_encoder
->encoder_id
) {
1613 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1614 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1615 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1616 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1617 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1618 dig
= amdgpu_encoder
->enc_priv
;
1619 switch (dig
->dig_encoder
) {
1621 args
.v3
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1624 args
.v3
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1627 args
.v3
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1630 args
.v3
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1633 args
.v3
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1636 args
.v3
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1639 args
.v3
.ucEncoderID
= ASIC_INT_DIG7_ENCODER_ID
;
1643 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1644 args
.v3
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1646 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1647 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1648 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1649 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1650 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1652 args
.v3
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1654 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1655 if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1656 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1657 else if (amdgpu_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1658 args
.v3
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1660 args
.v3
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1667 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1671 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1674 /* This only needs to be called once at startup */
1676 amdgpu_atombios_encoder_init_dig(struct amdgpu_device
*adev
)
1678 struct drm_device
*dev
= adev
->ddev
;
1679 struct drm_encoder
*encoder
;
1681 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1682 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1683 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1685 switch (amdgpu_encoder
->encoder_id
) {
1686 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1687 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1688 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1689 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
1690 amdgpu_atombios_encoder_setup_dig_transmitter(encoder
, ATOM_TRANSMITTER_ACTION_INIT
,
1696 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1697 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
);
1702 amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder
*encoder
,
1703 struct drm_connector
*connector
)
1705 struct drm_device
*dev
= encoder
->dev
;
1706 struct amdgpu_device
*adev
= dev
->dev_private
;
1707 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1708 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1710 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
|
1711 ATOM_DEVICE_CV_SUPPORT
|
1712 ATOM_DEVICE_CRT_SUPPORT
)) {
1713 DAC_LOAD_DETECTION_PS_ALLOCATION args
;
1714 int index
= GetIndexIntoMasterTable(COMMAND
, DAC_LoadDetection
);
1717 memset(&args
, 0, sizeof(args
));
1719 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1722 args
.sDacload
.ucMisc
= 0;
1724 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) ||
1725 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
))
1726 args
.sDacload
.ucDacType
= ATOM_DAC_A
;
1728 args
.sDacload
.ucDacType
= ATOM_DAC_B
;
1730 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)
1731 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT
);
1732 else if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)
1733 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT
);
1734 else if (amdgpu_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1735 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CV_SUPPORT
);
1737 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1738 } else if (amdgpu_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1739 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT
);
1741 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1744 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1751 enum drm_connector_status
1752 amdgpu_atombios_encoder_dac_detect(struct drm_encoder
*encoder
,
1753 struct drm_connector
*connector
)
1755 struct drm_device
*dev
= encoder
->dev
;
1756 struct amdgpu_device
*adev
= dev
->dev_private
;
1757 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1758 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1759 uint32_t bios_0_scratch
;
1761 if (!amdgpu_atombios_encoder_dac_load_detect(encoder
, connector
)) {
1762 DRM_DEBUG_KMS("detect returned false \n");
1763 return connector_status_unknown
;
1766 bios_0_scratch
= RREG32(mmBIOS_SCRATCH_0
);
1768 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, amdgpu_encoder
->devices
);
1769 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1770 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
1771 return connector_status_connected
;
1773 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1774 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
1775 return connector_status_connected
;
1777 if (amdgpu_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1778 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
1779 return connector_status_connected
;
1781 if (amdgpu_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1782 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
1783 return connector_status_connected
; /* CTV */
1784 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
1785 return connector_status_connected
; /* STV */
1787 return connector_status_disconnected
;
1790 enum drm_connector_status
1791 amdgpu_atombios_encoder_dig_detect(struct drm_encoder
*encoder
,
1792 struct drm_connector
*connector
)
1794 struct drm_device
*dev
= encoder
->dev
;
1795 struct amdgpu_device
*adev
= dev
->dev_private
;
1796 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1797 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
1798 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1802 return connector_status_unknown
;
1804 if ((amdgpu_connector
->devices
& ATOM_DEVICE_CRT_SUPPORT
) == 0)
1805 return connector_status_unknown
;
1807 /* load detect on the dp bridge */
1808 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1809 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION
);
1811 bios_0_scratch
= RREG32(mmBIOS_SCRATCH_0
);
1813 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, amdgpu_encoder
->devices
);
1814 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1815 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
1816 return connector_status_connected
;
1818 if (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1819 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
1820 return connector_status_connected
;
1822 if (amdgpu_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1823 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
1824 return connector_status_connected
;
1826 if (amdgpu_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1827 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
1828 return connector_status_connected
; /* CTV */
1829 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
1830 return connector_status_connected
; /* STV */
1832 return connector_status_disconnected
;
1836 amdgpu_atombios_encoder_setup_ext_encoder_ddc(struct drm_encoder
*encoder
)
1838 struct drm_encoder
*ext_encoder
= amdgpu_get_external_encoder(encoder
);
1841 /* ddc_setup on the dp bridge */
1842 amdgpu_atombios_encoder_setup_external_encoder(encoder
, ext_encoder
,
1843 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP
);
1848 amdgpu_atombios_encoder_set_bios_scratch_regs(struct drm_connector
*connector
,
1849 struct drm_encoder
*encoder
,
1852 struct drm_device
*dev
= connector
->dev
;
1853 struct amdgpu_device
*adev
= dev
->dev_private
;
1854 struct amdgpu_connector
*amdgpu_connector
=
1855 to_amdgpu_connector(connector
);
1856 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1857 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
1859 bios_0_scratch
= RREG32(mmBIOS_SCRATCH_0
);
1860 bios_3_scratch
= RREG32(mmBIOS_SCRATCH_3
);
1861 bios_6_scratch
= RREG32(mmBIOS_SCRATCH_6
);
1863 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
1864 (amdgpu_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
1866 DRM_DEBUG_KMS("LCD1 connected\n");
1867 bios_0_scratch
|= ATOM_S0_LCD1
;
1868 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
1869 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
1871 DRM_DEBUG_KMS("LCD1 disconnected\n");
1872 bios_0_scratch
&= ~ATOM_S0_LCD1
;
1873 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
1874 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
1877 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
1878 (amdgpu_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
1880 DRM_DEBUG_KMS("CRT1 connected\n");
1881 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
1882 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
1883 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
1885 DRM_DEBUG_KMS("CRT1 disconnected\n");
1886 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
1887 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
1888 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
1891 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
1892 (amdgpu_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
1894 DRM_DEBUG_KMS("CRT2 connected\n");
1895 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
1896 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
1897 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
1899 DRM_DEBUG_KMS("CRT2 disconnected\n");
1900 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
1901 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
1902 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
1905 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
1906 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
1908 DRM_DEBUG_KMS("DFP1 connected\n");
1909 bios_0_scratch
|= ATOM_S0_DFP1
;
1910 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
1911 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
1913 DRM_DEBUG_KMS("DFP1 disconnected\n");
1914 bios_0_scratch
&= ~ATOM_S0_DFP1
;
1915 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
1916 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
1919 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
1920 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
1922 DRM_DEBUG_KMS("DFP2 connected\n");
1923 bios_0_scratch
|= ATOM_S0_DFP2
;
1924 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
1925 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
1927 DRM_DEBUG_KMS("DFP2 disconnected\n");
1928 bios_0_scratch
&= ~ATOM_S0_DFP2
;
1929 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
1930 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
1933 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
1934 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
1936 DRM_DEBUG_KMS("DFP3 connected\n");
1937 bios_0_scratch
|= ATOM_S0_DFP3
;
1938 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
1939 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
1941 DRM_DEBUG_KMS("DFP3 disconnected\n");
1942 bios_0_scratch
&= ~ATOM_S0_DFP3
;
1943 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
1944 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
1947 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
1948 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
1950 DRM_DEBUG_KMS("DFP4 connected\n");
1951 bios_0_scratch
|= ATOM_S0_DFP4
;
1952 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
1953 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
1955 DRM_DEBUG_KMS("DFP4 disconnected\n");
1956 bios_0_scratch
&= ~ATOM_S0_DFP4
;
1957 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
1958 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
1961 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
1962 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
1964 DRM_DEBUG_KMS("DFP5 connected\n");
1965 bios_0_scratch
|= ATOM_S0_DFP5
;
1966 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
1967 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
1969 DRM_DEBUG_KMS("DFP5 disconnected\n");
1970 bios_0_scratch
&= ~ATOM_S0_DFP5
;
1971 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
1972 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
1975 if ((amdgpu_encoder
->devices
& ATOM_DEVICE_DFP6_SUPPORT
) &&
1976 (amdgpu_connector
->devices
& ATOM_DEVICE_DFP6_SUPPORT
)) {
1978 DRM_DEBUG_KMS("DFP6 connected\n");
1979 bios_0_scratch
|= ATOM_S0_DFP6
;
1980 bios_3_scratch
|= ATOM_S3_DFP6_ACTIVE
;
1981 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP6
;
1983 DRM_DEBUG_KMS("DFP6 disconnected\n");
1984 bios_0_scratch
&= ~ATOM_S0_DFP6
;
1985 bios_3_scratch
&= ~ATOM_S3_DFP6_ACTIVE
;
1986 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP6
;
1990 WREG32(mmBIOS_SCRATCH_0
, bios_0_scratch
);
1991 WREG32(mmBIOS_SCRATCH_3
, bios_3_scratch
);
1992 WREG32(mmBIOS_SCRATCH_6
, bios_6_scratch
);
1996 struct _ATOM_LVDS_INFO info
;
1997 struct _ATOM_LVDS_INFO_V12 info_12
;
2000 struct amdgpu_encoder_atom_dig
*
2001 amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder
*encoder
)
2003 struct drm_device
*dev
= encoder
->base
.dev
;
2004 struct amdgpu_device
*adev
= dev
->dev_private
;
2005 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
2006 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
2007 uint16_t data_offset
, misc
;
2008 union lvds_info
*lvds_info
;
2010 struct amdgpu_encoder_atom_dig
*lvds
= NULL
;
2011 int encoder_enum
= (encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
2013 if (amdgpu_atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2014 &frev
, &crev
, &data_offset
)) {
2016 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2018 kzalloc(sizeof(struct amdgpu_encoder_atom_dig
), GFP_KERNEL
);
2023 lvds
->native_mode
.clock
=
2024 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
2025 lvds
->native_mode
.hdisplay
=
2026 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
2027 lvds
->native_mode
.vdisplay
=
2028 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
2029 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
2030 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
2031 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
2032 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
2033 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
2034 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
2035 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
2036 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
2037 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
2038 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncOffset
);
2039 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
2040 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
2041 lvds
->panel_pwr_delay
=
2042 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
2043 lvds
->lcd_misc
= lvds_info
->info
.ucLVDS_Misc
;
2045 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
2046 if (misc
& ATOM_VSYNC_POLARITY
)
2047 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
2048 if (misc
& ATOM_HSYNC_POLARITY
)
2049 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
2050 if (misc
& ATOM_COMPOSITESYNC
)
2051 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
2052 if (misc
& ATOM_INTERLACE
)
2053 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
2054 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
2055 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
2057 lvds
->native_mode
.width_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageHSize
);
2058 lvds
->native_mode
.height_mm
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.usImageVSize
);
2060 /* set crtc values */
2061 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
2063 lvds
->lcd_ss_id
= lvds_info
->info
.ucSS_Id
;
2065 encoder
->native_mode
= lvds
->native_mode
;
2067 if (encoder_enum
== 2)
2070 lvds
->linkb
= false;
2072 /* parse the lcd record table */
2073 if (le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
)) {
2074 ATOM_FAKE_EDID_PATCH_RECORD
*fake_edid_record
;
2075 ATOM_PANEL_RESOLUTION_PATCH_RECORD
*panel_res_record
;
2076 bool bad_record
= false;
2079 if ((frev
== 1) && (crev
< 2))
2081 record
= (u8
*)(mode_info
->atom_context
->bios
+
2082 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
2085 record
= (u8
*)(mode_info
->atom_context
->bios
+
2087 le16_to_cpu(lvds_info
->info
.usModePatchTableOffset
));
2088 while (*record
!= ATOM_RECORD_END_TYPE
) {
2090 case LCD_MODE_PATCH_RECORD_MODE_TYPE
:
2091 record
+= sizeof(ATOM_PATCH_RECORD_MODE
);
2093 case LCD_RTS_RECORD_TYPE
:
2094 record
+= sizeof(ATOM_LCD_RTS_RECORD
);
2096 case LCD_CAP_RECORD_TYPE
:
2097 record
+= sizeof(ATOM_LCD_MODE_CONTROL_CAP
);
2099 case LCD_FAKE_EDID_PATCH_RECORD_TYPE
:
2100 fake_edid_record
= (ATOM_FAKE_EDID_PATCH_RECORD
*)record
;
2101 if (fake_edid_record
->ucFakeEDIDLength
) {
2104 max((int)EDID_LENGTH
, (int)fake_edid_record
->ucFakeEDIDLength
);
2105 edid
= kmalloc(edid_size
, GFP_KERNEL
);
2107 memcpy((u8
*)edid
, (u8
*)&fake_edid_record
->ucFakeEDIDString
[0],
2108 fake_edid_record
->ucFakeEDIDLength
);
2110 if (drm_edid_is_valid(edid
)) {
2111 adev
->mode_info
.bios_hardcoded_edid
= edid
;
2112 adev
->mode_info
.bios_hardcoded_edid_size
= edid_size
;
2117 record
+= fake_edid_record
->ucFakeEDIDLength
?
2118 fake_edid_record
->ucFakeEDIDLength
+ 2 :
2119 sizeof(ATOM_FAKE_EDID_PATCH_RECORD
);
2121 case LCD_PANEL_RESOLUTION_RECORD_TYPE
:
2122 panel_res_record
= (ATOM_PANEL_RESOLUTION_PATCH_RECORD
*)record
;
2123 lvds
->native_mode
.width_mm
= panel_res_record
->usHSize
;
2124 lvds
->native_mode
.height_mm
= panel_res_record
->usVSize
;
2125 record
+= sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD
);
2128 DRM_ERROR("Bad LCD record %d\n", *record
);
2140 struct amdgpu_encoder_atom_dig
*
2141 amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder
*amdgpu_encoder
)
2143 int encoder_enum
= (amdgpu_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
2144 struct amdgpu_encoder_atom_dig
*dig
= kzalloc(sizeof(struct amdgpu_encoder_atom_dig
), GFP_KERNEL
);
2149 /* coherent mode by default */
2150 dig
->coherent_mode
= true;
2151 dig
->dig_encoder
= -1;
2153 if (encoder_enum
== 2)