2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "bif/bif_4_1_d.h"
33 #include "bif/bif_4_1_sh_mask.h"
35 #include "gca/gfx_7_2_d.h"
36 #include "gca/gfx_7_2_enum.h"
37 #include "gca/gfx_7_2_sh_mask.h"
39 #include "gmc/gmc_7_1_d.h"
40 #include "gmc/gmc_7_1_sh_mask.h"
42 #include "oss/oss_2_0_d.h"
43 #include "oss/oss_2_0_sh_mask.h"
45 static const u32 sdma_offsets
[SDMA_MAX_INSTANCE
] =
47 SDMA0_REGISTER_OFFSET
,
51 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
);
52 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
);
53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
);
54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
);
56 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
57 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
58 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
59 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
60 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
61 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
62 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
63 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
64 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
65 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
67 u32
amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device
*adev
);
71 * Starting with CIK, the GPU has new asynchronous
72 * DMA engines. These engines are used for compute
73 * and gfx. There are two DMA engines (SDMA0, SDMA1)
74 * and each one supports 1 ring buffer used for gfx
75 * and 2 queues used for compute.
77 * The programming model is very similar to the CP
78 * (ring buffer, IBs, etc.), but sDMA has it's own
79 * packet format that is different from the PM4 format
80 * used by the CP. sDMA supports copying data, writing
81 * embedded data, solid fills, and a number of other
82 * things. It also has support for tiling/detiling of
87 * cik_sdma_init_microcode - load ucode images from disk
89 * @adev: amdgpu_device pointer
91 * Use the firmware interface to load the ucode images into
92 * the driver (not loaded into hw).
93 * Returns 0 on success, error on failure.
95 static int cik_sdma_init_microcode(struct amdgpu_device
*adev
)
97 const char *chip_name
;
103 switch (adev
->asic_type
) {
105 chip_name
= "bonaire";
108 chip_name
= "hawaii";
111 chip_name
= "kaveri";
114 chip_name
= "kabini";
117 chip_name
= "mullins";
122 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
124 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma.bin", chip_name
);
126 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma1.bin", chip_name
);
127 err
= request_firmware(&adev
->sdma
.instance
[i
].fw
, fw_name
, adev
->dev
);
130 err
= amdgpu_ucode_validate(adev
->sdma
.instance
[i
].fw
);
135 "cik_sdma: Failed to load firmware \"%s\"\n",
137 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
138 release_firmware(adev
->sdma
.instance
[i
].fw
);
139 adev
->sdma
.instance
[i
].fw
= NULL
;
146 * cik_sdma_ring_get_rptr - get the current read pointer
148 * @ring: amdgpu ring pointer
150 * Get the current rptr from the hardware (CIK+).
152 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring
*ring
)
156 rptr
= ring
->adev
->wb
.wb
[ring
->rptr_offs
];
158 return (rptr
& 0x3fffc) >> 2;
162 * cik_sdma_ring_get_wptr - get the current write pointer
164 * @ring: amdgpu ring pointer
166 * Get the current wptr from the hardware (CIK+).
168 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring
*ring
)
170 struct amdgpu_device
*adev
= ring
->adev
;
171 u32 me
= (ring
== &adev
->sdma
.instance
[0].ring
) ? 0 : 1;
173 return (RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
]) & 0x3fffc) >> 2;
177 * cik_sdma_ring_set_wptr - commit the write pointer
179 * @ring: amdgpu ring pointer
181 * Write the wptr back to the hardware (CIK+).
183 static void cik_sdma_ring_set_wptr(struct amdgpu_ring
*ring
)
185 struct amdgpu_device
*adev
= ring
->adev
;
186 u32 me
= (ring
== &adev
->sdma
.instance
[0].ring
) ? 0 : 1;
188 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
], (ring
->wptr
<< 2) & 0x3fffc);
191 static void cik_sdma_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
193 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
196 for (i
= 0; i
< count
; i
++)
197 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
198 amdgpu_ring_write(ring
, ring
->nop
|
199 SDMA_NOP_COUNT(count
- 1));
201 amdgpu_ring_write(ring
, ring
->nop
);
205 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
207 * @ring: amdgpu ring pointer
208 * @ib: IB object to schedule
210 * Schedule an IB in the DMA ring (CIK).
212 static void cik_sdma_ring_emit_ib(struct amdgpu_ring
*ring
,
213 struct amdgpu_ib
*ib
,
214 unsigned vm_id
, bool ctx_switch
)
216 u32 extra_bits
= vm_id
& 0xf;
217 u32 next_rptr
= ring
->wptr
+ 5;
219 while ((next_rptr
& 7) != 4)
223 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0));
224 amdgpu_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
225 amdgpu_ring_write(ring
, upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xffffffff);
226 amdgpu_ring_write(ring
, 1); /* number of DWs to follow */
227 amdgpu_ring_write(ring
, next_rptr
);
229 /* IB packet must end on a 8 DW boundary */
230 cik_sdma_ring_insert_nop(ring
, (12 - (ring
->wptr
& 7)) % 8);
232 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER
, 0, extra_bits
));
233 amdgpu_ring_write(ring
, ib
->gpu_addr
& 0xffffffe0); /* base must be 32 byte aligned */
234 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xffffffff);
235 amdgpu_ring_write(ring
, ib
->length_dw
);
240 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
242 * @ring: amdgpu ring pointer
244 * Emit an hdp flush packet on the requested DMA ring.
246 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
248 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
249 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
252 if (ring
== &ring
->adev
->sdma
.instance
[0].ring
)
253 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA0_MASK
;
255 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA1_MASK
;
257 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
258 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
<< 2);
259 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
<< 2);
260 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
261 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
262 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
265 static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring
*ring
)
267 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
268 amdgpu_ring_write(ring
, mmHDP_DEBUG0
);
269 amdgpu_ring_write(ring
, 1);
273 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
275 * @ring: amdgpu ring pointer
276 * @fence: amdgpu fence object
278 * Add a DMA fence packet to the ring to write
279 * the fence seq number and DMA trap packet to generate
280 * an interrupt if needed (CIK).
282 static void cik_sdma_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
285 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
286 /* write the fence */
287 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
288 amdgpu_ring_write(ring
, lower_32_bits(addr
));
289 amdgpu_ring_write(ring
, upper_32_bits(addr
));
290 amdgpu_ring_write(ring
, lower_32_bits(seq
));
292 /* optionally write high bits as well */
295 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
296 amdgpu_ring_write(ring
, lower_32_bits(addr
));
297 amdgpu_ring_write(ring
, upper_32_bits(addr
));
298 amdgpu_ring_write(ring
, upper_32_bits(seq
));
301 /* generate an interrupt */
302 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_TRAP
, 0, 0));
306 * cik_sdma_gfx_stop - stop the gfx async dma engines
308 * @adev: amdgpu_device pointer
310 * Stop the gfx async dma ring buffers (CIK).
312 static void cik_sdma_gfx_stop(struct amdgpu_device
*adev
)
314 struct amdgpu_ring
*sdma0
= &adev
->sdma
.instance
[0].ring
;
315 struct amdgpu_ring
*sdma1
= &adev
->sdma
.instance
[1].ring
;
319 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
320 (adev
->mman
.buffer_funcs_ring
== sdma1
))
321 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
323 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
324 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
325 rb_cntl
&= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
;
326 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
327 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], 0);
329 sdma0
->ready
= false;
330 sdma1
->ready
= false;
334 * cik_sdma_rlc_stop - stop the compute async dma engines
336 * @adev: amdgpu_device pointer
338 * Stop the compute async dma queues (CIK).
340 static void cik_sdma_rlc_stop(struct amdgpu_device
*adev
)
346 * cik_sdma_enable - stop the async dma engines
348 * @adev: amdgpu_device pointer
349 * @enable: enable/disable the DMA MEs.
351 * Halt or unhalt the async dma engines (CIK).
353 static void cik_sdma_enable(struct amdgpu_device
*adev
, bool enable
)
358 if (enable
== false) {
359 cik_sdma_gfx_stop(adev
);
360 cik_sdma_rlc_stop(adev
);
363 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
364 me_cntl
= RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]);
366 me_cntl
&= ~SDMA0_F32_CNTL__HALT_MASK
;
368 me_cntl
|= SDMA0_F32_CNTL__HALT_MASK
;
369 WREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
], me_cntl
);
374 * cik_sdma_gfx_resume - setup and start the async dma engines
376 * @adev: amdgpu_device pointer
378 * Set up the gfx DMA ring buffers and enable them (CIK).
379 * Returns 0 for success, error for failure.
381 static int cik_sdma_gfx_resume(struct amdgpu_device
*adev
)
383 struct amdgpu_ring
*ring
;
384 u32 rb_cntl
, ib_cntl
;
389 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
390 ring
= &adev
->sdma
.instance
[i
].ring
;
391 wb_offset
= (ring
->rptr_offs
* 4);
393 mutex_lock(&adev
->srbm_mutex
);
394 for (j
= 0; j
< 16; j
++) {
395 cik_srbm_select(adev
, 0, 0, 0, j
);
397 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
], 0);
398 WREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
], 0);
399 /* XXX SDMA RLC - todo */
401 cik_srbm_select(adev
, 0, 0, 0, 0);
402 mutex_unlock(&adev
->srbm_mutex
);
404 WREG32(mmSDMA0_TILING_CONFIG
+ sdma_offsets
[i
],
405 adev
->gfx
.config
.gb_addr_config
& 0x70);
407 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL
+ sdma_offsets
[i
], 0);
408 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
], 0);
410 /* Set ring buffer size in dwords */
411 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
412 rb_cntl
= rb_bufsz
<< 1;
414 rb_cntl
|= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK
|
415 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK
;
417 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
419 /* Initialize the ring buffer's read and write pointers */
420 WREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
], 0);
421 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], 0);
423 /* set the wb address whether it's enabled or not */
424 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
],
425 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
426 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
],
427 ((adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC));
429 rb_cntl
|= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK
;
431 WREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
], ring
->gpu_addr
>> 8);
432 WREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
], ring
->gpu_addr
>> 40);
435 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], ring
->wptr
<< 2);
438 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
],
439 rb_cntl
| SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
);
441 ib_cntl
= SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK
;
443 ib_cntl
|= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK
;
446 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
450 r
= amdgpu_ring_test_ring(ring
);
456 if (adev
->mman
.buffer_funcs_ring
== ring
)
457 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.real_vram_size
);
464 * cik_sdma_rlc_resume - setup and start the async dma engines
466 * @adev: amdgpu_device pointer
468 * Set up the compute DMA queues and enable them (CIK).
469 * Returns 0 for success, error for failure.
471 static int cik_sdma_rlc_resume(struct amdgpu_device
*adev
)
478 * cik_sdma_load_microcode - load the sDMA ME ucode
480 * @adev: amdgpu_device pointer
482 * Loads the sDMA0/1 ucode.
483 * Returns 0 for success, -EINVAL if the ucode is not available.
485 static int cik_sdma_load_microcode(struct amdgpu_device
*adev
)
487 const struct sdma_firmware_header_v1_0
*hdr
;
488 const __le32
*fw_data
;
493 cik_sdma_enable(adev
, false);
495 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
496 if (!adev
->sdma
.instance
[i
].fw
)
498 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
499 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
500 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
501 adev
->sdma
.instance
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
502 adev
->sdma
.instance
[i
].feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
503 if (adev
->sdma
.instance
[i
].feature_version
>= 20)
504 adev
->sdma
.instance
[i
].burst_nop
= true;
505 fw_data
= (const __le32
*)
506 (adev
->sdma
.instance
[i
].fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
507 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], 0);
508 for (j
= 0; j
< fw_size
; j
++)
509 WREG32(mmSDMA0_UCODE_DATA
+ sdma_offsets
[i
], le32_to_cpup(fw_data
++));
510 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], adev
->sdma
.instance
[i
].fw_version
);
517 * cik_sdma_start - setup and start the async dma engines
519 * @adev: amdgpu_device pointer
521 * Set up the DMA engines and enable them (CIK).
522 * Returns 0 for success, error for failure.
524 static int cik_sdma_start(struct amdgpu_device
*adev
)
528 r
= cik_sdma_load_microcode(adev
);
533 cik_sdma_enable(adev
, true);
535 /* start the gfx rings and rlc compute queues */
536 r
= cik_sdma_gfx_resume(adev
);
539 r
= cik_sdma_rlc_resume(adev
);
547 * cik_sdma_ring_test_ring - simple async dma engine test
549 * @ring: amdgpu_ring structure holding ring information
551 * Test the DMA engine by writing using it to write an
552 * value to memory. (CIK).
553 * Returns 0 for success, error for failure.
555 static int cik_sdma_ring_test_ring(struct amdgpu_ring
*ring
)
557 struct amdgpu_device
*adev
= ring
->adev
;
564 r
= amdgpu_wb_get(adev
, &index
);
566 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
570 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
572 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
574 r
= amdgpu_ring_alloc(ring
, 5);
576 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
577 amdgpu_wb_free(adev
, index
);
580 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0));
581 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
582 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
583 amdgpu_ring_write(ring
, 1); /* number of DWs to follow */
584 amdgpu_ring_write(ring
, 0xDEADBEEF);
585 amdgpu_ring_commit(ring
);
587 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
588 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
589 if (tmp
== 0xDEADBEEF)
594 if (i
< adev
->usec_timeout
) {
595 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
597 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
601 amdgpu_wb_free(adev
, index
);
607 * cik_sdma_ring_test_ib - test an IB on the DMA engine
609 * @ring: amdgpu_ring structure holding ring information
611 * Test a simple IB in the DMA ring (CIK).
612 * Returns 0 on success, error on failure.
614 static int cik_sdma_ring_test_ib(struct amdgpu_ring
*ring
)
616 struct amdgpu_device
*adev
= ring
->adev
;
618 struct fence
*f
= NULL
;
625 r
= amdgpu_wb_get(adev
, &index
);
627 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
631 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
633 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
634 memset(&ib
, 0, sizeof(ib
));
635 r
= amdgpu_ib_get(adev
, NULL
, 256, &ib
);
637 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r
);
641 ib
.ptr
[0] = SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
642 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
643 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
645 ib
.ptr
[4] = 0xDEADBEEF;
647 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, NULL
, &f
);
651 r
= fence_wait(f
, false);
653 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r
);
656 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
657 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
658 if (tmp
== 0xDEADBEEF)
662 if (i
< adev
->usec_timeout
) {
663 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
667 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp
);
673 amdgpu_ib_free(adev
, &ib
, NULL
);
676 amdgpu_wb_free(adev
, index
);
681 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
683 * @ib: indirect buffer to fill with commands
684 * @pe: addr of the page entry
685 * @src: src addr to copy from
686 * @count: number of page entries to update
688 * Update PTEs by copying them from the GART using sDMA (CIK).
690 static void cik_sdma_vm_copy_pte(struct amdgpu_ib
*ib
,
691 uint64_t pe
, uint64_t src
,
695 unsigned bytes
= count
* 8;
696 if (bytes
> 0x1FFFF8)
699 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_COPY
,
700 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
701 ib
->ptr
[ib
->length_dw
++] = bytes
;
702 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
703 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
704 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
705 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
706 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
715 * cik_sdma_vm_write_pages - update PTEs by writing them manually
717 * @ib: indirect buffer to fill with commands
718 * @pe: addr of the page entry
719 * @addr: dst addr to write into pe
720 * @count: number of page entries to update
721 * @incr: increase next addr by incr bytes
722 * @flags: access flags
724 * Update PTEs by writing them manually using sDMA (CIK).
726 static void cik_sdma_vm_write_pte(struct amdgpu_ib
*ib
,
727 const dma_addr_t
*pages_addr
, uint64_t pe
,
728 uint64_t addr
, unsigned count
,
729 uint32_t incr
, uint32_t flags
)
739 /* for non-physically contiguous pages (system) */
740 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_WRITE
,
741 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
742 ib
->ptr
[ib
->length_dw
++] = pe
;
743 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
744 ib
->ptr
[ib
->length_dw
++] = ndw
;
745 for (; ndw
> 0; ndw
-= 2, --count
, pe
+= 8) {
746 value
= amdgpu_vm_map_gart(pages_addr
, addr
);
749 ib
->ptr
[ib
->length_dw
++] = value
;
750 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
756 * cik_sdma_vm_set_pages - update the page tables using sDMA
758 * @ib: indirect buffer to fill with commands
759 * @pe: addr of the page entry
760 * @addr: dst addr to write into pe
761 * @count: number of page entries to update
762 * @incr: increase next addr by incr bytes
763 * @flags: access flags
765 * Update the page tables using sDMA (CIK).
767 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib
*ib
,
769 uint64_t addr
, unsigned count
,
770 uint32_t incr
, uint32_t flags
)
780 if (flags
& AMDGPU_PTE_VALID
)
785 /* for physically contiguous pages (vram) */
786 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE
, 0, 0);
787 ib
->ptr
[ib
->length_dw
++] = pe
; /* dst addr */
788 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
789 ib
->ptr
[ib
->length_dw
++] = flags
; /* mask */
790 ib
->ptr
[ib
->length_dw
++] = 0;
791 ib
->ptr
[ib
->length_dw
++] = value
; /* value */
792 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
793 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
794 ib
->ptr
[ib
->length_dw
++] = 0;
795 ib
->ptr
[ib
->length_dw
++] = ndw
; /* number of entries */
804 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
806 * @ib: indirect buffer to fill with padding
809 static void cik_sdma_ring_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
)
811 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
815 pad_count
= (8 - (ib
->length_dw
& 0x7)) % 8;
816 for (i
= 0; i
< pad_count
; i
++)
817 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
818 ib
->ptr
[ib
->length_dw
++] =
819 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0) |
820 SDMA_NOP_COUNT(pad_count
- 1);
822 ib
->ptr
[ib
->length_dw
++] =
823 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0);
827 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
829 * @ring: amdgpu_ring pointer
831 * Make sure all previous operations are completed (CIK).
833 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring
*ring
)
835 uint32_t seq
= ring
->fence_drv
.sync_seq
;
836 uint64_t addr
= ring
->fence_drv
.gpu_addr
;
839 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0,
840 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
841 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
842 SDMA_POLL_REG_MEM_EXTRA_M
));
843 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
844 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
845 amdgpu_ring_write(ring
, seq
); /* reference */
846 amdgpu_ring_write(ring
, 0xfffffff); /* mask */
847 amdgpu_ring_write(ring
, (0xfff << 16) | 4); /* retry count, poll interval */
851 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
853 * @ring: amdgpu_ring pointer
854 * @vm: amdgpu_vm pointer
856 * Update the page table base and flush the VM TLB
859 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
860 unsigned vm_id
, uint64_t pd_addr
)
862 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
863 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
865 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
867 amdgpu_ring_write(ring
, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
869 amdgpu_ring_write(ring
, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
871 amdgpu_ring_write(ring
, pd_addr
>> 12);
874 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
875 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
876 amdgpu_ring_write(ring
, 1 << vm_id
);
878 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
879 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
<< 2);
880 amdgpu_ring_write(ring
, 0);
881 amdgpu_ring_write(ring
, 0); /* reference */
882 amdgpu_ring_write(ring
, 0); /* mask */
883 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
886 static void cik_enable_sdma_mgcg(struct amdgpu_device
*adev
,
891 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_MGCG
)) {
892 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, 0x00000100);
893 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, 0x00000100);
895 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
);
898 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, data
);
900 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
);
903 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, data
);
907 static void cik_enable_sdma_mgls(struct amdgpu_device
*adev
,
912 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_LS
)) {
913 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
916 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
918 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
921 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
923 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
926 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
928 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
931 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
935 static int cik_sdma_early_init(void *handle
)
937 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
939 adev
->sdma
.num_instances
= SDMA_MAX_INSTANCE
;
941 cik_sdma_set_ring_funcs(adev
);
942 cik_sdma_set_irq_funcs(adev
);
943 cik_sdma_set_buffer_funcs(adev
);
944 cik_sdma_set_vm_pte_funcs(adev
);
949 static int cik_sdma_sw_init(void *handle
)
951 struct amdgpu_ring
*ring
;
952 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
955 r
= cik_sdma_init_microcode(adev
);
957 DRM_ERROR("Failed to load sdma firmware!\n");
961 /* SDMA trap event */
962 r
= amdgpu_irq_add_id(adev
, 224, &adev
->sdma
.trap_irq
);
966 /* SDMA Privileged inst */
967 r
= amdgpu_irq_add_id(adev
, 241, &adev
->sdma
.illegal_inst_irq
);
971 /* SDMA Privileged inst */
972 r
= amdgpu_irq_add_id(adev
, 247, &adev
->sdma
.illegal_inst_irq
);
976 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
977 ring
= &adev
->sdma
.instance
[i
].ring
;
978 ring
->ring_obj
= NULL
;
979 sprintf(ring
->name
, "sdma%d", i
);
980 r
= amdgpu_ring_init(adev
, ring
, 1024,
981 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0), 0xf,
982 &adev
->sdma
.trap_irq
,
984 AMDGPU_SDMA_IRQ_TRAP0
: AMDGPU_SDMA_IRQ_TRAP1
,
985 AMDGPU_RING_TYPE_SDMA
);
993 static int cik_sdma_sw_fini(void *handle
)
995 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
998 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
999 amdgpu_ring_fini(&adev
->sdma
.instance
[i
].ring
);
1004 static int cik_sdma_hw_init(void *handle
)
1007 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1009 r
= cik_sdma_start(adev
);
1016 static int cik_sdma_hw_fini(void *handle
)
1018 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1020 cik_sdma_enable(adev
, false);
1025 static int cik_sdma_suspend(void *handle
)
1027 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1029 return cik_sdma_hw_fini(adev
);
1032 static int cik_sdma_resume(void *handle
)
1034 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1036 return cik_sdma_hw_init(adev
);
1039 static bool cik_sdma_is_idle(void *handle
)
1041 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1042 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1044 if (tmp
& (SRBM_STATUS2__SDMA_BUSY_MASK
|
1045 SRBM_STATUS2__SDMA1_BUSY_MASK
))
1051 static int cik_sdma_wait_for_idle(void *handle
)
1055 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1057 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1058 tmp
= RREG32(mmSRBM_STATUS2
) & (SRBM_STATUS2__SDMA_BUSY_MASK
|
1059 SRBM_STATUS2__SDMA1_BUSY_MASK
);
1068 static int cik_sdma_soft_reset(void *handle
)
1070 u32 srbm_soft_reset
= 0;
1071 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1072 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1074 if (tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
) {
1076 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
1077 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1078 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
1079 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK
;
1081 if (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
) {
1083 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
1084 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1085 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
1086 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK
;
1089 if (srbm_soft_reset
) {
1090 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1091 tmp
|= srbm_soft_reset
;
1092 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1093 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1094 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1098 tmp
&= ~srbm_soft_reset
;
1099 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1100 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1102 /* Wait a little for things to settle down */
1109 static int cik_sdma_set_trap_irq_state(struct amdgpu_device
*adev
,
1110 struct amdgpu_irq_src
*src
,
1112 enum amdgpu_interrupt_state state
)
1117 case AMDGPU_SDMA_IRQ_TRAP0
:
1119 case AMDGPU_IRQ_STATE_DISABLE
:
1120 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1121 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1122 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1124 case AMDGPU_IRQ_STATE_ENABLE
:
1125 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1126 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1127 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1133 case AMDGPU_SDMA_IRQ_TRAP1
:
1135 case AMDGPU_IRQ_STATE_DISABLE
:
1136 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1137 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1138 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1140 case AMDGPU_IRQ_STATE_ENABLE
:
1141 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1142 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1143 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1155 static int cik_sdma_process_trap_irq(struct amdgpu_device
*adev
,
1156 struct amdgpu_irq_src
*source
,
1157 struct amdgpu_iv_entry
*entry
)
1159 u8 instance_id
, queue_id
;
1161 instance_id
= (entry
->ring_id
& 0x3) >> 0;
1162 queue_id
= (entry
->ring_id
& 0xc) >> 2;
1163 DRM_DEBUG("IH: SDMA trap\n");
1164 switch (instance_id
) {
1168 amdgpu_fence_process(&adev
->sdma
.instance
[0].ring
);
1181 amdgpu_fence_process(&adev
->sdma
.instance
[1].ring
);
1196 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1197 struct amdgpu_irq_src
*source
,
1198 struct amdgpu_iv_entry
*entry
)
1200 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1201 schedule_work(&adev
->reset_work
);
1205 static int cik_sdma_set_clockgating_state(void *handle
,
1206 enum amd_clockgating_state state
)
1209 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1211 if (state
== AMD_CG_STATE_GATE
)
1214 cik_enable_sdma_mgcg(adev
, gate
);
1215 cik_enable_sdma_mgls(adev
, gate
);
1220 static int cik_sdma_set_powergating_state(void *handle
,
1221 enum amd_powergating_state state
)
1226 const struct amd_ip_funcs cik_sdma_ip_funcs
= {
1228 .early_init
= cik_sdma_early_init
,
1230 .sw_init
= cik_sdma_sw_init
,
1231 .sw_fini
= cik_sdma_sw_fini
,
1232 .hw_init
= cik_sdma_hw_init
,
1233 .hw_fini
= cik_sdma_hw_fini
,
1234 .suspend
= cik_sdma_suspend
,
1235 .resume
= cik_sdma_resume
,
1236 .is_idle
= cik_sdma_is_idle
,
1237 .wait_for_idle
= cik_sdma_wait_for_idle
,
1238 .soft_reset
= cik_sdma_soft_reset
,
1239 .set_clockgating_state
= cik_sdma_set_clockgating_state
,
1240 .set_powergating_state
= cik_sdma_set_powergating_state
,
1243 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs
= {
1244 .get_rptr
= cik_sdma_ring_get_rptr
,
1245 .get_wptr
= cik_sdma_ring_get_wptr
,
1246 .set_wptr
= cik_sdma_ring_set_wptr
,
1248 .emit_ib
= cik_sdma_ring_emit_ib
,
1249 .emit_fence
= cik_sdma_ring_emit_fence
,
1250 .emit_pipeline_sync
= cik_sdma_ring_emit_pipeline_sync
,
1251 .emit_vm_flush
= cik_sdma_ring_emit_vm_flush
,
1252 .emit_hdp_flush
= cik_sdma_ring_emit_hdp_flush
,
1253 .emit_hdp_invalidate
= cik_sdma_ring_emit_hdp_invalidate
,
1254 .test_ring
= cik_sdma_ring_test_ring
,
1255 .test_ib
= cik_sdma_ring_test_ib
,
1256 .insert_nop
= cik_sdma_ring_insert_nop
,
1257 .pad_ib
= cik_sdma_ring_pad_ib
,
1260 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
)
1264 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1265 adev
->sdma
.instance
[i
].ring
.funcs
= &cik_sdma_ring_funcs
;
1268 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs
= {
1269 .set
= cik_sdma_set_trap_irq_state
,
1270 .process
= cik_sdma_process_trap_irq
,
1273 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs
= {
1274 .process
= cik_sdma_process_illegal_inst_irq
,
1277 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
)
1279 adev
->sdma
.trap_irq
.num_types
= AMDGPU_SDMA_IRQ_LAST
;
1280 adev
->sdma
.trap_irq
.funcs
= &cik_sdma_trap_irq_funcs
;
1281 adev
->sdma
.illegal_inst_irq
.funcs
= &cik_sdma_illegal_inst_irq_funcs
;
1285 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1287 * @ring: amdgpu_ring structure holding ring information
1288 * @src_offset: src GPU address
1289 * @dst_offset: dst GPU address
1290 * @byte_count: number of bytes to xfer
1292 * Copy GPU buffers using the DMA engine (CIK).
1293 * Used by the amdgpu ttm implementation to move pages if
1294 * registered as the asic copy callback.
1296 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib
*ib
,
1297 uint64_t src_offset
,
1298 uint64_t dst_offset
,
1299 uint32_t byte_count
)
1301 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_COPY
, SDMA_COPY_SUB_OPCODE_LINEAR
, 0);
1302 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1303 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1304 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src_offset
);
1305 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src_offset
);
1306 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1307 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1311 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1313 * @ring: amdgpu_ring structure holding ring information
1314 * @src_data: value to write to buffer
1315 * @dst_offset: dst GPU address
1316 * @byte_count: number of bytes to xfer
1318 * Fill GPU buffers using the DMA engine (CIK).
1320 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib
*ib
,
1322 uint64_t dst_offset
,
1323 uint32_t byte_count
)
1325 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL
, 0, 0);
1326 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1327 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1328 ib
->ptr
[ib
->length_dw
++] = src_data
;
1329 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1332 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs
= {
1333 .copy_max_bytes
= 0x1fffff,
1335 .emit_copy_buffer
= cik_sdma_emit_copy_buffer
,
1337 .fill_max_bytes
= 0x1fffff,
1339 .emit_fill_buffer
= cik_sdma_emit_fill_buffer
,
1342 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
)
1344 if (adev
->mman
.buffer_funcs
== NULL
) {
1345 adev
->mman
.buffer_funcs
= &cik_sdma_buffer_funcs
;
1346 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
.instance
[0].ring
;
1350 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs
= {
1351 .copy_pte
= cik_sdma_vm_copy_pte
,
1352 .write_pte
= cik_sdma_vm_write_pte
,
1353 .set_pte_pde
= cik_sdma_vm_set_pte_pde
,
1356 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1360 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1361 adev
->vm_manager
.vm_pte_funcs
= &cik_sdma_vm_pte_funcs
;
1362 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1363 adev
->vm_manager
.vm_pte_rings
[i
] =
1364 &adev
->sdma
.instance
[i
].ring
;
1366 adev
->vm_manager
.vm_pte_num_rings
= adev
->sdma
.num_instances
;