2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "bif/bif_4_1_d.h"
33 #include "bif/bif_4_1_sh_mask.h"
35 #include "gca/gfx_7_2_d.h"
36 #include "gca/gfx_7_2_enum.h"
37 #include "gca/gfx_7_2_sh_mask.h"
39 #include "gmc/gmc_7_1_d.h"
40 #include "gmc/gmc_7_1_sh_mask.h"
42 #include "oss/oss_2_0_d.h"
43 #include "oss/oss_2_0_sh_mask.h"
45 static const u32 sdma_offsets
[SDMA_MAX_INSTANCE
] =
47 SDMA0_REGISTER_OFFSET
,
51 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
);
52 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
);
53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
);
54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
);
56 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
57 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
58 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
59 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
60 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
61 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
62 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
63 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
64 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
65 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
67 u32
amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device
*adev
);
70 static void cik_sdma_free_microcode(struct amdgpu_device
*adev
)
73 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
74 release_firmware(adev
->sdma
.instance
[i
].fw
);
75 adev
->sdma
.instance
[i
].fw
= NULL
;
81 * Starting with CIK, the GPU has new asynchronous
82 * DMA engines. These engines are used for compute
83 * and gfx. There are two DMA engines (SDMA0, SDMA1)
84 * and each one supports 1 ring buffer used for gfx
85 * and 2 queues used for compute.
87 * The programming model is very similar to the CP
88 * (ring buffer, IBs, etc.), but sDMA has it's own
89 * packet format that is different from the PM4 format
90 * used by the CP. sDMA supports copying data, writing
91 * embedded data, solid fills, and a number of other
92 * things. It also has support for tiling/detiling of
97 * cik_sdma_init_microcode - load ucode images from disk
99 * @adev: amdgpu_device pointer
101 * Use the firmware interface to load the ucode images into
102 * the driver (not loaded into hw).
103 * Returns 0 on success, error on failure.
105 static int cik_sdma_init_microcode(struct amdgpu_device
*adev
)
107 const char *chip_name
;
113 switch (adev
->asic_type
) {
115 chip_name
= "bonaire";
118 chip_name
= "hawaii";
121 chip_name
= "kaveri";
124 chip_name
= "kabini";
127 chip_name
= "mullins";
132 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
134 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma.bin", chip_name
);
136 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma1.bin", chip_name
);
137 err
= request_firmware(&adev
->sdma
.instance
[i
].fw
, fw_name
, adev
->dev
);
140 err
= amdgpu_ucode_validate(adev
->sdma
.instance
[i
].fw
);
145 "cik_sdma: Failed to load firmware \"%s\"\n",
147 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
148 release_firmware(adev
->sdma
.instance
[i
].fw
);
149 adev
->sdma
.instance
[i
].fw
= NULL
;
156 * cik_sdma_ring_get_rptr - get the current read pointer
158 * @ring: amdgpu ring pointer
160 * Get the current rptr from the hardware (CIK+).
162 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring
*ring
)
166 rptr
= ring
->adev
->wb
.wb
[ring
->rptr_offs
];
168 return (rptr
& 0x3fffc) >> 2;
172 * cik_sdma_ring_get_wptr - get the current write pointer
174 * @ring: amdgpu ring pointer
176 * Get the current wptr from the hardware (CIK+).
178 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring
*ring
)
180 struct amdgpu_device
*adev
= ring
->adev
;
181 u32 me
= (ring
== &adev
->sdma
.instance
[0].ring
) ? 0 : 1;
183 return (RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
]) & 0x3fffc) >> 2;
187 * cik_sdma_ring_set_wptr - commit the write pointer
189 * @ring: amdgpu ring pointer
191 * Write the wptr back to the hardware (CIK+).
193 static void cik_sdma_ring_set_wptr(struct amdgpu_ring
*ring
)
195 struct amdgpu_device
*adev
= ring
->adev
;
196 u32 me
= (ring
== &adev
->sdma
.instance
[0].ring
) ? 0 : 1;
198 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
], (ring
->wptr
<< 2) & 0x3fffc);
201 static void cik_sdma_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
203 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
206 for (i
= 0; i
< count
; i
++)
207 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
208 amdgpu_ring_write(ring
, ring
->nop
|
209 SDMA_NOP_COUNT(count
- 1));
211 amdgpu_ring_write(ring
, ring
->nop
);
215 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
217 * @ring: amdgpu ring pointer
218 * @ib: IB object to schedule
220 * Schedule an IB in the DMA ring (CIK).
222 static void cik_sdma_ring_emit_ib(struct amdgpu_ring
*ring
,
223 struct amdgpu_ib
*ib
,
224 unsigned vm_id
, bool ctx_switch
)
226 u32 extra_bits
= vm_id
& 0xf;
228 /* IB packet must end on a 8 DW boundary */
229 cik_sdma_ring_insert_nop(ring
, (12 - (ring
->wptr
& 7)) % 8);
231 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER
, 0, extra_bits
));
232 amdgpu_ring_write(ring
, ib
->gpu_addr
& 0xffffffe0); /* base must be 32 byte aligned */
233 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xffffffff);
234 amdgpu_ring_write(ring
, ib
->length_dw
);
239 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
241 * @ring: amdgpu ring pointer
243 * Emit an hdp flush packet on the requested DMA ring.
245 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
247 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
248 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
251 if (ring
== &ring
->adev
->sdma
.instance
[0].ring
)
252 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA0_MASK
;
254 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA1_MASK
;
256 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
257 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
<< 2);
258 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
<< 2);
259 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
260 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
261 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
264 static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring
*ring
)
266 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
267 amdgpu_ring_write(ring
, mmHDP_DEBUG0
);
268 amdgpu_ring_write(ring
, 1);
272 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
274 * @ring: amdgpu ring pointer
275 * @fence: amdgpu fence object
277 * Add a DMA fence packet to the ring to write
278 * the fence seq number and DMA trap packet to generate
279 * an interrupt if needed (CIK).
281 static void cik_sdma_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
284 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
285 /* write the fence */
286 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
287 amdgpu_ring_write(ring
, lower_32_bits(addr
));
288 amdgpu_ring_write(ring
, upper_32_bits(addr
));
289 amdgpu_ring_write(ring
, lower_32_bits(seq
));
291 /* optionally write high bits as well */
294 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
295 amdgpu_ring_write(ring
, lower_32_bits(addr
));
296 amdgpu_ring_write(ring
, upper_32_bits(addr
));
297 amdgpu_ring_write(ring
, upper_32_bits(seq
));
300 /* generate an interrupt */
301 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_TRAP
, 0, 0));
305 * cik_sdma_gfx_stop - stop the gfx async dma engines
307 * @adev: amdgpu_device pointer
309 * Stop the gfx async dma ring buffers (CIK).
311 static void cik_sdma_gfx_stop(struct amdgpu_device
*adev
)
313 struct amdgpu_ring
*sdma0
= &adev
->sdma
.instance
[0].ring
;
314 struct amdgpu_ring
*sdma1
= &adev
->sdma
.instance
[1].ring
;
318 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
319 (adev
->mman
.buffer_funcs_ring
== sdma1
))
320 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
322 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
323 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
324 rb_cntl
&= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
;
325 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
326 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], 0);
328 sdma0
->ready
= false;
329 sdma1
->ready
= false;
333 * cik_sdma_rlc_stop - stop the compute async dma engines
335 * @adev: amdgpu_device pointer
337 * Stop the compute async dma queues (CIK).
339 static void cik_sdma_rlc_stop(struct amdgpu_device
*adev
)
345 * cik_sdma_enable - stop the async dma engines
347 * @adev: amdgpu_device pointer
348 * @enable: enable/disable the DMA MEs.
350 * Halt or unhalt the async dma engines (CIK).
352 static void cik_sdma_enable(struct amdgpu_device
*adev
, bool enable
)
358 cik_sdma_gfx_stop(adev
);
359 cik_sdma_rlc_stop(adev
);
362 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
363 me_cntl
= RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]);
365 me_cntl
&= ~SDMA0_F32_CNTL__HALT_MASK
;
367 me_cntl
|= SDMA0_F32_CNTL__HALT_MASK
;
368 WREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
], me_cntl
);
373 * cik_sdma_gfx_resume - setup and start the async dma engines
375 * @adev: amdgpu_device pointer
377 * Set up the gfx DMA ring buffers and enable them (CIK).
378 * Returns 0 for success, error for failure.
380 static int cik_sdma_gfx_resume(struct amdgpu_device
*adev
)
382 struct amdgpu_ring
*ring
;
383 u32 rb_cntl
, ib_cntl
;
388 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
389 ring
= &adev
->sdma
.instance
[i
].ring
;
390 wb_offset
= (ring
->rptr_offs
* 4);
392 mutex_lock(&adev
->srbm_mutex
);
393 for (j
= 0; j
< 16; j
++) {
394 cik_srbm_select(adev
, 0, 0, 0, j
);
396 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
], 0);
397 WREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
], 0);
398 /* XXX SDMA RLC - todo */
400 cik_srbm_select(adev
, 0, 0, 0, 0);
401 mutex_unlock(&adev
->srbm_mutex
);
403 WREG32(mmSDMA0_TILING_CONFIG
+ sdma_offsets
[i
],
404 adev
->gfx
.config
.gb_addr_config
& 0x70);
406 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL
+ sdma_offsets
[i
], 0);
407 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
], 0);
409 /* Set ring buffer size in dwords */
410 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
411 rb_cntl
= rb_bufsz
<< 1;
413 rb_cntl
|= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK
|
414 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK
;
416 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
418 /* Initialize the ring buffer's read and write pointers */
419 WREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
], 0);
420 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], 0);
421 WREG32(mmSDMA0_GFX_IB_RPTR
+ sdma_offsets
[i
], 0);
422 WREG32(mmSDMA0_GFX_IB_OFFSET
+ sdma_offsets
[i
], 0);
424 /* set the wb address whether it's enabled or not */
425 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
],
426 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
427 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
],
428 ((adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC));
430 rb_cntl
|= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK
;
432 WREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
], ring
->gpu_addr
>> 8);
433 WREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
], ring
->gpu_addr
>> 40);
436 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], ring
->wptr
<< 2);
439 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
],
440 rb_cntl
| SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
);
442 ib_cntl
= SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK
;
444 ib_cntl
|= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK
;
447 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
452 cik_sdma_enable(adev
, true);
454 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
455 ring
= &adev
->sdma
.instance
[i
].ring
;
456 r
= amdgpu_ring_test_ring(ring
);
462 if (adev
->mman
.buffer_funcs_ring
== ring
)
463 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.real_vram_size
);
470 * cik_sdma_rlc_resume - setup and start the async dma engines
472 * @adev: amdgpu_device pointer
474 * Set up the compute DMA queues and enable them (CIK).
475 * Returns 0 for success, error for failure.
477 static int cik_sdma_rlc_resume(struct amdgpu_device
*adev
)
484 * cik_sdma_load_microcode - load the sDMA ME ucode
486 * @adev: amdgpu_device pointer
488 * Loads the sDMA0/1 ucode.
489 * Returns 0 for success, -EINVAL if the ucode is not available.
491 static int cik_sdma_load_microcode(struct amdgpu_device
*adev
)
493 const struct sdma_firmware_header_v1_0
*hdr
;
494 const __le32
*fw_data
;
499 cik_sdma_enable(adev
, false);
501 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
502 if (!adev
->sdma
.instance
[i
].fw
)
504 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
505 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
506 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
507 adev
->sdma
.instance
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
508 adev
->sdma
.instance
[i
].feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
509 if (adev
->sdma
.instance
[i
].feature_version
>= 20)
510 adev
->sdma
.instance
[i
].burst_nop
= true;
511 fw_data
= (const __le32
*)
512 (adev
->sdma
.instance
[i
].fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
513 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], 0);
514 for (j
= 0; j
< fw_size
; j
++)
515 WREG32(mmSDMA0_UCODE_DATA
+ sdma_offsets
[i
], le32_to_cpup(fw_data
++));
516 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], adev
->sdma
.instance
[i
].fw_version
);
523 * cik_sdma_start - setup and start the async dma engines
525 * @adev: amdgpu_device pointer
527 * Set up the DMA engines and enable them (CIK).
528 * Returns 0 for success, error for failure.
530 static int cik_sdma_start(struct amdgpu_device
*adev
)
534 r
= cik_sdma_load_microcode(adev
);
538 /* halt the engine before programing */
539 cik_sdma_enable(adev
, false);
541 /* start the gfx rings and rlc compute queues */
542 r
= cik_sdma_gfx_resume(adev
);
545 r
= cik_sdma_rlc_resume(adev
);
553 * cik_sdma_ring_test_ring - simple async dma engine test
555 * @ring: amdgpu_ring structure holding ring information
557 * Test the DMA engine by writing using it to write an
558 * value to memory. (CIK).
559 * Returns 0 for success, error for failure.
561 static int cik_sdma_ring_test_ring(struct amdgpu_ring
*ring
)
563 struct amdgpu_device
*adev
= ring
->adev
;
570 r
= amdgpu_wb_get(adev
, &index
);
572 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
576 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
578 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
580 r
= amdgpu_ring_alloc(ring
, 5);
582 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
583 amdgpu_wb_free(adev
, index
);
586 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0));
587 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
588 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
589 amdgpu_ring_write(ring
, 1); /* number of DWs to follow */
590 amdgpu_ring_write(ring
, 0xDEADBEEF);
591 amdgpu_ring_commit(ring
);
593 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
594 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
595 if (tmp
== 0xDEADBEEF)
600 if (i
< adev
->usec_timeout
) {
601 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
603 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
607 amdgpu_wb_free(adev
, index
);
613 * cik_sdma_ring_test_ib - test an IB on the DMA engine
615 * @ring: amdgpu_ring structure holding ring information
617 * Test a simple IB in the DMA ring (CIK).
618 * Returns 0 on success, error on failure.
620 static int cik_sdma_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
622 struct amdgpu_device
*adev
= ring
->adev
;
624 struct fence
*f
= NULL
;
630 r
= amdgpu_wb_get(adev
, &index
);
632 dev_err(adev
->dev
, "(%ld) failed to allocate wb slot\n", r
);
636 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
638 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
639 memset(&ib
, 0, sizeof(ib
));
640 r
= amdgpu_ib_get(adev
, NULL
, 256, &ib
);
642 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r
);
646 ib
.ptr
[0] = SDMA_PACKET(SDMA_OPCODE_WRITE
,
647 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
648 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
649 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
651 ib
.ptr
[4] = 0xDEADBEEF;
653 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, NULL
, &f
);
657 r
= fence_wait_timeout(f
, false, timeout
);
659 DRM_ERROR("amdgpu: IB test timed out\n");
663 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
666 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
667 if (tmp
== 0xDEADBEEF) {
668 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
671 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp
);
676 amdgpu_ib_free(adev
, &ib
, NULL
);
679 amdgpu_wb_free(adev
, index
);
684 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
686 * @ib: indirect buffer to fill with commands
687 * @pe: addr of the page entry
688 * @src: src addr to copy from
689 * @count: number of page entries to update
691 * Update PTEs by copying them from the GART using sDMA (CIK).
693 static void cik_sdma_vm_copy_pte(struct amdgpu_ib
*ib
,
694 uint64_t pe
, uint64_t src
,
698 unsigned bytes
= count
* 8;
699 if (bytes
> 0x1FFFF8)
702 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_COPY
,
703 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
704 ib
->ptr
[ib
->length_dw
++] = bytes
;
705 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
706 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
707 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
708 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
709 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
718 * cik_sdma_vm_write_pages - update PTEs by writing them manually
720 * @ib: indirect buffer to fill with commands
721 * @pe: addr of the page entry
722 * @addr: dst addr to write into pe
723 * @count: number of page entries to update
724 * @incr: increase next addr by incr bytes
725 * @flags: access flags
727 * Update PTEs by writing them manually using sDMA (CIK).
729 static void cik_sdma_vm_write_pte(struct amdgpu_ib
*ib
,
730 const dma_addr_t
*pages_addr
, uint64_t pe
,
731 uint64_t addr
, unsigned count
,
732 uint32_t incr
, uint32_t flags
)
742 /* for non-physically contiguous pages (system) */
743 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_WRITE
,
744 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
745 ib
->ptr
[ib
->length_dw
++] = pe
;
746 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
747 ib
->ptr
[ib
->length_dw
++] = ndw
;
748 for (; ndw
> 0; ndw
-= 2, --count
, pe
+= 8) {
749 value
= amdgpu_vm_map_gart(pages_addr
, addr
);
752 ib
->ptr
[ib
->length_dw
++] = value
;
753 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
759 * cik_sdma_vm_set_pages - update the page tables using sDMA
761 * @ib: indirect buffer to fill with commands
762 * @pe: addr of the page entry
763 * @addr: dst addr to write into pe
764 * @count: number of page entries to update
765 * @incr: increase next addr by incr bytes
766 * @flags: access flags
768 * Update the page tables using sDMA (CIK).
770 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib
*ib
,
772 uint64_t addr
, unsigned count
,
773 uint32_t incr
, uint32_t flags
)
783 if (flags
& AMDGPU_PTE_VALID
)
788 /* for physically contiguous pages (vram) */
789 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE
, 0, 0);
790 ib
->ptr
[ib
->length_dw
++] = pe
; /* dst addr */
791 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
792 ib
->ptr
[ib
->length_dw
++] = flags
; /* mask */
793 ib
->ptr
[ib
->length_dw
++] = 0;
794 ib
->ptr
[ib
->length_dw
++] = value
; /* value */
795 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
796 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
797 ib
->ptr
[ib
->length_dw
++] = 0;
798 ib
->ptr
[ib
->length_dw
++] = ndw
; /* number of entries */
807 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
809 * @ib: indirect buffer to fill with padding
812 static void cik_sdma_ring_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
)
814 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
818 pad_count
= (8 - (ib
->length_dw
& 0x7)) % 8;
819 for (i
= 0; i
< pad_count
; i
++)
820 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
821 ib
->ptr
[ib
->length_dw
++] =
822 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0) |
823 SDMA_NOP_COUNT(pad_count
- 1);
825 ib
->ptr
[ib
->length_dw
++] =
826 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0);
830 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
832 * @ring: amdgpu_ring pointer
834 * Make sure all previous operations are completed (CIK).
836 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring
*ring
)
838 uint32_t seq
= ring
->fence_drv
.sync_seq
;
839 uint64_t addr
= ring
->fence_drv
.gpu_addr
;
842 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0,
843 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
844 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
845 SDMA_POLL_REG_MEM_EXTRA_M
));
846 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
847 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
848 amdgpu_ring_write(ring
, seq
); /* reference */
849 amdgpu_ring_write(ring
, 0xfffffff); /* mask */
850 amdgpu_ring_write(ring
, (0xfff << 16) | 4); /* retry count, poll interval */
854 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
856 * @ring: amdgpu_ring pointer
857 * @vm: amdgpu_vm pointer
859 * Update the page table base and flush the VM TLB
862 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
863 unsigned vm_id
, uint64_t pd_addr
)
865 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
866 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
868 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
870 amdgpu_ring_write(ring
, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
872 amdgpu_ring_write(ring
, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
874 amdgpu_ring_write(ring
, pd_addr
>> 12);
877 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
878 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
879 amdgpu_ring_write(ring
, 1 << vm_id
);
881 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
882 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
<< 2);
883 amdgpu_ring_write(ring
, 0);
884 amdgpu_ring_write(ring
, 0); /* reference */
885 amdgpu_ring_write(ring
, 0); /* mask */
886 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
889 static void cik_enable_sdma_mgcg(struct amdgpu_device
*adev
,
894 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_MGCG
)) {
895 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, 0x00000100);
896 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, 0x00000100);
898 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
);
901 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, data
);
903 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
);
906 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, data
);
910 static void cik_enable_sdma_mgls(struct amdgpu_device
*adev
,
915 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_LS
)) {
916 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
919 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
921 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
924 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
926 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
929 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
931 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
934 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
938 static int cik_sdma_early_init(void *handle
)
940 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
942 adev
->sdma
.num_instances
= SDMA_MAX_INSTANCE
;
944 cik_sdma_set_ring_funcs(adev
);
945 cik_sdma_set_irq_funcs(adev
);
946 cik_sdma_set_buffer_funcs(adev
);
947 cik_sdma_set_vm_pte_funcs(adev
);
952 static int cik_sdma_sw_init(void *handle
)
954 struct amdgpu_ring
*ring
;
955 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
958 r
= cik_sdma_init_microcode(adev
);
960 DRM_ERROR("Failed to load sdma firmware!\n");
964 /* SDMA trap event */
965 r
= amdgpu_irq_add_id(adev
, 224, &adev
->sdma
.trap_irq
);
969 /* SDMA Privileged inst */
970 r
= amdgpu_irq_add_id(adev
, 241, &adev
->sdma
.illegal_inst_irq
);
974 /* SDMA Privileged inst */
975 r
= amdgpu_irq_add_id(adev
, 247, &adev
->sdma
.illegal_inst_irq
);
979 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
980 ring
= &adev
->sdma
.instance
[i
].ring
;
981 ring
->ring_obj
= NULL
;
982 sprintf(ring
->name
, "sdma%d", i
);
983 r
= amdgpu_ring_init(adev
, ring
, 1024,
984 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0), 0xf,
985 &adev
->sdma
.trap_irq
,
987 AMDGPU_SDMA_IRQ_TRAP0
: AMDGPU_SDMA_IRQ_TRAP1
,
988 AMDGPU_RING_TYPE_SDMA
);
996 static int cik_sdma_sw_fini(void *handle
)
998 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1001 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1002 amdgpu_ring_fini(&adev
->sdma
.instance
[i
].ring
);
1004 cik_sdma_free_microcode(adev
);
1008 static int cik_sdma_hw_init(void *handle
)
1011 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1013 r
= cik_sdma_start(adev
);
1020 static int cik_sdma_hw_fini(void *handle
)
1022 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1024 cik_sdma_enable(adev
, false);
1029 static int cik_sdma_suspend(void *handle
)
1031 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1033 return cik_sdma_hw_fini(adev
);
1036 static int cik_sdma_resume(void *handle
)
1038 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1040 return cik_sdma_hw_init(adev
);
1043 static bool cik_sdma_is_idle(void *handle
)
1045 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1046 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1048 if (tmp
& (SRBM_STATUS2__SDMA_BUSY_MASK
|
1049 SRBM_STATUS2__SDMA1_BUSY_MASK
))
1055 static int cik_sdma_wait_for_idle(void *handle
)
1059 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1061 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1062 tmp
= RREG32(mmSRBM_STATUS2
) & (SRBM_STATUS2__SDMA_BUSY_MASK
|
1063 SRBM_STATUS2__SDMA1_BUSY_MASK
);
1072 static int cik_sdma_soft_reset(void *handle
)
1074 u32 srbm_soft_reset
= 0;
1075 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1076 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1078 if (tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
) {
1080 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
1081 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1082 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
1083 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK
;
1085 if (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
) {
1087 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
1088 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1089 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
1090 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK
;
1093 if (srbm_soft_reset
) {
1094 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1095 tmp
|= srbm_soft_reset
;
1096 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1097 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1098 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1102 tmp
&= ~srbm_soft_reset
;
1103 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1104 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1106 /* Wait a little for things to settle down */
1113 static int cik_sdma_set_trap_irq_state(struct amdgpu_device
*adev
,
1114 struct amdgpu_irq_src
*src
,
1116 enum amdgpu_interrupt_state state
)
1121 case AMDGPU_SDMA_IRQ_TRAP0
:
1123 case AMDGPU_IRQ_STATE_DISABLE
:
1124 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1125 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1126 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1128 case AMDGPU_IRQ_STATE_ENABLE
:
1129 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1130 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1131 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1137 case AMDGPU_SDMA_IRQ_TRAP1
:
1139 case AMDGPU_IRQ_STATE_DISABLE
:
1140 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1141 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1142 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1144 case AMDGPU_IRQ_STATE_ENABLE
:
1145 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1146 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1147 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1159 static int cik_sdma_process_trap_irq(struct amdgpu_device
*adev
,
1160 struct amdgpu_irq_src
*source
,
1161 struct amdgpu_iv_entry
*entry
)
1163 u8 instance_id
, queue_id
;
1165 instance_id
= (entry
->ring_id
& 0x3) >> 0;
1166 queue_id
= (entry
->ring_id
& 0xc) >> 2;
1167 DRM_DEBUG("IH: SDMA trap\n");
1168 switch (instance_id
) {
1172 amdgpu_fence_process(&adev
->sdma
.instance
[0].ring
);
1185 amdgpu_fence_process(&adev
->sdma
.instance
[1].ring
);
1200 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1201 struct amdgpu_irq_src
*source
,
1202 struct amdgpu_iv_entry
*entry
)
1204 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1205 schedule_work(&adev
->reset_work
);
1209 static int cik_sdma_set_clockgating_state(void *handle
,
1210 enum amd_clockgating_state state
)
1213 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1215 if (state
== AMD_CG_STATE_GATE
)
1218 cik_enable_sdma_mgcg(adev
, gate
);
1219 cik_enable_sdma_mgls(adev
, gate
);
1224 static int cik_sdma_set_powergating_state(void *handle
,
1225 enum amd_powergating_state state
)
1230 const struct amd_ip_funcs cik_sdma_ip_funcs
= {
1232 .early_init
= cik_sdma_early_init
,
1234 .sw_init
= cik_sdma_sw_init
,
1235 .sw_fini
= cik_sdma_sw_fini
,
1236 .hw_init
= cik_sdma_hw_init
,
1237 .hw_fini
= cik_sdma_hw_fini
,
1238 .suspend
= cik_sdma_suspend
,
1239 .resume
= cik_sdma_resume
,
1240 .is_idle
= cik_sdma_is_idle
,
1241 .wait_for_idle
= cik_sdma_wait_for_idle
,
1242 .soft_reset
= cik_sdma_soft_reset
,
1243 .set_clockgating_state
= cik_sdma_set_clockgating_state
,
1244 .set_powergating_state
= cik_sdma_set_powergating_state
,
1247 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs
= {
1248 .get_rptr
= cik_sdma_ring_get_rptr
,
1249 .get_wptr
= cik_sdma_ring_get_wptr
,
1250 .set_wptr
= cik_sdma_ring_set_wptr
,
1252 .emit_ib
= cik_sdma_ring_emit_ib
,
1253 .emit_fence
= cik_sdma_ring_emit_fence
,
1254 .emit_pipeline_sync
= cik_sdma_ring_emit_pipeline_sync
,
1255 .emit_vm_flush
= cik_sdma_ring_emit_vm_flush
,
1256 .emit_hdp_flush
= cik_sdma_ring_emit_hdp_flush
,
1257 .emit_hdp_invalidate
= cik_sdma_ring_emit_hdp_invalidate
,
1258 .test_ring
= cik_sdma_ring_test_ring
,
1259 .test_ib
= cik_sdma_ring_test_ib
,
1260 .insert_nop
= cik_sdma_ring_insert_nop
,
1261 .pad_ib
= cik_sdma_ring_pad_ib
,
1264 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
)
1268 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1269 adev
->sdma
.instance
[i
].ring
.funcs
= &cik_sdma_ring_funcs
;
1272 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs
= {
1273 .set
= cik_sdma_set_trap_irq_state
,
1274 .process
= cik_sdma_process_trap_irq
,
1277 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs
= {
1278 .process
= cik_sdma_process_illegal_inst_irq
,
1281 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
)
1283 adev
->sdma
.trap_irq
.num_types
= AMDGPU_SDMA_IRQ_LAST
;
1284 adev
->sdma
.trap_irq
.funcs
= &cik_sdma_trap_irq_funcs
;
1285 adev
->sdma
.illegal_inst_irq
.funcs
= &cik_sdma_illegal_inst_irq_funcs
;
1289 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1291 * @ring: amdgpu_ring structure holding ring information
1292 * @src_offset: src GPU address
1293 * @dst_offset: dst GPU address
1294 * @byte_count: number of bytes to xfer
1296 * Copy GPU buffers using the DMA engine (CIK).
1297 * Used by the amdgpu ttm implementation to move pages if
1298 * registered as the asic copy callback.
1300 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib
*ib
,
1301 uint64_t src_offset
,
1302 uint64_t dst_offset
,
1303 uint32_t byte_count
)
1305 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_COPY
, SDMA_COPY_SUB_OPCODE_LINEAR
, 0);
1306 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1307 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1308 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src_offset
);
1309 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src_offset
);
1310 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1311 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1315 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1317 * @ring: amdgpu_ring structure holding ring information
1318 * @src_data: value to write to buffer
1319 * @dst_offset: dst GPU address
1320 * @byte_count: number of bytes to xfer
1322 * Fill GPU buffers using the DMA engine (CIK).
1324 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib
*ib
,
1326 uint64_t dst_offset
,
1327 uint32_t byte_count
)
1329 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL
, 0, 0);
1330 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1331 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1332 ib
->ptr
[ib
->length_dw
++] = src_data
;
1333 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1336 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs
= {
1337 .copy_max_bytes
= 0x1fffff,
1339 .emit_copy_buffer
= cik_sdma_emit_copy_buffer
,
1341 .fill_max_bytes
= 0x1fffff,
1343 .emit_fill_buffer
= cik_sdma_emit_fill_buffer
,
1346 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
)
1348 if (adev
->mman
.buffer_funcs
== NULL
) {
1349 adev
->mman
.buffer_funcs
= &cik_sdma_buffer_funcs
;
1350 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
.instance
[0].ring
;
1354 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs
= {
1355 .copy_pte
= cik_sdma_vm_copy_pte
,
1356 .write_pte
= cik_sdma_vm_write_pte
,
1357 .set_pte_pde
= cik_sdma_vm_set_pte_pde
,
1360 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1364 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1365 adev
->vm_manager
.vm_pte_funcs
= &cik_sdma_vm_pte_funcs
;
1366 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1367 adev
->vm_manager
.vm_pte_rings
[i
] =
1368 &adev
->sdma
.instance
[i
].ring
;
1370 adev
->vm_manager
.vm_pte_num_rings
= adev
->sdma
.num_instances
;