drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "cikd.h"
  30 #include "cik.h"
  31
  32 #include "bif/bif_4_1_d.h"
  33 #include "bif/bif_4_1_sh_mask.h"
  34
  35 #include "gca/gfx_7_2_d.h"
  36 #include "gca/gfx_7_2_enum.h"
  37 #include "gca/gfx_7_2_sh_mask.h"
  38
  39 #include "gmc/gmc_7_1_d.h"
  40 #include "gmc/gmc_7_1_sh_mask.h"
  41
  42 #include "oss/oss_2_0_d.h"
  43 #include "oss/oss_2_0_sh_mask.h"
  44
  45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  46 {
  47         SDMA0_REGISTER_OFFSET,
  48         SDMA1_REGISTER_OFFSET
  49 };
  50
  51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  55
  56 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
  57 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
  58 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
  59 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
  60 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
  61 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
  62 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
  63 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
  64 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
  65 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
  66
  67 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  68
  69
  70 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
  71 {
  72         int i;
  73         for (i = 0; i < adev->sdma.num_instances; i++) {
  74                         release_firmware(adev->sdma.instance[i].fw);
  75                         adev->sdma.instance[i].fw = NULL;
  76         }
  77 }
  78
  79 /*
  80  * sDMA - System DMA
  81  * Starting with CIK, the GPU has new asynchronous
  82  * DMA engines.  These engines are used for compute
  83  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  84  * and each one supports 1 ring buffer used for gfx
  85  * and 2 queues used for compute.
  86  *
  87  * The programming model is very similar to the CP
  88  * (ring buffer, IBs, etc.), but sDMA has it's own
  89  * packet format that is different from the PM4 format
  90  * used by the CP. sDMA supports copying data, writing
  91  * embedded data, solid fills, and a number of other
  92  * things.  It also has support for tiling/detiling of
  93  * buffers.
  94  */
  95
  96 /**
  97  * cik_sdma_init_microcode - load ucode images from disk
  98  *
  99  * @adev: amdgpu_device pointer
 100  *
 101  * Use the firmware interface to load the ucode images into
 102  * the driver (not loaded into hw).
 103  * Returns 0 on success, error on failure.
 104  */
 105 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
 106 {
 107         const char *chip_name;
 108         char fw_name[30];
 109         int err = 0, i;
 110
 111         DRM_DEBUG("\n");
 112
 113         switch (adev->asic_type) {
 114         case CHIP_BONAIRE:
 115                 chip_name = "bonaire";
 116                 break;
 117         case CHIP_HAWAII:
 118                 chip_name = "hawaii";
 119                 break;
 120         case CHIP_KAVERI:
 121                 chip_name = "kaveri";
 122                 break;
 123         case CHIP_KABINI:
 124                 chip_name = "kabini";
 125                 break;
 126         case CHIP_MULLINS:
 127                 chip_name = "mullins";
 128                 break;
 129         default: BUG();
 130         }
 131
 132         for (i = 0; i < adev->sdma.num_instances; i++) {
 133                 if (i == 0)
 134                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
 135                 else
 136                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
 137                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 138                 if (err)
 139                         goto out;
 140                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 141         }
 142 out:
 143         if (err) {
 144                 printk(KERN_ERR
 145                        "cik_sdma: Failed to load firmware \"%s\"\n",
 146                        fw_name);
 147                 for (i = 0; i < adev->sdma.num_instances; i++) {
 148                         release_firmware(adev->sdma.instance[i].fw);
 149                         adev->sdma.instance[i].fw = NULL;
 150                 }
 151         }
 152         return err;
 153 }
 154
 155 /**
 156  * cik_sdma_ring_get_rptr - get the current read pointer
 157  *
 158  * @ring: amdgpu ring pointer
 159  *
 160  * Get the current rptr from the hardware (CIK+).
 161  */
 162 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 163 {
 164         u32 rptr;
 165
 166         rptr = ring->adev->wb.wb[ring->rptr_offs];
 167
 168         return (rptr & 0x3fffc) >> 2;
 169 }
 170
 171 /**
 172  * cik_sdma_ring_get_wptr - get the current write pointer
 173  *
 174  * @ring: amdgpu ring pointer
 175  *
 176  * Get the current wptr from the hardware (CIK+).
 177  */
 178 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 179 {
 180         struct amdgpu_device *adev = ring->adev;
 181         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 182
 183         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
 184 }
 185
 186 /**
 187  * cik_sdma_ring_set_wptr - commit the write pointer
 188  *
 189  * @ring: amdgpu ring pointer
 190  *
 191  * Write the wptr back to the hardware (CIK+).
 192  */
 193 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 194 {
 195         struct amdgpu_device *adev = ring->adev;
 196         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 197
 198         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
 199 }
 200
 201 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 202 {
 203         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 204         int i;
 205
 206         for (i = 0; i < count; i++)
 207                 if (sdma && sdma->burst_nop && (i == 0))
 208                         amdgpu_ring_write(ring, ring->nop |
 209                                           SDMA_NOP_COUNT(count - 1));
 210                 else
 211                         amdgpu_ring_write(ring, ring->nop);
 212 }
 213
 214 /**
 215  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 216  *
 217  * @ring: amdgpu ring pointer
 218  * @ib: IB object to schedule
 219  *
 220  * Schedule an IB in the DMA ring (CIK).
 221  */
 222 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 223                                   struct amdgpu_ib *ib,
 224                                   unsigned vm_id, bool ctx_switch)
 225 {
 226         u32 extra_bits = vm_id & 0xf;
 227         u32 next_rptr = ring->wptr + 5;
 228
 229         while ((next_rptr & 7) != 4)
 230                 next_rptr++;
 231
 232         next_rptr += 4;
 233         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 234         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
 235         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
 236         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 237         amdgpu_ring_write(ring, next_rptr);
 238
 239         /* IB packet must end on a 8 DW boundary */
 240         cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
 241
 242         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 243         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 244         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 245         amdgpu_ring_write(ring, ib->length_dw);
 246
 247 }
 248
 249 /**
 250  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 251  *
 252  * @ring: amdgpu ring pointer
 253  *
 254  * Emit an hdp flush packet on the requested DMA ring.
 255  */
 256 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 257 {
 258         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 259                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 260         u32 ref_and_mask;
 261
 262         if (ring == &ring->adev->sdma.instance[0].ring)
 263                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 264         else
 265                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 266
 267         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 268         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 269         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 270         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 271         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 272         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 273 }
 274
 275 static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 276 {
 277         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 278         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 279         amdgpu_ring_write(ring, 1);
 280 }
 281
 282 /**
 283  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 284  *
 285  * @ring: amdgpu ring pointer
 286  * @fence: amdgpu fence object
 287  *
 288  * Add a DMA fence packet to the ring to write
 289  * the fence seq number and DMA trap packet to generate
 290  * an interrupt if needed (CIK).
 291  */
 292 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 293                                      unsigned flags)
 294 {
 295         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 296         /* write the fence */
 297         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 298         amdgpu_ring_write(ring, lower_32_bits(addr));
 299         amdgpu_ring_write(ring, upper_32_bits(addr));
 300         amdgpu_ring_write(ring, lower_32_bits(seq));
 301
 302         /* optionally write high bits as well */
 303         if (write64bit) {
 304                 addr += 4;
 305                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 306                 amdgpu_ring_write(ring, lower_32_bits(addr));
 307                 amdgpu_ring_write(ring, upper_32_bits(addr));
 308                 amdgpu_ring_write(ring, upper_32_bits(seq));
 309         }
 310
 311         /* generate an interrupt */
 312         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 313 }
 314
 315 /**
 316  * cik_sdma_gfx_stop - stop the gfx async dma engines
 317  *
 318  * @adev: amdgpu_device pointer
 319  *
 320  * Stop the gfx async dma ring buffers (CIK).
 321  */
 322 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 323 {
 324         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 325         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 326         u32 rb_cntl;
 327         int i;
 328
 329         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 330             (adev->mman.buffer_funcs_ring == sdma1))
 331                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 332
 333         for (i = 0; i < adev->sdma.num_instances; i++) {
 334                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 335                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 336                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 337                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 338         }
 339         sdma0->ready = false;
 340         sdma1->ready = false;
 341 }
 342
 343 /**
 344  * cik_sdma_rlc_stop - stop the compute async dma engines
 345  *
 346  * @adev: amdgpu_device pointer
 347  *
 348  * Stop the compute async dma queues (CIK).
 349  */
 350 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 351 {
 352         /* XXX todo */
 353 }
 354
 355 /**
 356  * cik_sdma_enable - stop the async dma engines
 357  *
 358  * @adev: amdgpu_device pointer
 359  * @enable: enable/disable the DMA MEs.
 360  *
 361  * Halt or unhalt the async dma engines (CIK).
 362  */
 363 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 364 {
 365         u32 me_cntl;
 366         int i;
 367
 368         if (enable == false) {
 369                 cik_sdma_gfx_stop(adev);
 370                 cik_sdma_rlc_stop(adev);
 371         }
 372
 373         for (i = 0; i < adev->sdma.num_instances; i++) {
 374                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 375                 if (enable)
 376                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 377                 else
 378                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 379                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 380         }
 381 }
 382
 383 /**
 384  * cik_sdma_gfx_resume - setup and start the async dma engines
 385  *
 386  * @adev: amdgpu_device pointer
 387  *
 388  * Set up the gfx DMA ring buffers and enable them (CIK).
 389  * Returns 0 for success, error for failure.
 390  */
 391 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 392 {
 393         struct amdgpu_ring *ring;
 394         u32 rb_cntl, ib_cntl;
 395         u32 rb_bufsz;
 396         u32 wb_offset;
 397         int i, j, r;
 398
 399         for (i = 0; i < adev->sdma.num_instances; i++) {
 400                 ring = &adev->sdma.instance[i].ring;
 401                 wb_offset = (ring->rptr_offs * 4);
 402
 403                 mutex_lock(&adev->srbm_mutex);
 404                 for (j = 0; j < 16; j++) {
 405                         cik_srbm_select(adev, 0, 0, 0, j);
 406                         /* SDMA GFX */
 407                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 408                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 409                         /* XXX SDMA RLC - todo */
 410                 }
 411                 cik_srbm_select(adev, 0, 0, 0, 0);
 412                 mutex_unlock(&adev->srbm_mutex);
 413
 414                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 415                        adev->gfx.config.gb_addr_config & 0x70);
 416
 417                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 418                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 419
 420                 /* Set ring buffer size in dwords */
 421                 rb_bufsz = order_base_2(ring->ring_size / 4);
 422                 rb_cntl = rb_bufsz << 1;
 423 #ifdef __BIG_ENDIAN
 424                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 425                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 426 #endif
 427                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 428
 429                 /* Initialize the ring buffer's read and write pointers */
 430                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 431                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 432                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 433                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 434
 435                 /* set the wb address whether it's enabled or not */
 436                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 437                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 438                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 439                        ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 440
 441                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 442
 443                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 444                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 445
 446                 ring->wptr = 0;
 447                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 448
 449                 /* enable DMA RB */
 450                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 451                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 452
 453                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 454 #ifdef __BIG_ENDIAN
 455                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 456 #endif
 457                 /* enable DMA IBs */
 458                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 459
 460                 ring->ready = true;
 461         }
 462
 463         cik_sdma_enable(adev, true);
 464
 465         for (i = 0; i < adev->sdma.num_instances; i++) {
 466                 ring = &adev->sdma.instance[i].ring;
 467                 r = amdgpu_ring_test_ring(ring);
 468                 if (r) {
 469                         ring->ready = false;
 470                         return r;
 471                 }
 472
 473                 if (adev->mman.buffer_funcs_ring == ring)
 474                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 475         }
 476
 477         return 0;
 478 }
 479
 480 /**
 481  * cik_sdma_rlc_resume - setup and start the async dma engines
 482  *
 483  * @adev: amdgpu_device pointer
 484  *
 485  * Set up the compute DMA queues and enable them (CIK).
 486  * Returns 0 for success, error for failure.
 487  */
 488 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 489 {
 490         /* XXX todo */
 491         return 0;
 492 }
 493
 494 /**
 495  * cik_sdma_load_microcode - load the sDMA ME ucode
 496  *
 497  * @adev: amdgpu_device pointer
 498  *
 499  * Loads the sDMA0/1 ucode.
 500  * Returns 0 for success, -EINVAL if the ucode is not available.
 501  */
 502 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 503 {
 504         const struct sdma_firmware_header_v1_0 *hdr;
 505         const __le32 *fw_data;
 506         u32 fw_size;
 507         int i, j;
 508
 509         /* halt the MEs */
 510         cik_sdma_enable(adev, false);
 511
 512         for (i = 0; i < adev->sdma.num_instances; i++) {
 513                 if (!adev->sdma.instance[i].fw)
 514                         return -EINVAL;
 515                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 516                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 517                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 518                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 519                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 520                 if (adev->sdma.instance[i].feature_version >= 20)
 521                         adev->sdma.instance[i].burst_nop = true;
 522                 fw_data = (const __le32 *)
 523                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 524                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 525                 for (j = 0; j < fw_size; j++)
 526                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 527                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 528         }
 529
 530         return 0;
 531 }
 532
 533 /**
 534  * cik_sdma_start - setup and start the async dma engines
 535  *
 536  * @adev: amdgpu_device pointer
 537  *
 538  * Set up the DMA engines and enable them (CIK).
 539  * Returns 0 for success, error for failure.
 540  */
 541 static int cik_sdma_start(struct amdgpu_device *adev)
 542 {
 543         int r;
 544
 545         r = cik_sdma_load_microcode(adev);
 546         if (r)
 547                 return r;
 548
 549         /* halt the engine before programing */
 550         cik_sdma_enable(adev, false);
 551
 552         /* start the gfx rings and rlc compute queues */
 553         r = cik_sdma_gfx_resume(adev);
 554         if (r)
 555                 return r;
 556         r = cik_sdma_rlc_resume(adev);
 557         if (r)
 558                 return r;
 559
 560         return 0;
 561 }
 562
 563 /**
 564  * cik_sdma_ring_test_ring - simple async dma engine test
 565  *
 566  * @ring: amdgpu_ring structure holding ring information
 567  *
 568  * Test the DMA engine by writing using it to write an
 569  * value to memory. (CIK).
 570  * Returns 0 for success, error for failure.
 571  */
 572 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 573 {
 574         struct amdgpu_device *adev = ring->adev;
 575         unsigned i;
 576         unsigned index;
 577         int r;
 578         u32 tmp;
 579         u64 gpu_addr;
 580
 581         r = amdgpu_wb_get(adev, &index);
 582         if (r) {
 583                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 584                 return r;
 585         }
 586
 587         gpu_addr = adev->wb.gpu_addr + (index * 4);
 588         tmp = 0xCAFEDEAD;
 589         adev->wb.wb[index] = cpu_to_le32(tmp);
 590
 591         r = amdgpu_ring_alloc(ring, 5);
 592         if (r) {
 593                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 594                 amdgpu_wb_free(adev, index);
 595                 return r;
 596         }
 597         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 598         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 599         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 600         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 601         amdgpu_ring_write(ring, 0xDEADBEEF);
 602         amdgpu_ring_commit(ring);
 603
 604         for (i = 0; i < adev->usec_timeout; i++) {
 605                 tmp = le32_to_cpu(adev->wb.wb[index]);
 606                 if (tmp == 0xDEADBEEF)
 607                         break;
 608                 DRM_UDELAY(1);
 609         }
 610
 611         if (i < adev->usec_timeout) {
 612                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 613         } else {
 614                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 615                           ring->idx, tmp);
 616                 r = -EINVAL;
 617         }
 618         amdgpu_wb_free(adev, index);
 619
 620         return r;
 621 }
 622
 623 /**
 624  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 625  *
 626  * @ring: amdgpu_ring structure holding ring information
 627  *
 628  * Test a simple IB in the DMA ring (CIK).
 629  * Returns 0 on success, error on failure.
 630  */
 631 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
 632 {
 633         struct amdgpu_device *adev = ring->adev;
 634         struct amdgpu_ib ib;
 635         struct fence *f = NULL;
 636         unsigned i;
 637         unsigned index;
 638         int r;
 639         u32 tmp = 0;
 640         u64 gpu_addr;
 641
 642         r = amdgpu_wb_get(adev, &index);
 643         if (r) {
 644                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 645                 return r;
 646         }
 647
 648         gpu_addr = adev->wb.gpu_addr + (index * 4);
 649         tmp = 0xCAFEDEAD;
 650         adev->wb.wb[index] = cpu_to_le32(tmp);
 651         memset(&ib, 0, sizeof(ib));
 652         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 653         if (r) {
 654                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 655                 goto err0;
 656         }
 657
 658         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 659         ib.ptr[1] = lower_32_bits(gpu_addr);
 660         ib.ptr[2] = upper_32_bits(gpu_addr);
 661         ib.ptr[3] = 1;
 662         ib.ptr[4] = 0xDEADBEEF;
 663         ib.length_dw = 5;
 664         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
 665         if (r)
 666                 goto err1;
 667
 668         r = fence_wait(f, false);
 669         if (r) {
 670                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 671                 goto err1;
 672         }
 673         for (i = 0; i < adev->usec_timeout; i++) {
 674                 tmp = le32_to_cpu(adev->wb.wb[index]);
 675                 if (tmp == 0xDEADBEEF)
 676                         break;
 677                 DRM_UDELAY(1);
 678         }
 679         if (i < adev->usec_timeout) {
 680                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 681                          ring->idx, i);
 682                 goto err1;
 683         } else {
 684                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 685                 r = -EINVAL;
 686         }
 687
 688 err1:
 689         fence_put(f);
 690         amdgpu_ib_free(adev, &ib, NULL);
 691         fence_put(f);
 692 err0:
 693         amdgpu_wb_free(adev, index);
 694         return r;
 695 }
 696
 697 /**
 698  * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
 699  *
 700  * @ib: indirect buffer to fill with commands
 701  * @pe: addr of the page entry
 702  * @src: src addr to copy from
 703  * @count: number of page entries to update
 704  *
 705  * Update PTEs by copying them from the GART using sDMA (CIK).
 706  */
 707 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 708                                  uint64_t pe, uint64_t src,
 709                                  unsigned count)
 710 {
 711         while (count) {
 712                 unsigned bytes = count * 8;
 713                 if (bytes > 0x1FFFF8)
 714                         bytes = 0x1FFFF8;
 715
 716                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 717                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 718                 ib->ptr[ib->length_dw++] = bytes;
 719                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 720                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 721                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 722                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 723                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 724
 725                 pe += bytes;
 726                 src += bytes;
 727                 count -= bytes / 8;
 728         }
 729 }
 730
 731 /**
 732  * cik_sdma_vm_write_pages - update PTEs by writing them manually
 733  *
 734  * @ib: indirect buffer to fill with commands
 735  * @pe: addr of the page entry
 736  * @addr: dst addr to write into pe
 737  * @count: number of page entries to update
 738  * @incr: increase next addr by incr bytes
 739  * @flags: access flags
 740  *
 741  * Update PTEs by writing them manually using sDMA (CIK).
 742  */
 743 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
 744                                   const dma_addr_t *pages_addr, uint64_t pe,
 745                                   uint64_t addr, unsigned count,
 746                                   uint32_t incr, uint32_t flags)
 747 {
 748         uint64_t value;
 749         unsigned ndw;
 750
 751         while (count) {
 752                 ndw = count * 2;
 753                 if (ndw > 0xFFFFE)
 754                         ndw = 0xFFFFE;
 755
 756                 /* for non-physically contiguous pages (system) */
 757                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 758                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 759                 ib->ptr[ib->length_dw++] = pe;
 760                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 761                 ib->ptr[ib->length_dw++] = ndw;
 762                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 763                         value = amdgpu_vm_map_gart(pages_addr, addr);
 764                         addr += incr;
 765                         value |= flags;
 766                         ib->ptr[ib->length_dw++] = value;
 767                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 768                 }
 769         }
 770 }
 771
 772 /**
 773  * cik_sdma_vm_set_pages - update the page tables using sDMA
 774  *
 775  * @ib: indirect buffer to fill with commands
 776  * @pe: addr of the page entry
 777  * @addr: dst addr to write into pe
 778  * @count: number of page entries to update
 779  * @incr: increase next addr by incr bytes
 780  * @flags: access flags
 781  *
 782  * Update the page tables using sDMA (CIK).
 783  */
 784 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
 785                                     uint64_t pe,
 786                                     uint64_t addr, unsigned count,
 787                                     uint32_t incr, uint32_t flags)
 788 {
 789         uint64_t value;
 790         unsigned ndw;
 791
 792         while (count) {
 793                 ndw = count;
 794                 if (ndw > 0x7FFFF)
 795                         ndw = 0x7FFFF;
 796
 797                 if (flags & AMDGPU_PTE_VALID)
 798                         value = addr;
 799                 else
 800                         value = 0;
 801
 802                 /* for physically contiguous pages (vram) */
 803                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 804                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 805                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 806                 ib->ptr[ib->length_dw++] = flags; /* mask */
 807                 ib->ptr[ib->length_dw++] = 0;
 808                 ib->ptr[ib->length_dw++] = value; /* value */
 809                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 810                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 811                 ib->ptr[ib->length_dw++] = 0;
 812                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 813
 814                 pe += ndw * 8;
 815                 addr += ndw * incr;
 816                 count -= ndw;
 817         }
 818 }
 819
 820 /**
 821  * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
 822  *
 823  * @ib: indirect buffer to fill with padding
 824  *
 825  */
 826 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 827 {
 828         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 829         u32 pad_count;
 830         int i;
 831
 832         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 833         for (i = 0; i < pad_count; i++)
 834                 if (sdma && sdma->burst_nop && (i == 0))
 835                         ib->ptr[ib->length_dw++] =
 836                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 837                                         SDMA_NOP_COUNT(pad_count - 1);
 838                 else
 839                         ib->ptr[ib->length_dw++] =
 840                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 841 }
 842
 843 /**
 844  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
 845  *
 846  * @ring: amdgpu_ring pointer
 847  *
 848  * Make sure all previous operations are completed (CIK).
 849  */
 850 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 851 {
 852         uint32_t seq = ring->fence_drv.sync_seq;
 853         uint64_t addr = ring->fence_drv.gpu_addr;
 854
 855         /* wait for idle */
 856         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
 857                                             SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 858                                             SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
 859                                             SDMA_POLL_REG_MEM_EXTRA_M));
 860         amdgpu_ring_write(ring, addr & 0xfffffffc);
 861         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 862         amdgpu_ring_write(ring, seq); /* reference */
 863         amdgpu_ring_write(ring, 0xfffffff); /* mask */
 864         amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
 865 }
 866
 867 /**
 868  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 869  *
 870  * @ring: amdgpu_ring pointer
 871  * @vm: amdgpu_vm pointer
 872  *
 873  * Update the page table base and flush the VM TLB
 874  * using sDMA (CIK).
 875  */
 876 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 877                                         unsigned vm_id, uint64_t pd_addr)
 878 {
 879         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 880                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 881
 882         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 883         if (vm_id < 8) {
 884                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 885         } else {
 886                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 887         }
 888         amdgpu_ring_write(ring, pd_addr >> 12);
 889
 890         /* flush TLB */
 891         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 892         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 893         amdgpu_ring_write(ring, 1 << vm_id);
 894
 895         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 896         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 897         amdgpu_ring_write(ring, 0);
 898         amdgpu_ring_write(ring, 0); /* reference */
 899         amdgpu_ring_write(ring, 0); /* mask */
 900         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 901 }
 902
 903 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 904                                  bool enable)
 905 {
 906         u32 orig, data;
 907
 908         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 909                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 910                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 911         } else {
 912                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 913                 data |= 0xff000000;
 914                 if (data != orig)
 915                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 916
 917                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 918                 data |= 0xff000000;
 919                 if (data != orig)
 920                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 921         }
 922 }
 923
 924 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 925                                  bool enable)
 926 {
 927         u32 orig, data;
 928
 929         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 930                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 931                 data |= 0x100;
 932                 if (orig != data)
 933                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 934
 935                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 936                 data |= 0x100;
 937                 if (orig != data)
 938                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 939         } else {
 940                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 941                 data &= ~0x100;
 942                 if (orig != data)
 943                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 944
 945                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 946                 data &= ~0x100;
 947                 if (orig != data)
 948                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 949         }
 950 }
 951
 952 static int cik_sdma_early_init(void *handle)
 953 {
 954         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 955
 956         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 957
 958         cik_sdma_set_ring_funcs(adev);
 959         cik_sdma_set_irq_funcs(adev);
 960         cik_sdma_set_buffer_funcs(adev);
 961         cik_sdma_set_vm_pte_funcs(adev);
 962
 963         return 0;
 964 }
 965
 966 static int cik_sdma_sw_init(void *handle)
 967 {
 968         struct amdgpu_ring *ring;
 969         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 970         int r, i;
 971
 972         r = cik_sdma_init_microcode(adev);
 973         if (r) {
 974                 DRM_ERROR("Failed to load sdma firmware!\n");
 975                 return r;
 976         }
 977
 978         /* SDMA trap event */
 979         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 980         if (r)
 981                 return r;
 982
 983         /* SDMA Privileged inst */
 984         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 985         if (r)
 986                 return r;
 987
 988         /* SDMA Privileged inst */
 989         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 990         if (r)
 991                 return r;
 992
 993         for (i = 0; i < adev->sdma.num_instances; i++) {
 994                 ring = &adev->sdma.instance[i].ring;
 995                 ring->ring_obj = NULL;
 996                 sprintf(ring->name, "sdma%d", i);
 997                 r = amdgpu_ring_init(adev, ring, 1024,
 998                                      SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
 999                                      &adev->sdma.trap_irq,
1000                                      (i == 0) ?
1001                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1002                                      AMDGPU_RING_TYPE_SDMA);
1003                 if (r)
1004                         return r;
1005         }
1006
1007         return r;
1008 }
1009
1010 static int cik_sdma_sw_fini(void *handle)
1011 {
1012         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1013         int i;
1014
1015         for (i = 0; i < adev->sdma.num_instances; i++)
1016                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1017
1018         cik_sdma_free_microcode(adev);
1019         return 0;
1020 }
1021
1022 static int cik_sdma_hw_init(void *handle)
1023 {
1024         int r;
1025         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1026
1027         r = cik_sdma_start(adev);
1028         if (r)
1029                 return r;
1030
1031         return r;
1032 }
1033
1034 static int cik_sdma_hw_fini(void *handle)
1035 {
1036         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1037
1038         cik_sdma_enable(adev, false);
1039
1040         return 0;
1041 }
1042
1043 static int cik_sdma_suspend(void *handle)
1044 {
1045         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1046
1047         return cik_sdma_hw_fini(adev);
1048 }
1049
1050 static int cik_sdma_resume(void *handle)
1051 {
1052         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1054         return cik_sdma_hw_init(adev);
1055 }
1056
1057 static bool cik_sdma_is_idle(void *handle)
1058 {
1059         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1060         u32 tmp = RREG32(mmSRBM_STATUS2);
1061
1062         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1063                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1064             return false;
1065
1066         return true;
1067 }
1068
1069 static int cik_sdma_wait_for_idle(void *handle)
1070 {
1071         unsigned i;
1072         u32 tmp;
1073         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1074
1075         for (i = 0; i < adev->usec_timeout; i++) {
1076                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1077                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1078
1079                 if (!tmp)
1080                         return 0;
1081                 udelay(1);
1082         }
1083         return -ETIMEDOUT;
1084 }
1085
1086 static int cik_sdma_soft_reset(void *handle)
1087 {
1088         u32 srbm_soft_reset = 0;
1089         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1090         u32 tmp = RREG32(mmSRBM_STATUS2);
1091
1092         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1093                 /* sdma0 */
1094                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1095                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1096                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1097                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1098         }
1099         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1100                 /* sdma1 */
1101                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1102                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1103                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1104                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1105         }
1106
1107         if (srbm_soft_reset) {
1108                 tmp = RREG32(mmSRBM_SOFT_RESET);
1109                 tmp |= srbm_soft_reset;
1110                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1111                 WREG32(mmSRBM_SOFT_RESET, tmp);
1112                 tmp = RREG32(mmSRBM_SOFT_RESET);
1113
1114                 udelay(50);
1115
1116                 tmp &= ~srbm_soft_reset;
1117                 WREG32(mmSRBM_SOFT_RESET, tmp);
1118                 tmp = RREG32(mmSRBM_SOFT_RESET);
1119
1120                 /* Wait a little for things to settle down */
1121                 udelay(50);
1122         }
1123
1124         return 0;
1125 }
1126
1127 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1128                                        struct amdgpu_irq_src *src,
1129                                        unsigned type,
1130                                        enum amdgpu_interrupt_state state)
1131 {
1132         u32 sdma_cntl;
1133
1134         switch (type) {
1135         case AMDGPU_SDMA_IRQ_TRAP0:
1136                 switch (state) {
1137                 case AMDGPU_IRQ_STATE_DISABLE:
1138                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1139                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1140                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1141                         break;
1142                 case AMDGPU_IRQ_STATE_ENABLE:
1143                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1144                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1145                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1146                         break;
1147                 default:
1148                         break;
1149                 }
1150                 break;
1151         case AMDGPU_SDMA_IRQ_TRAP1:
1152                 switch (state) {
1153                 case AMDGPU_IRQ_STATE_DISABLE:
1154                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1155                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1156                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1157                         break;
1158                 case AMDGPU_IRQ_STATE_ENABLE:
1159                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1160                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1161                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1162                         break;
1163                 default:
1164                         break;
1165                 }
1166                 break;
1167         default:
1168                 break;
1169         }
1170         return 0;
1171 }
1172
1173 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1174                                      struct amdgpu_irq_src *source,
1175                                      struct amdgpu_iv_entry *entry)
1176 {
1177         u8 instance_id, queue_id;
1178
1179         instance_id = (entry->ring_id & 0x3) >> 0;
1180         queue_id = (entry->ring_id & 0xc) >> 2;
1181         DRM_DEBUG("IH: SDMA trap\n");
1182         switch (instance_id) {
1183         case 0:
1184                 switch (queue_id) {
1185                 case 0:
1186                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1187                         break;
1188                 case 1:
1189                         /* XXX compute */
1190                         break;
1191                 case 2:
1192                         /* XXX compute */
1193                         break;
1194                 }
1195                 break;
1196         case 1:
1197                 switch (queue_id) {
1198                 case 0:
1199                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1200                         break;
1201                 case 1:
1202                         /* XXX compute */
1203                         break;
1204                 case 2:
1205                         /* XXX compute */
1206                         break;
1207                 }
1208                 break;
1209         }
1210
1211         return 0;
1212 }
1213
1214 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1215                                              struct amdgpu_irq_src *source,
1216                                              struct amdgpu_iv_entry *entry)
1217 {
1218         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1219         schedule_work(&adev->reset_work);
1220         return 0;
1221 }
1222
1223 static int cik_sdma_set_clockgating_state(void *handle,
1224                                           enum amd_clockgating_state state)
1225 {
1226         bool gate = false;
1227         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1228
1229         if (state == AMD_CG_STATE_GATE)
1230                 gate = true;
1231
1232         cik_enable_sdma_mgcg(adev, gate);
1233         cik_enable_sdma_mgls(adev, gate);
1234
1235         return 0;
1236 }
1237
1238 static int cik_sdma_set_powergating_state(void *handle,
1239                                           enum amd_powergating_state state)
1240 {
1241         return 0;
1242 }
1243
1244 const struct amd_ip_funcs cik_sdma_ip_funcs = {
1245         .name = "cik_sdma",
1246         .early_init = cik_sdma_early_init,
1247         .late_init = NULL,
1248         .sw_init = cik_sdma_sw_init,
1249         .sw_fini = cik_sdma_sw_fini,
1250         .hw_init = cik_sdma_hw_init,
1251         .hw_fini = cik_sdma_hw_fini,
1252         .suspend = cik_sdma_suspend,
1253         .resume = cik_sdma_resume,
1254         .is_idle = cik_sdma_is_idle,
1255         .wait_for_idle = cik_sdma_wait_for_idle,
1256         .soft_reset = cik_sdma_soft_reset,
1257         .set_clockgating_state = cik_sdma_set_clockgating_state,
1258         .set_powergating_state = cik_sdma_set_powergating_state,
1259 };
1260
1261 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1262         .get_rptr = cik_sdma_ring_get_rptr,
1263         .get_wptr = cik_sdma_ring_get_wptr,
1264         .set_wptr = cik_sdma_ring_set_wptr,
1265         .parse_cs = NULL,
1266         .emit_ib = cik_sdma_ring_emit_ib,
1267         .emit_fence = cik_sdma_ring_emit_fence,
1268         .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1269         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1270         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1271         .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
1272         .test_ring = cik_sdma_ring_test_ring,
1273         .test_ib = cik_sdma_ring_test_ib,
1274         .insert_nop = cik_sdma_ring_insert_nop,
1275         .pad_ib = cik_sdma_ring_pad_ib,
1276 };
1277
1278 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1279 {
1280         int i;
1281
1282         for (i = 0; i < adev->sdma.num_instances; i++)
1283                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1284 }
1285
1286 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1287         .set = cik_sdma_set_trap_irq_state,
1288         .process = cik_sdma_process_trap_irq,
1289 };
1290
1291 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1292         .process = cik_sdma_process_illegal_inst_irq,
1293 };
1294
1295 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1296 {
1297         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1298         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1299         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1300 }
1301
1302 /**
1303  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1304  *
1305  * @ring: amdgpu_ring structure holding ring information
1306  * @src_offset: src GPU address
1307  * @dst_offset: dst GPU address
1308  * @byte_count: number of bytes to xfer
1309  *
1310  * Copy GPU buffers using the DMA engine (CIK).
1311  * Used by the amdgpu ttm implementation to move pages if
1312  * registered as the asic copy callback.
1313  */
1314 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1315                                       uint64_t src_offset,
1316                                       uint64_t dst_offset,
1317                                       uint32_t byte_count)
1318 {
1319         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1320         ib->ptr[ib->length_dw++] = byte_count;
1321         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1322         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1323         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1324         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1325         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1326 }
1327
1328 /**
1329  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1330  *
1331  * @ring: amdgpu_ring structure holding ring information
1332  * @src_data: value to write to buffer
1333  * @dst_offset: dst GPU address
1334  * @byte_count: number of bytes to xfer
1335  *
1336  * Fill GPU buffers using the DMA engine (CIK).
1337  */
1338 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1339                                       uint32_t src_data,
1340                                       uint64_t dst_offset,
1341                                       uint32_t byte_count)
1342 {
1343         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1344         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1345         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1346         ib->ptr[ib->length_dw++] = src_data;
1347         ib->ptr[ib->length_dw++] = byte_count;
1348 }
1349
1350 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1351         .copy_max_bytes = 0x1fffff,
1352         .copy_num_dw = 7,
1353         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1354
1355         .fill_max_bytes = 0x1fffff,
1356         .fill_num_dw = 5,
1357         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1358 };
1359
1360 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1361 {
1362         if (adev->mman.buffer_funcs == NULL) {
1363                 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1364                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1365         }
1366 }
1367
1368 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1369         .copy_pte = cik_sdma_vm_copy_pte,
1370         .write_pte = cik_sdma_vm_write_pte,
1371         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1372 };
1373
1374 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1375 {
1376         unsigned i;
1377
1378         if (adev->vm_manager.vm_pte_funcs == NULL) {
1379                 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1380                 for (i = 0; i < adev->sdma.num_instances; i++)
1381                         adev->vm_manager.vm_pte_rings[i] =
1382                                 &adev->sdma.instance[i].ring;
1383
1384                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1385         }
1386 }