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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / cz_dpm.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/seq_file.h>
26 #include "drmP.h"
27 #include "amdgpu.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_atombios.h"
30 #include "vid.h"
31 #include "vi_dpm.h"
32 #include "amdgpu_dpm.h"
33 #include "cz_dpm.h"
34 #include "cz_ppsmc.h"
35 #include "atom.h"
36
37 #include "smu/smu_8_0_d.h"
38 #include "smu/smu_8_0_sh_mask.h"
39 #include "gca/gfx_8_0_d.h"
40 #include "gca/gfx_8_0_sh_mask.h"
41 #include "gmc/gmc_8_1_d.h"
42 #include "bif/bif_5_1_d.h"
43 #include "gfx_v8_0.h"
44
45 static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
46 static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
47
48 static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps)
49 {
50 struct cz_ps *ps = rps->ps_priv;
51
52 return ps;
53 }
54
55 static struct cz_power_info *cz_get_pi(struct amdgpu_device *adev)
56 {
57 struct cz_power_info *pi = adev->pm.dpm.priv;
58
59 return pi;
60 }
61
62 static uint16_t cz_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
63 uint16_t voltage)
64 {
65 uint16_t tmp = 6200 - voltage * 25;
66
67 return tmp;
68 }
69
70 static void cz_construct_max_power_limits_table(struct amdgpu_device *adev,
71 struct amdgpu_clock_and_voltage_limits *table)
72 {
73 struct cz_power_info *pi = cz_get_pi(adev);
74 struct amdgpu_clock_voltage_dependency_table *dep_table =
75 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
76
77 if (dep_table->count > 0) {
78 table->sclk = dep_table->entries[dep_table->count - 1].clk;
79 table->vddc = cz_convert_8bit_index_to_voltage(adev,
80 dep_table->entries[dep_table->count - 1].v);
81 }
82
83 table->mclk = pi->sys_info.nbp_memory_clock[0];
84
85 }
86
87 union igp_info {
88 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
89 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
90 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
91 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
92 };
93
94 static int cz_parse_sys_info_table(struct amdgpu_device *adev)
95 {
96 struct cz_power_info *pi = cz_get_pi(adev);
97 struct amdgpu_mode_info *mode_info = &adev->mode_info;
98 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
99 union igp_info *igp_info;
100 u8 frev, crev;
101 u16 data_offset;
102 int i = 0;
103
104 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
105 &frev, &crev, &data_offset)) {
106 igp_info = (union igp_info *)(mode_info->atom_context->bios +
107 data_offset);
108
109 if (crev != 9) {
110 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
111 return -EINVAL;
112 }
113 pi->sys_info.bootup_sclk =
114 le32_to_cpu(igp_info->info_9.ulBootUpEngineClock);
115 pi->sys_info.bootup_uma_clk =
116 le32_to_cpu(igp_info->info_9.ulBootUpUMAClock);
117 pi->sys_info.dentist_vco_freq =
118 le32_to_cpu(igp_info->info_9.ulDentistVCOFreq);
119 pi->sys_info.bootup_nb_voltage_index =
120 le16_to_cpu(igp_info->info_9.usBootUpNBVoltage);
121
122 if (igp_info->info_9.ucHtcTmpLmt == 0)
123 pi->sys_info.htc_tmp_lmt = 203;
124 else
125 pi->sys_info.htc_tmp_lmt = igp_info->info_9.ucHtcTmpLmt;
126
127 if (igp_info->info_9.ucHtcHystLmt == 0)
128 pi->sys_info.htc_hyst_lmt = 5;
129 else
130 pi->sys_info.htc_hyst_lmt = igp_info->info_9.ucHtcHystLmt;
131
132 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
133 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
134 return -EINVAL;
135 }
136
137 if (le32_to_cpu(igp_info->info_9.ulSystemConfig) & (1 << 3) &&
138 pi->enable_nb_ps_policy)
139 pi->sys_info.nb_dpm_enable = true;
140 else
141 pi->sys_info.nb_dpm_enable = false;
142
143 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
144 if (i < CZ_NUM_NBPMEMORY_CLOCK)
145 pi->sys_info.nbp_memory_clock[i] =
146 le32_to_cpu(igp_info->info_9.ulNbpStateMemclkFreq[i]);
147 pi->sys_info.nbp_n_clock[i] =
148 le32_to_cpu(igp_info->info_9.ulNbpStateNClkFreq[i]);
149 }
150
151 for (i = 0; i < CZ_MAX_DISPLAY_CLOCK_LEVEL; i++)
152 pi->sys_info.display_clock[i] =
153 le32_to_cpu(igp_info->info_9.sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
154
155 for (i = 0; i < CZ_NUM_NBPSTATES; i++)
156 pi->sys_info.nbp_voltage_index[i] =
157 le32_to_cpu(igp_info->info_9.usNBPStateVoltage[i]);
158
159 if (le32_to_cpu(igp_info->info_9.ulGPUCapInfo) &
160 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
161 pi->caps_enable_dfs_bypass = true;
162
163 pi->sys_info.uma_channel_number =
164 igp_info->info_9.ucUMAChannelNumber;
165
166 cz_construct_max_power_limits_table(adev,
167 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
168 }
169
170 return 0;
171 }
172
173 static void cz_patch_voltage_values(struct amdgpu_device *adev)
174 {
175 int i;
176 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
177 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
178 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
179 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
180 struct amdgpu_clock_voltage_dependency_table *acp_table =
181 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
182
183 if (uvd_table->count) {
184 for (i = 0; i < uvd_table->count; i++)
185 uvd_table->entries[i].v =
186 cz_convert_8bit_index_to_voltage(adev,
187 uvd_table->entries[i].v);
188 }
189
190 if (vce_table->count) {
191 for (i = 0; i < vce_table->count; i++)
192 vce_table->entries[i].v =
193 cz_convert_8bit_index_to_voltage(adev,
194 vce_table->entries[i].v);
195 }
196
197 if (acp_table->count) {
198 for (i = 0; i < acp_table->count; i++)
199 acp_table->entries[i].v =
200 cz_convert_8bit_index_to_voltage(adev,
201 acp_table->entries[i].v);
202 }
203
204 }
205
206 static void cz_construct_boot_state(struct amdgpu_device *adev)
207 {
208 struct cz_power_info *pi = cz_get_pi(adev);
209
210 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
211 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
212 pi->boot_pl.ds_divider_index = 0;
213 pi->boot_pl.ss_divider_index = 0;
214 pi->boot_pl.allow_gnb_slow = 1;
215 pi->boot_pl.force_nbp_state = 0;
216 pi->boot_pl.display_wm = 0;
217 pi->boot_pl.vce_wm = 0;
218
219 }
220
221 static void cz_patch_boot_state(struct amdgpu_device *adev,
222 struct cz_ps *ps)
223 {
224 struct cz_power_info *pi = cz_get_pi(adev);
225
226 ps->num_levels = 1;
227 ps->levels[0] = pi->boot_pl;
228 }
229
230 union pplib_clock_info {
231 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
232 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
233 struct _ATOM_PPLIB_CZ_CLOCK_INFO carrizo;
234 };
235
236 static void cz_parse_pplib_clock_info(struct amdgpu_device *adev,
237 struct amdgpu_ps *rps, int index,
238 union pplib_clock_info *clock_info)
239 {
240 struct cz_power_info *pi = cz_get_pi(adev);
241 struct cz_ps *ps = cz_get_ps(rps);
242 struct cz_pl *pl = &ps->levels[index];
243 struct amdgpu_clock_voltage_dependency_table *table =
244 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
245
246 pl->sclk = table->entries[clock_info->carrizo.index].clk;
247 pl->vddc_index = table->entries[clock_info->carrizo.index].v;
248
249 ps->num_levels = index + 1;
250
251 if (pi->caps_sclk_ds) {
252 pl->ds_divider_index = 5;
253 pl->ss_divider_index = 5;
254 }
255
256 }
257
258 static void cz_parse_pplib_non_clock_info(struct amdgpu_device *adev,
259 struct amdgpu_ps *rps,
260 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
261 u8 table_rev)
262 {
263 struct cz_ps *ps = cz_get_ps(rps);
264
265 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
266 rps->class = le16_to_cpu(non_clock_info->usClassification);
267 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
268
269 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
270 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
271 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
272 } else {
273 rps->vclk = 0;
274 rps->dclk = 0;
275 }
276
277 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
278 adev->pm.dpm.boot_ps = rps;
279 cz_patch_boot_state(adev, ps);
280 }
281 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
282 adev->pm.dpm.uvd_ps = rps;
283
284 }
285
286 union power_info {
287 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
288 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
289 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
290 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
291 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
292 };
293
294 union pplib_power_state {
295 struct _ATOM_PPLIB_STATE v1;
296 struct _ATOM_PPLIB_STATE_V2 v2;
297 };
298
299 static int cz_parse_power_table(struct amdgpu_device *adev)
300 {
301 struct amdgpu_mode_info *mode_info = &adev->mode_info;
302 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
303 union pplib_power_state *power_state;
304 int i, j, k, non_clock_array_index, clock_array_index;
305 union pplib_clock_info *clock_info;
306 struct _StateArray *state_array;
307 struct _ClockInfoArray *clock_info_array;
308 struct _NonClockInfoArray *non_clock_info_array;
309 union power_info *power_info;
310 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
311 u16 data_offset;
312 u8 frev, crev;
313 u8 *power_state_offset;
314 struct cz_ps *ps;
315
316 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
317 &frev, &crev, &data_offset))
318 return -EINVAL;
319 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
320
321 state_array = (struct _StateArray *)
322 (mode_info->atom_context->bios + data_offset +
323 le16_to_cpu(power_info->pplib.usStateArrayOffset));
324 clock_info_array = (struct _ClockInfoArray *)
325 (mode_info->atom_context->bios + data_offset +
326 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
327 non_clock_info_array = (struct _NonClockInfoArray *)
328 (mode_info->atom_context->bios + data_offset +
329 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
330
331 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
332 state_array->ucNumEntries, GFP_KERNEL);
333
334 if (!adev->pm.dpm.ps)
335 return -ENOMEM;
336
337 power_state_offset = (u8 *)state_array->states;
338 adev->pm.dpm.platform_caps =
339 le32_to_cpu(power_info->pplib.ulPlatformCaps);
340 adev->pm.dpm.backbias_response_time =
341 le16_to_cpu(power_info->pplib.usBackbiasTime);
342 adev->pm.dpm.voltage_response_time =
343 le16_to_cpu(power_info->pplib.usVoltageTime);
344
345 for (i = 0; i < state_array->ucNumEntries; i++) {
346 power_state = (union pplib_power_state *)power_state_offset;
347 non_clock_array_index = power_state->v2.nonClockInfoIndex;
348 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
349 &non_clock_info_array->nonClockInfo[non_clock_array_index];
350
351 ps = kzalloc(sizeof(struct cz_ps), GFP_KERNEL);
352 if (ps == NULL) {
353 kfree(adev->pm.dpm.ps);
354 return -ENOMEM;
355 }
356
357 adev->pm.dpm.ps[i].ps_priv = ps;
358 k = 0;
359 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
360 clock_array_index = power_state->v2.clockInfoIndex[j];
361 if (clock_array_index >= clock_info_array->ucNumEntries)
362 continue;
363 if (k >= CZ_MAX_HARDWARE_POWERLEVELS)
364 break;
365 clock_info = (union pplib_clock_info *)
366 &clock_info_array->clockInfo[clock_array_index *
367 clock_info_array->ucEntrySize];
368 cz_parse_pplib_clock_info(adev, &adev->pm.dpm.ps[i],
369 k, clock_info);
370 k++;
371 }
372 cz_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
373 non_clock_info,
374 non_clock_info_array->ucEntrySize);
375 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
376 }
377 adev->pm.dpm.num_ps = state_array->ucNumEntries;
378
379 return 0;
380 }
381
382 static int cz_process_firmware_header(struct amdgpu_device *adev)
383 {
384 struct cz_power_info *pi = cz_get_pi(adev);
385 u32 tmp;
386 int ret;
387
388 ret = cz_read_smc_sram_dword(adev, SMU8_FIRMWARE_HEADER_LOCATION +
389 offsetof(struct SMU8_Firmware_Header,
390 DpmTable),
391 &tmp, pi->sram_end);
392
393 if (ret == 0)
394 pi->dpm_table_start = tmp;
395
396 return ret;
397 }
398
399 static int cz_dpm_init(struct amdgpu_device *adev)
400 {
401 struct cz_power_info *pi;
402 int ret, i;
403
404 pi = kzalloc(sizeof(struct cz_power_info), GFP_KERNEL);
405 if (NULL == pi)
406 return -ENOMEM;
407
408 adev->pm.dpm.priv = pi;
409
410 ret = amdgpu_get_platform_caps(adev);
411 if (ret)
412 return ret;
413
414 ret = amdgpu_parse_extended_power_table(adev);
415 if (ret)
416 return ret;
417
418 pi->sram_end = SMC_RAM_END;
419
420 /* set up DPM defaults */
421 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
422 pi->active_target[i] = CZ_AT_DFLT;
423
424 pi->mgcg_cgtt_local0 = 0x0;
425 pi->mgcg_cgtt_local1 = 0x0;
426 pi->clock_slow_down_step = 25000;
427 pi->skip_clock_slow_down = 1;
428 pi->enable_nb_ps_policy = 0;
429 pi->caps_power_containment = true;
430 pi->caps_cac = true;
431 pi->didt_enabled = false;
432 if (pi->didt_enabled) {
433 pi->caps_sq_ramping = true;
434 pi->caps_db_ramping = true;
435 pi->caps_td_ramping = true;
436 pi->caps_tcp_ramping = true;
437 }
438 pi->caps_sclk_ds = true;
439 pi->voting_clients = 0x00c00033;
440 pi->auto_thermal_throttling_enabled = true;
441 pi->bapm_enabled = false;
442 pi->disable_nb_ps3_in_battery = false;
443 pi->voltage_drop_threshold = 0;
444 pi->caps_sclk_throttle_low_notification = false;
445 pi->gfx_pg_threshold = 500;
446 pi->caps_fps = true;
447 /* uvd */
448 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false;
449 pi->caps_uvd_dpm = true;
450 /* vce */
451 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false;
452 pi->caps_vce_dpm = true;
453 /* acp */
454 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false;
455 pi->caps_acp_dpm = true;
456
457 pi->caps_stable_power_state = false;
458 pi->nb_dpm_enabled_by_driver = true;
459 pi->nb_dpm_enabled = false;
460 pi->caps_voltage_island = false;
461 /* flags which indicate need to upload pptable */
462 pi->need_pptable_upload = true;
463
464 ret = cz_parse_sys_info_table(adev);
465 if (ret)
466 return ret;
467
468 cz_patch_voltage_values(adev);
469 cz_construct_boot_state(adev);
470
471 ret = cz_parse_power_table(adev);
472 if (ret)
473 return ret;
474
475 ret = cz_process_firmware_header(adev);
476 if (ret)
477 return ret;
478
479 pi->dpm_enabled = true;
480 pi->uvd_dynamic_pg = false;
481
482 return 0;
483 }
484
485 static void cz_dpm_fini(struct amdgpu_device *adev)
486 {
487 int i;
488
489 for (i = 0; i < adev->pm.dpm.num_ps; i++)
490 kfree(adev->pm.dpm.ps[i].ps_priv);
491
492 kfree(adev->pm.dpm.ps);
493 kfree(adev->pm.dpm.priv);
494 amdgpu_free_extended_power_table(adev);
495 }
496
497 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
498 #define CURRENT_NB_VID_MASK 0xff000000
499 #define CURRENT_NB_VID__SHIFT 24
500 #define ixSMUSVI_GFX_CURRENTVID 0xD8230048
501 #define CURRENT_GFX_VID_MASK 0xff000000
502 #define CURRENT_GFX_VID__SHIFT 24
503
504 static void
505 cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
506 struct seq_file *m)
507 {
508 struct cz_power_info *pi = cz_get_pi(adev);
509 struct amdgpu_clock_voltage_dependency_table *table =
510 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
511 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
512 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
513 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
514 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
515 u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX),
516 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
517 u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
518 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
519 u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
520 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
521 u32 sclk, vclk, dclk, ecclk, tmp;
522 u16 vddnb, vddgfx;
523
524 if (sclk_index >= NUM_SCLK_LEVELS) {
525 seq_printf(m, "invalid sclk dpm profile %d\n", sclk_index);
526 } else {
527 sclk = table->entries[sclk_index].clk;
528 seq_printf(m, "%u sclk: %u\n", sclk_index, sclk);
529 }
530
531 tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
532 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
533 vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
534 tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
535 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
536 vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
537 seq_printf(m, "vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
538
539 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
540 if (!pi->uvd_power_gated) {
541 if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
542 seq_printf(m, "invalid uvd dpm level %d\n", uvd_index);
543 } else {
544 vclk = uvd_table->entries[uvd_index].vclk;
545 dclk = uvd_table->entries[uvd_index].dclk;
546 seq_printf(m, "%u uvd vclk: %u dclk: %u\n", uvd_index, vclk, dclk);
547 }
548 }
549
550 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
551 if (!pi->vce_power_gated) {
552 if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
553 seq_printf(m, "invalid vce dpm level %d\n", vce_index);
554 } else {
555 ecclk = vce_table->entries[vce_index].ecclk;
556 seq_printf(m, "%u vce ecclk: %u\n", vce_index, ecclk);
557 }
558 }
559 }
560
561 static void cz_dpm_print_power_state(struct amdgpu_device *adev,
562 struct amdgpu_ps *rps)
563 {
564 int i;
565 struct cz_ps *ps = cz_get_ps(rps);
566
567 amdgpu_dpm_print_class_info(rps->class, rps->class2);
568 amdgpu_dpm_print_cap_info(rps->caps);
569
570 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
571 for (i = 0; i < ps->num_levels; i++) {
572 struct cz_pl *pl = &ps->levels[i];
573
574 DRM_INFO("\t\tpower level %d sclk: %u vddc: %u\n",
575 i, pl->sclk,
576 cz_convert_8bit_index_to_voltage(adev, pl->vddc_index));
577 }
578
579 amdgpu_dpm_print_ps_status(adev, rps);
580 }
581
582 static void cz_dpm_set_funcs(struct amdgpu_device *adev);
583
584 static int cz_dpm_early_init(void *handle)
585 {
586 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
587
588 cz_dpm_set_funcs(adev);
589
590 return 0;
591 }
592
593
594 static int cz_dpm_late_init(void *handle)
595 {
596 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
597
598 if (amdgpu_dpm) {
599 int ret;
600 /* init the sysfs and debugfs files late */
601 ret = amdgpu_pm_sysfs_init(adev);
602 if (ret)
603 return ret;
604
605 /* powerdown unused blocks for now */
606 cz_dpm_powergate_uvd(adev, true);
607 cz_dpm_powergate_vce(adev, true);
608 }
609
610 return 0;
611 }
612
613 static int cz_dpm_sw_init(void *handle)
614 {
615 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
616 int ret = 0;
617 /* fix me to add thermal support TODO */
618
619 /* default to balanced state */
620 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
621 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
622 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
623 adev->pm.default_sclk = adev->clock.default_sclk;
624 adev->pm.default_mclk = adev->clock.default_mclk;
625 adev->pm.current_sclk = adev->clock.default_sclk;
626 adev->pm.current_mclk = adev->clock.default_mclk;
627 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
628
629 if (amdgpu_dpm == 0)
630 return 0;
631
632 mutex_lock(&adev->pm.mutex);
633 ret = cz_dpm_init(adev);
634 if (ret)
635 goto dpm_init_failed;
636
637 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
638 if (amdgpu_dpm == 1)
639 amdgpu_pm_print_power_states(adev);
640
641 mutex_unlock(&adev->pm.mutex);
642 DRM_INFO("amdgpu: dpm initialized\n");
643
644 return 0;
645
646 dpm_init_failed:
647 cz_dpm_fini(adev);
648 mutex_unlock(&adev->pm.mutex);
649 DRM_ERROR("amdgpu: dpm initialization failed\n");
650
651 return ret;
652 }
653
654 static int cz_dpm_sw_fini(void *handle)
655 {
656 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
657
658 mutex_lock(&adev->pm.mutex);
659 amdgpu_pm_sysfs_fini(adev);
660 cz_dpm_fini(adev);
661 mutex_unlock(&adev->pm.mutex);
662
663 return 0;
664 }
665
666 static void cz_reset_ap_mask(struct amdgpu_device *adev)
667 {
668 struct cz_power_info *pi = cz_get_pi(adev);
669
670 pi->active_process_mask = 0;
671
672 }
673
674 static int cz_dpm_download_pptable_from_smu(struct amdgpu_device *adev,
675 void **table)
676 {
677 int ret = 0;
678
679 ret = cz_smu_download_pptable(adev, table);
680
681 return ret;
682 }
683
684 static int cz_dpm_upload_pptable_to_smu(struct amdgpu_device *adev)
685 {
686 struct cz_power_info *pi = cz_get_pi(adev);
687 struct SMU8_Fusion_ClkTable *clock_table;
688 struct atom_clock_dividers dividers;
689 void *table = NULL;
690 uint8_t i = 0;
691 int ret = 0;
692
693 struct amdgpu_clock_voltage_dependency_table *vddc_table =
694 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
695 struct amdgpu_clock_voltage_dependency_table *vddgfx_table =
696 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk;
697 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
698 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
699 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
700 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
701 struct amdgpu_clock_voltage_dependency_table *acp_table =
702 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
703
704 if (!pi->need_pptable_upload)
705 return 0;
706
707 ret = cz_dpm_download_pptable_from_smu(adev, &table);
708 if (ret) {
709 DRM_ERROR("amdgpu: Failed to get power play table from SMU!\n");
710 return -EINVAL;
711 }
712
713 clock_table = (struct SMU8_Fusion_ClkTable *)table;
714 /* patch clock table */
715 if (vddc_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
716 vddgfx_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
717 uvd_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
718 vce_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
719 acp_table->count > CZ_MAX_HARDWARE_POWERLEVELS) {
720 DRM_ERROR("amdgpu: Invalid Clock Voltage Dependency Table!\n");
721 return -EINVAL;
722 }
723
724 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
725
726 /* vddc sclk */
727 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
728 (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
729 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
730 (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
731 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
732 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
733 false, &dividers);
734 if (ret)
735 return ret;
736 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
737 (uint8_t)dividers.post_divider;
738
739 /* vddgfx sclk */
740 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
741 (i < vddgfx_table->count) ? (uint8_t)vddgfx_table->entries[i].v : 0;
742
743 /* acp breakdown */
744 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
745 (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
746 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
747 (i < acp_table->count) ? acp_table->entries[i].clk : 0;
748 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
749 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
750 false, &dividers);
751 if (ret)
752 return ret;
753 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
754 (uint8_t)dividers.post_divider;
755
756 /* uvd breakdown */
757 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
758 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
759 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
760 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
761 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
762 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
763 false, &dividers);
764 if (ret)
765 return ret;
766 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
767 (uint8_t)dividers.post_divider;
768
769 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
770 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
771 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
772 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
773 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
774 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
775 false, &dividers);
776 if (ret)
777 return ret;
778 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
779 (uint8_t)dividers.post_divider;
780
781 /* vce breakdown */
782 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
783 (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
784 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
785 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
786 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
787 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
788 false, &dividers);
789 if (ret)
790 return ret;
791 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
792 (uint8_t)dividers.post_divider;
793 }
794
795 /* its time to upload to SMU */
796 ret = cz_smu_upload_pptable(adev);
797 if (ret) {
798 DRM_ERROR("amdgpu: Failed to put power play table to SMU!\n");
799 return ret;
800 }
801
802 return 0;
803 }
804
805 static void cz_init_sclk_limit(struct amdgpu_device *adev)
806 {
807 struct cz_power_info *pi = cz_get_pi(adev);
808 struct amdgpu_clock_voltage_dependency_table *table =
809 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
810 uint32_t clock = 0, level;
811
812 if (!table || !table->count) {
813 DRM_ERROR("Invalid Voltage Dependency table.\n");
814 return;
815 }
816
817 pi->sclk_dpm.soft_min_clk = 0;
818 pi->sclk_dpm.hard_min_clk = 0;
819 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
820 level = cz_get_argument(adev);
821 if (level < table->count)
822 clock = table->entries[level].clk;
823 else {
824 DRM_ERROR("Invalid SLCK Voltage Dependency table entry.\n");
825 clock = table->entries[table->count - 1].clk;
826 }
827
828 pi->sclk_dpm.soft_max_clk = clock;
829 pi->sclk_dpm.hard_max_clk = clock;
830
831 }
832
833 static void cz_init_uvd_limit(struct amdgpu_device *adev)
834 {
835 struct cz_power_info *pi = cz_get_pi(adev);
836 struct amdgpu_uvd_clock_voltage_dependency_table *table =
837 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
838 uint32_t clock = 0, level;
839
840 if (!table || !table->count) {
841 DRM_ERROR("Invalid Voltage Dependency table.\n");
842 return;
843 }
844
845 pi->uvd_dpm.soft_min_clk = 0;
846 pi->uvd_dpm.hard_min_clk = 0;
847 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel);
848 level = cz_get_argument(adev);
849 if (level < table->count)
850 clock = table->entries[level].vclk;
851 else {
852 DRM_ERROR("Invalid UVD Voltage Dependency table entry.\n");
853 clock = table->entries[table->count - 1].vclk;
854 }
855
856 pi->uvd_dpm.soft_max_clk = clock;
857 pi->uvd_dpm.hard_max_clk = clock;
858
859 }
860
861 static void cz_init_vce_limit(struct amdgpu_device *adev)
862 {
863 struct cz_power_info *pi = cz_get_pi(adev);
864 struct amdgpu_vce_clock_voltage_dependency_table *table =
865 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
866 uint32_t clock = 0, level;
867
868 if (!table || !table->count) {
869 DRM_ERROR("Invalid Voltage Dependency table.\n");
870 return;
871 }
872
873 pi->vce_dpm.soft_min_clk = table->entries[0].ecclk;
874 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
875 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
876 level = cz_get_argument(adev);
877 if (level < table->count)
878 clock = table->entries[level].ecclk;
879 else {
880 /* future BIOS would fix this error */
881 DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n");
882 clock = table->entries[table->count - 1].ecclk;
883 }
884
885 pi->vce_dpm.soft_max_clk = clock;
886 pi->vce_dpm.hard_max_clk = clock;
887
888 }
889
890 static void cz_init_acp_limit(struct amdgpu_device *adev)
891 {
892 struct cz_power_info *pi = cz_get_pi(adev);
893 struct amdgpu_clock_voltage_dependency_table *table =
894 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
895 uint32_t clock = 0, level;
896
897 if (!table || !table->count) {
898 DRM_ERROR("Invalid Voltage Dependency table.\n");
899 return;
900 }
901
902 pi->acp_dpm.soft_min_clk = 0;
903 pi->acp_dpm.hard_min_clk = 0;
904 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxAclkLevel);
905 level = cz_get_argument(adev);
906 if (level < table->count)
907 clock = table->entries[level].clk;
908 else {
909 DRM_ERROR("Invalid ACP Voltage Dependency table entry.\n");
910 clock = table->entries[table->count - 1].clk;
911 }
912
913 pi->acp_dpm.soft_max_clk = clock;
914 pi->acp_dpm.hard_max_clk = clock;
915
916 }
917
918 static void cz_init_pg_state(struct amdgpu_device *adev)
919 {
920 struct cz_power_info *pi = cz_get_pi(adev);
921
922 pi->uvd_power_gated = false;
923 pi->vce_power_gated = false;
924 pi->acp_power_gated = false;
925
926 }
927
928 static void cz_init_sclk_threshold(struct amdgpu_device *adev)
929 {
930 struct cz_power_info *pi = cz_get_pi(adev);
931
932 pi->low_sclk_interrupt_threshold = 0;
933
934 }
935
936 static void cz_dpm_setup_asic(struct amdgpu_device *adev)
937 {
938 cz_reset_ap_mask(adev);
939 cz_dpm_upload_pptable_to_smu(adev);
940 cz_init_sclk_limit(adev);
941 cz_init_uvd_limit(adev);
942 cz_init_vce_limit(adev);
943 cz_init_acp_limit(adev);
944 cz_init_pg_state(adev);
945 cz_init_sclk_threshold(adev);
946
947 }
948
949 static bool cz_check_smu_feature(struct amdgpu_device *adev,
950 uint32_t feature)
951 {
952 uint32_t smu_feature = 0;
953 int ret;
954
955 ret = cz_send_msg_to_smc_with_parameter(adev,
956 PPSMC_MSG_GetFeatureStatus, 0);
957 if (ret) {
958 DRM_ERROR("Failed to get SMU features from SMC.\n");
959 return false;
960 } else {
961 smu_feature = cz_get_argument(adev);
962 if (feature & smu_feature)
963 return true;
964 }
965
966 return false;
967 }
968
969 static bool cz_check_for_dpm_enabled(struct amdgpu_device *adev)
970 {
971 if (cz_check_smu_feature(adev,
972 SMU_EnabledFeatureScoreboard_SclkDpmOn))
973 return true;
974
975 return false;
976 }
977
978 static void cz_program_voting_clients(struct amdgpu_device *adev)
979 {
980 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
981 }
982
983 static void cz_clear_voting_clients(struct amdgpu_device *adev)
984 {
985 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
986 }
987
988 static int cz_start_dpm(struct amdgpu_device *adev)
989 {
990 int ret = 0;
991
992 if (amdgpu_dpm) {
993 ret = cz_send_msg_to_smc_with_parameter(adev,
994 PPSMC_MSG_EnableAllSmuFeatures, SCLK_DPM_MASK);
995 if (ret) {
996 DRM_ERROR("SMU feature: SCLK_DPM enable failed\n");
997 return -EINVAL;
998 }
999 }
1000
1001 return 0;
1002 }
1003
1004 static int cz_stop_dpm(struct amdgpu_device *adev)
1005 {
1006 int ret = 0;
1007
1008 if (amdgpu_dpm && adev->pm.dpm_enabled) {
1009 ret = cz_send_msg_to_smc_with_parameter(adev,
1010 PPSMC_MSG_DisableAllSmuFeatures, SCLK_DPM_MASK);
1011 if (ret) {
1012 DRM_ERROR("SMU feature: SCLK_DPM disable failed\n");
1013 return -EINVAL;
1014 }
1015 }
1016
1017 return 0;
1018 }
1019
1020 static uint32_t cz_get_sclk_level(struct amdgpu_device *adev,
1021 uint32_t clock, uint16_t msg)
1022 {
1023 int i = 0;
1024 struct amdgpu_clock_voltage_dependency_table *table =
1025 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1026
1027 switch (msg) {
1028 case PPSMC_MSG_SetSclkSoftMin:
1029 case PPSMC_MSG_SetSclkHardMin:
1030 for (i = 0; i < table->count; i++)
1031 if (clock <= table->entries[i].clk)
1032 break;
1033 if (i == table->count)
1034 i = table->count - 1;
1035 break;
1036 case PPSMC_MSG_SetSclkSoftMax:
1037 case PPSMC_MSG_SetSclkHardMax:
1038 for (i = table->count - 1; i >= 0; i--)
1039 if (clock >= table->entries[i].clk)
1040 break;
1041 if (i < 0)
1042 i = 0;
1043 break;
1044 default:
1045 break;
1046 }
1047
1048 return i;
1049 }
1050
1051 static uint32_t cz_get_eclk_level(struct amdgpu_device *adev,
1052 uint32_t clock, uint16_t msg)
1053 {
1054 int i = 0;
1055 struct amdgpu_vce_clock_voltage_dependency_table *table =
1056 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1057
1058 if (table->count == 0)
1059 return 0;
1060
1061 switch (msg) {
1062 case PPSMC_MSG_SetEclkSoftMin:
1063 case PPSMC_MSG_SetEclkHardMin:
1064 for (i = 0; i < table->count-1; i++)
1065 if (clock <= table->entries[i].ecclk)
1066 break;
1067 break;
1068 case PPSMC_MSG_SetEclkSoftMax:
1069 case PPSMC_MSG_SetEclkHardMax:
1070 for (i = table->count - 1; i > 0; i--)
1071 if (clock >= table->entries[i].ecclk)
1072 break;
1073 break;
1074 default:
1075 break;
1076 }
1077
1078 return i;
1079 }
1080
1081 static int cz_program_bootup_state(struct amdgpu_device *adev)
1082 {
1083 struct cz_power_info *pi = cz_get_pi(adev);
1084 uint32_t soft_min_clk = 0;
1085 uint32_t soft_max_clk = 0;
1086 int ret = 0;
1087
1088 pi->sclk_dpm.soft_min_clk = pi->sys_info.bootup_sclk;
1089 pi->sclk_dpm.soft_max_clk = pi->sys_info.bootup_sclk;
1090
1091 soft_min_clk = cz_get_sclk_level(adev,
1092 pi->sclk_dpm.soft_min_clk,
1093 PPSMC_MSG_SetSclkSoftMin);
1094 soft_max_clk = cz_get_sclk_level(adev,
1095 pi->sclk_dpm.soft_max_clk,
1096 PPSMC_MSG_SetSclkSoftMax);
1097
1098 ret = cz_send_msg_to_smc_with_parameter(adev,
1099 PPSMC_MSG_SetSclkSoftMin, soft_min_clk);
1100 if (ret)
1101 return -EINVAL;
1102
1103 ret = cz_send_msg_to_smc_with_parameter(adev,
1104 PPSMC_MSG_SetSclkSoftMax, soft_max_clk);
1105 if (ret)
1106 return -EINVAL;
1107
1108 return 0;
1109 }
1110
1111 /* TODO */
1112 static int cz_disable_cgpg(struct amdgpu_device *adev)
1113 {
1114 return 0;
1115 }
1116
1117 /* TODO */
1118 static int cz_enable_cgpg(struct amdgpu_device *adev)
1119 {
1120 return 0;
1121 }
1122
1123 /* TODO */
1124 static int cz_program_pt_config_registers(struct amdgpu_device *adev)
1125 {
1126 return 0;
1127 }
1128
1129 static void cz_do_enable_didt(struct amdgpu_device *adev, bool enable)
1130 {
1131 struct cz_power_info *pi = cz_get_pi(adev);
1132 uint32_t reg = 0;
1133
1134 if (pi->caps_sq_ramping) {
1135 reg = RREG32_DIDT(ixDIDT_SQ_CTRL0);
1136 if (enable)
1137 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1138 else
1139 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1140 WREG32_DIDT(ixDIDT_SQ_CTRL0, reg);
1141 }
1142 if (pi->caps_db_ramping) {
1143 reg = RREG32_DIDT(ixDIDT_DB_CTRL0);
1144 if (enable)
1145 reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 1);
1146 else
1147 reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 0);
1148 WREG32_DIDT(ixDIDT_DB_CTRL0, reg);
1149 }
1150 if (pi->caps_td_ramping) {
1151 reg = RREG32_DIDT(ixDIDT_TD_CTRL0);
1152 if (enable)
1153 reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 1);
1154 else
1155 reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 0);
1156 WREG32_DIDT(ixDIDT_TD_CTRL0, reg);
1157 }
1158 if (pi->caps_tcp_ramping) {
1159 reg = RREG32_DIDT(ixDIDT_TCP_CTRL0);
1160 if (enable)
1161 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1162 else
1163 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1164 WREG32_DIDT(ixDIDT_TCP_CTRL0, reg);
1165 }
1166
1167 }
1168
1169 static int cz_enable_didt(struct amdgpu_device *adev, bool enable)
1170 {
1171 struct cz_power_info *pi = cz_get_pi(adev);
1172 int ret;
1173
1174 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
1175 pi->caps_td_ramping || pi->caps_tcp_ramping) {
1176 if (adev->gfx.gfx_current_status != AMDGPU_GFX_SAFE_MODE) {
1177 ret = cz_disable_cgpg(adev);
1178 if (ret) {
1179 DRM_ERROR("Pre Di/Dt disable cg/pg failed\n");
1180 return -EINVAL;
1181 }
1182 adev->gfx.gfx_current_status = AMDGPU_GFX_SAFE_MODE;
1183 }
1184
1185 ret = cz_program_pt_config_registers(adev);
1186 if (ret) {
1187 DRM_ERROR("Di/Dt config failed\n");
1188 return -EINVAL;
1189 }
1190 cz_do_enable_didt(adev, enable);
1191
1192 if (adev->gfx.gfx_current_status == AMDGPU_GFX_SAFE_MODE) {
1193 ret = cz_enable_cgpg(adev);
1194 if (ret) {
1195 DRM_ERROR("Post Di/Dt enable cg/pg failed\n");
1196 return -EINVAL;
1197 }
1198 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1199 }
1200 }
1201
1202 return 0;
1203 }
1204
1205 /* TODO */
1206 static void cz_reset_acp_boot_level(struct amdgpu_device *adev)
1207 {
1208 }
1209
1210 static void cz_update_current_ps(struct amdgpu_device *adev,
1211 struct amdgpu_ps *rps)
1212 {
1213 struct cz_power_info *pi = cz_get_pi(adev);
1214 struct cz_ps *ps = cz_get_ps(rps);
1215
1216 pi->current_ps = *ps;
1217 pi->current_rps = *rps;
1218 pi->current_rps.ps_priv = ps;
1219
1220 }
1221
1222 static void cz_update_requested_ps(struct amdgpu_device *adev,
1223 struct amdgpu_ps *rps)
1224 {
1225 struct cz_power_info *pi = cz_get_pi(adev);
1226 struct cz_ps *ps = cz_get_ps(rps);
1227
1228 pi->requested_ps = *ps;
1229 pi->requested_rps = *rps;
1230 pi->requested_rps.ps_priv = ps;
1231
1232 }
1233
1234 /* PP arbiter support needed TODO */
1235 static void cz_apply_state_adjust_rules(struct amdgpu_device *adev,
1236 struct amdgpu_ps *new_rps,
1237 struct amdgpu_ps *old_rps)
1238 {
1239 struct cz_ps *ps = cz_get_ps(new_rps);
1240 struct cz_power_info *pi = cz_get_pi(adev);
1241 struct amdgpu_clock_and_voltage_limits *limits =
1242 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1243 /* 10kHz memory clock */
1244 uint32_t mclk = 0;
1245
1246 ps->force_high = false;
1247 ps->need_dfs_bypass = true;
1248 pi->video_start = new_rps->dclk || new_rps->vclk ||
1249 new_rps->evclk || new_rps->ecclk;
1250
1251 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
1252 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
1253 pi->battery_state = true;
1254 else
1255 pi->battery_state = false;
1256
1257 if (pi->caps_stable_power_state)
1258 mclk = limits->mclk;
1259
1260 if (mclk > pi->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK - 1])
1261 ps->force_high = true;
1262
1263 }
1264
1265 static int cz_dpm_enable(struct amdgpu_device *adev)
1266 {
1267 int ret = 0;
1268
1269 /* renable will hang up SMU, so check first */
1270 if (cz_check_for_dpm_enabled(adev))
1271 return -EINVAL;
1272
1273 cz_program_voting_clients(adev);
1274
1275 ret = cz_start_dpm(adev);
1276 if (ret) {
1277 DRM_ERROR("Carrizo DPM enable failed\n");
1278 return -EINVAL;
1279 }
1280
1281 ret = cz_program_bootup_state(adev);
1282 if (ret) {
1283 DRM_ERROR("Carrizo bootup state program failed\n");
1284 return -EINVAL;
1285 }
1286
1287 ret = cz_enable_didt(adev, true);
1288 if (ret) {
1289 DRM_ERROR("Carrizo enable di/dt failed\n");
1290 return -EINVAL;
1291 }
1292
1293 cz_reset_acp_boot_level(adev);
1294
1295 cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1296
1297 return 0;
1298 }
1299
1300 static int cz_dpm_hw_init(void *handle)
1301 {
1302 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1303 int ret = 0;
1304
1305 mutex_lock(&adev->pm.mutex);
1306
1307 /* smu init only needs to be called at startup, not resume.
1308 * It should be in sw_init, but requires the fw info gathered
1309 * in sw_init from other IP modules.
1310 */
1311 ret = cz_smu_init(adev);
1312 if (ret) {
1313 DRM_ERROR("amdgpu: smc initialization failed\n");
1314 mutex_unlock(&adev->pm.mutex);
1315 return ret;
1316 }
1317
1318 /* do the actual fw loading */
1319 ret = cz_smu_start(adev);
1320 if (ret) {
1321 DRM_ERROR("amdgpu: smc start failed\n");
1322 mutex_unlock(&adev->pm.mutex);
1323 return ret;
1324 }
1325
1326 if (!amdgpu_dpm) {
1327 adev->pm.dpm_enabled = false;
1328 mutex_unlock(&adev->pm.mutex);
1329 return ret;
1330 }
1331
1332 /* cz dpm setup asic */
1333 cz_dpm_setup_asic(adev);
1334
1335 /* cz dpm enable */
1336 ret = cz_dpm_enable(adev);
1337 if (ret)
1338 adev->pm.dpm_enabled = false;
1339 else
1340 adev->pm.dpm_enabled = true;
1341
1342 mutex_unlock(&adev->pm.mutex);
1343
1344 return 0;
1345 }
1346
1347 static int cz_dpm_disable(struct amdgpu_device *adev)
1348 {
1349 int ret = 0;
1350
1351 if (!cz_check_for_dpm_enabled(adev))
1352 return -EINVAL;
1353
1354 ret = cz_enable_didt(adev, false);
1355 if (ret) {
1356 DRM_ERROR("Carrizo disable di/dt failed\n");
1357 return -EINVAL;
1358 }
1359
1360 /* powerup blocks */
1361 cz_dpm_powergate_uvd(adev, false);
1362 cz_dpm_powergate_vce(adev, false);
1363
1364 cz_clear_voting_clients(adev);
1365 cz_stop_dpm(adev);
1366 cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1367
1368 return 0;
1369 }
1370
1371 static int cz_dpm_hw_fini(void *handle)
1372 {
1373 int ret = 0;
1374 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1375
1376 mutex_lock(&adev->pm.mutex);
1377
1378 /* smu fini only needs to be called at teardown, not suspend.
1379 * It should be in sw_fini, but we put it here for symmetry
1380 * with smu init.
1381 */
1382 cz_smu_fini(adev);
1383
1384 if (adev->pm.dpm_enabled) {
1385 ret = cz_dpm_disable(adev);
1386
1387 adev->pm.dpm.current_ps =
1388 adev->pm.dpm.requested_ps =
1389 adev->pm.dpm.boot_ps;
1390 }
1391
1392 adev->pm.dpm_enabled = false;
1393
1394 mutex_unlock(&adev->pm.mutex);
1395
1396 return ret;
1397 }
1398
1399 static int cz_dpm_suspend(void *handle)
1400 {
1401 int ret = 0;
1402 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1403
1404 if (adev->pm.dpm_enabled) {
1405 mutex_lock(&adev->pm.mutex);
1406
1407 ret = cz_dpm_disable(adev);
1408
1409 adev->pm.dpm.current_ps =
1410 adev->pm.dpm.requested_ps =
1411 adev->pm.dpm.boot_ps;
1412
1413 mutex_unlock(&adev->pm.mutex);
1414 }
1415
1416 return ret;
1417 }
1418
1419 static int cz_dpm_resume(void *handle)
1420 {
1421 int ret = 0;
1422 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1423
1424 mutex_lock(&adev->pm.mutex);
1425
1426 /* do the actual fw loading */
1427 ret = cz_smu_start(adev);
1428 if (ret) {
1429 DRM_ERROR("amdgpu: smc start failed\n");
1430 mutex_unlock(&adev->pm.mutex);
1431 return ret;
1432 }
1433
1434 if (!amdgpu_dpm) {
1435 adev->pm.dpm_enabled = false;
1436 mutex_unlock(&adev->pm.mutex);
1437 return ret;
1438 }
1439
1440 /* cz dpm setup asic */
1441 cz_dpm_setup_asic(adev);
1442
1443 /* cz dpm enable */
1444 ret = cz_dpm_enable(adev);
1445 if (ret)
1446 adev->pm.dpm_enabled = false;
1447 else
1448 adev->pm.dpm_enabled = true;
1449
1450 mutex_unlock(&adev->pm.mutex);
1451 /* upon resume, re-compute the clocks */
1452 if (adev->pm.dpm_enabled)
1453 amdgpu_pm_compute_clocks(adev);
1454
1455 return 0;
1456 }
1457
1458 static int cz_dpm_set_clockgating_state(void *handle,
1459 enum amd_clockgating_state state)
1460 {
1461 return 0;
1462 }
1463
1464 static int cz_dpm_set_powergating_state(void *handle,
1465 enum amd_powergating_state state)
1466 {
1467 return 0;
1468 }
1469
1470 /* borrowed from KV, need future unify */
1471 static int cz_dpm_get_temperature(struct amdgpu_device *adev)
1472 {
1473 int actual_temp = 0;
1474 uint32_t temp = RREG32_SMC(0xC0300E0C);
1475
1476 if (temp)
1477 actual_temp = 1000 * ((temp / 8) - 49);
1478
1479 return actual_temp;
1480 }
1481
1482 static int cz_dpm_pre_set_power_state(struct amdgpu_device *adev)
1483 {
1484 struct cz_power_info *pi = cz_get_pi(adev);
1485 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1486 struct amdgpu_ps *new_ps = &requested_ps;
1487
1488 cz_update_requested_ps(adev, new_ps);
1489 cz_apply_state_adjust_rules(adev, &pi->requested_rps,
1490 &pi->current_rps);
1491
1492 return 0;
1493 }
1494
1495 static int cz_dpm_update_sclk_limit(struct amdgpu_device *adev)
1496 {
1497 struct cz_power_info *pi = cz_get_pi(adev);
1498 struct amdgpu_clock_and_voltage_limits *limits =
1499 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1500 uint32_t clock, stable_ps_clock = 0;
1501
1502 clock = pi->sclk_dpm.soft_min_clk;
1503
1504 if (pi->caps_stable_power_state) {
1505 stable_ps_clock = limits->sclk * 75 / 100;
1506 if (clock < stable_ps_clock)
1507 clock = stable_ps_clock;
1508 }
1509
1510 if (clock != pi->sclk_dpm.soft_min_clk) {
1511 pi->sclk_dpm.soft_min_clk = clock;
1512 cz_send_msg_to_smc_with_parameter(adev,
1513 PPSMC_MSG_SetSclkSoftMin,
1514 cz_get_sclk_level(adev, clock,
1515 PPSMC_MSG_SetSclkSoftMin));
1516 }
1517
1518 if (pi->caps_stable_power_state &&
1519 pi->sclk_dpm.soft_max_clk != clock) {
1520 pi->sclk_dpm.soft_max_clk = clock;
1521 cz_send_msg_to_smc_with_parameter(adev,
1522 PPSMC_MSG_SetSclkSoftMax,
1523 cz_get_sclk_level(adev, clock,
1524 PPSMC_MSG_SetSclkSoftMax));
1525 } else {
1526 cz_send_msg_to_smc_with_parameter(adev,
1527 PPSMC_MSG_SetSclkSoftMax,
1528 cz_get_sclk_level(adev,
1529 pi->sclk_dpm.soft_max_clk,
1530 PPSMC_MSG_SetSclkSoftMax));
1531 }
1532
1533 return 0;
1534 }
1535
1536 static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
1537 {
1538 int ret = 0;
1539 struct cz_power_info *pi = cz_get_pi(adev);
1540
1541 if (pi->caps_sclk_ds) {
1542 cz_send_msg_to_smc_with_parameter(adev,
1543 PPSMC_MSG_SetMinDeepSleepSclk,
1544 CZ_MIN_DEEP_SLEEP_SCLK);
1545 }
1546
1547 return ret;
1548 }
1549
1550 /* ?? without dal support, is this still needed in setpowerstate list*/
1551 static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev)
1552 {
1553 int ret = 0;
1554 struct cz_power_info *pi = cz_get_pi(adev);
1555
1556 cz_send_msg_to_smc_with_parameter(adev,
1557 PPSMC_MSG_SetWatermarkFrequency,
1558 pi->sclk_dpm.soft_max_clk);
1559
1560 return ret;
1561 }
1562
1563 static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev)
1564 {
1565 int ret = 0;
1566 struct cz_power_info *pi = cz_get_pi(adev);
1567
1568 /* also depend on dal NBPStateDisableRequired */
1569 if (pi->nb_dpm_enabled_by_driver && !pi->nb_dpm_enabled) {
1570 ret = cz_send_msg_to_smc_with_parameter(adev,
1571 PPSMC_MSG_EnableAllSmuFeatures,
1572 NB_DPM_MASK);
1573 if (ret) {
1574 DRM_ERROR("amdgpu: nb dpm enable failed\n");
1575 return ret;
1576 }
1577 pi->nb_dpm_enabled = true;
1578 }
1579
1580 return ret;
1581 }
1582
1583 static void cz_dpm_nbdpm_lm_pstate_enable(struct amdgpu_device *adev,
1584 bool enable)
1585 {
1586 if (enable)
1587 cz_send_msg_to_smc(adev, PPSMC_MSG_EnableLowMemoryPstate);
1588 else
1589 cz_send_msg_to_smc(adev, PPSMC_MSG_DisableLowMemoryPstate);
1590
1591 }
1592
1593 static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
1594 {
1595 int ret = 0;
1596 struct cz_power_info *pi = cz_get_pi(adev);
1597 struct cz_ps *ps = &pi->requested_ps;
1598
1599 if (pi->sys_info.nb_dpm_enable) {
1600 if (ps->force_high)
1601 cz_dpm_nbdpm_lm_pstate_enable(adev, false);
1602 else
1603 cz_dpm_nbdpm_lm_pstate_enable(adev, true);
1604 }
1605
1606 return ret;
1607 }
1608
1609 /* with dpm enabled */
1610 static int cz_dpm_set_power_state(struct amdgpu_device *adev)
1611 {
1612 int ret = 0;
1613
1614 cz_dpm_update_sclk_limit(adev);
1615 cz_dpm_set_deep_sleep_sclk_threshold(adev);
1616 cz_dpm_set_watermark_threshold(adev);
1617 cz_dpm_enable_nbdpm(adev);
1618 cz_dpm_update_low_memory_pstate(adev);
1619
1620 return ret;
1621 }
1622
1623 static void cz_dpm_post_set_power_state(struct amdgpu_device *adev)
1624 {
1625 struct cz_power_info *pi = cz_get_pi(adev);
1626 struct amdgpu_ps *ps = &pi->requested_rps;
1627
1628 cz_update_current_ps(adev, ps);
1629
1630 }
1631
1632 static int cz_dpm_force_highest(struct amdgpu_device *adev)
1633 {
1634 struct cz_power_info *pi = cz_get_pi(adev);
1635 int ret = 0;
1636
1637 if (pi->sclk_dpm.soft_min_clk != pi->sclk_dpm.soft_max_clk) {
1638 pi->sclk_dpm.soft_min_clk =
1639 pi->sclk_dpm.soft_max_clk;
1640 ret = cz_send_msg_to_smc_with_parameter(adev,
1641 PPSMC_MSG_SetSclkSoftMin,
1642 cz_get_sclk_level(adev,
1643 pi->sclk_dpm.soft_min_clk,
1644 PPSMC_MSG_SetSclkSoftMin));
1645 if (ret)
1646 return ret;
1647 }
1648
1649 return ret;
1650 }
1651
1652 static int cz_dpm_force_lowest(struct amdgpu_device *adev)
1653 {
1654 struct cz_power_info *pi = cz_get_pi(adev);
1655 int ret = 0;
1656
1657 if (pi->sclk_dpm.soft_max_clk != pi->sclk_dpm.soft_min_clk) {
1658 pi->sclk_dpm.soft_max_clk = pi->sclk_dpm.soft_min_clk;
1659 ret = cz_send_msg_to_smc_with_parameter(adev,
1660 PPSMC_MSG_SetSclkSoftMax,
1661 cz_get_sclk_level(adev,
1662 pi->sclk_dpm.soft_max_clk,
1663 PPSMC_MSG_SetSclkSoftMax));
1664 if (ret)
1665 return ret;
1666 }
1667
1668 return ret;
1669 }
1670
1671 static uint32_t cz_dpm_get_max_sclk_level(struct amdgpu_device *adev)
1672 {
1673 struct cz_power_info *pi = cz_get_pi(adev);
1674
1675 if (!pi->max_sclk_level) {
1676 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
1677 pi->max_sclk_level = cz_get_argument(adev) + 1;
1678 }
1679
1680 if (pi->max_sclk_level > CZ_MAX_HARDWARE_POWERLEVELS) {
1681 DRM_ERROR("Invalid max sclk level!\n");
1682 return -EINVAL;
1683 }
1684
1685 return pi->max_sclk_level;
1686 }
1687
1688 static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev)
1689 {
1690 struct cz_power_info *pi = cz_get_pi(adev);
1691 struct amdgpu_clock_voltage_dependency_table *dep_table =
1692 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1693 uint32_t level = 0;
1694 int ret = 0;
1695
1696 pi->sclk_dpm.soft_min_clk = dep_table->entries[0].clk;
1697 level = cz_dpm_get_max_sclk_level(adev) - 1;
1698 if (level < dep_table->count)
1699 pi->sclk_dpm.soft_max_clk = dep_table->entries[level].clk;
1700 else
1701 pi->sclk_dpm.soft_max_clk =
1702 dep_table->entries[dep_table->count - 1].clk;
1703
1704 /* get min/max sclk soft value
1705 * notify SMU to execute */
1706 ret = cz_send_msg_to_smc_with_parameter(adev,
1707 PPSMC_MSG_SetSclkSoftMin,
1708 cz_get_sclk_level(adev,
1709 pi->sclk_dpm.soft_min_clk,
1710 PPSMC_MSG_SetSclkSoftMin));
1711 if (ret)
1712 return ret;
1713
1714 ret = cz_send_msg_to_smc_with_parameter(adev,
1715 PPSMC_MSG_SetSclkSoftMax,
1716 cz_get_sclk_level(adev,
1717 pi->sclk_dpm.soft_max_clk,
1718 PPSMC_MSG_SetSclkSoftMax));
1719 if (ret)
1720 return ret;
1721
1722 DRM_DEBUG("DPM unforce state min=%d, max=%d.\n",
1723 pi->sclk_dpm.soft_min_clk,
1724 pi->sclk_dpm.soft_max_clk);
1725
1726 return 0;
1727 }
1728
1729 static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
1730 enum amdgpu_dpm_forced_level level)
1731 {
1732 int ret = 0;
1733
1734 switch (level) {
1735 case AMDGPU_DPM_FORCED_LEVEL_HIGH:
1736 ret = cz_dpm_unforce_dpm_levels(adev);
1737 if (ret)
1738 return ret;
1739 ret = cz_dpm_force_highest(adev);
1740 if (ret)
1741 return ret;
1742 break;
1743 case AMDGPU_DPM_FORCED_LEVEL_LOW:
1744 ret = cz_dpm_unforce_dpm_levels(adev);
1745 if (ret)
1746 return ret;
1747 ret = cz_dpm_force_lowest(adev);
1748 if (ret)
1749 return ret;
1750 break;
1751 case AMDGPU_DPM_FORCED_LEVEL_AUTO:
1752 ret = cz_dpm_unforce_dpm_levels(adev);
1753 if (ret)
1754 return ret;
1755 break;
1756 default:
1757 break;
1758 }
1759
1760 adev->pm.dpm.forced_level = level;
1761
1762 return ret;
1763 }
1764
1765 /* fix me, display configuration change lists here
1766 * mostly dal related*/
1767 static void cz_dpm_display_configuration_changed(struct amdgpu_device *adev)
1768 {
1769 }
1770
1771 static uint32_t cz_dpm_get_sclk(struct amdgpu_device *adev, bool low)
1772 {
1773 struct cz_power_info *pi = cz_get_pi(adev);
1774 struct cz_ps *requested_state = cz_get_ps(&pi->requested_rps);
1775
1776 if (low)
1777 return requested_state->levels[0].sclk;
1778 else
1779 return requested_state->levels[requested_state->num_levels - 1].sclk;
1780
1781 }
1782
1783 static uint32_t cz_dpm_get_mclk(struct amdgpu_device *adev, bool low)
1784 {
1785 struct cz_power_info *pi = cz_get_pi(adev);
1786
1787 return pi->sys_info.bootup_uma_clk;
1788 }
1789
1790 static int cz_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
1791 {
1792 struct cz_power_info *pi = cz_get_pi(adev);
1793 int ret = 0;
1794
1795 if (enable && pi->caps_uvd_dpm ) {
1796 pi->dpm_flags |= DPMFlags_UVD_Enabled;
1797 DRM_DEBUG("UVD DPM Enabled.\n");
1798
1799 ret = cz_send_msg_to_smc_with_parameter(adev,
1800 PPSMC_MSG_EnableAllSmuFeatures, UVD_DPM_MASK);
1801 } else {
1802 pi->dpm_flags &= ~DPMFlags_UVD_Enabled;
1803 DRM_DEBUG("UVD DPM Stopped\n");
1804
1805 ret = cz_send_msg_to_smc_with_parameter(adev,
1806 PPSMC_MSG_DisableAllSmuFeatures, UVD_DPM_MASK);
1807 }
1808
1809 return ret;
1810 }
1811
1812 static int cz_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
1813 {
1814 return cz_enable_uvd_dpm(adev, !gate);
1815 }
1816
1817
1818 static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
1819 {
1820 struct cz_power_info *pi = cz_get_pi(adev);
1821 int ret;
1822
1823 if (pi->uvd_power_gated == gate)
1824 return;
1825
1826 pi->uvd_power_gated = gate;
1827
1828 if (gate) {
1829 if (pi->caps_uvd_pg) {
1830 /* disable clockgating so we can properly shut down the block */
1831 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1832 AMD_CG_STATE_UNGATE);
1833 /* shutdown the UVD block */
1834 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1835 AMD_PG_STATE_GATE);
1836 /* XXX: check for errors */
1837 }
1838 cz_update_uvd_dpm(adev, gate);
1839 if (pi->caps_uvd_pg)
1840 /* power off the UVD block */
1841 cz_send_msg_to_smc(adev, PPSMC_MSG_UVDPowerOFF);
1842 } else {
1843 if (pi->caps_uvd_pg) {
1844 /* power on the UVD block */
1845 if (pi->uvd_dynamic_pg)
1846 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 1);
1847 else
1848 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0);
1849 /* re-init the UVD block */
1850 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1851 AMD_PG_STATE_UNGATE);
1852 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
1853 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1854 AMD_CG_STATE_GATE);
1855 /* XXX: check for errors */
1856 }
1857 cz_update_uvd_dpm(adev, gate);
1858 }
1859 }
1860
1861 static int cz_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1862 {
1863 struct cz_power_info *pi = cz_get_pi(adev);
1864 int ret = 0;
1865
1866 if (enable && pi->caps_vce_dpm) {
1867 pi->dpm_flags |= DPMFlags_VCE_Enabled;
1868 DRM_DEBUG("VCE DPM Enabled.\n");
1869
1870 ret = cz_send_msg_to_smc_with_parameter(adev,
1871 PPSMC_MSG_EnableAllSmuFeatures, VCE_DPM_MASK);
1872
1873 } else {
1874 pi->dpm_flags &= ~DPMFlags_VCE_Enabled;
1875 DRM_DEBUG("VCE DPM Stopped\n");
1876
1877 ret = cz_send_msg_to_smc_with_parameter(adev,
1878 PPSMC_MSG_DisableAllSmuFeatures, VCE_DPM_MASK);
1879 }
1880
1881 return ret;
1882 }
1883
1884 static int cz_update_vce_dpm(struct amdgpu_device *adev)
1885 {
1886 struct cz_power_info *pi = cz_get_pi(adev);
1887 struct amdgpu_vce_clock_voltage_dependency_table *table =
1888 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1889
1890 /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1891 if (pi->caps_stable_power_state) {
1892 pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk;
1893
1894 } else { /* non-stable p-state cases. without vce.Arbiter.EcclkHardMin */
1895 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
1896 }
1897
1898 cz_send_msg_to_smc_with_parameter(adev,
1899 PPSMC_MSG_SetEclkHardMin,
1900 cz_get_eclk_level(adev,
1901 pi->vce_dpm.hard_min_clk,
1902 PPSMC_MSG_SetEclkHardMin));
1903 return 0;
1904 }
1905
1906 static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1907 {
1908 struct cz_power_info *pi = cz_get_pi(adev);
1909
1910 if (pi->caps_vce_pg) {
1911 if (pi->vce_power_gated != gate) {
1912 if (gate) {
1913 /* disable clockgating so we can properly shut down the block */
1914 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1915 AMD_CG_STATE_UNGATE);
1916 /* shutdown the VCE block */
1917 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1918 AMD_PG_STATE_GATE);
1919
1920 cz_enable_vce_dpm(adev, false);
1921 /* TODO: to figure out why vce can't be poweroff. */
1922 /* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */
1923 pi->vce_power_gated = true;
1924 } else {
1925 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
1926 pi->vce_power_gated = false;
1927
1928 /* re-init the VCE block */
1929 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1930 AMD_PG_STATE_UNGATE);
1931 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
1932 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1933 AMD_CG_STATE_GATE);
1934
1935 cz_update_vce_dpm(adev);
1936 cz_enable_vce_dpm(adev, true);
1937 }
1938 } else {
1939 if (! pi->vce_power_gated) {
1940 cz_update_vce_dpm(adev);
1941 }
1942 }
1943 } else { /*pi->caps_vce_pg*/
1944 cz_update_vce_dpm(adev);
1945 cz_enable_vce_dpm(adev, true);
1946 }
1947
1948 return;
1949 }
1950
1951 const struct amd_ip_funcs cz_dpm_ip_funcs = {
1952 .early_init = cz_dpm_early_init,
1953 .late_init = cz_dpm_late_init,
1954 .sw_init = cz_dpm_sw_init,
1955 .sw_fini = cz_dpm_sw_fini,
1956 .hw_init = cz_dpm_hw_init,
1957 .hw_fini = cz_dpm_hw_fini,
1958 .suspend = cz_dpm_suspend,
1959 .resume = cz_dpm_resume,
1960 .is_idle = NULL,
1961 .wait_for_idle = NULL,
1962 .soft_reset = NULL,
1963 .print_status = NULL,
1964 .set_clockgating_state = cz_dpm_set_clockgating_state,
1965 .set_powergating_state = cz_dpm_set_powergating_state,
1966 };
1967
1968 static const struct amdgpu_dpm_funcs cz_dpm_funcs = {
1969 .get_temperature = cz_dpm_get_temperature,
1970 .pre_set_power_state = cz_dpm_pre_set_power_state,
1971 .set_power_state = cz_dpm_set_power_state,
1972 .post_set_power_state = cz_dpm_post_set_power_state,
1973 .display_configuration_changed = cz_dpm_display_configuration_changed,
1974 .get_sclk = cz_dpm_get_sclk,
1975 .get_mclk = cz_dpm_get_mclk,
1976 .print_power_state = cz_dpm_print_power_state,
1977 .debugfs_print_current_performance_level =
1978 cz_dpm_debugfs_print_current_performance_level,
1979 .force_performance_level = cz_dpm_force_dpm_level,
1980 .vblank_too_short = NULL,
1981 .powergate_uvd = cz_dpm_powergate_uvd,
1982 .powergate_vce = cz_dpm_powergate_vce,
1983 };
1984
1985 static void cz_dpm_set_funcs(struct amdgpu_device *adev)
1986 {
1987 if (NULL == adev->pm.funcs)
1988 adev->pm.funcs = &cz_dpm_funcs;
1989 }
Linux kernel - Deliverables
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