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drm/amdgpu/gmc7: remove dead code (v2)
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / dce_v10_0.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "drmP.h"
24 #include "amdgpu.h"
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
27 #include "vid.h"
28 #include "atom.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
34
35 #include "dce/dce_10_0_d.h"
36 #include "dce/dce_10_0_sh_mask.h"
37 #include "dce/dce_10_0_enum.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
42
43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
45
46 static const u32 crtc_offsets[] =
47 {
48 CRTC0_REGISTER_OFFSET,
49 CRTC1_REGISTER_OFFSET,
50 CRTC2_REGISTER_OFFSET,
51 CRTC3_REGISTER_OFFSET,
52 CRTC4_REGISTER_OFFSET,
53 CRTC5_REGISTER_OFFSET,
54 CRTC6_REGISTER_OFFSET
55 };
56
57 static const u32 hpd_offsets[] =
58 {
59 HPD0_REGISTER_OFFSET,
60 HPD1_REGISTER_OFFSET,
61 HPD2_REGISTER_OFFSET,
62 HPD3_REGISTER_OFFSET,
63 HPD4_REGISTER_OFFSET,
64 HPD5_REGISTER_OFFSET
65 };
66
67 static const uint32_t dig_offsets[] = {
68 DIG0_REGISTER_OFFSET,
69 DIG1_REGISTER_OFFSET,
70 DIG2_REGISTER_OFFSET,
71 DIG3_REGISTER_OFFSET,
72 DIG4_REGISTER_OFFSET,
73 DIG5_REGISTER_OFFSET,
74 DIG6_REGISTER_OFFSET
75 };
76
77 static const struct {
78 uint32_t reg;
79 uint32_t vblank;
80 uint32_t vline;
81 uint32_t hpd;
82
83 } interrupt_status_offsets[] = { {
84 .reg = mmDISP_INTERRUPT_STATUS,
85 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
86 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
87 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
88 }, {
89 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
90 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
91 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
92 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
93 }, {
94 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
95 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
96 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
97 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
98 }, {
99 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
100 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
101 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
102 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
103 }, {
104 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
105 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
106 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
107 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
108 }, {
109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
111 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
113 } };
114
115 static const u32 golden_settings_tonga_a11[] =
116 {
117 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
118 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
119 mmFBC_MISC, 0x1f311fff, 0x12300000,
120 mmHDMI_CONTROL, 0x31000111, 0x00000011,
121 };
122
123 static const u32 tonga_mgcg_cgcg_init[] =
124 {
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127 };
128
129 static const u32 golden_settings_fiji_a10[] =
130 {
131 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
132 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
133 mmFBC_MISC, 0x1f311fff, 0x12300000,
134 mmHDMI_CONTROL, 0x31000111, 0x00000011,
135 };
136
137 static const u32 fiji_mgcg_cgcg_init[] =
138 {
139 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
140 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
141 };
142
143 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
144 {
145 switch (adev->asic_type) {
146 case CHIP_FIJI:
147 amdgpu_program_register_sequence(adev,
148 fiji_mgcg_cgcg_init,
149 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
150 amdgpu_program_register_sequence(adev,
151 golden_settings_fiji_a10,
152 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
153 break;
154 case CHIP_TONGA:
155 amdgpu_program_register_sequence(adev,
156 tonga_mgcg_cgcg_init,
157 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
158 amdgpu_program_register_sequence(adev,
159 golden_settings_tonga_a11,
160 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
161 break;
162 default:
163 break;
164 }
165 }
166
167 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
168 u32 block_offset, u32 reg)
169 {
170 unsigned long flags;
171 u32 r;
172
173 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
174 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
175 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
176 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
177
178 return r;
179 }
180
181 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
182 u32 block_offset, u32 reg, u32 v)
183 {
184 unsigned long flags;
185
186 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
187 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
188 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
189 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
190 }
191
192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
193 {
194 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
195 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
196 return true;
197 else
198 return false;
199 }
200
201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
202 {
203 u32 pos1, pos2;
204
205 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
206 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
207
208 if (pos1 != pos2)
209 return true;
210 else
211 return false;
212 }
213
214 /**
215 * dce_v10_0_vblank_wait - vblank wait asic callback.
216 *
217 * @adev: amdgpu_device pointer
218 * @crtc: crtc to wait for vblank on
219 *
220 * Wait for vblank on the requested crtc (evergreen+).
221 */
222 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
223 {
224 unsigned i = 0;
225
226 if (crtc >= adev->mode_info.num_crtc)
227 return;
228
229 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
230 return;
231
232 /* depending on when we hit vblank, we may be close to active; if so,
233 * wait for another frame.
234 */
235 while (dce_v10_0_is_in_vblank(adev, crtc)) {
236 if (i++ % 100 == 0) {
237 if (!dce_v10_0_is_counter_moving(adev, crtc))
238 break;
239 }
240 }
241
242 while (!dce_v10_0_is_in_vblank(adev, crtc)) {
243 if (i++ % 100 == 0) {
244 if (!dce_v10_0_is_counter_moving(adev, crtc))
245 break;
246 }
247 }
248 }
249
250 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
251 {
252 if (crtc >= adev->mode_info.num_crtc)
253 return 0;
254 else
255 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
256 }
257
258 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
259 {
260 unsigned i;
261
262 /* Enable pflip interrupts */
263 for (i = 0; i < adev->mode_info.num_crtc; i++)
264 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
265 }
266
267 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
268 {
269 unsigned i;
270
271 /* Disable pflip interrupts */
272 for (i = 0; i < adev->mode_info.num_crtc; i++)
273 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
274 }
275
276 /**
277 * dce_v10_0_page_flip - pageflip callback.
278 *
279 * @adev: amdgpu_device pointer
280 * @crtc_id: crtc to cleanup pageflip on
281 * @crtc_base: new address of the crtc (GPU MC address)
282 *
283 * Triggers the actual pageflip by updating the primary
284 * surface base address.
285 */
286 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
287 int crtc_id, u64 crtc_base, bool async)
288 {
289 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
290 u32 tmp;
291
292 /* flip at hsync for async, default is vsync */
293 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
294 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
295 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
296 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
297 /* update the primary scanout address */
298 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
299 upper_32_bits(crtc_base));
300 /* writing to the low address triggers the update */
301 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
302 lower_32_bits(crtc_base));
303 /* post the write */
304 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
305 }
306
307 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
308 u32 *vbl, u32 *position)
309 {
310 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
311 return -EINVAL;
312
313 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
314 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
315
316 return 0;
317 }
318
319 /**
320 * dce_v10_0_hpd_sense - hpd sense callback.
321 *
322 * @adev: amdgpu_device pointer
323 * @hpd: hpd (hotplug detect) pin
324 *
325 * Checks if a digital monitor is connected (evergreen+).
326 * Returns true if connected, false if not connected.
327 */
328 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
329 enum amdgpu_hpd_id hpd)
330 {
331 int idx;
332 bool connected = false;
333
334 switch (hpd) {
335 case AMDGPU_HPD_1:
336 idx = 0;
337 break;
338 case AMDGPU_HPD_2:
339 idx = 1;
340 break;
341 case AMDGPU_HPD_3:
342 idx = 2;
343 break;
344 case AMDGPU_HPD_4:
345 idx = 3;
346 break;
347 case AMDGPU_HPD_5:
348 idx = 4;
349 break;
350 case AMDGPU_HPD_6:
351 idx = 5;
352 break;
353 default:
354 return connected;
355 }
356
357 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
358 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
359 connected = true;
360
361 return connected;
362 }
363
364 /**
365 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
366 *
367 * @adev: amdgpu_device pointer
368 * @hpd: hpd (hotplug detect) pin
369 *
370 * Set the polarity of the hpd pin (evergreen+).
371 */
372 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
373 enum amdgpu_hpd_id hpd)
374 {
375 u32 tmp;
376 bool connected = dce_v10_0_hpd_sense(adev, hpd);
377 int idx;
378
379 switch (hpd) {
380 case AMDGPU_HPD_1:
381 idx = 0;
382 break;
383 case AMDGPU_HPD_2:
384 idx = 1;
385 break;
386 case AMDGPU_HPD_3:
387 idx = 2;
388 break;
389 case AMDGPU_HPD_4:
390 idx = 3;
391 break;
392 case AMDGPU_HPD_5:
393 idx = 4;
394 break;
395 case AMDGPU_HPD_6:
396 idx = 5;
397 break;
398 default:
399 return;
400 }
401
402 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
403 if (connected)
404 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
405 else
406 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
407 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
408 }
409
410 /**
411 * dce_v10_0_hpd_init - hpd setup callback.
412 *
413 * @adev: amdgpu_device pointer
414 *
415 * Setup the hpd pins used by the card (evergreen+).
416 * Enable the pin, set the polarity, and enable the hpd interrupts.
417 */
418 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
419 {
420 struct drm_device *dev = adev->ddev;
421 struct drm_connector *connector;
422 u32 tmp;
423 int idx;
424
425 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
426 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
427
428 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
429 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
430 /* don't try to enable hpd on eDP or LVDS avoid breaking the
431 * aux dp channel on imac and help (but not completely fix)
432 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
433 * also avoid interrupt storms during dpms.
434 */
435 continue;
436 }
437
438 switch (amdgpu_connector->hpd.hpd) {
439 case AMDGPU_HPD_1:
440 idx = 0;
441 break;
442 case AMDGPU_HPD_2:
443 idx = 1;
444 break;
445 case AMDGPU_HPD_3:
446 idx = 2;
447 break;
448 case AMDGPU_HPD_4:
449 idx = 3;
450 break;
451 case AMDGPU_HPD_5:
452 idx = 4;
453 break;
454 case AMDGPU_HPD_6:
455 idx = 5;
456 break;
457 default:
458 continue;
459 }
460
461 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
462 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
463 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
464
465 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
466 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
467 DC_HPD_CONNECT_INT_DELAY,
468 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
469 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
470 DC_HPD_DISCONNECT_INT_DELAY,
471 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
472 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
473
474 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
475 amdgpu_irq_get(adev, &adev->hpd_irq,
476 amdgpu_connector->hpd.hpd);
477 }
478 }
479
480 /**
481 * dce_v10_0_hpd_fini - hpd tear down callback.
482 *
483 * @adev: amdgpu_device pointer
484 *
485 * Tear down the hpd pins used by the card (evergreen+).
486 * Disable the hpd interrupts.
487 */
488 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
489 {
490 struct drm_device *dev = adev->ddev;
491 struct drm_connector *connector;
492 u32 tmp;
493 int idx;
494
495 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
496 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
497
498 switch (amdgpu_connector->hpd.hpd) {
499 case AMDGPU_HPD_1:
500 idx = 0;
501 break;
502 case AMDGPU_HPD_2:
503 idx = 1;
504 break;
505 case AMDGPU_HPD_3:
506 idx = 2;
507 break;
508 case AMDGPU_HPD_4:
509 idx = 3;
510 break;
511 case AMDGPU_HPD_5:
512 idx = 4;
513 break;
514 case AMDGPU_HPD_6:
515 idx = 5;
516 break;
517 default:
518 continue;
519 }
520
521 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
522 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
523 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
524
525 amdgpu_irq_put(adev, &adev->hpd_irq,
526 amdgpu_connector->hpd.hpd);
527 }
528 }
529
530 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
531 {
532 return mmDC_GPIO_HPD_A;
533 }
534
535 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
536 {
537 u32 crtc_hung = 0;
538 u32 crtc_status[6];
539 u32 i, j, tmp;
540
541 for (i = 0; i < adev->mode_info.num_crtc; i++) {
542 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
543 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
544 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
545 crtc_hung |= (1 << i);
546 }
547 }
548
549 for (j = 0; j < 10; j++) {
550 for (i = 0; i < adev->mode_info.num_crtc; i++) {
551 if (crtc_hung & (1 << i)) {
552 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
553 if (tmp != crtc_status[i])
554 crtc_hung &= ~(1 << i);
555 }
556 }
557 if (crtc_hung == 0)
558 return false;
559 udelay(100);
560 }
561
562 return true;
563 }
564
565 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
566 struct amdgpu_mode_mc_save *save)
567 {
568 u32 crtc_enabled, tmp;
569 int i;
570
571 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
572 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
573
574 /* disable VGA render */
575 tmp = RREG32(mmVGA_RENDER_CONTROL);
576 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
577 WREG32(mmVGA_RENDER_CONTROL, tmp);
578
579 /* blank the display controllers */
580 for (i = 0; i < adev->mode_info.num_crtc; i++) {
581 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
582 CRTC_CONTROL, CRTC_MASTER_EN);
583 if (crtc_enabled) {
584 #if 0
585 u32 frame_count;
586 int j;
587
588 save->crtc_enabled[i] = true;
589 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
590 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
591 amdgpu_display_vblank_wait(adev, i);
592 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
593 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
594 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
595 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
596 }
597 /* wait for the next frame */
598 frame_count = amdgpu_display_vblank_get_counter(adev, i);
599 for (j = 0; j < adev->usec_timeout; j++) {
600 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
601 break;
602 udelay(1);
603 }
604 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
605 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
606 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
607 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
608 }
609 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
610 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
611 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
612 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
613 }
614 #else
615 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
616 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
617 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
618 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
619 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
620 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
621 save->crtc_enabled[i] = false;
622 /* ***** */
623 #endif
624 } else {
625 save->crtc_enabled[i] = false;
626 }
627 }
628 }
629
630 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
631 struct amdgpu_mode_mc_save *save)
632 {
633 u32 tmp, frame_count;
634 int i, j;
635
636 /* update crtc base addresses */
637 for (i = 0; i < adev->mode_info.num_crtc; i++) {
638 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
639 upper_32_bits(adev->mc.vram_start));
640 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
641 upper_32_bits(adev->mc.vram_start));
642 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
643 (u32)adev->mc.vram_start);
644 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
645 (u32)adev->mc.vram_start);
646
647 if (save->crtc_enabled[i]) {
648 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
649 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 0) {
650 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 0);
651 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
652 }
653 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
654 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
655 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
656 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
657 }
658 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
659 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
660 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
661 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
662 }
663 for (j = 0; j < adev->usec_timeout; j++) {
664 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
665 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
666 break;
667 udelay(1);
668 }
669 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
670 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
671 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
672 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
673 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
674 /* wait for the next frame */
675 frame_count = amdgpu_display_vblank_get_counter(adev, i);
676 for (j = 0; j < adev->usec_timeout; j++) {
677 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
678 break;
679 udelay(1);
680 }
681 }
682 }
683
684 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
685 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
686
687 /* Unlock vga access */
688 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
689 mdelay(1);
690 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
691 }
692
693 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
694 bool render)
695 {
696 u32 tmp;
697
698 /* Lockout access through VGA aperture*/
699 tmp = RREG32(mmVGA_HDP_CONTROL);
700 if (render)
701 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
702 else
703 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
704 WREG32(mmVGA_HDP_CONTROL, tmp);
705
706 /* disable VGA render */
707 tmp = RREG32(mmVGA_RENDER_CONTROL);
708 if (render)
709 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
710 else
711 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
712 WREG32(mmVGA_RENDER_CONTROL, tmp);
713 }
714
715 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
716 {
717 int num_crtc = 0;
718
719 switch (adev->asic_type) {
720 case CHIP_FIJI:
721 case CHIP_TONGA:
722 num_crtc = 6;
723 break;
724 default:
725 num_crtc = 0;
726 }
727 return num_crtc;
728 }
729
730 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
731 {
732 /*Disable VGA render and enabled crtc, if has DCE engine*/
733 if (amdgpu_atombios_has_dce_engine_info(adev)) {
734 u32 tmp;
735 int crtc_enabled, i;
736
737 dce_v10_0_set_vga_render_state(adev, false);
738
739 /*Disable crtc*/
740 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
741 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
742 CRTC_CONTROL, CRTC_MASTER_EN);
743 if (crtc_enabled) {
744 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
745 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
746 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
747 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
748 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
749 }
750 }
751 }
752 }
753
754 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
755 {
756 struct drm_device *dev = encoder->dev;
757 struct amdgpu_device *adev = dev->dev_private;
758 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
759 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
760 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
761 int bpc = 0;
762 u32 tmp = 0;
763 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
764
765 if (connector) {
766 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
767 bpc = amdgpu_connector_get_monitor_bpc(connector);
768 dither = amdgpu_connector->dither;
769 }
770
771 /* LVDS/eDP FMT is set up by atom */
772 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
773 return;
774
775 /* not needed for analog */
776 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
777 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
778 return;
779
780 if (bpc == 0)
781 return;
782
783 switch (bpc) {
784 case 6:
785 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
786 /* XXX sort out optimal dither settings */
787 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
788 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
789 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
790 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
791 } else {
792 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
793 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
794 }
795 break;
796 case 8:
797 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
798 /* XXX sort out optimal dither settings */
799 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
800 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
801 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
802 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
803 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
804 } else {
805 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
806 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
807 }
808 break;
809 case 10:
810 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
811 /* XXX sort out optimal dither settings */
812 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
813 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
814 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
815 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
816 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
817 } else {
818 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
819 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
820 }
821 break;
822 default:
823 /* not needed */
824 break;
825 }
826
827 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
828 }
829
830
831 /* display watermark setup */
832 /**
833 * dce_v10_0_line_buffer_adjust - Set up the line buffer
834 *
835 * @adev: amdgpu_device pointer
836 * @amdgpu_crtc: the selected display controller
837 * @mode: the current display mode on the selected display
838 * controller
839 *
840 * Setup up the line buffer allocation for
841 * the selected display controller (CIK).
842 * Returns the line buffer size in pixels.
843 */
844 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
845 struct amdgpu_crtc *amdgpu_crtc,
846 struct drm_display_mode *mode)
847 {
848 u32 tmp, buffer_alloc, i, mem_cfg;
849 u32 pipe_offset = amdgpu_crtc->crtc_id;
850 /*
851 * Line Buffer Setup
852 * There are 6 line buffers, one for each display controllers.
853 * There are 3 partitions per LB. Select the number of partitions
854 * to enable based on the display width. For display widths larger
855 * than 4096, you need use to use 2 display controllers and combine
856 * them using the stereo blender.
857 */
858 if (amdgpu_crtc->base.enabled && mode) {
859 if (mode->crtc_hdisplay < 1920) {
860 mem_cfg = 1;
861 buffer_alloc = 2;
862 } else if (mode->crtc_hdisplay < 2560) {
863 mem_cfg = 2;
864 buffer_alloc = 2;
865 } else if (mode->crtc_hdisplay < 4096) {
866 mem_cfg = 0;
867 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
868 } else {
869 DRM_DEBUG_KMS("Mode too big for LB!\n");
870 mem_cfg = 0;
871 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
872 }
873 } else {
874 mem_cfg = 1;
875 buffer_alloc = 0;
876 }
877
878 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
879 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
880 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
881
882 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
883 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
884 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
885
886 for (i = 0; i < adev->usec_timeout; i++) {
887 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
888 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
889 break;
890 udelay(1);
891 }
892
893 if (amdgpu_crtc->base.enabled && mode) {
894 switch (mem_cfg) {
895 case 0:
896 default:
897 return 4096 * 2;
898 case 1:
899 return 1920 * 2;
900 case 2:
901 return 2560 * 2;
902 }
903 }
904
905 /* controller not enabled, so no lb used */
906 return 0;
907 }
908
909 /**
910 * cik_get_number_of_dram_channels - get the number of dram channels
911 *
912 * @adev: amdgpu_device pointer
913 *
914 * Look up the number of video ram channels (CIK).
915 * Used for display watermark bandwidth calculations
916 * Returns the number of dram channels
917 */
918 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
919 {
920 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
921
922 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
923 case 0:
924 default:
925 return 1;
926 case 1:
927 return 2;
928 case 2:
929 return 4;
930 case 3:
931 return 8;
932 case 4:
933 return 3;
934 case 5:
935 return 6;
936 case 6:
937 return 10;
938 case 7:
939 return 12;
940 case 8:
941 return 16;
942 }
943 }
944
945 struct dce10_wm_params {
946 u32 dram_channels; /* number of dram channels */
947 u32 yclk; /* bandwidth per dram data pin in kHz */
948 u32 sclk; /* engine clock in kHz */
949 u32 disp_clk; /* display clock in kHz */
950 u32 src_width; /* viewport width */
951 u32 active_time; /* active display time in ns */
952 u32 blank_time; /* blank time in ns */
953 bool interlaced; /* mode is interlaced */
954 fixed20_12 vsc; /* vertical scale ratio */
955 u32 num_heads; /* number of active crtcs */
956 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
957 u32 lb_size; /* line buffer allocated to pipe */
958 u32 vtaps; /* vertical scaler taps */
959 };
960
961 /**
962 * dce_v10_0_dram_bandwidth - get the dram bandwidth
963 *
964 * @wm: watermark calculation data
965 *
966 * Calculate the raw dram bandwidth (CIK).
967 * Used for display watermark bandwidth calculations
968 * Returns the dram bandwidth in MBytes/s
969 */
970 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
971 {
972 /* Calculate raw DRAM Bandwidth */
973 fixed20_12 dram_efficiency; /* 0.7 */
974 fixed20_12 yclk, dram_channels, bandwidth;
975 fixed20_12 a;
976
977 a.full = dfixed_const(1000);
978 yclk.full = dfixed_const(wm->yclk);
979 yclk.full = dfixed_div(yclk, a);
980 dram_channels.full = dfixed_const(wm->dram_channels * 4);
981 a.full = dfixed_const(10);
982 dram_efficiency.full = dfixed_const(7);
983 dram_efficiency.full = dfixed_div(dram_efficiency, a);
984 bandwidth.full = dfixed_mul(dram_channels, yclk);
985 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
986
987 return dfixed_trunc(bandwidth);
988 }
989
990 /**
991 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
992 *
993 * @wm: watermark calculation data
994 *
995 * Calculate the dram bandwidth used for display (CIK).
996 * Used for display watermark bandwidth calculations
997 * Returns the dram bandwidth for display in MBytes/s
998 */
999 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1000 {
1001 /* Calculate DRAM Bandwidth and the part allocated to display. */
1002 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
1003 fixed20_12 yclk, dram_channels, bandwidth;
1004 fixed20_12 a;
1005
1006 a.full = dfixed_const(1000);
1007 yclk.full = dfixed_const(wm->yclk);
1008 yclk.full = dfixed_div(yclk, a);
1009 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1010 a.full = dfixed_const(10);
1011 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
1012 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
1013 bandwidth.full = dfixed_mul(dram_channels, yclk);
1014 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
1015
1016 return dfixed_trunc(bandwidth);
1017 }
1018
1019 /**
1020 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
1021 *
1022 * @wm: watermark calculation data
1023 *
1024 * Calculate the data return bandwidth used for display (CIK).
1025 * Used for display watermark bandwidth calculations
1026 * Returns the data return bandwidth in MBytes/s
1027 */
1028 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
1029 {
1030 /* Calculate the display Data return Bandwidth */
1031 fixed20_12 return_efficiency; /* 0.8 */
1032 fixed20_12 sclk, bandwidth;
1033 fixed20_12 a;
1034
1035 a.full = dfixed_const(1000);
1036 sclk.full = dfixed_const(wm->sclk);
1037 sclk.full = dfixed_div(sclk, a);
1038 a.full = dfixed_const(10);
1039 return_efficiency.full = dfixed_const(8);
1040 return_efficiency.full = dfixed_div(return_efficiency, a);
1041 a.full = dfixed_const(32);
1042 bandwidth.full = dfixed_mul(a, sclk);
1043 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1044
1045 return dfixed_trunc(bandwidth);
1046 }
1047
1048 /**
1049 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
1050 *
1051 * @wm: watermark calculation data
1052 *
1053 * Calculate the dmif bandwidth used for display (CIK).
1054 * Used for display watermark bandwidth calculations
1055 * Returns the dmif bandwidth in MBytes/s
1056 */
1057 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1058 {
1059 /* Calculate the DMIF Request Bandwidth */
1060 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1061 fixed20_12 disp_clk, bandwidth;
1062 fixed20_12 a, b;
1063
1064 a.full = dfixed_const(1000);
1065 disp_clk.full = dfixed_const(wm->disp_clk);
1066 disp_clk.full = dfixed_div(disp_clk, a);
1067 a.full = dfixed_const(32);
1068 b.full = dfixed_mul(a, disp_clk);
1069
1070 a.full = dfixed_const(10);
1071 disp_clk_request_efficiency.full = dfixed_const(8);
1072 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1073
1074 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1075
1076 return dfixed_trunc(bandwidth);
1077 }
1078
1079 /**
1080 * dce_v10_0_available_bandwidth - get the min available bandwidth
1081 *
1082 * @wm: watermark calculation data
1083 *
1084 * Calculate the min available bandwidth used for display (CIK).
1085 * Used for display watermark bandwidth calculations
1086 * Returns the min available bandwidth in MBytes/s
1087 */
1088 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1089 {
1090 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1091 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1092 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1093 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1094
1095 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1096 }
1097
1098 /**
1099 * dce_v10_0_average_bandwidth - get the average available bandwidth
1100 *
1101 * @wm: watermark calculation data
1102 *
1103 * Calculate the average available bandwidth used for display (CIK).
1104 * Used for display watermark bandwidth calculations
1105 * Returns the average available bandwidth in MBytes/s
1106 */
1107 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1108 {
1109 /* Calculate the display mode Average Bandwidth
1110 * DisplayMode should contain the source and destination dimensions,
1111 * timing, etc.
1112 */
1113 fixed20_12 bpp;
1114 fixed20_12 line_time;
1115 fixed20_12 src_width;
1116 fixed20_12 bandwidth;
1117 fixed20_12 a;
1118
1119 a.full = dfixed_const(1000);
1120 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1121 line_time.full = dfixed_div(line_time, a);
1122 bpp.full = dfixed_const(wm->bytes_per_pixel);
1123 src_width.full = dfixed_const(wm->src_width);
1124 bandwidth.full = dfixed_mul(src_width, bpp);
1125 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1126 bandwidth.full = dfixed_div(bandwidth, line_time);
1127
1128 return dfixed_trunc(bandwidth);
1129 }
1130
1131 /**
1132 * dce_v10_0_latency_watermark - get the latency watermark
1133 *
1134 * @wm: watermark calculation data
1135 *
1136 * Calculate the latency watermark (CIK).
1137 * Used for display watermark bandwidth calculations
1138 * Returns the latency watermark in ns
1139 */
1140 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1141 {
1142 /* First calculate the latency in ns */
1143 u32 mc_latency = 2000; /* 2000 ns. */
1144 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1145 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1146 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1147 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1148 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1149 (wm->num_heads * cursor_line_pair_return_time);
1150 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1151 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1152 u32 tmp, dmif_size = 12288;
1153 fixed20_12 a, b, c;
1154
1155 if (wm->num_heads == 0)
1156 return 0;
1157
1158 a.full = dfixed_const(2);
1159 b.full = dfixed_const(1);
1160 if ((wm->vsc.full > a.full) ||
1161 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1162 (wm->vtaps >= 5) ||
1163 ((wm->vsc.full >= a.full) && wm->interlaced))
1164 max_src_lines_per_dst_line = 4;
1165 else
1166 max_src_lines_per_dst_line = 2;
1167
1168 a.full = dfixed_const(available_bandwidth);
1169 b.full = dfixed_const(wm->num_heads);
1170 a.full = dfixed_div(a, b);
1171
1172 b.full = dfixed_const(mc_latency + 512);
1173 c.full = dfixed_const(wm->disp_clk);
1174 b.full = dfixed_div(b, c);
1175
1176 c.full = dfixed_const(dmif_size);
1177 b.full = dfixed_div(c, b);
1178
1179 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1180
1181 b.full = dfixed_const(1000);
1182 c.full = dfixed_const(wm->disp_clk);
1183 b.full = dfixed_div(c, b);
1184 c.full = dfixed_const(wm->bytes_per_pixel);
1185 b.full = dfixed_mul(b, c);
1186
1187 lb_fill_bw = min(tmp, dfixed_trunc(b));
1188
1189 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1190 b.full = dfixed_const(1000);
1191 c.full = dfixed_const(lb_fill_bw);
1192 b.full = dfixed_div(c, b);
1193 a.full = dfixed_div(a, b);
1194 line_fill_time = dfixed_trunc(a);
1195
1196 if (line_fill_time < wm->active_time)
1197 return latency;
1198 else
1199 return latency + (line_fill_time - wm->active_time);
1200
1201 }
1202
1203 /**
1204 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1205 * average and available dram bandwidth
1206 *
1207 * @wm: watermark calculation data
1208 *
1209 * Check if the display average bandwidth fits in the display
1210 * dram bandwidth (CIK).
1211 * Used for display watermark bandwidth calculations
1212 * Returns true if the display fits, false if not.
1213 */
1214 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1215 {
1216 if (dce_v10_0_average_bandwidth(wm) <=
1217 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1218 return true;
1219 else
1220 return false;
1221 }
1222
1223 /**
1224 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1225 * average and available bandwidth
1226 *
1227 * @wm: watermark calculation data
1228 *
1229 * Check if the display average bandwidth fits in the display
1230 * available bandwidth (CIK).
1231 * Used for display watermark bandwidth calculations
1232 * Returns true if the display fits, false if not.
1233 */
1234 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1235 {
1236 if (dce_v10_0_average_bandwidth(wm) <=
1237 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1238 return true;
1239 else
1240 return false;
1241 }
1242
1243 /**
1244 * dce_v10_0_check_latency_hiding - check latency hiding
1245 *
1246 * @wm: watermark calculation data
1247 *
1248 * Check latency hiding (CIK).
1249 * Used for display watermark bandwidth calculations
1250 * Returns true if the display fits, false if not.
1251 */
1252 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1253 {
1254 u32 lb_partitions = wm->lb_size / wm->src_width;
1255 u32 line_time = wm->active_time + wm->blank_time;
1256 u32 latency_tolerant_lines;
1257 u32 latency_hiding;
1258 fixed20_12 a;
1259
1260 a.full = dfixed_const(1);
1261 if (wm->vsc.full > a.full)
1262 latency_tolerant_lines = 1;
1263 else {
1264 if (lb_partitions <= (wm->vtaps + 1))
1265 latency_tolerant_lines = 1;
1266 else
1267 latency_tolerant_lines = 2;
1268 }
1269
1270 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1271
1272 if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1273 return true;
1274 else
1275 return false;
1276 }
1277
1278 /**
1279 * dce_v10_0_program_watermarks - program display watermarks
1280 *
1281 * @adev: amdgpu_device pointer
1282 * @amdgpu_crtc: the selected display controller
1283 * @lb_size: line buffer size
1284 * @num_heads: number of display controllers in use
1285 *
1286 * Calculate and program the display watermarks for the
1287 * selected display controller (CIK).
1288 */
1289 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1290 struct amdgpu_crtc *amdgpu_crtc,
1291 u32 lb_size, u32 num_heads)
1292 {
1293 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1294 struct dce10_wm_params wm_low, wm_high;
1295 u32 pixel_period;
1296 u32 line_time = 0;
1297 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1298 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1299
1300 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1301 pixel_period = 1000000 / (u32)mode->clock;
1302 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1303
1304 /* watermark for high clocks */
1305 if (adev->pm.dpm_enabled) {
1306 wm_high.yclk =
1307 amdgpu_dpm_get_mclk(adev, false) * 10;
1308 wm_high.sclk =
1309 amdgpu_dpm_get_sclk(adev, false) * 10;
1310 } else {
1311 wm_high.yclk = adev->pm.current_mclk * 10;
1312 wm_high.sclk = adev->pm.current_sclk * 10;
1313 }
1314
1315 wm_high.disp_clk = mode->clock;
1316 wm_high.src_width = mode->crtc_hdisplay;
1317 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1318 wm_high.blank_time = line_time - wm_high.active_time;
1319 wm_high.interlaced = false;
1320 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1321 wm_high.interlaced = true;
1322 wm_high.vsc = amdgpu_crtc->vsc;
1323 wm_high.vtaps = 1;
1324 if (amdgpu_crtc->rmx_type != RMX_OFF)
1325 wm_high.vtaps = 2;
1326 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1327 wm_high.lb_size = lb_size;
1328 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1329 wm_high.num_heads = num_heads;
1330
1331 /* set for high clocks */
1332 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1333
1334 /* possibly force display priority to high */
1335 /* should really do this at mode validation time... */
1336 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1337 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1338 !dce_v10_0_check_latency_hiding(&wm_high) ||
1339 (adev->mode_info.disp_priority == 2)) {
1340 DRM_DEBUG_KMS("force priority to high\n");
1341 }
1342
1343 /* watermark for low clocks */
1344 if (adev->pm.dpm_enabled) {
1345 wm_low.yclk =
1346 amdgpu_dpm_get_mclk(adev, true) * 10;
1347 wm_low.sclk =
1348 amdgpu_dpm_get_sclk(adev, true) * 10;
1349 } else {
1350 wm_low.yclk = adev->pm.current_mclk * 10;
1351 wm_low.sclk = adev->pm.current_sclk * 10;
1352 }
1353
1354 wm_low.disp_clk = mode->clock;
1355 wm_low.src_width = mode->crtc_hdisplay;
1356 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1357 wm_low.blank_time = line_time - wm_low.active_time;
1358 wm_low.interlaced = false;
1359 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1360 wm_low.interlaced = true;
1361 wm_low.vsc = amdgpu_crtc->vsc;
1362 wm_low.vtaps = 1;
1363 if (amdgpu_crtc->rmx_type != RMX_OFF)
1364 wm_low.vtaps = 2;
1365 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1366 wm_low.lb_size = lb_size;
1367 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1368 wm_low.num_heads = num_heads;
1369
1370 /* set for low clocks */
1371 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1372
1373 /* possibly force display priority to high */
1374 /* should really do this at mode validation time... */
1375 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1376 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1377 !dce_v10_0_check_latency_hiding(&wm_low) ||
1378 (adev->mode_info.disp_priority == 2)) {
1379 DRM_DEBUG_KMS("force priority to high\n");
1380 }
1381 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1382 }
1383
1384 /* select wm A */
1385 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1386 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1387 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1388 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1389 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1390 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1391 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1392 /* select wm B */
1393 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1394 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1395 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1396 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1397 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1398 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1399 /* restore original selection */
1400 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1401
1402 /* save values for DPM */
1403 amdgpu_crtc->line_time = line_time;
1404 amdgpu_crtc->wm_high = latency_watermark_a;
1405 amdgpu_crtc->wm_low = latency_watermark_b;
1406 /* Save number of lines the linebuffer leads before the scanout */
1407 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1408 }
1409
1410 /**
1411 * dce_v10_0_bandwidth_update - program display watermarks
1412 *
1413 * @adev: amdgpu_device pointer
1414 *
1415 * Calculate and program the display watermarks and line
1416 * buffer allocation (CIK).
1417 */
1418 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1419 {
1420 struct drm_display_mode *mode = NULL;
1421 u32 num_heads = 0, lb_size;
1422 int i;
1423
1424 amdgpu_update_display_priority(adev);
1425
1426 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1427 if (adev->mode_info.crtcs[i]->base.enabled)
1428 num_heads++;
1429 }
1430 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1431 mode = &adev->mode_info.crtcs[i]->base.mode;
1432 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1433 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1434 lb_size, num_heads);
1435 }
1436 }
1437
1438 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1439 {
1440 int i;
1441 u32 offset, tmp;
1442
1443 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1444 offset = adev->mode_info.audio.pin[i].offset;
1445 tmp = RREG32_AUDIO_ENDPT(offset,
1446 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1447 if (((tmp &
1448 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1449 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1450 adev->mode_info.audio.pin[i].connected = false;
1451 else
1452 adev->mode_info.audio.pin[i].connected = true;
1453 }
1454 }
1455
1456 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1457 {
1458 int i;
1459
1460 dce_v10_0_audio_get_connected_pins(adev);
1461
1462 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1463 if (adev->mode_info.audio.pin[i].connected)
1464 return &adev->mode_info.audio.pin[i];
1465 }
1466 DRM_ERROR("No connected audio pins found!\n");
1467 return NULL;
1468 }
1469
1470 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1471 {
1472 struct amdgpu_device *adev = encoder->dev->dev_private;
1473 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1474 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1475 u32 tmp;
1476
1477 if (!dig || !dig->afmt || !dig->afmt->pin)
1478 return;
1479
1480 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1481 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1482 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1483 }
1484
1485 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1486 struct drm_display_mode *mode)
1487 {
1488 struct amdgpu_device *adev = encoder->dev->dev_private;
1489 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1490 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1491 struct drm_connector *connector;
1492 struct amdgpu_connector *amdgpu_connector = NULL;
1493 u32 tmp;
1494 int interlace = 0;
1495
1496 if (!dig || !dig->afmt || !dig->afmt->pin)
1497 return;
1498
1499 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1500 if (connector->encoder == encoder) {
1501 amdgpu_connector = to_amdgpu_connector(connector);
1502 break;
1503 }
1504 }
1505
1506 if (!amdgpu_connector) {
1507 DRM_ERROR("Couldn't find encoder's connector\n");
1508 return;
1509 }
1510
1511 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1512 interlace = 1;
1513 if (connector->latency_present[interlace]) {
1514 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1515 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1516 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1517 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1518 } else {
1519 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1520 VIDEO_LIPSYNC, 0);
1521 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1522 AUDIO_LIPSYNC, 0);
1523 }
1524 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1525 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1526 }
1527
1528 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1529 {
1530 struct amdgpu_device *adev = encoder->dev->dev_private;
1531 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1532 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1533 struct drm_connector *connector;
1534 struct amdgpu_connector *amdgpu_connector = NULL;
1535 u32 tmp;
1536 u8 *sadb = NULL;
1537 int sad_count;
1538
1539 if (!dig || !dig->afmt || !dig->afmt->pin)
1540 return;
1541
1542 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1543 if (connector->encoder == encoder) {
1544 amdgpu_connector = to_amdgpu_connector(connector);
1545 break;
1546 }
1547 }
1548
1549 if (!amdgpu_connector) {
1550 DRM_ERROR("Couldn't find encoder's connector\n");
1551 return;
1552 }
1553
1554 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1555 if (sad_count < 0) {
1556 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1557 sad_count = 0;
1558 }
1559
1560 /* program the speaker allocation */
1561 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1562 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1563 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1564 DP_CONNECTION, 0);
1565 /* set HDMI mode */
1566 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1567 HDMI_CONNECTION, 1);
1568 if (sad_count)
1569 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1570 SPEAKER_ALLOCATION, sadb[0]);
1571 else
1572 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1573 SPEAKER_ALLOCATION, 5); /* stereo */
1574 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1575 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1576
1577 kfree(sadb);
1578 }
1579
1580 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1581 {
1582 struct amdgpu_device *adev = encoder->dev->dev_private;
1583 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1584 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1585 struct drm_connector *connector;
1586 struct amdgpu_connector *amdgpu_connector = NULL;
1587 struct cea_sad *sads;
1588 int i, sad_count;
1589
1590 static const u16 eld_reg_to_type[][2] = {
1591 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1592 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1593 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1594 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1595 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1596 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1597 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1598 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1599 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1600 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1601 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1602 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1603 };
1604
1605 if (!dig || !dig->afmt || !dig->afmt->pin)
1606 return;
1607
1608 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1609 if (connector->encoder == encoder) {
1610 amdgpu_connector = to_amdgpu_connector(connector);
1611 break;
1612 }
1613 }
1614
1615 if (!amdgpu_connector) {
1616 DRM_ERROR("Couldn't find encoder's connector\n");
1617 return;
1618 }
1619
1620 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1621 if (sad_count <= 0) {
1622 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1623 return;
1624 }
1625 BUG_ON(!sads);
1626
1627 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1628 u32 tmp = 0;
1629 u8 stereo_freqs = 0;
1630 int max_channels = -1;
1631 int j;
1632
1633 for (j = 0; j < sad_count; j++) {
1634 struct cea_sad *sad = &sads[j];
1635
1636 if (sad->format == eld_reg_to_type[i][1]) {
1637 if (sad->channels > max_channels) {
1638 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1639 MAX_CHANNELS, sad->channels);
1640 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1641 DESCRIPTOR_BYTE_2, sad->byte2);
1642 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1643 SUPPORTED_FREQUENCIES, sad->freq);
1644 max_channels = sad->channels;
1645 }
1646
1647 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1648 stereo_freqs |= sad->freq;
1649 else
1650 break;
1651 }
1652 }
1653
1654 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1655 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1656 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1657 }
1658
1659 kfree(sads);
1660 }
1661
1662 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1663 struct amdgpu_audio_pin *pin,
1664 bool enable)
1665 {
1666 if (!pin)
1667 return;
1668
1669 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1670 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1671 }
1672
1673 static const u32 pin_offsets[] =
1674 {
1675 AUD0_REGISTER_OFFSET,
1676 AUD1_REGISTER_OFFSET,
1677 AUD2_REGISTER_OFFSET,
1678 AUD3_REGISTER_OFFSET,
1679 AUD4_REGISTER_OFFSET,
1680 AUD5_REGISTER_OFFSET,
1681 AUD6_REGISTER_OFFSET,
1682 };
1683
1684 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1685 {
1686 int i;
1687
1688 if (!amdgpu_audio)
1689 return 0;
1690
1691 adev->mode_info.audio.enabled = true;
1692
1693 adev->mode_info.audio.num_pins = 7;
1694
1695 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1696 adev->mode_info.audio.pin[i].channels = -1;
1697 adev->mode_info.audio.pin[i].rate = -1;
1698 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1699 adev->mode_info.audio.pin[i].status_bits = 0;
1700 adev->mode_info.audio.pin[i].category_code = 0;
1701 adev->mode_info.audio.pin[i].connected = false;
1702 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1703 adev->mode_info.audio.pin[i].id = i;
1704 /* disable audio. it will be set up later */
1705 /* XXX remove once we switch to ip funcs */
1706 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1707 }
1708
1709 return 0;
1710 }
1711
1712 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1713 {
1714 int i;
1715
1716 if (!amdgpu_audio)
1717 return;
1718
1719 if (!adev->mode_info.audio.enabled)
1720 return;
1721
1722 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1723 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1724
1725 adev->mode_info.audio.enabled = false;
1726 }
1727
1728 /*
1729 * update the N and CTS parameters for a given pixel clock rate
1730 */
1731 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1732 {
1733 struct drm_device *dev = encoder->dev;
1734 struct amdgpu_device *adev = dev->dev_private;
1735 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1736 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1737 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1738 u32 tmp;
1739
1740 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1741 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1742 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1743 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1744 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1745 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1746
1747 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1748 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1749 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1750 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1751 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1752 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1753
1754 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1755 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1756 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1757 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1758 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1759 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1760
1761 }
1762
1763 /*
1764 * build a HDMI Video Info Frame
1765 */
1766 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1767 void *buffer, size_t size)
1768 {
1769 struct drm_device *dev = encoder->dev;
1770 struct amdgpu_device *adev = dev->dev_private;
1771 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1772 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1773 uint8_t *frame = buffer + 3;
1774 uint8_t *header = buffer;
1775
1776 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1777 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1778 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1779 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1780 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1781 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1782 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1783 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1784 }
1785
1786 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1787 {
1788 struct drm_device *dev = encoder->dev;
1789 struct amdgpu_device *adev = dev->dev_private;
1790 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1791 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1792 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1793 u32 dto_phase = 24 * 1000;
1794 u32 dto_modulo = clock;
1795 u32 tmp;
1796
1797 if (!dig || !dig->afmt)
1798 return;
1799
1800 /* XXX two dtos; generally use dto0 for hdmi */
1801 /* Express [24MHz / target pixel clock] as an exact rational
1802 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1803 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1804 */
1805 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1806 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1807 amdgpu_crtc->crtc_id);
1808 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1809 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1810 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1811 }
1812
1813 /*
1814 * update the info frames with the data from the current display mode
1815 */
1816 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1817 struct drm_display_mode *mode)
1818 {
1819 struct drm_device *dev = encoder->dev;
1820 struct amdgpu_device *adev = dev->dev_private;
1821 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1822 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1823 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1824 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1825 struct hdmi_avi_infoframe frame;
1826 ssize_t err;
1827 u32 tmp;
1828 int bpc = 8;
1829
1830 if (!dig || !dig->afmt)
1831 return;
1832
1833 /* Silent, r600_hdmi_enable will raise WARN for us */
1834 if (!dig->afmt->enabled)
1835 return;
1836
1837 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1838 if (encoder->crtc) {
1839 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1840 bpc = amdgpu_crtc->bpc;
1841 }
1842
1843 /* disable audio prior to setting up hw */
1844 dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1845 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1846
1847 dce_v10_0_audio_set_dto(encoder, mode->clock);
1848
1849 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1850 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1851 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1852
1853 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1854
1855 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1856 switch (bpc) {
1857 case 0:
1858 case 6:
1859 case 8:
1860 case 16:
1861 default:
1862 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1863 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1864 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1865 connector->name, bpc);
1866 break;
1867 case 10:
1868 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1869 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1870 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1871 connector->name);
1872 break;
1873 case 12:
1874 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1875 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1876 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1877 connector->name);
1878 break;
1879 }
1880 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1881
1882 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1883 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1884 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1885 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1886 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1887
1888 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1889 /* enable audio info frames (frames won't be set until audio is enabled) */
1890 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1891 /* required for audio info values to be updated */
1892 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1893 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1894
1895 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1896 /* required for audio info values to be updated */
1897 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1898 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1899
1900 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1901 /* anything other than 0 */
1902 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1903 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1904
1905 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1906
1907 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1908 /* set the default audio delay */
1909 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1910 /* should be suffient for all audio modes and small enough for all hblanks */
1911 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1912 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1913
1914 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1915 /* allow 60958 channel status fields to be updated */
1916 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1917 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1918
1919 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1920 if (bpc > 8)
1921 /* clear SW CTS value */
1922 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1923 else
1924 /* select SW CTS value */
1925 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1926 /* allow hw to sent ACR packets when required */
1927 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1928 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1929
1930 dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1931
1932 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1933 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1934 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1935
1936 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1937 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1938 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1939
1940 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1941 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1942 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1943 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1944 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1945 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1946 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1947 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1948
1949 dce_v10_0_audio_write_speaker_allocation(encoder);
1950
1951 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1952 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1953
1954 dce_v10_0_afmt_audio_select_pin(encoder);
1955 dce_v10_0_audio_write_sad_regs(encoder);
1956 dce_v10_0_audio_write_latency_fields(encoder, mode);
1957
1958 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1959 if (err < 0) {
1960 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1961 return;
1962 }
1963
1964 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1965 if (err < 0) {
1966 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1967 return;
1968 }
1969
1970 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1971
1972 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1973 /* enable AVI info frames */
1974 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1975 /* required for audio info values to be updated */
1976 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1977 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1978
1979 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1980 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1981 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1982
1983 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1984 /* send audio packets */
1985 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1986 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1987
1988 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1989 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1990 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1991 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1992
1993 /* enable audio after to setting up hw */
1994 dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1995 }
1996
1997 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1998 {
1999 struct drm_device *dev = encoder->dev;
2000 struct amdgpu_device *adev = dev->dev_private;
2001 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2002 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2003
2004 if (!dig || !dig->afmt)
2005 return;
2006
2007 /* Silent, r600_hdmi_enable will raise WARN for us */
2008 if (enable && dig->afmt->enabled)
2009 return;
2010 if (!enable && !dig->afmt->enabled)
2011 return;
2012
2013 if (!enable && dig->afmt->pin) {
2014 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
2015 dig->afmt->pin = NULL;
2016 }
2017
2018 dig->afmt->enabled = enable;
2019
2020 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
2021 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
2022 }
2023
2024 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
2025 {
2026 int i;
2027
2028 for (i = 0; i < adev->mode_info.num_dig; i++)
2029 adev->mode_info.afmt[i] = NULL;
2030
2031 /* DCE10 has audio blocks tied to DIG encoders */
2032 for (i = 0; i < adev->mode_info.num_dig; i++) {
2033 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
2034 if (adev->mode_info.afmt[i]) {
2035 adev->mode_info.afmt[i]->offset = dig_offsets[i];
2036 adev->mode_info.afmt[i]->id = i;
2037 } else {
2038 int j;
2039 for (j = 0; j < i; j++) {
2040 kfree(adev->mode_info.afmt[j]);
2041 adev->mode_info.afmt[j] = NULL;
2042 }
2043 return -ENOMEM;
2044 }
2045 }
2046 return 0;
2047 }
2048
2049 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
2050 {
2051 int i;
2052
2053 for (i = 0; i < adev->mode_info.num_dig; i++) {
2054 kfree(adev->mode_info.afmt[i]);
2055 adev->mode_info.afmt[i] = NULL;
2056 }
2057 }
2058
2059 static const u32 vga_control_regs[6] =
2060 {
2061 mmD1VGA_CONTROL,
2062 mmD2VGA_CONTROL,
2063 mmD3VGA_CONTROL,
2064 mmD4VGA_CONTROL,
2065 mmD5VGA_CONTROL,
2066 mmD6VGA_CONTROL,
2067 };
2068
2069 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
2070 {
2071 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2072 struct drm_device *dev = crtc->dev;
2073 struct amdgpu_device *adev = dev->dev_private;
2074 u32 vga_control;
2075
2076 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2077 if (enable)
2078 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2079 else
2080 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2081 }
2082
2083 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
2084 {
2085 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2086 struct drm_device *dev = crtc->dev;
2087 struct amdgpu_device *adev = dev->dev_private;
2088
2089 if (enable)
2090 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2091 else
2092 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2093 }
2094
2095 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2096 struct drm_framebuffer *fb,
2097 int x, int y, int atomic)
2098 {
2099 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2100 struct drm_device *dev = crtc->dev;
2101 struct amdgpu_device *adev = dev->dev_private;
2102 struct amdgpu_framebuffer *amdgpu_fb;
2103 struct drm_framebuffer *target_fb;
2104 struct drm_gem_object *obj;
2105 struct amdgpu_bo *rbo;
2106 uint64_t fb_location, tiling_flags;
2107 uint32_t fb_format, fb_pitch_pixels;
2108 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2109 u32 pipe_config;
2110 u32 tmp, viewport_w, viewport_h;
2111 int r;
2112 bool bypass_lut = false;
2113
2114 /* no fb bound */
2115 if (!atomic && !crtc->primary->fb) {
2116 DRM_DEBUG_KMS("No FB bound\n");
2117 return 0;
2118 }
2119
2120 if (atomic) {
2121 amdgpu_fb = to_amdgpu_framebuffer(fb);
2122 target_fb = fb;
2123 } else {
2124 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2125 target_fb = crtc->primary->fb;
2126 }
2127
2128 /* If atomic, assume fb object is pinned & idle & fenced and
2129 * just update base pointers
2130 */
2131 obj = amdgpu_fb->obj;
2132 rbo = gem_to_amdgpu_bo(obj);
2133 r = amdgpu_bo_reserve(rbo, false);
2134 if (unlikely(r != 0))
2135 return r;
2136
2137 if (atomic) {
2138 fb_location = amdgpu_bo_gpu_offset(rbo);
2139 } else {
2140 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2141 if (unlikely(r != 0)) {
2142 amdgpu_bo_unreserve(rbo);
2143 return -EINVAL;
2144 }
2145 }
2146
2147 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2148 amdgpu_bo_unreserve(rbo);
2149
2150 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2151
2152 switch (target_fb->pixel_format) {
2153 case DRM_FORMAT_C8:
2154 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2155 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2156 break;
2157 case DRM_FORMAT_XRGB4444:
2158 case DRM_FORMAT_ARGB4444:
2159 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2160 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2161 #ifdef __BIG_ENDIAN
2162 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2163 ENDIAN_8IN16);
2164 #endif
2165 break;
2166 case DRM_FORMAT_XRGB1555:
2167 case DRM_FORMAT_ARGB1555:
2168 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2169 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2170 #ifdef __BIG_ENDIAN
2171 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2172 ENDIAN_8IN16);
2173 #endif
2174 break;
2175 case DRM_FORMAT_BGRX5551:
2176 case DRM_FORMAT_BGRA5551:
2177 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2178 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2179 #ifdef __BIG_ENDIAN
2180 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2181 ENDIAN_8IN16);
2182 #endif
2183 break;
2184 case DRM_FORMAT_RGB565:
2185 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2186 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2187 #ifdef __BIG_ENDIAN
2188 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2189 ENDIAN_8IN16);
2190 #endif
2191 break;
2192 case DRM_FORMAT_XRGB8888:
2193 case DRM_FORMAT_ARGB8888:
2194 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2195 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2196 #ifdef __BIG_ENDIAN
2197 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2198 ENDIAN_8IN32);
2199 #endif
2200 break;
2201 case DRM_FORMAT_XRGB2101010:
2202 case DRM_FORMAT_ARGB2101010:
2203 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2204 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2205 #ifdef __BIG_ENDIAN
2206 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2207 ENDIAN_8IN32);
2208 #endif
2209 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2210 bypass_lut = true;
2211 break;
2212 case DRM_FORMAT_BGRX1010102:
2213 case DRM_FORMAT_BGRA1010102:
2214 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2215 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2216 #ifdef __BIG_ENDIAN
2217 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2218 ENDIAN_8IN32);
2219 #endif
2220 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2221 bypass_lut = true;
2222 break;
2223 default:
2224 DRM_ERROR("Unsupported screen format %s\n",
2225 drm_get_format_name(target_fb->pixel_format));
2226 return -EINVAL;
2227 }
2228
2229 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2230 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2231
2232 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2233 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2234 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2235 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2236 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2237
2238 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2239 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2240 ARRAY_2D_TILED_THIN1);
2241 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2242 tile_split);
2243 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2244 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2245 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2246 mtaspect);
2247 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2248 ADDR_SURF_MICRO_TILING_DISPLAY);
2249 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2250 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2251 ARRAY_1D_TILED_THIN1);
2252 }
2253
2254 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2255 pipe_config);
2256
2257 dce_v10_0_vga_enable(crtc, false);
2258
2259 /* Make sure surface address is updated at vertical blank rather than
2260 * horizontal blank
2261 */
2262 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2263 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2264 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2265 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2266
2267 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2268 upper_32_bits(fb_location));
2269 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2270 upper_32_bits(fb_location));
2271 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2272 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2273 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2274 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2275 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2276 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2277
2278 /*
2279 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2280 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2281 * retain the full precision throughout the pipeline.
2282 */
2283 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2284 if (bypass_lut)
2285 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2286 else
2287 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2288 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2289
2290 if (bypass_lut)
2291 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2292
2293 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2294 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2295 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2296 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2297 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2298 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2299
2300 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2301 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2302
2303 dce_v10_0_grph_enable(crtc, true);
2304
2305 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2306 target_fb->height);
2307
2308 x &= ~3;
2309 y &= ~1;
2310 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2311 (x << 16) | y);
2312 viewport_w = crtc->mode.hdisplay;
2313 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2314 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2315 (viewport_w << 16) | viewport_h);
2316
2317 /* set pageflip to happen anywhere in vblank interval */
2318 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2319
2320 if (!atomic && fb && fb != crtc->primary->fb) {
2321 amdgpu_fb = to_amdgpu_framebuffer(fb);
2322 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2323 r = amdgpu_bo_reserve(rbo, false);
2324 if (unlikely(r != 0))
2325 return r;
2326 amdgpu_bo_unpin(rbo);
2327 amdgpu_bo_unreserve(rbo);
2328 }
2329
2330 /* Bytes per pixel may have changed */
2331 dce_v10_0_bandwidth_update(adev);
2332
2333 return 0;
2334 }
2335
2336 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2337 struct drm_display_mode *mode)
2338 {
2339 struct drm_device *dev = crtc->dev;
2340 struct amdgpu_device *adev = dev->dev_private;
2341 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2342 u32 tmp;
2343
2344 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2345 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2346 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2347 else
2348 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2349 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2350 }
2351
2352 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2353 {
2354 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2355 struct drm_device *dev = crtc->dev;
2356 struct amdgpu_device *adev = dev->dev_private;
2357 int i;
2358 u32 tmp;
2359
2360 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2361
2362 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2363 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2364 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2365 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2366
2367 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2368 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2369 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2370
2371 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2372 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2373 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2374
2375 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2376 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2377 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2378 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2379
2380 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2381
2382 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2383 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2384 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2385
2386 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2387 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2388 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2389
2390 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2391 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2392
2393 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2394 for (i = 0; i < 256; i++) {
2395 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2396 (amdgpu_crtc->lut_r[i] << 20) |
2397 (amdgpu_crtc->lut_g[i] << 10) |
2398 (amdgpu_crtc->lut_b[i] << 0));
2399 }
2400
2401 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2402 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2403 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2404 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2405 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2406
2407 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2408 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2409 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2410 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2411
2412 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2413 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2414 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2415 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2416
2417 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2418 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2419 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2420 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2421
2422 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2423 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2424 /* XXX this only needs to be programmed once per crtc at startup,
2425 * not sure where the best place for it is
2426 */
2427 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2428 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2429 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2430 }
2431
2432 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2433 {
2434 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2435 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2436
2437 switch (amdgpu_encoder->encoder_id) {
2438 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2439 if (dig->linkb)
2440 return 1;
2441 else
2442 return 0;
2443 break;
2444 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2445 if (dig->linkb)
2446 return 3;
2447 else
2448 return 2;
2449 break;
2450 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2451 if (dig->linkb)
2452 return 5;
2453 else
2454 return 4;
2455 break;
2456 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2457 return 6;
2458 break;
2459 default:
2460 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2461 return 0;
2462 }
2463 }
2464
2465 /**
2466 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2467 *
2468 * @crtc: drm crtc
2469 *
2470 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2471 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2472 * monitors a dedicated PPLL must be used. If a particular board has
2473 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2474 * as there is no need to program the PLL itself. If we are not able to
2475 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2476 * avoid messing up an existing monitor.
2477 *
2478 * Asic specific PLL information
2479 *
2480 * DCE 10.x
2481 * Tonga
2482 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2483 * CI
2484 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2485 *
2486 */
2487 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2488 {
2489 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2490 struct drm_device *dev = crtc->dev;
2491 struct amdgpu_device *adev = dev->dev_private;
2492 u32 pll_in_use;
2493 int pll;
2494
2495 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2496 if (adev->clock.dp_extclk)
2497 /* skip PPLL programming if using ext clock */
2498 return ATOM_PPLL_INVALID;
2499 else {
2500 /* use the same PPLL for all DP monitors */
2501 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2502 if (pll != ATOM_PPLL_INVALID)
2503 return pll;
2504 }
2505 } else {
2506 /* use the same PPLL for all monitors with the same clock */
2507 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2508 if (pll != ATOM_PPLL_INVALID)
2509 return pll;
2510 }
2511
2512 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2513 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2514 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2515 return ATOM_PPLL2;
2516 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2517 return ATOM_PPLL1;
2518 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2519 return ATOM_PPLL0;
2520 DRM_ERROR("unable to allocate a PPLL\n");
2521 return ATOM_PPLL_INVALID;
2522 }
2523
2524 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2525 {
2526 struct amdgpu_device *adev = crtc->dev->dev_private;
2527 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2528 uint32_t cur_lock;
2529
2530 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2531 if (lock)
2532 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2533 else
2534 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2535 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2536 }
2537
2538 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2539 {
2540 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2541 struct amdgpu_device *adev = crtc->dev->dev_private;
2542 u32 tmp;
2543
2544 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2545 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2546 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2547 }
2548
2549 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2550 {
2551 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2552 struct amdgpu_device *adev = crtc->dev->dev_private;
2553 u32 tmp;
2554
2555 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2556 upper_32_bits(amdgpu_crtc->cursor_addr));
2557 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2558 lower_32_bits(amdgpu_crtc->cursor_addr));
2559
2560 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2561 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2562 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2563 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2564 }
2565
2566 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2567 int x, int y)
2568 {
2569 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2570 struct amdgpu_device *adev = crtc->dev->dev_private;
2571 int xorigin = 0, yorigin = 0;
2572
2573 /* avivo cursor are offset into the total surface */
2574 x += crtc->x;
2575 y += crtc->y;
2576 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2577
2578 if (x < 0) {
2579 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2580 x = 0;
2581 }
2582 if (y < 0) {
2583 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2584 y = 0;
2585 }
2586
2587 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2588 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2589 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2590 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2591
2592 amdgpu_crtc->cursor_x = x;
2593 amdgpu_crtc->cursor_y = y;
2594
2595 return 0;
2596 }
2597
2598 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2599 int x, int y)
2600 {
2601 int ret;
2602
2603 dce_v10_0_lock_cursor(crtc, true);
2604 ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2605 dce_v10_0_lock_cursor(crtc, false);
2606
2607 return ret;
2608 }
2609
2610 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2611 struct drm_file *file_priv,
2612 uint32_t handle,
2613 uint32_t width,
2614 uint32_t height,
2615 int32_t hot_x,
2616 int32_t hot_y)
2617 {
2618 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2619 struct drm_gem_object *obj;
2620 struct amdgpu_bo *aobj;
2621 int ret;
2622
2623 if (!handle) {
2624 /* turn off cursor */
2625 dce_v10_0_hide_cursor(crtc);
2626 obj = NULL;
2627 goto unpin;
2628 }
2629
2630 if ((width > amdgpu_crtc->max_cursor_width) ||
2631 (height > amdgpu_crtc->max_cursor_height)) {
2632 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2633 return -EINVAL;
2634 }
2635
2636 obj = drm_gem_object_lookup(file_priv, handle);
2637 if (!obj) {
2638 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2639 return -ENOENT;
2640 }
2641
2642 aobj = gem_to_amdgpu_bo(obj);
2643 ret = amdgpu_bo_reserve(aobj, false);
2644 if (ret != 0) {
2645 drm_gem_object_unreference_unlocked(obj);
2646 return ret;
2647 }
2648
2649 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2650 amdgpu_bo_unreserve(aobj);
2651 if (ret) {
2652 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2653 drm_gem_object_unreference_unlocked(obj);
2654 return ret;
2655 }
2656
2657 amdgpu_crtc->cursor_width = width;
2658 amdgpu_crtc->cursor_height = height;
2659
2660 dce_v10_0_lock_cursor(crtc, true);
2661
2662 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2663 hot_y != amdgpu_crtc->cursor_hot_y) {
2664 int x, y;
2665
2666 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2667 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2668
2669 dce_v10_0_cursor_move_locked(crtc, x, y);
2670
2671 amdgpu_crtc->cursor_hot_x = hot_x;
2672 amdgpu_crtc->cursor_hot_y = hot_y;
2673 }
2674
2675 dce_v10_0_show_cursor(crtc);
2676 dce_v10_0_lock_cursor(crtc, false);
2677
2678 unpin:
2679 if (amdgpu_crtc->cursor_bo) {
2680 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2681 ret = amdgpu_bo_reserve(aobj, false);
2682 if (likely(ret == 0)) {
2683 amdgpu_bo_unpin(aobj);
2684 amdgpu_bo_unreserve(aobj);
2685 }
2686 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2687 }
2688
2689 amdgpu_crtc->cursor_bo = obj;
2690 return 0;
2691 }
2692
2693 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2694 {
2695 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2696
2697 if (amdgpu_crtc->cursor_bo) {
2698 dce_v10_0_lock_cursor(crtc, true);
2699
2700 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2701 amdgpu_crtc->cursor_y);
2702
2703 dce_v10_0_show_cursor(crtc);
2704
2705 dce_v10_0_lock_cursor(crtc, false);
2706 }
2707 }
2708
2709 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2710 u16 *blue, uint32_t size)
2711 {
2712 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2713 int i;
2714
2715 /* userspace palettes are always correct as is */
2716 for (i = 0; i < size; i++) {
2717 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2718 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2719 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2720 }
2721 dce_v10_0_crtc_load_lut(crtc);
2722
2723 return 0;
2724 }
2725
2726 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2727 {
2728 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2729
2730 drm_crtc_cleanup(crtc);
2731 kfree(amdgpu_crtc);
2732 }
2733
2734 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2735 .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2736 .cursor_move = dce_v10_0_crtc_cursor_move,
2737 .gamma_set = dce_v10_0_crtc_gamma_set,
2738 .set_config = amdgpu_crtc_set_config,
2739 .destroy = dce_v10_0_crtc_destroy,
2740 .page_flip_target = amdgpu_crtc_page_flip_target,
2741 };
2742
2743 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2744 {
2745 struct drm_device *dev = crtc->dev;
2746 struct amdgpu_device *adev = dev->dev_private;
2747 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2748 unsigned type;
2749
2750 switch (mode) {
2751 case DRM_MODE_DPMS_ON:
2752 amdgpu_crtc->enabled = true;
2753 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2754 dce_v10_0_vga_enable(crtc, true);
2755 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2756 dce_v10_0_vga_enable(crtc, false);
2757 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2758 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2759 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2760 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2761 drm_crtc_vblank_on(crtc);
2762 dce_v10_0_crtc_load_lut(crtc);
2763 break;
2764 case DRM_MODE_DPMS_STANDBY:
2765 case DRM_MODE_DPMS_SUSPEND:
2766 case DRM_MODE_DPMS_OFF:
2767 drm_crtc_vblank_off(crtc);
2768 if (amdgpu_crtc->enabled) {
2769 dce_v10_0_vga_enable(crtc, true);
2770 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2771 dce_v10_0_vga_enable(crtc, false);
2772 }
2773 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2774 amdgpu_crtc->enabled = false;
2775 break;
2776 }
2777 /* adjust pm to dpms */
2778 amdgpu_pm_compute_clocks(adev);
2779 }
2780
2781 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2782 {
2783 /* disable crtc pair power gating before programming */
2784 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2785 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2786 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2787 }
2788
2789 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2790 {
2791 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2792 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2793 }
2794
2795 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2796 {
2797 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2798 struct drm_device *dev = crtc->dev;
2799 struct amdgpu_device *adev = dev->dev_private;
2800 struct amdgpu_atom_ss ss;
2801 int i;
2802
2803 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2804 if (crtc->primary->fb) {
2805 int r;
2806 struct amdgpu_framebuffer *amdgpu_fb;
2807 struct amdgpu_bo *rbo;
2808
2809 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2810 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2811 r = amdgpu_bo_reserve(rbo, false);
2812 if (unlikely(r))
2813 DRM_ERROR("failed to reserve rbo before unpin\n");
2814 else {
2815 amdgpu_bo_unpin(rbo);
2816 amdgpu_bo_unreserve(rbo);
2817 }
2818 }
2819 /* disable the GRPH */
2820 dce_v10_0_grph_enable(crtc, false);
2821
2822 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2823
2824 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2825 if (adev->mode_info.crtcs[i] &&
2826 adev->mode_info.crtcs[i]->enabled &&
2827 i != amdgpu_crtc->crtc_id &&
2828 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2829 /* one other crtc is using this pll don't turn
2830 * off the pll
2831 */
2832 goto done;
2833 }
2834 }
2835
2836 switch (amdgpu_crtc->pll_id) {
2837 case ATOM_PPLL0:
2838 case ATOM_PPLL1:
2839 case ATOM_PPLL2:
2840 /* disable the ppll */
2841 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2842 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2843 break;
2844 default:
2845 break;
2846 }
2847 done:
2848 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2849 amdgpu_crtc->adjusted_clock = 0;
2850 amdgpu_crtc->encoder = NULL;
2851 amdgpu_crtc->connector = NULL;
2852 }
2853
2854 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2855 struct drm_display_mode *mode,
2856 struct drm_display_mode *adjusted_mode,
2857 int x, int y, struct drm_framebuffer *old_fb)
2858 {
2859 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2860
2861 if (!amdgpu_crtc->adjusted_clock)
2862 return -EINVAL;
2863
2864 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2865 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2866 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2867 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2868 amdgpu_atombios_crtc_scaler_setup(crtc);
2869 dce_v10_0_cursor_reset(crtc);
2870 /* update the hw version fpr dpm */
2871 amdgpu_crtc->hw_mode = *adjusted_mode;
2872
2873 return 0;
2874 }
2875
2876 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2877 const struct drm_display_mode *mode,
2878 struct drm_display_mode *adjusted_mode)
2879 {
2880 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2881 struct drm_device *dev = crtc->dev;
2882 struct drm_encoder *encoder;
2883
2884 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2885 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2886 if (encoder->crtc == crtc) {
2887 amdgpu_crtc->encoder = encoder;
2888 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2889 break;
2890 }
2891 }
2892 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2893 amdgpu_crtc->encoder = NULL;
2894 amdgpu_crtc->connector = NULL;
2895 return false;
2896 }
2897 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2898 return false;
2899 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2900 return false;
2901 /* pick pll */
2902 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2903 /* if we can't get a PPLL for a non-DP encoder, fail */
2904 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2905 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2906 return false;
2907
2908 return true;
2909 }
2910
2911 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2912 struct drm_framebuffer *old_fb)
2913 {
2914 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2915 }
2916
2917 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2918 struct drm_framebuffer *fb,
2919 int x, int y, enum mode_set_atomic state)
2920 {
2921 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2922 }
2923
2924 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2925 .dpms = dce_v10_0_crtc_dpms,
2926 .mode_fixup = dce_v10_0_crtc_mode_fixup,
2927 .mode_set = dce_v10_0_crtc_mode_set,
2928 .mode_set_base = dce_v10_0_crtc_set_base,
2929 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2930 .prepare = dce_v10_0_crtc_prepare,
2931 .commit = dce_v10_0_crtc_commit,
2932 .load_lut = dce_v10_0_crtc_load_lut,
2933 .disable = dce_v10_0_crtc_disable,
2934 };
2935
2936 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2937 {
2938 struct amdgpu_crtc *amdgpu_crtc;
2939 int i;
2940
2941 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2942 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2943 if (amdgpu_crtc == NULL)
2944 return -ENOMEM;
2945
2946 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2947
2948 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2949 amdgpu_crtc->crtc_id = index;
2950 adev->mode_info.crtcs[index] = amdgpu_crtc;
2951
2952 amdgpu_crtc->max_cursor_width = 128;
2953 amdgpu_crtc->max_cursor_height = 128;
2954 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2955 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2956
2957 for (i = 0; i < 256; i++) {
2958 amdgpu_crtc->lut_r[i] = i << 2;
2959 amdgpu_crtc->lut_g[i] = i << 2;
2960 amdgpu_crtc->lut_b[i] = i << 2;
2961 }
2962
2963 switch (amdgpu_crtc->crtc_id) {
2964 case 0:
2965 default:
2966 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2967 break;
2968 case 1:
2969 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2970 break;
2971 case 2:
2972 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2973 break;
2974 case 3:
2975 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2976 break;
2977 case 4:
2978 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2979 break;
2980 case 5:
2981 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2982 break;
2983 }
2984
2985 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2986 amdgpu_crtc->adjusted_clock = 0;
2987 amdgpu_crtc->encoder = NULL;
2988 amdgpu_crtc->connector = NULL;
2989 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2990
2991 return 0;
2992 }
2993
2994 static int dce_v10_0_early_init(void *handle)
2995 {
2996 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2997
2998 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2999 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
3000
3001 dce_v10_0_set_display_funcs(adev);
3002 dce_v10_0_set_irq_funcs(adev);
3003
3004 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
3005
3006 switch (adev->asic_type) {
3007 case CHIP_FIJI:
3008 case CHIP_TONGA:
3009 adev->mode_info.num_hpd = 6;
3010 adev->mode_info.num_dig = 7;
3011 break;
3012 default:
3013 /* FIXME: not supported yet */
3014 return -EINVAL;
3015 }
3016
3017 return 0;
3018 }
3019
3020 static int dce_v10_0_sw_init(void *handle)
3021 {
3022 int r, i;
3023 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3024
3025 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3026 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3027 if (r)
3028 return r;
3029 }
3030
3031 for (i = 8; i < 20; i += 2) {
3032 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3033 if (r)
3034 return r;
3035 }
3036
3037 /* HPD hotplug */
3038 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3039 if (r)
3040 return r;
3041
3042 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3043
3044 adev->ddev->mode_config.async_page_flip = true;
3045
3046 adev->ddev->mode_config.max_width = 16384;
3047 adev->ddev->mode_config.max_height = 16384;
3048
3049 adev->ddev->mode_config.preferred_depth = 24;
3050 adev->ddev->mode_config.prefer_shadow = 1;
3051
3052 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3053
3054 r = amdgpu_modeset_create_props(adev);
3055 if (r)
3056 return r;
3057
3058 adev->ddev->mode_config.max_width = 16384;
3059 adev->ddev->mode_config.max_height = 16384;
3060
3061 /* allocate crtcs */
3062 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3063 r = dce_v10_0_crtc_init(adev, i);
3064 if (r)
3065 return r;
3066 }
3067
3068 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3069 amdgpu_print_display_setup(adev->ddev);
3070 else
3071 return -EINVAL;
3072
3073 /* setup afmt */
3074 r = dce_v10_0_afmt_init(adev);
3075 if (r)
3076 return r;
3077
3078 r = dce_v10_0_audio_init(adev);
3079 if (r)
3080 return r;
3081
3082 drm_kms_helper_poll_init(adev->ddev);
3083
3084 adev->mode_info.mode_config_initialized = true;
3085 return 0;
3086 }
3087
3088 static int dce_v10_0_sw_fini(void *handle)
3089 {
3090 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3091
3092 kfree(adev->mode_info.bios_hardcoded_edid);
3093
3094 drm_kms_helper_poll_fini(adev->ddev);
3095
3096 dce_v10_0_audio_fini(adev);
3097
3098 dce_v10_0_afmt_fini(adev);
3099
3100 drm_mode_config_cleanup(adev->ddev);
3101 adev->mode_info.mode_config_initialized = false;
3102
3103 return 0;
3104 }
3105
3106 static int dce_v10_0_hw_init(void *handle)
3107 {
3108 int i;
3109 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3110
3111 dce_v10_0_init_golden_registers(adev);
3112
3113 /* init dig PHYs, disp eng pll */
3114 amdgpu_atombios_encoder_init_dig(adev);
3115 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3116
3117 /* initialize hpd */
3118 dce_v10_0_hpd_init(adev);
3119
3120 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3121 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3122 }
3123
3124 dce_v10_0_pageflip_interrupt_init(adev);
3125
3126 return 0;
3127 }
3128
3129 static int dce_v10_0_hw_fini(void *handle)
3130 {
3131 int i;
3132 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3133
3134 dce_v10_0_hpd_fini(adev);
3135
3136 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3137 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3138 }
3139
3140 dce_v10_0_pageflip_interrupt_fini(adev);
3141
3142 return 0;
3143 }
3144
3145 static int dce_v10_0_suspend(void *handle)
3146 {
3147 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3148
3149 amdgpu_atombios_scratch_regs_save(adev);
3150
3151 return dce_v10_0_hw_fini(handle);
3152 }
3153
3154 static int dce_v10_0_resume(void *handle)
3155 {
3156 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3157 int ret;
3158
3159 ret = dce_v10_0_hw_init(handle);
3160
3161 amdgpu_atombios_scratch_regs_restore(adev);
3162
3163 /* turn on the BL */
3164 if (adev->mode_info.bl_encoder) {
3165 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3166 adev->mode_info.bl_encoder);
3167 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3168 bl_level);
3169 }
3170
3171 return ret;
3172 }
3173
3174 static bool dce_v10_0_is_idle(void *handle)
3175 {
3176 return true;
3177 }
3178
3179 static int dce_v10_0_wait_for_idle(void *handle)
3180 {
3181 return 0;
3182 }
3183
3184 static int dce_v10_0_check_soft_reset(void *handle)
3185 {
3186 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3187
3188 if (dce_v10_0_is_display_hung(adev))
3189 adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang = true;
3190 else
3191 adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang = false;
3192
3193 return 0;
3194 }
3195
3196 static int dce_v10_0_soft_reset(void *handle)
3197 {
3198 u32 srbm_soft_reset = 0, tmp;
3199 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3200
3201 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang)
3202 return 0;
3203
3204 if (dce_v10_0_is_display_hung(adev))
3205 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3206
3207 if (srbm_soft_reset) {
3208 tmp = RREG32(mmSRBM_SOFT_RESET);
3209 tmp |= srbm_soft_reset;
3210 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3211 WREG32(mmSRBM_SOFT_RESET, tmp);
3212 tmp = RREG32(mmSRBM_SOFT_RESET);
3213
3214 udelay(50);
3215
3216 tmp &= ~srbm_soft_reset;
3217 WREG32(mmSRBM_SOFT_RESET, tmp);
3218 tmp = RREG32(mmSRBM_SOFT_RESET);
3219
3220 /* Wait a little for things to settle down */
3221 udelay(50);
3222 }
3223 return 0;
3224 }
3225
3226 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3227 int crtc,
3228 enum amdgpu_interrupt_state state)
3229 {
3230 u32 lb_interrupt_mask;
3231
3232 if (crtc >= adev->mode_info.num_crtc) {
3233 DRM_DEBUG("invalid crtc %d\n", crtc);
3234 return;
3235 }
3236
3237 switch (state) {
3238 case AMDGPU_IRQ_STATE_DISABLE:
3239 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3240 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3241 VBLANK_INTERRUPT_MASK, 0);
3242 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3243 break;
3244 case AMDGPU_IRQ_STATE_ENABLE:
3245 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3246 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3247 VBLANK_INTERRUPT_MASK, 1);
3248 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3249 break;
3250 default:
3251 break;
3252 }
3253 }
3254
3255 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3256 int crtc,
3257 enum amdgpu_interrupt_state state)
3258 {
3259 u32 lb_interrupt_mask;
3260
3261 if (crtc >= adev->mode_info.num_crtc) {
3262 DRM_DEBUG("invalid crtc %d\n", crtc);
3263 return;
3264 }
3265
3266 switch (state) {
3267 case AMDGPU_IRQ_STATE_DISABLE:
3268 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3269 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3270 VLINE_INTERRUPT_MASK, 0);
3271 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3272 break;
3273 case AMDGPU_IRQ_STATE_ENABLE:
3274 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3275 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3276 VLINE_INTERRUPT_MASK, 1);
3277 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3278 break;
3279 default:
3280 break;
3281 }
3282 }
3283
3284 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3285 struct amdgpu_irq_src *source,
3286 unsigned hpd,
3287 enum amdgpu_interrupt_state state)
3288 {
3289 u32 tmp;
3290
3291 if (hpd >= adev->mode_info.num_hpd) {
3292 DRM_DEBUG("invalid hdp %d\n", hpd);
3293 return 0;
3294 }
3295
3296 switch (state) {
3297 case AMDGPU_IRQ_STATE_DISABLE:
3298 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3299 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3300 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3301 break;
3302 case AMDGPU_IRQ_STATE_ENABLE:
3303 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3304 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3305 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3306 break;
3307 default:
3308 break;
3309 }
3310
3311 return 0;
3312 }
3313
3314 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3315 struct amdgpu_irq_src *source,
3316 unsigned type,
3317 enum amdgpu_interrupt_state state)
3318 {
3319 switch (type) {
3320 case AMDGPU_CRTC_IRQ_VBLANK1:
3321 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3322 break;
3323 case AMDGPU_CRTC_IRQ_VBLANK2:
3324 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3325 break;
3326 case AMDGPU_CRTC_IRQ_VBLANK3:
3327 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3328 break;
3329 case AMDGPU_CRTC_IRQ_VBLANK4:
3330 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3331 break;
3332 case AMDGPU_CRTC_IRQ_VBLANK5:
3333 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3334 break;
3335 case AMDGPU_CRTC_IRQ_VBLANK6:
3336 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3337 break;
3338 case AMDGPU_CRTC_IRQ_VLINE1:
3339 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3340 break;
3341 case AMDGPU_CRTC_IRQ_VLINE2:
3342 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3343 break;
3344 case AMDGPU_CRTC_IRQ_VLINE3:
3345 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3346 break;
3347 case AMDGPU_CRTC_IRQ_VLINE4:
3348 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3349 break;
3350 case AMDGPU_CRTC_IRQ_VLINE5:
3351 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3352 break;
3353 case AMDGPU_CRTC_IRQ_VLINE6:
3354 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3355 break;
3356 default:
3357 break;
3358 }
3359 return 0;
3360 }
3361
3362 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3363 struct amdgpu_irq_src *src,
3364 unsigned type,
3365 enum amdgpu_interrupt_state state)
3366 {
3367 u32 reg;
3368
3369 if (type >= adev->mode_info.num_crtc) {
3370 DRM_ERROR("invalid pageflip crtc %d\n", type);
3371 return -EINVAL;
3372 }
3373
3374 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3375 if (state == AMDGPU_IRQ_STATE_DISABLE)
3376 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3377 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3378 else
3379 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3380 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3381
3382 return 0;
3383 }
3384
3385 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3386 struct amdgpu_irq_src *source,
3387 struct amdgpu_iv_entry *entry)
3388 {
3389 unsigned long flags;
3390 unsigned crtc_id;
3391 struct amdgpu_crtc *amdgpu_crtc;
3392 struct amdgpu_flip_work *works;
3393
3394 crtc_id = (entry->src_id - 8) >> 1;
3395 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3396
3397 if (crtc_id >= adev->mode_info.num_crtc) {
3398 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3399 return -EINVAL;
3400 }
3401
3402 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3403 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3404 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3405 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3406
3407 /* IRQ could occur when in initial stage */
3408 if (amdgpu_crtc == NULL)
3409 return 0;
3410
3411 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3412 works = amdgpu_crtc->pflip_works;
3413 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3414 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3415 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3416 amdgpu_crtc->pflip_status,
3417 AMDGPU_FLIP_SUBMITTED);
3418 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3419 return 0;
3420 }
3421
3422 /* page flip completed. clean up */
3423 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3424 amdgpu_crtc->pflip_works = NULL;
3425
3426 /* wakeup usersapce */
3427 if (works->event)
3428 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3429
3430 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3431
3432 drm_crtc_vblank_put(&amdgpu_crtc->base);
3433 schedule_work(&works->unpin_work);
3434
3435 return 0;
3436 }
3437
3438 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3439 int hpd)
3440 {
3441 u32 tmp;
3442
3443 if (hpd >= adev->mode_info.num_hpd) {
3444 DRM_DEBUG("invalid hdp %d\n", hpd);
3445 return;
3446 }
3447
3448 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3449 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3450 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3451 }
3452
3453 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3454 int crtc)
3455 {
3456 u32 tmp;
3457
3458 if (crtc >= adev->mode_info.num_crtc) {
3459 DRM_DEBUG("invalid crtc %d\n", crtc);
3460 return;
3461 }
3462
3463 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3464 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3465 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3466 }
3467
3468 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3469 int crtc)
3470 {
3471 u32 tmp;
3472
3473 if (crtc >= adev->mode_info.num_crtc) {
3474 DRM_DEBUG("invalid crtc %d\n", crtc);
3475 return;
3476 }
3477
3478 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3479 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3480 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3481 }
3482
3483 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3484 struct amdgpu_irq_src *source,
3485 struct amdgpu_iv_entry *entry)
3486 {
3487 unsigned crtc = entry->src_id - 1;
3488 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3489 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3490
3491 switch (entry->src_data) {
3492 case 0: /* vblank */
3493 if (disp_int & interrupt_status_offsets[crtc].vblank)
3494 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3495 else
3496 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3497
3498 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3499 drm_handle_vblank(adev->ddev, crtc);
3500 }
3501 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3502
3503 break;
3504 case 1: /* vline */
3505 if (disp_int & interrupt_status_offsets[crtc].vline)
3506 dce_v10_0_crtc_vline_int_ack(adev, crtc);
3507 else
3508 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3509
3510 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3511
3512 break;
3513 default:
3514 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3515 break;
3516 }
3517
3518 return 0;
3519 }
3520
3521 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3522 struct amdgpu_irq_src *source,
3523 struct amdgpu_iv_entry *entry)
3524 {
3525 uint32_t disp_int, mask;
3526 unsigned hpd;
3527
3528 if (entry->src_data >= adev->mode_info.num_hpd) {
3529 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3530 return 0;
3531 }
3532
3533 hpd = entry->src_data;
3534 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3535 mask = interrupt_status_offsets[hpd].hpd;
3536
3537 if (disp_int & mask) {
3538 dce_v10_0_hpd_int_ack(adev, hpd);
3539 schedule_work(&adev->hotplug_work);
3540 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3541 }
3542
3543 return 0;
3544 }
3545
3546 static int dce_v10_0_set_clockgating_state(void *handle,
3547 enum amd_clockgating_state state)
3548 {
3549 return 0;
3550 }
3551
3552 static int dce_v10_0_set_powergating_state(void *handle,
3553 enum amd_powergating_state state)
3554 {
3555 return 0;
3556 }
3557
3558 const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3559 .name = "dce_v10_0",
3560 .early_init = dce_v10_0_early_init,
3561 .late_init = NULL,
3562 .sw_init = dce_v10_0_sw_init,
3563 .sw_fini = dce_v10_0_sw_fini,
3564 .hw_init = dce_v10_0_hw_init,
3565 .hw_fini = dce_v10_0_hw_fini,
3566 .suspend = dce_v10_0_suspend,
3567 .resume = dce_v10_0_resume,
3568 .is_idle = dce_v10_0_is_idle,
3569 .wait_for_idle = dce_v10_0_wait_for_idle,
3570 .check_soft_reset = dce_v10_0_check_soft_reset,
3571 .soft_reset = dce_v10_0_soft_reset,
3572 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3573 .set_powergating_state = dce_v10_0_set_powergating_state,
3574 };
3575
3576 static void
3577 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3578 struct drm_display_mode *mode,
3579 struct drm_display_mode *adjusted_mode)
3580 {
3581 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3582
3583 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3584
3585 /* need to call this here rather than in prepare() since we need some crtc info */
3586 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3587
3588 /* set scaler clears this on some chips */
3589 dce_v10_0_set_interleave(encoder->crtc, mode);
3590
3591 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3592 dce_v10_0_afmt_enable(encoder, true);
3593 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3594 }
3595 }
3596
3597 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3598 {
3599 struct amdgpu_device *adev = encoder->dev->dev_private;
3600 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3601 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3602
3603 if ((amdgpu_encoder->active_device &
3604 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3605 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3606 ENCODER_OBJECT_ID_NONE)) {
3607 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3608 if (dig) {
3609 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3610 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3611 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3612 }
3613 }
3614
3615 amdgpu_atombios_scratch_regs_lock(adev, true);
3616
3617 if (connector) {
3618 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3619
3620 /* select the clock/data port if it uses a router */
3621 if (amdgpu_connector->router.cd_valid)
3622 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3623
3624 /* turn eDP panel on for mode set */
3625 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3626 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3627 ATOM_TRANSMITTER_ACTION_POWER_ON);
3628 }
3629
3630 /* this is needed for the pll/ss setup to work correctly in some cases */
3631 amdgpu_atombios_encoder_set_crtc_source(encoder);
3632 /* set up the FMT blocks */
3633 dce_v10_0_program_fmt(encoder);
3634 }
3635
3636 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3637 {
3638 struct drm_device *dev = encoder->dev;
3639 struct amdgpu_device *adev = dev->dev_private;
3640
3641 /* need to call this here as we need the crtc set up */
3642 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3643 amdgpu_atombios_scratch_regs_lock(adev, false);
3644 }
3645
3646 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3647 {
3648 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3649 struct amdgpu_encoder_atom_dig *dig;
3650
3651 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3652
3653 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3654 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3655 dce_v10_0_afmt_enable(encoder, false);
3656 dig = amdgpu_encoder->enc_priv;
3657 dig->dig_encoder = -1;
3658 }
3659 amdgpu_encoder->active_device = 0;
3660 }
3661
3662 /* these are handled by the primary encoders */
3663 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3664 {
3665
3666 }
3667
3668 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3669 {
3670
3671 }
3672
3673 static void
3674 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3675 struct drm_display_mode *mode,
3676 struct drm_display_mode *adjusted_mode)
3677 {
3678
3679 }
3680
3681 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3682 {
3683
3684 }
3685
3686 static void
3687 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3688 {
3689
3690 }
3691
3692 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3693 .dpms = dce_v10_0_ext_dpms,
3694 .prepare = dce_v10_0_ext_prepare,
3695 .mode_set = dce_v10_0_ext_mode_set,
3696 .commit = dce_v10_0_ext_commit,
3697 .disable = dce_v10_0_ext_disable,
3698 /* no detect for TMDS/LVDS yet */
3699 };
3700
3701 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3702 .dpms = amdgpu_atombios_encoder_dpms,
3703 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3704 .prepare = dce_v10_0_encoder_prepare,
3705 .mode_set = dce_v10_0_encoder_mode_set,
3706 .commit = dce_v10_0_encoder_commit,
3707 .disable = dce_v10_0_encoder_disable,
3708 .detect = amdgpu_atombios_encoder_dig_detect,
3709 };
3710
3711 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3712 .dpms = amdgpu_atombios_encoder_dpms,
3713 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3714 .prepare = dce_v10_0_encoder_prepare,
3715 .mode_set = dce_v10_0_encoder_mode_set,
3716 .commit = dce_v10_0_encoder_commit,
3717 .detect = amdgpu_atombios_encoder_dac_detect,
3718 };
3719
3720 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3721 {
3722 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3723 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3724 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3725 kfree(amdgpu_encoder->enc_priv);
3726 drm_encoder_cleanup(encoder);
3727 kfree(amdgpu_encoder);
3728 }
3729
3730 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3731 .destroy = dce_v10_0_encoder_destroy,
3732 };
3733
3734 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3735 uint32_t encoder_enum,
3736 uint32_t supported_device,
3737 u16 caps)
3738 {
3739 struct drm_device *dev = adev->ddev;
3740 struct drm_encoder *encoder;
3741 struct amdgpu_encoder *amdgpu_encoder;
3742
3743 /* see if we already added it */
3744 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3745 amdgpu_encoder = to_amdgpu_encoder(encoder);
3746 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3747 amdgpu_encoder->devices |= supported_device;
3748 return;
3749 }
3750
3751 }
3752
3753 /* add a new one */
3754 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3755 if (!amdgpu_encoder)
3756 return;
3757
3758 encoder = &amdgpu_encoder->base;
3759 switch (adev->mode_info.num_crtc) {
3760 case 1:
3761 encoder->possible_crtcs = 0x1;
3762 break;
3763 case 2:
3764 default:
3765 encoder->possible_crtcs = 0x3;
3766 break;
3767 case 4:
3768 encoder->possible_crtcs = 0xf;
3769 break;
3770 case 6:
3771 encoder->possible_crtcs = 0x3f;
3772 break;
3773 }
3774
3775 amdgpu_encoder->enc_priv = NULL;
3776
3777 amdgpu_encoder->encoder_enum = encoder_enum;
3778 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3779 amdgpu_encoder->devices = supported_device;
3780 amdgpu_encoder->rmx_type = RMX_OFF;
3781 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3782 amdgpu_encoder->is_ext_encoder = false;
3783 amdgpu_encoder->caps = caps;
3784
3785 switch (amdgpu_encoder->encoder_id) {
3786 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3787 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3788 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3789 DRM_MODE_ENCODER_DAC, NULL);
3790 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3791 break;
3792 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3793 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3794 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3795 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3796 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3797 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3798 amdgpu_encoder->rmx_type = RMX_FULL;
3799 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3800 DRM_MODE_ENCODER_LVDS, NULL);
3801 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3802 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3803 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3804 DRM_MODE_ENCODER_DAC, NULL);
3805 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3806 } else {
3807 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3808 DRM_MODE_ENCODER_TMDS, NULL);
3809 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3810 }
3811 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3812 break;
3813 case ENCODER_OBJECT_ID_SI170B:
3814 case ENCODER_OBJECT_ID_CH7303:
3815 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3816 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3817 case ENCODER_OBJECT_ID_TITFP513:
3818 case ENCODER_OBJECT_ID_VT1623:
3819 case ENCODER_OBJECT_ID_HDMI_SI1930:
3820 case ENCODER_OBJECT_ID_TRAVIS:
3821 case ENCODER_OBJECT_ID_NUTMEG:
3822 /* these are handled by the primary encoders */
3823 amdgpu_encoder->is_ext_encoder = true;
3824 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3825 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3826 DRM_MODE_ENCODER_LVDS, NULL);
3827 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3828 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3829 DRM_MODE_ENCODER_DAC, NULL);
3830 else
3831 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3832 DRM_MODE_ENCODER_TMDS, NULL);
3833 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3834 break;
3835 }
3836 }
3837
3838 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3839 .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3840 .bandwidth_update = &dce_v10_0_bandwidth_update,
3841 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3842 .vblank_wait = &dce_v10_0_vblank_wait,
3843 .is_display_hung = &dce_v10_0_is_display_hung,
3844 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3845 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3846 .hpd_sense = &dce_v10_0_hpd_sense,
3847 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3848 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3849 .page_flip = &dce_v10_0_page_flip,
3850 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3851 .add_encoder = &dce_v10_0_encoder_add,
3852 .add_connector = &amdgpu_connector_add,
3853 .stop_mc_access = &dce_v10_0_stop_mc_access,
3854 .resume_mc_access = &dce_v10_0_resume_mc_access,
3855 };
3856
3857 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3858 {
3859 if (adev->mode_info.funcs == NULL)
3860 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3861 }
3862
3863 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3864 .set = dce_v10_0_set_crtc_irq_state,
3865 .process = dce_v10_0_crtc_irq,
3866 };
3867
3868 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3869 .set = dce_v10_0_set_pageflip_irq_state,
3870 .process = dce_v10_0_pageflip_irq,
3871 };
3872
3873 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3874 .set = dce_v10_0_set_hpd_irq_state,
3875 .process = dce_v10_0_hpd_irq,
3876 };
3877
3878 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3879 {
3880 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3881 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3882
3883 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3884 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3885
3886 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3887 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3888 }
Linux kernel - Deliverables
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