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Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa...
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / dce_v11_0.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "drmP.h"
24 #include "amdgpu.h"
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
27 #include "vid.h"
28 #include "atom.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
34
35 #include "dce/dce_11_0_d.h"
36 #include "dce/dce_11_0_sh_mask.h"
37 #include "dce/dce_11_0_enum.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
42
43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
45
46 static const u32 crtc_offsets[] =
47 {
48 CRTC0_REGISTER_OFFSET,
49 CRTC1_REGISTER_OFFSET,
50 CRTC2_REGISTER_OFFSET,
51 CRTC3_REGISTER_OFFSET,
52 CRTC4_REGISTER_OFFSET,
53 CRTC5_REGISTER_OFFSET,
54 CRTC6_REGISTER_OFFSET
55 };
56
57 static const u32 hpd_offsets[] =
58 {
59 HPD0_REGISTER_OFFSET,
60 HPD1_REGISTER_OFFSET,
61 HPD2_REGISTER_OFFSET,
62 HPD3_REGISTER_OFFSET,
63 HPD4_REGISTER_OFFSET,
64 HPD5_REGISTER_OFFSET
65 };
66
67 static const uint32_t dig_offsets[] = {
68 DIG0_REGISTER_OFFSET,
69 DIG1_REGISTER_OFFSET,
70 DIG2_REGISTER_OFFSET,
71 DIG3_REGISTER_OFFSET,
72 DIG4_REGISTER_OFFSET,
73 DIG5_REGISTER_OFFSET,
74 DIG6_REGISTER_OFFSET,
75 DIG7_REGISTER_OFFSET,
76 DIG8_REGISTER_OFFSET
77 };
78
79 static const struct {
80 uint32_t reg;
81 uint32_t vblank;
82 uint32_t vline;
83 uint32_t hpd;
84
85 } interrupt_status_offsets[] = { {
86 .reg = mmDISP_INTERRUPT_STATUS,
87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
90 }, {
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
95 }, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
100 }, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
105 }, {
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
110 }, {
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
115 } };
116
117 static const u32 cz_golden_settings_a11[] =
118 {
119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
120 mmFBC_MISC, 0x1f311fff, 0x14300000,
121 };
122
123 static const u32 cz_mgcg_cgcg_init[] =
124 {
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127 };
128
129 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
130 {
131 switch (adev->asic_type) {
132 case CHIP_CARRIZO:
133 amdgpu_program_register_sequence(adev,
134 cz_mgcg_cgcg_init,
135 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
136 amdgpu_program_register_sequence(adev,
137 cz_golden_settings_a11,
138 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
139 break;
140 default:
141 break;
142 }
143 }
144
145 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
146 u32 block_offset, u32 reg)
147 {
148 unsigned long flags;
149 u32 r;
150
151 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
152 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
153 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
154 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
155
156 return r;
157 }
158
159 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
160 u32 block_offset, u32 reg, u32 v)
161 {
162 unsigned long flags;
163
164 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
165 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
166 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
167 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
168 }
169
170 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
171 {
172 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
173 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
174 return true;
175 else
176 return false;
177 }
178
179 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
180 {
181 u32 pos1, pos2;
182
183 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
184 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
185
186 if (pos1 != pos2)
187 return true;
188 else
189 return false;
190 }
191
192 /**
193 * dce_v11_0_vblank_wait - vblank wait asic callback.
194 *
195 * @adev: amdgpu_device pointer
196 * @crtc: crtc to wait for vblank on
197 *
198 * Wait for vblank on the requested crtc (evergreen+).
199 */
200 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
201 {
202 unsigned i = 0;
203
204 if (crtc >= adev->mode_info.num_crtc)
205 return;
206
207 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
208 return;
209
210 /* depending on when we hit vblank, we may be close to active; if so,
211 * wait for another frame.
212 */
213 while (dce_v11_0_is_in_vblank(adev, crtc)) {
214 if (i++ % 100 == 0) {
215 if (!dce_v11_0_is_counter_moving(adev, crtc))
216 break;
217 }
218 }
219
220 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
221 if (i++ % 100 == 0) {
222 if (!dce_v11_0_is_counter_moving(adev, crtc))
223 break;
224 }
225 }
226 }
227
228 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
229 {
230 if (crtc >= adev->mode_info.num_crtc)
231 return 0;
232 else
233 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
234 }
235
236 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
237 {
238 unsigned i;
239
240 /* Enable pflip interrupts */
241 for (i = 0; i < adev->mode_info.num_crtc; i++)
242 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
243 }
244
245 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
246 {
247 unsigned i;
248
249 /* Disable pflip interrupts */
250 for (i = 0; i < adev->mode_info.num_crtc; i++)
251 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
252 }
253
254 /**
255 * dce_v11_0_page_flip - pageflip callback.
256 *
257 * @adev: amdgpu_device pointer
258 * @crtc_id: crtc to cleanup pageflip on
259 * @crtc_base: new address of the crtc (GPU MC address)
260 *
261 * Does the actual pageflip (evergreen+).
262 * During vblank we take the crtc lock and wait for the update_pending
263 * bit to go high, when it does, we release the lock, and allow the
264 * double buffered update to take place.
265 * Returns the current update pending status.
266 */
267 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
268 int crtc_id, u64 crtc_base)
269 {
270 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
271 u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset);
272 int i;
273
274 /* Lock the graphics update lock */
275 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
276 WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
277
278 /* update the scanout addresses */
279 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
280 upper_32_bits(crtc_base));
281 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
282 lower_32_bits(crtc_base));
283
284 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
285 upper_32_bits(crtc_base));
286 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
287 lower_32_bits(crtc_base));
288
289 /* Wait for update_pending to go high. */
290 for (i = 0; i < adev->usec_timeout; i++) {
291 if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) &
292 GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK)
293 break;
294 udelay(1);
295 }
296 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
297
298 /* Unlock the lock, so double-buffering can take place inside vblank */
299 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
300 WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
301 }
302
303 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
304 u32 *vbl, u32 *position)
305 {
306 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
307 return -EINVAL;
308
309 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
310 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
311
312 return 0;
313 }
314
315 /**
316 * dce_v11_0_hpd_sense - hpd sense callback.
317 *
318 * @adev: amdgpu_device pointer
319 * @hpd: hpd (hotplug detect) pin
320 *
321 * Checks if a digital monitor is connected (evergreen+).
322 * Returns true if connected, false if not connected.
323 */
324 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
325 enum amdgpu_hpd_id hpd)
326 {
327 int idx;
328 bool connected = false;
329
330 switch (hpd) {
331 case AMDGPU_HPD_1:
332 idx = 0;
333 break;
334 case AMDGPU_HPD_2:
335 idx = 1;
336 break;
337 case AMDGPU_HPD_3:
338 idx = 2;
339 break;
340 case AMDGPU_HPD_4:
341 idx = 3;
342 break;
343 case AMDGPU_HPD_5:
344 idx = 4;
345 break;
346 case AMDGPU_HPD_6:
347 idx = 5;
348 break;
349 default:
350 return connected;
351 }
352
353 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
354 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
355 connected = true;
356
357 return connected;
358 }
359
360 /**
361 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
362 *
363 * @adev: amdgpu_device pointer
364 * @hpd: hpd (hotplug detect) pin
365 *
366 * Set the polarity of the hpd pin (evergreen+).
367 */
368 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
369 enum amdgpu_hpd_id hpd)
370 {
371 u32 tmp;
372 bool connected = dce_v11_0_hpd_sense(adev, hpd);
373 int idx;
374
375 switch (hpd) {
376 case AMDGPU_HPD_1:
377 idx = 0;
378 break;
379 case AMDGPU_HPD_2:
380 idx = 1;
381 break;
382 case AMDGPU_HPD_3:
383 idx = 2;
384 break;
385 case AMDGPU_HPD_4:
386 idx = 3;
387 break;
388 case AMDGPU_HPD_5:
389 idx = 4;
390 break;
391 case AMDGPU_HPD_6:
392 idx = 5;
393 break;
394 default:
395 return;
396 }
397
398 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
399 if (connected)
400 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
401 else
402 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
403 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
404 }
405
406 /**
407 * dce_v11_0_hpd_init - hpd setup callback.
408 *
409 * @adev: amdgpu_device pointer
410 *
411 * Setup the hpd pins used by the card (evergreen+).
412 * Enable the pin, set the polarity, and enable the hpd interrupts.
413 */
414 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
415 {
416 struct drm_device *dev = adev->ddev;
417 struct drm_connector *connector;
418 u32 tmp;
419 int idx;
420
421 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
422 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
423
424 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
425 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
426 /* don't try to enable hpd on eDP or LVDS avoid breaking the
427 * aux dp channel on imac and help (but not completely fix)
428 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
429 * also avoid interrupt storms during dpms.
430 */
431 continue;
432 }
433
434 switch (amdgpu_connector->hpd.hpd) {
435 case AMDGPU_HPD_1:
436 idx = 0;
437 break;
438 case AMDGPU_HPD_2:
439 idx = 1;
440 break;
441 case AMDGPU_HPD_3:
442 idx = 2;
443 break;
444 case AMDGPU_HPD_4:
445 idx = 3;
446 break;
447 case AMDGPU_HPD_5:
448 idx = 4;
449 break;
450 case AMDGPU_HPD_6:
451 idx = 5;
452 break;
453 default:
454 continue;
455 }
456
457 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
458 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
459 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
460
461 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
462 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
463 DC_HPD_CONNECT_INT_DELAY,
464 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
465 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
466 DC_HPD_DISCONNECT_INT_DELAY,
467 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
468 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
469
470 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
471 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
472 }
473 }
474
475 /**
476 * dce_v11_0_hpd_fini - hpd tear down callback.
477 *
478 * @adev: amdgpu_device pointer
479 *
480 * Tear down the hpd pins used by the card (evergreen+).
481 * Disable the hpd interrupts.
482 */
483 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
484 {
485 struct drm_device *dev = adev->ddev;
486 struct drm_connector *connector;
487 u32 tmp;
488 int idx;
489
490 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
491 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
492
493 switch (amdgpu_connector->hpd.hpd) {
494 case AMDGPU_HPD_1:
495 idx = 0;
496 break;
497 case AMDGPU_HPD_2:
498 idx = 1;
499 break;
500 case AMDGPU_HPD_3:
501 idx = 2;
502 break;
503 case AMDGPU_HPD_4:
504 idx = 3;
505 break;
506 case AMDGPU_HPD_5:
507 idx = 4;
508 break;
509 case AMDGPU_HPD_6:
510 idx = 5;
511 break;
512 default:
513 continue;
514 }
515
516 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
517 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
518 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
519
520 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
521 }
522 }
523
524 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
525 {
526 return mmDC_GPIO_HPD_A;
527 }
528
529 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
530 {
531 u32 crtc_hung = 0;
532 u32 crtc_status[6];
533 u32 i, j, tmp;
534
535 for (i = 0; i < adev->mode_info.num_crtc; i++) {
536 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
537 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
538 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
539 crtc_hung |= (1 << i);
540 }
541 }
542
543 for (j = 0; j < 10; j++) {
544 for (i = 0; i < adev->mode_info.num_crtc; i++) {
545 if (crtc_hung & (1 << i)) {
546 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
547 if (tmp != crtc_status[i])
548 crtc_hung &= ~(1 << i);
549 }
550 }
551 if (crtc_hung == 0)
552 return false;
553 udelay(100);
554 }
555
556 return true;
557 }
558
559 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
560 struct amdgpu_mode_mc_save *save)
561 {
562 u32 crtc_enabled, tmp;
563 int i;
564
565 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
566 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
567
568 /* disable VGA render */
569 tmp = RREG32(mmVGA_RENDER_CONTROL);
570 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
571 WREG32(mmVGA_RENDER_CONTROL, tmp);
572
573 /* blank the display controllers */
574 for (i = 0; i < adev->mode_info.num_crtc; i++) {
575 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
576 CRTC_CONTROL, CRTC_MASTER_EN);
577 if (crtc_enabled) {
578 #if 0
579 u32 frame_count;
580 int j;
581
582 save->crtc_enabled[i] = true;
583 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
584 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
585 amdgpu_display_vblank_wait(adev, i);
586 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
587 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
588 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
589 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
590 }
591 /* wait for the next frame */
592 frame_count = amdgpu_display_vblank_get_counter(adev, i);
593 for (j = 0; j < adev->usec_timeout; j++) {
594 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
595 break;
596 udelay(1);
597 }
598 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
599 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
600 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
601 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
602 }
603 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
604 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
605 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
606 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
607 }
608 #else
609 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
610 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
611 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
612 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
613 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
614 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
615 save->crtc_enabled[i] = false;
616 /* ***** */
617 #endif
618 } else {
619 save->crtc_enabled[i] = false;
620 }
621 }
622 }
623
624 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
625 struct amdgpu_mode_mc_save *save)
626 {
627 u32 tmp, frame_count;
628 int i, j;
629
630 /* update crtc base addresses */
631 for (i = 0; i < adev->mode_info.num_crtc; i++) {
632 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
633 upper_32_bits(adev->mc.vram_start));
634 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
635 upper_32_bits(adev->mc.vram_start));
636 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
637 (u32)adev->mc.vram_start);
638 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
639 (u32)adev->mc.vram_start);
640
641 if (save->crtc_enabled[i]) {
642 tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
643 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
644 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
645 WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
646 }
647 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
648 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
649 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
650 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
651 }
652 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
653 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
654 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
655 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
656 }
657 for (j = 0; j < adev->usec_timeout; j++) {
658 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
659 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
660 break;
661 udelay(1);
662 }
663 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
664 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
665 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
666 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
667 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
668 /* wait for the next frame */
669 frame_count = amdgpu_display_vblank_get_counter(adev, i);
670 for (j = 0; j < adev->usec_timeout; j++) {
671 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
672 break;
673 udelay(1);
674 }
675 }
676 }
677
678 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
679 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
680
681 /* Unlock vga access */
682 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
683 mdelay(1);
684 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
685 }
686
687 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
688 bool render)
689 {
690 u32 tmp;
691
692 /* Lockout access through VGA aperture*/
693 tmp = RREG32(mmVGA_HDP_CONTROL);
694 if (render)
695 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
696 else
697 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
698 WREG32(mmVGA_HDP_CONTROL, tmp);
699
700 /* disable VGA render */
701 tmp = RREG32(mmVGA_RENDER_CONTROL);
702 if (render)
703 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
704 else
705 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
706 WREG32(mmVGA_RENDER_CONTROL, tmp);
707 }
708
709 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
710 {
711 struct drm_device *dev = encoder->dev;
712 struct amdgpu_device *adev = dev->dev_private;
713 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
714 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
715 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
716 int bpc = 0;
717 u32 tmp = 0;
718 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
719
720 if (connector) {
721 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
722 bpc = amdgpu_connector_get_monitor_bpc(connector);
723 dither = amdgpu_connector->dither;
724 }
725
726 /* LVDS/eDP FMT is set up by atom */
727 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
728 return;
729
730 /* not needed for analog */
731 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
732 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
733 return;
734
735 if (bpc == 0)
736 return;
737
738 switch (bpc) {
739 case 6:
740 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
741 /* XXX sort out optimal dither settings */
742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
743 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
745 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
746 } else {
747 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
748 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
749 }
750 break;
751 case 8:
752 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
753 /* XXX sort out optimal dither settings */
754 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
755 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
756 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
759 } else {
760 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
762 }
763 break;
764 case 10:
765 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
766 /* XXX sort out optimal dither settings */
767 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
768 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
769 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
770 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
771 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
772 } else {
773 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
774 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
775 }
776 break;
777 default:
778 /* not needed */
779 break;
780 }
781
782 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
783 }
784
785
786 /* display watermark setup */
787 /**
788 * dce_v11_0_line_buffer_adjust - Set up the line buffer
789 *
790 * @adev: amdgpu_device pointer
791 * @amdgpu_crtc: the selected display controller
792 * @mode: the current display mode on the selected display
793 * controller
794 *
795 * Setup up the line buffer allocation for
796 * the selected display controller (CIK).
797 * Returns the line buffer size in pixels.
798 */
799 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
800 struct amdgpu_crtc *amdgpu_crtc,
801 struct drm_display_mode *mode)
802 {
803 u32 tmp, buffer_alloc, i, mem_cfg;
804 u32 pipe_offset = amdgpu_crtc->crtc_id;
805 /*
806 * Line Buffer Setup
807 * There are 6 line buffers, one for each display controllers.
808 * There are 3 partitions per LB. Select the number of partitions
809 * to enable based on the display width. For display widths larger
810 * than 4096, you need use to use 2 display controllers and combine
811 * them using the stereo blender.
812 */
813 if (amdgpu_crtc->base.enabled && mode) {
814 if (mode->crtc_hdisplay < 1920) {
815 mem_cfg = 1;
816 buffer_alloc = 2;
817 } else if (mode->crtc_hdisplay < 2560) {
818 mem_cfg = 2;
819 buffer_alloc = 2;
820 } else if (mode->crtc_hdisplay < 4096) {
821 mem_cfg = 0;
822 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
823 } else {
824 DRM_DEBUG_KMS("Mode too big for LB!\n");
825 mem_cfg = 0;
826 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
827 }
828 } else {
829 mem_cfg = 1;
830 buffer_alloc = 0;
831 }
832
833 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
834 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
835 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
836
837 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
838 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
839 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
840
841 for (i = 0; i < adev->usec_timeout; i++) {
842 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
843 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
844 break;
845 udelay(1);
846 }
847
848 if (amdgpu_crtc->base.enabled && mode) {
849 switch (mem_cfg) {
850 case 0:
851 default:
852 return 4096 * 2;
853 case 1:
854 return 1920 * 2;
855 case 2:
856 return 2560 * 2;
857 }
858 }
859
860 /* controller not enabled, so no lb used */
861 return 0;
862 }
863
864 /**
865 * cik_get_number_of_dram_channels - get the number of dram channels
866 *
867 * @adev: amdgpu_device pointer
868 *
869 * Look up the number of video ram channels (CIK).
870 * Used for display watermark bandwidth calculations
871 * Returns the number of dram channels
872 */
873 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
874 {
875 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
876
877 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
878 case 0:
879 default:
880 return 1;
881 case 1:
882 return 2;
883 case 2:
884 return 4;
885 case 3:
886 return 8;
887 case 4:
888 return 3;
889 case 5:
890 return 6;
891 case 6:
892 return 10;
893 case 7:
894 return 12;
895 case 8:
896 return 16;
897 }
898 }
899
900 struct dce10_wm_params {
901 u32 dram_channels; /* number of dram channels */
902 u32 yclk; /* bandwidth per dram data pin in kHz */
903 u32 sclk; /* engine clock in kHz */
904 u32 disp_clk; /* display clock in kHz */
905 u32 src_width; /* viewport width */
906 u32 active_time; /* active display time in ns */
907 u32 blank_time; /* blank time in ns */
908 bool interlaced; /* mode is interlaced */
909 fixed20_12 vsc; /* vertical scale ratio */
910 u32 num_heads; /* number of active crtcs */
911 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
912 u32 lb_size; /* line buffer allocated to pipe */
913 u32 vtaps; /* vertical scaler taps */
914 };
915
916 /**
917 * dce_v11_0_dram_bandwidth - get the dram bandwidth
918 *
919 * @wm: watermark calculation data
920 *
921 * Calculate the raw dram bandwidth (CIK).
922 * Used for display watermark bandwidth calculations
923 * Returns the dram bandwidth in MBytes/s
924 */
925 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
926 {
927 /* Calculate raw DRAM Bandwidth */
928 fixed20_12 dram_efficiency; /* 0.7 */
929 fixed20_12 yclk, dram_channels, bandwidth;
930 fixed20_12 a;
931
932 a.full = dfixed_const(1000);
933 yclk.full = dfixed_const(wm->yclk);
934 yclk.full = dfixed_div(yclk, a);
935 dram_channels.full = dfixed_const(wm->dram_channels * 4);
936 a.full = dfixed_const(10);
937 dram_efficiency.full = dfixed_const(7);
938 dram_efficiency.full = dfixed_div(dram_efficiency, a);
939 bandwidth.full = dfixed_mul(dram_channels, yclk);
940 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
941
942 return dfixed_trunc(bandwidth);
943 }
944
945 /**
946 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
947 *
948 * @wm: watermark calculation data
949 *
950 * Calculate the dram bandwidth used for display (CIK).
951 * Used for display watermark bandwidth calculations
952 * Returns the dram bandwidth for display in MBytes/s
953 */
954 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
955 {
956 /* Calculate DRAM Bandwidth and the part allocated to display. */
957 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
958 fixed20_12 yclk, dram_channels, bandwidth;
959 fixed20_12 a;
960
961 a.full = dfixed_const(1000);
962 yclk.full = dfixed_const(wm->yclk);
963 yclk.full = dfixed_div(yclk, a);
964 dram_channels.full = dfixed_const(wm->dram_channels * 4);
965 a.full = dfixed_const(10);
966 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
967 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
968 bandwidth.full = dfixed_mul(dram_channels, yclk);
969 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
970
971 return dfixed_trunc(bandwidth);
972 }
973
974 /**
975 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
976 *
977 * @wm: watermark calculation data
978 *
979 * Calculate the data return bandwidth used for display (CIK).
980 * Used for display watermark bandwidth calculations
981 * Returns the data return bandwidth in MBytes/s
982 */
983 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
984 {
985 /* Calculate the display Data return Bandwidth */
986 fixed20_12 return_efficiency; /* 0.8 */
987 fixed20_12 sclk, bandwidth;
988 fixed20_12 a;
989
990 a.full = dfixed_const(1000);
991 sclk.full = dfixed_const(wm->sclk);
992 sclk.full = dfixed_div(sclk, a);
993 a.full = dfixed_const(10);
994 return_efficiency.full = dfixed_const(8);
995 return_efficiency.full = dfixed_div(return_efficiency, a);
996 a.full = dfixed_const(32);
997 bandwidth.full = dfixed_mul(a, sclk);
998 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
999
1000 return dfixed_trunc(bandwidth);
1001 }
1002
1003 /**
1004 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
1005 *
1006 * @wm: watermark calculation data
1007 *
1008 * Calculate the dmif bandwidth used for display (CIK).
1009 * Used for display watermark bandwidth calculations
1010 * Returns the dmif bandwidth in MBytes/s
1011 */
1012 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1013 {
1014 /* Calculate the DMIF Request Bandwidth */
1015 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1016 fixed20_12 disp_clk, bandwidth;
1017 fixed20_12 a, b;
1018
1019 a.full = dfixed_const(1000);
1020 disp_clk.full = dfixed_const(wm->disp_clk);
1021 disp_clk.full = dfixed_div(disp_clk, a);
1022 a.full = dfixed_const(32);
1023 b.full = dfixed_mul(a, disp_clk);
1024
1025 a.full = dfixed_const(10);
1026 disp_clk_request_efficiency.full = dfixed_const(8);
1027 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1028
1029 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1030
1031 return dfixed_trunc(bandwidth);
1032 }
1033
1034 /**
1035 * dce_v11_0_available_bandwidth - get the min available bandwidth
1036 *
1037 * @wm: watermark calculation data
1038 *
1039 * Calculate the min available bandwidth used for display (CIK).
1040 * Used for display watermark bandwidth calculations
1041 * Returns the min available bandwidth in MBytes/s
1042 */
1043 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1044 {
1045 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1046 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1047 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1048 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1049
1050 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1051 }
1052
1053 /**
1054 * dce_v11_0_average_bandwidth - get the average available bandwidth
1055 *
1056 * @wm: watermark calculation data
1057 *
1058 * Calculate the average available bandwidth used for display (CIK).
1059 * Used for display watermark bandwidth calculations
1060 * Returns the average available bandwidth in MBytes/s
1061 */
1062 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1063 {
1064 /* Calculate the display mode Average Bandwidth
1065 * DisplayMode should contain the source and destination dimensions,
1066 * timing, etc.
1067 */
1068 fixed20_12 bpp;
1069 fixed20_12 line_time;
1070 fixed20_12 src_width;
1071 fixed20_12 bandwidth;
1072 fixed20_12 a;
1073
1074 a.full = dfixed_const(1000);
1075 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1076 line_time.full = dfixed_div(line_time, a);
1077 bpp.full = dfixed_const(wm->bytes_per_pixel);
1078 src_width.full = dfixed_const(wm->src_width);
1079 bandwidth.full = dfixed_mul(src_width, bpp);
1080 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1081 bandwidth.full = dfixed_div(bandwidth, line_time);
1082
1083 return dfixed_trunc(bandwidth);
1084 }
1085
1086 /**
1087 * dce_v11_0_latency_watermark - get the latency watermark
1088 *
1089 * @wm: watermark calculation data
1090 *
1091 * Calculate the latency watermark (CIK).
1092 * Used for display watermark bandwidth calculations
1093 * Returns the latency watermark in ns
1094 */
1095 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1096 {
1097 /* First calculate the latency in ns */
1098 u32 mc_latency = 2000; /* 2000 ns. */
1099 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1100 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1101 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1102 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1103 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1104 (wm->num_heads * cursor_line_pair_return_time);
1105 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1106 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1107 u32 tmp, dmif_size = 12288;
1108 fixed20_12 a, b, c;
1109
1110 if (wm->num_heads == 0)
1111 return 0;
1112
1113 a.full = dfixed_const(2);
1114 b.full = dfixed_const(1);
1115 if ((wm->vsc.full > a.full) ||
1116 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1117 (wm->vtaps >= 5) ||
1118 ((wm->vsc.full >= a.full) && wm->interlaced))
1119 max_src_lines_per_dst_line = 4;
1120 else
1121 max_src_lines_per_dst_line = 2;
1122
1123 a.full = dfixed_const(available_bandwidth);
1124 b.full = dfixed_const(wm->num_heads);
1125 a.full = dfixed_div(a, b);
1126
1127 b.full = dfixed_const(mc_latency + 512);
1128 c.full = dfixed_const(wm->disp_clk);
1129 b.full = dfixed_div(b, c);
1130
1131 c.full = dfixed_const(dmif_size);
1132 b.full = dfixed_div(c, b);
1133
1134 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1135
1136 b.full = dfixed_const(1000);
1137 c.full = dfixed_const(wm->disp_clk);
1138 b.full = dfixed_div(c, b);
1139 c.full = dfixed_const(wm->bytes_per_pixel);
1140 b.full = dfixed_mul(b, c);
1141
1142 lb_fill_bw = min(tmp, dfixed_trunc(b));
1143
1144 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1145 b.full = dfixed_const(1000);
1146 c.full = dfixed_const(lb_fill_bw);
1147 b.full = dfixed_div(c, b);
1148 a.full = dfixed_div(a, b);
1149 line_fill_time = dfixed_trunc(a);
1150
1151 if (line_fill_time < wm->active_time)
1152 return latency;
1153 else
1154 return latency + (line_fill_time - wm->active_time);
1155
1156 }
1157
1158 /**
1159 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1160 * average and available dram bandwidth
1161 *
1162 * @wm: watermark calculation data
1163 *
1164 * Check if the display average bandwidth fits in the display
1165 * dram bandwidth (CIK).
1166 * Used for display watermark bandwidth calculations
1167 * Returns true if the display fits, false if not.
1168 */
1169 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1170 {
1171 if (dce_v11_0_average_bandwidth(wm) <=
1172 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1173 return true;
1174 else
1175 return false;
1176 }
1177
1178 /**
1179 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1180 * average and available bandwidth
1181 *
1182 * @wm: watermark calculation data
1183 *
1184 * Check if the display average bandwidth fits in the display
1185 * available bandwidth (CIK).
1186 * Used for display watermark bandwidth calculations
1187 * Returns true if the display fits, false if not.
1188 */
1189 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1190 {
1191 if (dce_v11_0_average_bandwidth(wm) <=
1192 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1193 return true;
1194 else
1195 return false;
1196 }
1197
1198 /**
1199 * dce_v11_0_check_latency_hiding - check latency hiding
1200 *
1201 * @wm: watermark calculation data
1202 *
1203 * Check latency hiding (CIK).
1204 * Used for display watermark bandwidth calculations
1205 * Returns true if the display fits, false if not.
1206 */
1207 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1208 {
1209 u32 lb_partitions = wm->lb_size / wm->src_width;
1210 u32 line_time = wm->active_time + wm->blank_time;
1211 u32 latency_tolerant_lines;
1212 u32 latency_hiding;
1213 fixed20_12 a;
1214
1215 a.full = dfixed_const(1);
1216 if (wm->vsc.full > a.full)
1217 latency_tolerant_lines = 1;
1218 else {
1219 if (lb_partitions <= (wm->vtaps + 1))
1220 latency_tolerant_lines = 1;
1221 else
1222 latency_tolerant_lines = 2;
1223 }
1224
1225 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1226
1227 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1228 return true;
1229 else
1230 return false;
1231 }
1232
1233 /**
1234 * dce_v11_0_program_watermarks - program display watermarks
1235 *
1236 * @adev: amdgpu_device pointer
1237 * @amdgpu_crtc: the selected display controller
1238 * @lb_size: line buffer size
1239 * @num_heads: number of display controllers in use
1240 *
1241 * Calculate and program the display watermarks for the
1242 * selected display controller (CIK).
1243 */
1244 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1245 struct amdgpu_crtc *amdgpu_crtc,
1246 u32 lb_size, u32 num_heads)
1247 {
1248 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1249 struct dce10_wm_params wm_low, wm_high;
1250 u32 pixel_period;
1251 u32 line_time = 0;
1252 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1253 u32 tmp, wm_mask;
1254
1255 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1256 pixel_period = 1000000 / (u32)mode->clock;
1257 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1258
1259 /* watermark for high clocks */
1260 if (adev->pm.dpm_enabled) {
1261 wm_high.yclk =
1262 amdgpu_dpm_get_mclk(adev, false) * 10;
1263 wm_high.sclk =
1264 amdgpu_dpm_get_sclk(adev, false) * 10;
1265 } else {
1266 wm_high.yclk = adev->pm.current_mclk * 10;
1267 wm_high.sclk = adev->pm.current_sclk * 10;
1268 }
1269
1270 wm_high.disp_clk = mode->clock;
1271 wm_high.src_width = mode->crtc_hdisplay;
1272 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1273 wm_high.blank_time = line_time - wm_high.active_time;
1274 wm_high.interlaced = false;
1275 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1276 wm_high.interlaced = true;
1277 wm_high.vsc = amdgpu_crtc->vsc;
1278 wm_high.vtaps = 1;
1279 if (amdgpu_crtc->rmx_type != RMX_OFF)
1280 wm_high.vtaps = 2;
1281 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1282 wm_high.lb_size = lb_size;
1283 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1284 wm_high.num_heads = num_heads;
1285
1286 /* set for high clocks */
1287 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1288
1289 /* possibly force display priority to high */
1290 /* should really do this at mode validation time... */
1291 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1292 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1293 !dce_v11_0_check_latency_hiding(&wm_high) ||
1294 (adev->mode_info.disp_priority == 2)) {
1295 DRM_DEBUG_KMS("force priority to high\n");
1296 }
1297
1298 /* watermark for low clocks */
1299 if (adev->pm.dpm_enabled) {
1300 wm_low.yclk =
1301 amdgpu_dpm_get_mclk(adev, true) * 10;
1302 wm_low.sclk =
1303 amdgpu_dpm_get_sclk(adev, true) * 10;
1304 } else {
1305 wm_low.yclk = adev->pm.current_mclk * 10;
1306 wm_low.sclk = adev->pm.current_sclk * 10;
1307 }
1308
1309 wm_low.disp_clk = mode->clock;
1310 wm_low.src_width = mode->crtc_hdisplay;
1311 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1312 wm_low.blank_time = line_time - wm_low.active_time;
1313 wm_low.interlaced = false;
1314 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1315 wm_low.interlaced = true;
1316 wm_low.vsc = amdgpu_crtc->vsc;
1317 wm_low.vtaps = 1;
1318 if (amdgpu_crtc->rmx_type != RMX_OFF)
1319 wm_low.vtaps = 2;
1320 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1321 wm_low.lb_size = lb_size;
1322 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1323 wm_low.num_heads = num_heads;
1324
1325 /* set for low clocks */
1326 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1327
1328 /* possibly force display priority to high */
1329 /* should really do this at mode validation time... */
1330 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1331 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1332 !dce_v11_0_check_latency_hiding(&wm_low) ||
1333 (adev->mode_info.disp_priority == 2)) {
1334 DRM_DEBUG_KMS("force priority to high\n");
1335 }
1336 }
1337
1338 /* select wm A */
1339 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1340 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1341 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1342 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1343 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1344 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1345 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1346 /* select wm B */
1347 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1348 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1349 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1350 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1351 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1352 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1353 /* restore original selection */
1354 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1355
1356 /* save values for DPM */
1357 amdgpu_crtc->line_time = line_time;
1358 amdgpu_crtc->wm_high = latency_watermark_a;
1359 amdgpu_crtc->wm_low = latency_watermark_b;
1360 }
1361
1362 /**
1363 * dce_v11_0_bandwidth_update - program display watermarks
1364 *
1365 * @adev: amdgpu_device pointer
1366 *
1367 * Calculate and program the display watermarks and line
1368 * buffer allocation (CIK).
1369 */
1370 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1371 {
1372 struct drm_display_mode *mode = NULL;
1373 u32 num_heads = 0, lb_size;
1374 int i;
1375
1376 amdgpu_update_display_priority(adev);
1377
1378 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1379 if (adev->mode_info.crtcs[i]->base.enabled)
1380 num_heads++;
1381 }
1382 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1383 mode = &adev->mode_info.crtcs[i]->base.mode;
1384 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1385 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1386 lb_size, num_heads);
1387 }
1388 }
1389
1390 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1391 {
1392 int i;
1393 u32 offset, tmp;
1394
1395 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1396 offset = adev->mode_info.audio.pin[i].offset;
1397 tmp = RREG32_AUDIO_ENDPT(offset,
1398 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1399 if (((tmp &
1400 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1401 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1402 adev->mode_info.audio.pin[i].connected = false;
1403 else
1404 adev->mode_info.audio.pin[i].connected = true;
1405 }
1406 }
1407
1408 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1409 {
1410 int i;
1411
1412 dce_v11_0_audio_get_connected_pins(adev);
1413
1414 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1415 if (adev->mode_info.audio.pin[i].connected)
1416 return &adev->mode_info.audio.pin[i];
1417 }
1418 DRM_ERROR("No connected audio pins found!\n");
1419 return NULL;
1420 }
1421
1422 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1423 {
1424 struct amdgpu_device *adev = encoder->dev->dev_private;
1425 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1426 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1427 u32 tmp;
1428
1429 if (!dig || !dig->afmt || !dig->afmt->pin)
1430 return;
1431
1432 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1433 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1434 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1435 }
1436
1437 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1438 struct drm_display_mode *mode)
1439 {
1440 struct amdgpu_device *adev = encoder->dev->dev_private;
1441 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1442 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1443 struct drm_connector *connector;
1444 struct amdgpu_connector *amdgpu_connector = NULL;
1445 u32 tmp;
1446 int interlace = 0;
1447
1448 if (!dig || !dig->afmt || !dig->afmt->pin)
1449 return;
1450
1451 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1452 if (connector->encoder == encoder) {
1453 amdgpu_connector = to_amdgpu_connector(connector);
1454 break;
1455 }
1456 }
1457
1458 if (!amdgpu_connector) {
1459 DRM_ERROR("Couldn't find encoder's connector\n");
1460 return;
1461 }
1462
1463 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1464 interlace = 1;
1465 if (connector->latency_present[interlace]) {
1466 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1467 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1468 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1469 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1470 } else {
1471 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1472 VIDEO_LIPSYNC, 0);
1473 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1474 AUDIO_LIPSYNC, 0);
1475 }
1476 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1477 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1478 }
1479
1480 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1481 {
1482 struct amdgpu_device *adev = encoder->dev->dev_private;
1483 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1484 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1485 struct drm_connector *connector;
1486 struct amdgpu_connector *amdgpu_connector = NULL;
1487 u32 tmp;
1488 u8 *sadb = NULL;
1489 int sad_count;
1490
1491 if (!dig || !dig->afmt || !dig->afmt->pin)
1492 return;
1493
1494 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1495 if (connector->encoder == encoder) {
1496 amdgpu_connector = to_amdgpu_connector(connector);
1497 break;
1498 }
1499 }
1500
1501 if (!amdgpu_connector) {
1502 DRM_ERROR("Couldn't find encoder's connector\n");
1503 return;
1504 }
1505
1506 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1507 if (sad_count < 0) {
1508 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1509 sad_count = 0;
1510 }
1511
1512 /* program the speaker allocation */
1513 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1514 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1515 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1516 DP_CONNECTION, 0);
1517 /* set HDMI mode */
1518 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1519 HDMI_CONNECTION, 1);
1520 if (sad_count)
1521 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1522 SPEAKER_ALLOCATION, sadb[0]);
1523 else
1524 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1525 SPEAKER_ALLOCATION, 5); /* stereo */
1526 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1527 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1528
1529 kfree(sadb);
1530 }
1531
1532 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1533 {
1534 struct amdgpu_device *adev = encoder->dev->dev_private;
1535 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1536 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1537 struct drm_connector *connector;
1538 struct amdgpu_connector *amdgpu_connector = NULL;
1539 struct cea_sad *sads;
1540 int i, sad_count;
1541
1542 static const u16 eld_reg_to_type[][2] = {
1543 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1544 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1545 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1546 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1547 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1548 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1549 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1550 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1551 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1552 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1553 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1554 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1555 };
1556
1557 if (!dig || !dig->afmt || !dig->afmt->pin)
1558 return;
1559
1560 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1561 if (connector->encoder == encoder) {
1562 amdgpu_connector = to_amdgpu_connector(connector);
1563 break;
1564 }
1565 }
1566
1567 if (!amdgpu_connector) {
1568 DRM_ERROR("Couldn't find encoder's connector\n");
1569 return;
1570 }
1571
1572 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1573 if (sad_count <= 0) {
1574 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1575 return;
1576 }
1577 BUG_ON(!sads);
1578
1579 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1580 u32 tmp = 0;
1581 u8 stereo_freqs = 0;
1582 int max_channels = -1;
1583 int j;
1584
1585 for (j = 0; j < sad_count; j++) {
1586 struct cea_sad *sad = &sads[j];
1587
1588 if (sad->format == eld_reg_to_type[i][1]) {
1589 if (sad->channels > max_channels) {
1590 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1591 MAX_CHANNELS, sad->channels);
1592 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1593 DESCRIPTOR_BYTE_2, sad->byte2);
1594 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1595 SUPPORTED_FREQUENCIES, sad->freq);
1596 max_channels = sad->channels;
1597 }
1598
1599 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1600 stereo_freqs |= sad->freq;
1601 else
1602 break;
1603 }
1604 }
1605
1606 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1607 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1608 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1609 }
1610
1611 kfree(sads);
1612 }
1613
1614 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1615 struct amdgpu_audio_pin *pin,
1616 bool enable)
1617 {
1618 if (!pin)
1619 return;
1620
1621 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1622 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1623 }
1624
1625 static const u32 pin_offsets[] =
1626 {
1627 AUD0_REGISTER_OFFSET,
1628 AUD1_REGISTER_OFFSET,
1629 AUD2_REGISTER_OFFSET,
1630 AUD3_REGISTER_OFFSET,
1631 AUD4_REGISTER_OFFSET,
1632 AUD5_REGISTER_OFFSET,
1633 AUD6_REGISTER_OFFSET,
1634 };
1635
1636 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1637 {
1638 int i;
1639
1640 if (!amdgpu_audio)
1641 return 0;
1642
1643 adev->mode_info.audio.enabled = true;
1644
1645 adev->mode_info.audio.num_pins = 7;
1646
1647 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1648 adev->mode_info.audio.pin[i].channels = -1;
1649 adev->mode_info.audio.pin[i].rate = -1;
1650 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1651 adev->mode_info.audio.pin[i].status_bits = 0;
1652 adev->mode_info.audio.pin[i].category_code = 0;
1653 adev->mode_info.audio.pin[i].connected = false;
1654 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1655 adev->mode_info.audio.pin[i].id = i;
1656 /* disable audio. it will be set up later */
1657 /* XXX remove once we switch to ip funcs */
1658 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1659 }
1660
1661 return 0;
1662 }
1663
1664 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1665 {
1666 int i;
1667
1668 if (!adev->mode_info.audio.enabled)
1669 return;
1670
1671 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1672 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1673
1674 adev->mode_info.audio.enabled = false;
1675 }
1676
1677 /*
1678 * update the N and CTS parameters for a given pixel clock rate
1679 */
1680 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1681 {
1682 struct drm_device *dev = encoder->dev;
1683 struct amdgpu_device *adev = dev->dev_private;
1684 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1685 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1686 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1687 u32 tmp;
1688
1689 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1690 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1691 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1692 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1693 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1694 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1695
1696 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1697 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1698 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1699 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1700 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1701 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1702
1703 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1704 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1705 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1706 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1707 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1708 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1709
1710 }
1711
1712 /*
1713 * build a HDMI Video Info Frame
1714 */
1715 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1716 void *buffer, size_t size)
1717 {
1718 struct drm_device *dev = encoder->dev;
1719 struct amdgpu_device *adev = dev->dev_private;
1720 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1721 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1722 uint8_t *frame = buffer + 3;
1723 uint8_t *header = buffer;
1724
1725 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1726 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1727 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1728 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1729 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1730 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1731 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1732 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1733 }
1734
1735 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1736 {
1737 struct drm_device *dev = encoder->dev;
1738 struct amdgpu_device *adev = dev->dev_private;
1739 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1740 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1741 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1742 u32 dto_phase = 24 * 1000;
1743 u32 dto_modulo = clock;
1744 u32 tmp;
1745
1746 if (!dig || !dig->afmt)
1747 return;
1748
1749 /* XXX two dtos; generally use dto0 for hdmi */
1750 /* Express [24MHz / target pixel clock] as an exact rational
1751 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1752 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1753 */
1754 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1755 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1756 amdgpu_crtc->crtc_id);
1757 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1758 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1759 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1760 }
1761
1762 /*
1763 * update the info frames with the data from the current display mode
1764 */
1765 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1766 struct drm_display_mode *mode)
1767 {
1768 struct drm_device *dev = encoder->dev;
1769 struct amdgpu_device *adev = dev->dev_private;
1770 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1771 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1772 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1773 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1774 struct hdmi_avi_infoframe frame;
1775 ssize_t err;
1776 u32 tmp;
1777 int bpc = 8;
1778
1779 if (!dig || !dig->afmt)
1780 return;
1781
1782 /* Silent, r600_hdmi_enable will raise WARN for us */
1783 if (!dig->afmt->enabled)
1784 return;
1785
1786 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1787 if (encoder->crtc) {
1788 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1789 bpc = amdgpu_crtc->bpc;
1790 }
1791
1792 /* disable audio prior to setting up hw */
1793 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1794 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1795
1796 dce_v11_0_audio_set_dto(encoder, mode->clock);
1797
1798 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1799 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1800 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1801
1802 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1803
1804 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1805 switch (bpc) {
1806 case 0:
1807 case 6:
1808 case 8:
1809 case 16:
1810 default:
1811 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1812 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1813 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1814 connector->name, bpc);
1815 break;
1816 case 10:
1817 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1818 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1819 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1820 connector->name);
1821 break;
1822 case 12:
1823 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1824 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1825 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1826 connector->name);
1827 break;
1828 }
1829 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1830
1831 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1832 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1833 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1834 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1835 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1836
1837 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1838 /* enable audio info frames (frames won't be set until audio is enabled) */
1839 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1840 /* required for audio info values to be updated */
1841 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1842 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1843
1844 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1845 /* required for audio info values to be updated */
1846 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1847 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1848
1849 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1850 /* anything other than 0 */
1851 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1852 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1853
1854 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1855
1856 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1857 /* set the default audio delay */
1858 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1859 /* should be suffient for all audio modes and small enough for all hblanks */
1860 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1861 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1862
1863 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1864 /* allow 60958 channel status fields to be updated */
1865 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1866 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1867
1868 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1869 if (bpc > 8)
1870 /* clear SW CTS value */
1871 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1872 else
1873 /* select SW CTS value */
1874 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1875 /* allow hw to sent ACR packets when required */
1876 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1877 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1878
1879 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1880
1881 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1882 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1883 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1884
1885 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1886 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1887 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1888
1889 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1890 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1891 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1892 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1893 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1894 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1895 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1896 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1897
1898 dce_v11_0_audio_write_speaker_allocation(encoder);
1899
1900 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1901 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1902
1903 dce_v11_0_afmt_audio_select_pin(encoder);
1904 dce_v11_0_audio_write_sad_regs(encoder);
1905 dce_v11_0_audio_write_latency_fields(encoder, mode);
1906
1907 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1908 if (err < 0) {
1909 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1910 return;
1911 }
1912
1913 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1914 if (err < 0) {
1915 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1916 return;
1917 }
1918
1919 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1920
1921 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1922 /* enable AVI info frames */
1923 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1924 /* required for audio info values to be updated */
1925 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1926 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1927
1928 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1929 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1930 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1931
1932 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1933 /* send audio packets */
1934 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1935 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1936
1937 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1938 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1939 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1940 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1941
1942 /* enable audio after to setting up hw */
1943 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1944 }
1945
1946 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1947 {
1948 struct drm_device *dev = encoder->dev;
1949 struct amdgpu_device *adev = dev->dev_private;
1950 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1951 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1952
1953 if (!dig || !dig->afmt)
1954 return;
1955
1956 /* Silent, r600_hdmi_enable will raise WARN for us */
1957 if (enable && dig->afmt->enabled)
1958 return;
1959 if (!enable && !dig->afmt->enabled)
1960 return;
1961
1962 if (!enable && dig->afmt->pin) {
1963 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1964 dig->afmt->pin = NULL;
1965 }
1966
1967 dig->afmt->enabled = enable;
1968
1969 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1970 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1971 }
1972
1973 static void dce_v11_0_afmt_init(struct amdgpu_device *adev)
1974 {
1975 int i;
1976
1977 for (i = 0; i < adev->mode_info.num_dig; i++)
1978 adev->mode_info.afmt[i] = NULL;
1979
1980 /* DCE11 has audio blocks tied to DIG encoders */
1981 for (i = 0; i < adev->mode_info.num_dig; i++) {
1982 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1983 if (adev->mode_info.afmt[i]) {
1984 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1985 adev->mode_info.afmt[i]->id = i;
1986 }
1987 }
1988 }
1989
1990 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1991 {
1992 int i;
1993
1994 for (i = 0; i < adev->mode_info.num_dig; i++) {
1995 kfree(adev->mode_info.afmt[i]);
1996 adev->mode_info.afmt[i] = NULL;
1997 }
1998 }
1999
2000 static const u32 vga_control_regs[6] =
2001 {
2002 mmD1VGA_CONTROL,
2003 mmD2VGA_CONTROL,
2004 mmD3VGA_CONTROL,
2005 mmD4VGA_CONTROL,
2006 mmD5VGA_CONTROL,
2007 mmD6VGA_CONTROL,
2008 };
2009
2010 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
2011 {
2012 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2013 struct drm_device *dev = crtc->dev;
2014 struct amdgpu_device *adev = dev->dev_private;
2015 u32 vga_control;
2016
2017 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2018 if (enable)
2019 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2020 else
2021 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2022 }
2023
2024 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2025 {
2026 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2027 struct drm_device *dev = crtc->dev;
2028 struct amdgpu_device *adev = dev->dev_private;
2029
2030 if (enable)
2031 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2032 else
2033 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2034 }
2035
2036 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2037 struct drm_framebuffer *fb,
2038 int x, int y, int atomic)
2039 {
2040 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2041 struct drm_device *dev = crtc->dev;
2042 struct amdgpu_device *adev = dev->dev_private;
2043 struct amdgpu_framebuffer *amdgpu_fb;
2044 struct drm_framebuffer *target_fb;
2045 struct drm_gem_object *obj;
2046 struct amdgpu_bo *rbo;
2047 uint64_t fb_location, tiling_flags;
2048 uint32_t fb_format, fb_pitch_pixels;
2049 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2050 u32 pipe_config;
2051 u32 tmp, viewport_w, viewport_h;
2052 int r;
2053 bool bypass_lut = false;
2054
2055 /* no fb bound */
2056 if (!atomic && !crtc->primary->fb) {
2057 DRM_DEBUG_KMS("No FB bound\n");
2058 return 0;
2059 }
2060
2061 if (atomic) {
2062 amdgpu_fb = to_amdgpu_framebuffer(fb);
2063 target_fb = fb;
2064 }
2065 else {
2066 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2067 target_fb = crtc->primary->fb;
2068 }
2069
2070 /* If atomic, assume fb object is pinned & idle & fenced and
2071 * just update base pointers
2072 */
2073 obj = amdgpu_fb->obj;
2074 rbo = gem_to_amdgpu_bo(obj);
2075 r = amdgpu_bo_reserve(rbo, false);
2076 if (unlikely(r != 0))
2077 return r;
2078
2079 if (atomic)
2080 fb_location = amdgpu_bo_gpu_offset(rbo);
2081 else {
2082 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2083 if (unlikely(r != 0)) {
2084 amdgpu_bo_unreserve(rbo);
2085 return -EINVAL;
2086 }
2087 }
2088
2089 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2090 amdgpu_bo_unreserve(rbo);
2091
2092 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2093
2094 switch (target_fb->pixel_format) {
2095 case DRM_FORMAT_C8:
2096 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2097 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2098 break;
2099 case DRM_FORMAT_XRGB4444:
2100 case DRM_FORMAT_ARGB4444:
2101 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2102 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2103 #ifdef __BIG_ENDIAN
2104 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2105 ENDIAN_8IN16);
2106 #endif
2107 break;
2108 case DRM_FORMAT_XRGB1555:
2109 case DRM_FORMAT_ARGB1555:
2110 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2111 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2112 #ifdef __BIG_ENDIAN
2113 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2114 ENDIAN_8IN16);
2115 #endif
2116 break;
2117 case DRM_FORMAT_BGRX5551:
2118 case DRM_FORMAT_BGRA5551:
2119 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2120 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2121 #ifdef __BIG_ENDIAN
2122 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2123 ENDIAN_8IN16);
2124 #endif
2125 break;
2126 case DRM_FORMAT_RGB565:
2127 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2128 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2129 #ifdef __BIG_ENDIAN
2130 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2131 ENDIAN_8IN16);
2132 #endif
2133 break;
2134 case DRM_FORMAT_XRGB8888:
2135 case DRM_FORMAT_ARGB8888:
2136 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2137 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2138 #ifdef __BIG_ENDIAN
2139 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2140 ENDIAN_8IN32);
2141 #endif
2142 break;
2143 case DRM_FORMAT_XRGB2101010:
2144 case DRM_FORMAT_ARGB2101010:
2145 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2146 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2147 #ifdef __BIG_ENDIAN
2148 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2149 ENDIAN_8IN32);
2150 #endif
2151 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2152 bypass_lut = true;
2153 break;
2154 case DRM_FORMAT_BGRX1010102:
2155 case DRM_FORMAT_BGRA1010102:
2156 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2157 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2158 #ifdef __BIG_ENDIAN
2159 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2160 ENDIAN_8IN32);
2161 #endif
2162 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2163 bypass_lut = true;
2164 break;
2165 default:
2166 DRM_ERROR("Unsupported screen format %s\n",
2167 drm_get_format_name(target_fb->pixel_format));
2168 return -EINVAL;
2169 }
2170
2171 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2172 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2173
2174 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2175 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2176 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2177 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2178 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2179
2180 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2181 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2182 ARRAY_2D_TILED_THIN1);
2183 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2184 tile_split);
2185 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2186 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2187 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2188 mtaspect);
2189 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2190 ADDR_SURF_MICRO_TILING_DISPLAY);
2191 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2192 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2193 ARRAY_1D_TILED_THIN1);
2194 }
2195
2196 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2197 pipe_config);
2198
2199 dce_v11_0_vga_enable(crtc, false);
2200
2201 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2202 upper_32_bits(fb_location));
2203 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2204 upper_32_bits(fb_location));
2205 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2206 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2207 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2208 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2209 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2210 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2211
2212 /*
2213 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2214 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2215 * retain the full precision throughout the pipeline.
2216 */
2217 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2218 if (bypass_lut)
2219 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2220 else
2221 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2222 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2223
2224 if (bypass_lut)
2225 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2226
2227 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2228 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2229 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2230 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2231 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2232 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2233
2234 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2235 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2236
2237 dce_v11_0_grph_enable(crtc, true);
2238
2239 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2240 target_fb->height);
2241
2242 x &= ~3;
2243 y &= ~1;
2244 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2245 (x << 16) | y);
2246 viewport_w = crtc->mode.hdisplay;
2247 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2248 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2249 (viewport_w << 16) | viewport_h);
2250
2251 /* pageflip setup */
2252 /* make sure flip is at vb rather than hb */
2253 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2254 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2255 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2256 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2257
2258 /* set pageflip to happen only at start of vblank interval (front porch) */
2259 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2260
2261 if (!atomic && fb && fb != crtc->primary->fb) {
2262 amdgpu_fb = to_amdgpu_framebuffer(fb);
2263 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2264 r = amdgpu_bo_reserve(rbo, false);
2265 if (unlikely(r != 0))
2266 return r;
2267 amdgpu_bo_unpin(rbo);
2268 amdgpu_bo_unreserve(rbo);
2269 }
2270
2271 /* Bytes per pixel may have changed */
2272 dce_v11_0_bandwidth_update(adev);
2273
2274 return 0;
2275 }
2276
2277 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2278 struct drm_display_mode *mode)
2279 {
2280 struct drm_device *dev = crtc->dev;
2281 struct amdgpu_device *adev = dev->dev_private;
2282 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2283 u32 tmp;
2284
2285 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2286 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2287 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2288 else
2289 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2290 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2291 }
2292
2293 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2294 {
2295 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2296 struct drm_device *dev = crtc->dev;
2297 struct amdgpu_device *adev = dev->dev_private;
2298 int i;
2299 u32 tmp;
2300
2301 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2302
2303 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2304 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2305 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2306
2307 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2308 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2309 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2310
2311 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2312 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2313 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2314
2315 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2316
2317 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2318 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2319 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2320
2321 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2322 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2323 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2324
2325 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2326 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2327
2328 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2329 for (i = 0; i < 256; i++) {
2330 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2331 (amdgpu_crtc->lut_r[i] << 20) |
2332 (amdgpu_crtc->lut_g[i] << 10) |
2333 (amdgpu_crtc->lut_b[i] << 0));
2334 }
2335
2336 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2337 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2338 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2339 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2340 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2341
2342 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2343 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2344 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2345
2346 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2347 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2348 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2349
2350 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2351 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2352 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2353
2354 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2355 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2356 /* XXX this only needs to be programmed once per crtc at startup,
2357 * not sure where the best place for it is
2358 */
2359 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2360 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2361 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2362 }
2363
2364 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2365 {
2366 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2367 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2368
2369 switch (amdgpu_encoder->encoder_id) {
2370 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2371 if (dig->linkb)
2372 return 1;
2373 else
2374 return 0;
2375 break;
2376 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2377 if (dig->linkb)
2378 return 3;
2379 else
2380 return 2;
2381 break;
2382 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2383 if (dig->linkb)
2384 return 5;
2385 else
2386 return 4;
2387 break;
2388 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2389 return 6;
2390 break;
2391 default:
2392 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2393 return 0;
2394 }
2395 }
2396
2397 /**
2398 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2399 *
2400 * @crtc: drm crtc
2401 *
2402 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2403 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2404 * monitors a dedicated PPLL must be used. If a particular board has
2405 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2406 * as there is no need to program the PLL itself. If we are not able to
2407 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2408 * avoid messing up an existing monitor.
2409 *
2410 * Asic specific PLL information
2411 *
2412 * DCE 10.x
2413 * Tonga
2414 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2415 * CI
2416 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2417 *
2418 */
2419 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2420 {
2421 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2422 struct drm_device *dev = crtc->dev;
2423 struct amdgpu_device *adev = dev->dev_private;
2424 u32 pll_in_use;
2425 int pll;
2426
2427 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2428 if (adev->clock.dp_extclk)
2429 /* skip PPLL programming if using ext clock */
2430 return ATOM_PPLL_INVALID;
2431 else {
2432 /* use the same PPLL for all DP monitors */
2433 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2434 if (pll != ATOM_PPLL_INVALID)
2435 return pll;
2436 }
2437 } else {
2438 /* use the same PPLL for all monitors with the same clock */
2439 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2440 if (pll != ATOM_PPLL_INVALID)
2441 return pll;
2442 }
2443
2444 /* XXX need to determine what plls are available on each DCE11 part */
2445 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2446 if (adev->asic_type == CHIP_CARRIZO) {
2447 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2448 return ATOM_PPLL1;
2449 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2450 return ATOM_PPLL0;
2451 DRM_ERROR("unable to allocate a PPLL\n");
2452 return ATOM_PPLL_INVALID;
2453 } else {
2454 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2455 return ATOM_PPLL2;
2456 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2457 return ATOM_PPLL1;
2458 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2459 return ATOM_PPLL0;
2460 DRM_ERROR("unable to allocate a PPLL\n");
2461 return ATOM_PPLL_INVALID;
2462 }
2463 return ATOM_PPLL_INVALID;
2464 }
2465
2466 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2467 {
2468 struct amdgpu_device *adev = crtc->dev->dev_private;
2469 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2470 uint32_t cur_lock;
2471
2472 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2473 if (lock)
2474 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2475 else
2476 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2477 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2478 }
2479
2480 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2481 {
2482 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2483 struct amdgpu_device *adev = crtc->dev->dev_private;
2484 u32 tmp;
2485
2486 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2487 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2488 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2489 }
2490
2491 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2492 {
2493 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2494 struct amdgpu_device *adev = crtc->dev->dev_private;
2495 u32 tmp;
2496
2497 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2498 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2499 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2500 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2501 }
2502
2503 static void dce_v11_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
2504 uint64_t gpu_addr)
2505 {
2506 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2507 struct amdgpu_device *adev = crtc->dev->dev_private;
2508
2509 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2510 upper_32_bits(gpu_addr));
2511 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2512 lower_32_bits(gpu_addr));
2513 }
2514
2515 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2516 int x, int y)
2517 {
2518 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2519 struct amdgpu_device *adev = crtc->dev->dev_private;
2520 int xorigin = 0, yorigin = 0;
2521
2522 /* avivo cursor are offset into the total surface */
2523 x += crtc->x;
2524 y += crtc->y;
2525 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2526
2527 if (x < 0) {
2528 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2529 x = 0;
2530 }
2531 if (y < 0) {
2532 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2533 y = 0;
2534 }
2535
2536 dce_v11_0_lock_cursor(crtc, true);
2537 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2538 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2539 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2540 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2541 dce_v11_0_lock_cursor(crtc, false);
2542
2543 return 0;
2544 }
2545
2546 static int dce_v11_0_crtc_cursor_set(struct drm_crtc *crtc,
2547 struct drm_file *file_priv,
2548 uint32_t handle,
2549 uint32_t width,
2550 uint32_t height)
2551 {
2552 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2553 struct drm_gem_object *obj;
2554 struct amdgpu_bo *robj;
2555 uint64_t gpu_addr;
2556 int ret;
2557
2558 if (!handle) {
2559 /* turn off cursor */
2560 dce_v11_0_hide_cursor(crtc);
2561 obj = NULL;
2562 goto unpin;
2563 }
2564
2565 if ((width > amdgpu_crtc->max_cursor_width) ||
2566 (height > amdgpu_crtc->max_cursor_height)) {
2567 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2568 return -EINVAL;
2569 }
2570
2571 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2572 if (!obj) {
2573 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2574 return -ENOENT;
2575 }
2576
2577 robj = gem_to_amdgpu_bo(obj);
2578 ret = amdgpu_bo_reserve(robj, false);
2579 if (unlikely(ret != 0))
2580 goto fail;
2581 ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM,
2582 0, 0, &gpu_addr);
2583 amdgpu_bo_unreserve(robj);
2584 if (ret)
2585 goto fail;
2586
2587 amdgpu_crtc->cursor_width = width;
2588 amdgpu_crtc->cursor_height = height;
2589
2590 dce_v11_0_lock_cursor(crtc, true);
2591 dce_v11_0_set_cursor(crtc, obj, gpu_addr);
2592 dce_v11_0_show_cursor(crtc);
2593 dce_v11_0_lock_cursor(crtc, false);
2594
2595 unpin:
2596 if (amdgpu_crtc->cursor_bo) {
2597 robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2598 ret = amdgpu_bo_reserve(robj, false);
2599 if (likely(ret == 0)) {
2600 amdgpu_bo_unpin(robj);
2601 amdgpu_bo_unreserve(robj);
2602 }
2603 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2604 }
2605
2606 amdgpu_crtc->cursor_bo = obj;
2607 return 0;
2608 fail:
2609 drm_gem_object_unreference_unlocked(obj);
2610
2611 return ret;
2612 }
2613
2614 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2615 u16 *blue, uint32_t start, uint32_t size)
2616 {
2617 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2618 int end = (start + size > 256) ? 256 : start + size, i;
2619
2620 /* userspace palettes are always correct as is */
2621 for (i = start; i < end; i++) {
2622 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2623 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2624 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2625 }
2626 dce_v11_0_crtc_load_lut(crtc);
2627 }
2628
2629 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2630 {
2631 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2632
2633 drm_crtc_cleanup(crtc);
2634 destroy_workqueue(amdgpu_crtc->pflip_queue);
2635 kfree(amdgpu_crtc);
2636 }
2637
2638 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2639 .cursor_set = dce_v11_0_crtc_cursor_set,
2640 .cursor_move = dce_v11_0_crtc_cursor_move,
2641 .gamma_set = dce_v11_0_crtc_gamma_set,
2642 .set_config = amdgpu_crtc_set_config,
2643 .destroy = dce_v11_0_crtc_destroy,
2644 .page_flip = amdgpu_crtc_page_flip,
2645 };
2646
2647 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2648 {
2649 struct drm_device *dev = crtc->dev;
2650 struct amdgpu_device *adev = dev->dev_private;
2651 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2652 unsigned type;
2653
2654 switch (mode) {
2655 case DRM_MODE_DPMS_ON:
2656 amdgpu_crtc->enabled = true;
2657 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2658 dce_v11_0_vga_enable(crtc, true);
2659 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2660 dce_v11_0_vga_enable(crtc, false);
2661 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2662 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2663 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2664 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2665 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2666 dce_v11_0_crtc_load_lut(crtc);
2667 break;
2668 case DRM_MODE_DPMS_STANDBY:
2669 case DRM_MODE_DPMS_SUSPEND:
2670 case DRM_MODE_DPMS_OFF:
2671 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2672 if (amdgpu_crtc->enabled) {
2673 dce_v11_0_vga_enable(crtc, true);
2674 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2675 dce_v11_0_vga_enable(crtc, false);
2676 }
2677 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2678 amdgpu_crtc->enabled = false;
2679 break;
2680 }
2681 /* adjust pm to dpms */
2682 amdgpu_pm_compute_clocks(adev);
2683 }
2684
2685 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2686 {
2687 /* disable crtc pair power gating before programming */
2688 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2689 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2690 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2691 }
2692
2693 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2694 {
2695 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2696 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2697 }
2698
2699 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2700 {
2701 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2702 struct drm_device *dev = crtc->dev;
2703 struct amdgpu_device *adev = dev->dev_private;
2704 struct amdgpu_atom_ss ss;
2705 int i;
2706
2707 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2708 if (crtc->primary->fb) {
2709 int r;
2710 struct amdgpu_framebuffer *amdgpu_fb;
2711 struct amdgpu_bo *rbo;
2712
2713 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2714 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2715 r = amdgpu_bo_reserve(rbo, false);
2716 if (unlikely(r))
2717 DRM_ERROR("failed to reserve rbo before unpin\n");
2718 else {
2719 amdgpu_bo_unpin(rbo);
2720 amdgpu_bo_unreserve(rbo);
2721 }
2722 }
2723 /* disable the GRPH */
2724 dce_v11_0_grph_enable(crtc, false);
2725
2726 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2727
2728 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2729 if (adev->mode_info.crtcs[i] &&
2730 adev->mode_info.crtcs[i]->enabled &&
2731 i != amdgpu_crtc->crtc_id &&
2732 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2733 /* one other crtc is using this pll don't turn
2734 * off the pll
2735 */
2736 goto done;
2737 }
2738 }
2739
2740 switch (amdgpu_crtc->pll_id) {
2741 case ATOM_PPLL0:
2742 case ATOM_PPLL1:
2743 case ATOM_PPLL2:
2744 /* disable the ppll */
2745 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2746 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2747 break;
2748 default:
2749 break;
2750 }
2751 done:
2752 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2753 amdgpu_crtc->adjusted_clock = 0;
2754 amdgpu_crtc->encoder = NULL;
2755 amdgpu_crtc->connector = NULL;
2756 }
2757
2758 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2759 struct drm_display_mode *mode,
2760 struct drm_display_mode *adjusted_mode,
2761 int x, int y, struct drm_framebuffer *old_fb)
2762 {
2763 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2764
2765 if (!amdgpu_crtc->adjusted_clock)
2766 return -EINVAL;
2767
2768 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2769 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2770 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2771 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2772 amdgpu_atombios_crtc_scaler_setup(crtc);
2773 /* update the hw version fpr dpm */
2774 amdgpu_crtc->hw_mode = *adjusted_mode;
2775
2776 return 0;
2777 }
2778
2779 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2780 const struct drm_display_mode *mode,
2781 struct drm_display_mode *adjusted_mode)
2782 {
2783 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2784 struct drm_device *dev = crtc->dev;
2785 struct drm_encoder *encoder;
2786
2787 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2788 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2789 if (encoder->crtc == crtc) {
2790 amdgpu_crtc->encoder = encoder;
2791 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2792 break;
2793 }
2794 }
2795 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2796 amdgpu_crtc->encoder = NULL;
2797 amdgpu_crtc->connector = NULL;
2798 return false;
2799 }
2800 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2801 return false;
2802 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2803 return false;
2804 /* pick pll */
2805 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2806 /* if we can't get a PPLL for a non-DP encoder, fail */
2807 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2808 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2809 return false;
2810
2811 return true;
2812 }
2813
2814 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2815 struct drm_framebuffer *old_fb)
2816 {
2817 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2818 }
2819
2820 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2821 struct drm_framebuffer *fb,
2822 int x, int y, enum mode_set_atomic state)
2823 {
2824 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2825 }
2826
2827 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2828 .dpms = dce_v11_0_crtc_dpms,
2829 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2830 .mode_set = dce_v11_0_crtc_mode_set,
2831 .mode_set_base = dce_v11_0_crtc_set_base,
2832 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2833 .prepare = dce_v11_0_crtc_prepare,
2834 .commit = dce_v11_0_crtc_commit,
2835 .load_lut = dce_v11_0_crtc_load_lut,
2836 .disable = dce_v11_0_crtc_disable,
2837 };
2838
2839 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2840 {
2841 struct amdgpu_crtc *amdgpu_crtc;
2842 int i;
2843
2844 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2845 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2846 if (amdgpu_crtc == NULL)
2847 return -ENOMEM;
2848
2849 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2850
2851 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2852 amdgpu_crtc->crtc_id = index;
2853 amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2854 adev->mode_info.crtcs[index] = amdgpu_crtc;
2855
2856 amdgpu_crtc->max_cursor_width = 128;
2857 amdgpu_crtc->max_cursor_height = 128;
2858 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2859 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2860
2861 for (i = 0; i < 256; i++) {
2862 amdgpu_crtc->lut_r[i] = i << 2;
2863 amdgpu_crtc->lut_g[i] = i << 2;
2864 amdgpu_crtc->lut_b[i] = i << 2;
2865 }
2866
2867 switch (amdgpu_crtc->crtc_id) {
2868 case 0:
2869 default:
2870 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2871 break;
2872 case 1:
2873 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2874 break;
2875 case 2:
2876 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2877 break;
2878 case 3:
2879 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2880 break;
2881 case 4:
2882 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2883 break;
2884 case 5:
2885 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2886 break;
2887 }
2888
2889 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2890 amdgpu_crtc->adjusted_clock = 0;
2891 amdgpu_crtc->encoder = NULL;
2892 amdgpu_crtc->connector = NULL;
2893 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2894
2895 return 0;
2896 }
2897
2898 static int dce_v11_0_early_init(void *handle)
2899 {
2900 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2901
2902 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2903 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2904
2905 dce_v11_0_set_display_funcs(adev);
2906 dce_v11_0_set_irq_funcs(adev);
2907
2908 switch (adev->asic_type) {
2909 case CHIP_CARRIZO:
2910 adev->mode_info.num_crtc = 3;
2911 adev->mode_info.num_hpd = 6;
2912 adev->mode_info.num_dig = 9;
2913 break;
2914 default:
2915 /* FIXME: not supported yet */
2916 return -EINVAL;
2917 }
2918
2919 return 0;
2920 }
2921
2922 static int dce_v11_0_sw_init(void *handle)
2923 {
2924 int r, i;
2925 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2926
2927 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2928 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2929 if (r)
2930 return r;
2931 }
2932
2933 for (i = 8; i < 20; i += 2) {
2934 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2935 if (r)
2936 return r;
2937 }
2938
2939 /* HPD hotplug */
2940 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2941 if (r)
2942 return r;
2943
2944 adev->mode_info.mode_config_initialized = true;
2945
2946 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2947
2948 adev->ddev->mode_config.max_width = 16384;
2949 adev->ddev->mode_config.max_height = 16384;
2950
2951 adev->ddev->mode_config.preferred_depth = 24;
2952 adev->ddev->mode_config.prefer_shadow = 1;
2953
2954 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2955
2956 r = amdgpu_modeset_create_props(adev);
2957 if (r)
2958 return r;
2959
2960 adev->ddev->mode_config.max_width = 16384;
2961 adev->ddev->mode_config.max_height = 16384;
2962
2963 /* allocate crtcs */
2964 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2965 r = dce_v11_0_crtc_init(adev, i);
2966 if (r)
2967 return r;
2968 }
2969
2970 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2971 amdgpu_print_display_setup(adev->ddev);
2972 else
2973 return -EINVAL;
2974
2975 /* setup afmt */
2976 dce_v11_0_afmt_init(adev);
2977
2978 r = dce_v11_0_audio_init(adev);
2979 if (r)
2980 return r;
2981
2982 drm_kms_helper_poll_init(adev->ddev);
2983
2984 return r;
2985 }
2986
2987 static int dce_v11_0_sw_fini(void *handle)
2988 {
2989 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2990
2991 kfree(adev->mode_info.bios_hardcoded_edid);
2992
2993 drm_kms_helper_poll_fini(adev->ddev);
2994
2995 dce_v11_0_audio_fini(adev);
2996
2997 dce_v11_0_afmt_fini(adev);
2998
2999 adev->mode_info.mode_config_initialized = false;
3000
3001 return 0;
3002 }
3003
3004 static int dce_v11_0_hw_init(void *handle)
3005 {
3006 int i;
3007 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3008
3009 dce_v11_0_init_golden_registers(adev);
3010
3011 /* init dig PHYs, disp eng pll */
3012 amdgpu_atombios_encoder_init_dig(adev);
3013 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3014
3015 /* initialize hpd */
3016 dce_v11_0_hpd_init(adev);
3017
3018 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3019 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3020 }
3021
3022 dce_v11_0_pageflip_interrupt_init(adev);
3023
3024 return 0;
3025 }
3026
3027 static int dce_v11_0_hw_fini(void *handle)
3028 {
3029 int i;
3030 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3031
3032 dce_v11_0_hpd_fini(adev);
3033
3034 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3035 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3036 }
3037
3038 dce_v11_0_pageflip_interrupt_fini(adev);
3039
3040 return 0;
3041 }
3042
3043 static int dce_v11_0_suspend(void *handle)
3044 {
3045 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3046
3047 amdgpu_atombios_scratch_regs_save(adev);
3048
3049 dce_v11_0_hpd_fini(adev);
3050
3051 dce_v11_0_pageflip_interrupt_fini(adev);
3052
3053 return 0;
3054 }
3055
3056 static int dce_v11_0_resume(void *handle)
3057 {
3058 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3059
3060 dce_v11_0_init_golden_registers(adev);
3061
3062 amdgpu_atombios_scratch_regs_restore(adev);
3063
3064 /* init dig PHYs, disp eng pll */
3065 amdgpu_atombios_crtc_powergate_init(adev);
3066 amdgpu_atombios_encoder_init_dig(adev);
3067 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3068 /* turn on the BL */
3069 if (adev->mode_info.bl_encoder) {
3070 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3071 adev->mode_info.bl_encoder);
3072 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3073 bl_level);
3074 }
3075
3076 /* initialize hpd */
3077 dce_v11_0_hpd_init(adev);
3078
3079 dce_v11_0_pageflip_interrupt_init(adev);
3080
3081 return 0;
3082 }
3083
3084 static bool dce_v11_0_is_idle(void *handle)
3085 {
3086 return true;
3087 }
3088
3089 static int dce_v11_0_wait_for_idle(void *handle)
3090 {
3091 return 0;
3092 }
3093
3094 static void dce_v11_0_print_status(void *handle)
3095 {
3096 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3097
3098 dev_info(adev->dev, "DCE 10.x registers\n");
3099 /* XXX todo */
3100 }
3101
3102 static int dce_v11_0_soft_reset(void *handle)
3103 {
3104 u32 srbm_soft_reset = 0, tmp;
3105 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3106
3107 if (dce_v11_0_is_display_hung(adev))
3108 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3109
3110 if (srbm_soft_reset) {
3111 dce_v11_0_print_status((void *)adev);
3112
3113 tmp = RREG32(mmSRBM_SOFT_RESET);
3114 tmp |= srbm_soft_reset;
3115 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3116 WREG32(mmSRBM_SOFT_RESET, tmp);
3117 tmp = RREG32(mmSRBM_SOFT_RESET);
3118
3119 udelay(50);
3120
3121 tmp &= ~srbm_soft_reset;
3122 WREG32(mmSRBM_SOFT_RESET, tmp);
3123 tmp = RREG32(mmSRBM_SOFT_RESET);
3124
3125 /* Wait a little for things to settle down */
3126 udelay(50);
3127 dce_v11_0_print_status((void *)adev);
3128 }
3129 return 0;
3130 }
3131
3132 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3133 int crtc,
3134 enum amdgpu_interrupt_state state)
3135 {
3136 u32 lb_interrupt_mask;
3137
3138 if (crtc >= adev->mode_info.num_crtc) {
3139 DRM_DEBUG("invalid crtc %d\n", crtc);
3140 return;
3141 }
3142
3143 switch (state) {
3144 case AMDGPU_IRQ_STATE_DISABLE:
3145 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3146 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3147 VBLANK_INTERRUPT_MASK, 0);
3148 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3149 break;
3150 case AMDGPU_IRQ_STATE_ENABLE:
3151 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3152 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3153 VBLANK_INTERRUPT_MASK, 1);
3154 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3155 break;
3156 default:
3157 break;
3158 }
3159 }
3160
3161 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3162 int crtc,
3163 enum amdgpu_interrupt_state state)
3164 {
3165 u32 lb_interrupt_mask;
3166
3167 if (crtc >= adev->mode_info.num_crtc) {
3168 DRM_DEBUG("invalid crtc %d\n", crtc);
3169 return;
3170 }
3171
3172 switch (state) {
3173 case AMDGPU_IRQ_STATE_DISABLE:
3174 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3175 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3176 VLINE_INTERRUPT_MASK, 0);
3177 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3178 break;
3179 case AMDGPU_IRQ_STATE_ENABLE:
3180 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3181 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3182 VLINE_INTERRUPT_MASK, 1);
3183 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3184 break;
3185 default:
3186 break;
3187 }
3188 }
3189
3190 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3191 struct amdgpu_irq_src *source,
3192 unsigned hpd,
3193 enum amdgpu_interrupt_state state)
3194 {
3195 u32 tmp;
3196
3197 if (hpd >= adev->mode_info.num_hpd) {
3198 DRM_DEBUG("invalid hdp %d\n", hpd);
3199 return 0;
3200 }
3201
3202 switch (state) {
3203 case AMDGPU_IRQ_STATE_DISABLE:
3204 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3205 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3206 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3207 break;
3208 case AMDGPU_IRQ_STATE_ENABLE:
3209 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3210 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3211 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3212 break;
3213 default:
3214 break;
3215 }
3216
3217 return 0;
3218 }
3219
3220 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3221 struct amdgpu_irq_src *source,
3222 unsigned type,
3223 enum amdgpu_interrupt_state state)
3224 {
3225 switch (type) {
3226 case AMDGPU_CRTC_IRQ_VBLANK1:
3227 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3228 break;
3229 case AMDGPU_CRTC_IRQ_VBLANK2:
3230 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3231 break;
3232 case AMDGPU_CRTC_IRQ_VBLANK3:
3233 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3234 break;
3235 case AMDGPU_CRTC_IRQ_VBLANK4:
3236 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3237 break;
3238 case AMDGPU_CRTC_IRQ_VBLANK5:
3239 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3240 break;
3241 case AMDGPU_CRTC_IRQ_VBLANK6:
3242 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3243 break;
3244 case AMDGPU_CRTC_IRQ_VLINE1:
3245 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3246 break;
3247 case AMDGPU_CRTC_IRQ_VLINE2:
3248 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3249 break;
3250 case AMDGPU_CRTC_IRQ_VLINE3:
3251 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3252 break;
3253 case AMDGPU_CRTC_IRQ_VLINE4:
3254 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3255 break;
3256 case AMDGPU_CRTC_IRQ_VLINE5:
3257 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3258 break;
3259 case AMDGPU_CRTC_IRQ_VLINE6:
3260 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3261 break;
3262 default:
3263 break;
3264 }
3265 return 0;
3266 }
3267
3268 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3269 struct amdgpu_irq_src *src,
3270 unsigned type,
3271 enum amdgpu_interrupt_state state)
3272 {
3273 u32 reg, reg_block;
3274 /* now deal with page flip IRQ */
3275 switch (type) {
3276 case AMDGPU_PAGEFLIP_IRQ_D1:
3277 reg_block = CRTC0_REGISTER_OFFSET;
3278 break;
3279 case AMDGPU_PAGEFLIP_IRQ_D2:
3280 reg_block = CRTC1_REGISTER_OFFSET;
3281 break;
3282 case AMDGPU_PAGEFLIP_IRQ_D3:
3283 reg_block = CRTC2_REGISTER_OFFSET;
3284 break;
3285 case AMDGPU_PAGEFLIP_IRQ_D4:
3286 reg_block = CRTC3_REGISTER_OFFSET;
3287 break;
3288 case AMDGPU_PAGEFLIP_IRQ_D5:
3289 reg_block = CRTC4_REGISTER_OFFSET;
3290 break;
3291 case AMDGPU_PAGEFLIP_IRQ_D6:
3292 reg_block = CRTC5_REGISTER_OFFSET;
3293 break;
3294 default:
3295 DRM_ERROR("invalid pageflip crtc %d\n", type);
3296 return -EINVAL;
3297 }
3298
3299 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
3300 if (state == AMDGPU_IRQ_STATE_DISABLE)
3301 WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3302 else
3303 WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3304
3305 return 0;
3306 }
3307
3308 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3309 struct amdgpu_irq_src *source,
3310 struct amdgpu_iv_entry *entry)
3311 {
3312 int reg_block;
3313 unsigned long flags;
3314 unsigned crtc_id;
3315 struct amdgpu_crtc *amdgpu_crtc;
3316 struct amdgpu_flip_work *works;
3317
3318 crtc_id = (entry->src_id - 8) >> 1;
3319 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3320
3321 /* ack the interrupt */
3322 switch(crtc_id){
3323 case AMDGPU_PAGEFLIP_IRQ_D1:
3324 reg_block = CRTC0_REGISTER_OFFSET;
3325 break;
3326 case AMDGPU_PAGEFLIP_IRQ_D2:
3327 reg_block = CRTC1_REGISTER_OFFSET;
3328 break;
3329 case AMDGPU_PAGEFLIP_IRQ_D3:
3330 reg_block = CRTC2_REGISTER_OFFSET;
3331 break;
3332 case AMDGPU_PAGEFLIP_IRQ_D4:
3333 reg_block = CRTC3_REGISTER_OFFSET;
3334 break;
3335 case AMDGPU_PAGEFLIP_IRQ_D5:
3336 reg_block = CRTC4_REGISTER_OFFSET;
3337 break;
3338 case AMDGPU_PAGEFLIP_IRQ_D6:
3339 reg_block = CRTC5_REGISTER_OFFSET;
3340 break;
3341 default:
3342 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3343 return -EINVAL;
3344 }
3345
3346 if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3347 WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3348
3349 /* IRQ could occur when in initial stage */
3350 if(amdgpu_crtc == NULL)
3351 return 0;
3352
3353 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3354 works = amdgpu_crtc->pflip_works;
3355 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3356 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3357 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3358 amdgpu_crtc->pflip_status,
3359 AMDGPU_FLIP_SUBMITTED);
3360 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3361 return 0;
3362 }
3363
3364 /* page flip completed. clean up */
3365 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3366 amdgpu_crtc->pflip_works = NULL;
3367
3368 /* wakeup usersapce */
3369 if(works->event)
3370 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3371
3372 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3373
3374 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3375 queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3376
3377 return 0;
3378 }
3379
3380 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3381 int hpd)
3382 {
3383 u32 tmp;
3384
3385 if (hpd >= adev->mode_info.num_hpd) {
3386 DRM_DEBUG("invalid hdp %d\n", hpd);
3387 return;
3388 }
3389
3390 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3391 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3392 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3393 }
3394
3395 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3396 int crtc)
3397 {
3398 u32 tmp;
3399
3400 if (crtc >= adev->mode_info.num_crtc) {
3401 DRM_DEBUG("invalid crtc %d\n", crtc);
3402 return;
3403 }
3404
3405 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3406 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3407 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3408 }
3409
3410 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3411 int crtc)
3412 {
3413 u32 tmp;
3414
3415 if (crtc >= adev->mode_info.num_crtc) {
3416 DRM_DEBUG("invalid crtc %d\n", crtc);
3417 return;
3418 }
3419
3420 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3421 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3422 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3423 }
3424
3425 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3426 struct amdgpu_irq_src *source,
3427 struct amdgpu_iv_entry *entry)
3428 {
3429 unsigned crtc = entry->src_id - 1;
3430 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3431 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3432
3433 switch (entry->src_data) {
3434 case 0: /* vblank */
3435 if (disp_int & interrupt_status_offsets[crtc].vblank)
3436 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3437 else
3438 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3439
3440 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3441 drm_handle_vblank(adev->ddev, crtc);
3442 }
3443 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3444
3445 break;
3446 case 1: /* vline */
3447 if (disp_int & interrupt_status_offsets[crtc].vline)
3448 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3449 else
3450 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3451
3452 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3453
3454 break;
3455 default:
3456 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3457 break;
3458 }
3459
3460 return 0;
3461 }
3462
3463 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3464 struct amdgpu_irq_src *source,
3465 struct amdgpu_iv_entry *entry)
3466 {
3467 uint32_t disp_int, mask;
3468 unsigned hpd;
3469
3470 if (entry->src_data >= adev->mode_info.num_hpd) {
3471 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3472 return 0;
3473 }
3474
3475 hpd = entry->src_data;
3476 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3477 mask = interrupt_status_offsets[hpd].hpd;
3478
3479 if (disp_int & mask) {
3480 dce_v11_0_hpd_int_ack(adev, hpd);
3481 schedule_work(&adev->hotplug_work);
3482 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3483 }
3484
3485 return 0;
3486 }
3487
3488 static int dce_v11_0_set_clockgating_state(void *handle,
3489 enum amd_clockgating_state state)
3490 {
3491 return 0;
3492 }
3493
3494 static int dce_v11_0_set_powergating_state(void *handle,
3495 enum amd_powergating_state state)
3496 {
3497 return 0;
3498 }
3499
3500 const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3501 .early_init = dce_v11_0_early_init,
3502 .late_init = NULL,
3503 .sw_init = dce_v11_0_sw_init,
3504 .sw_fini = dce_v11_0_sw_fini,
3505 .hw_init = dce_v11_0_hw_init,
3506 .hw_fini = dce_v11_0_hw_fini,
3507 .suspend = dce_v11_0_suspend,
3508 .resume = dce_v11_0_resume,
3509 .is_idle = dce_v11_0_is_idle,
3510 .wait_for_idle = dce_v11_0_wait_for_idle,
3511 .soft_reset = dce_v11_0_soft_reset,
3512 .print_status = dce_v11_0_print_status,
3513 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3514 .set_powergating_state = dce_v11_0_set_powergating_state,
3515 };
3516
3517 static void
3518 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3519 struct drm_display_mode *mode,
3520 struct drm_display_mode *adjusted_mode)
3521 {
3522 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3523
3524 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3525
3526 /* need to call this here rather than in prepare() since we need some crtc info */
3527 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3528
3529 /* set scaler clears this on some chips */
3530 dce_v11_0_set_interleave(encoder->crtc, mode);
3531
3532 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3533 dce_v11_0_afmt_enable(encoder, true);
3534 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3535 }
3536 }
3537
3538 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3539 {
3540 struct amdgpu_device *adev = encoder->dev->dev_private;
3541 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3542 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3543
3544 if ((amdgpu_encoder->active_device &
3545 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3546 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3547 ENCODER_OBJECT_ID_NONE)) {
3548 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3549 if (dig) {
3550 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3551 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3552 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3553 }
3554 }
3555
3556 amdgpu_atombios_scratch_regs_lock(adev, true);
3557
3558 if (connector) {
3559 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3560
3561 /* select the clock/data port if it uses a router */
3562 if (amdgpu_connector->router.cd_valid)
3563 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3564
3565 /* turn eDP panel on for mode set */
3566 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3567 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3568 ATOM_TRANSMITTER_ACTION_POWER_ON);
3569 }
3570
3571 /* this is needed for the pll/ss setup to work correctly in some cases */
3572 amdgpu_atombios_encoder_set_crtc_source(encoder);
3573 /* set up the FMT blocks */
3574 dce_v11_0_program_fmt(encoder);
3575 }
3576
3577 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3578 {
3579 struct drm_device *dev = encoder->dev;
3580 struct amdgpu_device *adev = dev->dev_private;
3581
3582 /* need to call this here as we need the crtc set up */
3583 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3584 amdgpu_atombios_scratch_regs_lock(adev, false);
3585 }
3586
3587 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3588 {
3589 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3590 struct amdgpu_encoder_atom_dig *dig;
3591
3592 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3593
3594 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3595 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3596 dce_v11_0_afmt_enable(encoder, false);
3597 dig = amdgpu_encoder->enc_priv;
3598 dig->dig_encoder = -1;
3599 }
3600 amdgpu_encoder->active_device = 0;
3601 }
3602
3603 /* these are handled by the primary encoders */
3604 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3605 {
3606
3607 }
3608
3609 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3610 {
3611
3612 }
3613
3614 static void
3615 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3616 struct drm_display_mode *mode,
3617 struct drm_display_mode *adjusted_mode)
3618 {
3619
3620 }
3621
3622 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3623 {
3624
3625 }
3626
3627 static void
3628 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3629 {
3630
3631 }
3632
3633 static bool dce_v11_0_ext_mode_fixup(struct drm_encoder *encoder,
3634 const struct drm_display_mode *mode,
3635 struct drm_display_mode *adjusted_mode)
3636 {
3637 return true;
3638 }
3639
3640 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3641 .dpms = dce_v11_0_ext_dpms,
3642 .mode_fixup = dce_v11_0_ext_mode_fixup,
3643 .prepare = dce_v11_0_ext_prepare,
3644 .mode_set = dce_v11_0_ext_mode_set,
3645 .commit = dce_v11_0_ext_commit,
3646 .disable = dce_v11_0_ext_disable,
3647 /* no detect for TMDS/LVDS yet */
3648 };
3649
3650 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3651 .dpms = amdgpu_atombios_encoder_dpms,
3652 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3653 .prepare = dce_v11_0_encoder_prepare,
3654 .mode_set = dce_v11_0_encoder_mode_set,
3655 .commit = dce_v11_0_encoder_commit,
3656 .disable = dce_v11_0_encoder_disable,
3657 .detect = amdgpu_atombios_encoder_dig_detect,
3658 };
3659
3660 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3661 .dpms = amdgpu_atombios_encoder_dpms,
3662 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3663 .prepare = dce_v11_0_encoder_prepare,
3664 .mode_set = dce_v11_0_encoder_mode_set,
3665 .commit = dce_v11_0_encoder_commit,
3666 .detect = amdgpu_atombios_encoder_dac_detect,
3667 };
3668
3669 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3670 {
3671 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3672 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3673 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3674 kfree(amdgpu_encoder->enc_priv);
3675 drm_encoder_cleanup(encoder);
3676 kfree(amdgpu_encoder);
3677 }
3678
3679 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3680 .destroy = dce_v11_0_encoder_destroy,
3681 };
3682
3683 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3684 uint32_t encoder_enum,
3685 uint32_t supported_device,
3686 u16 caps)
3687 {
3688 struct drm_device *dev = adev->ddev;
3689 struct drm_encoder *encoder;
3690 struct amdgpu_encoder *amdgpu_encoder;
3691
3692 /* see if we already added it */
3693 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3694 amdgpu_encoder = to_amdgpu_encoder(encoder);
3695 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3696 amdgpu_encoder->devices |= supported_device;
3697 return;
3698 }
3699
3700 }
3701
3702 /* add a new one */
3703 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3704 if (!amdgpu_encoder)
3705 return;
3706
3707 encoder = &amdgpu_encoder->base;
3708 switch (adev->mode_info.num_crtc) {
3709 case 1:
3710 encoder->possible_crtcs = 0x1;
3711 break;
3712 case 2:
3713 default:
3714 encoder->possible_crtcs = 0x3;
3715 break;
3716 case 4:
3717 encoder->possible_crtcs = 0xf;
3718 break;
3719 case 6:
3720 encoder->possible_crtcs = 0x3f;
3721 break;
3722 }
3723
3724 amdgpu_encoder->enc_priv = NULL;
3725
3726 amdgpu_encoder->encoder_enum = encoder_enum;
3727 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3728 amdgpu_encoder->devices = supported_device;
3729 amdgpu_encoder->rmx_type = RMX_OFF;
3730 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3731 amdgpu_encoder->is_ext_encoder = false;
3732 amdgpu_encoder->caps = caps;
3733
3734 switch (amdgpu_encoder->encoder_id) {
3735 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3736 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3737 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3738 DRM_MODE_ENCODER_DAC);
3739 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3740 break;
3741 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3742 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3743 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3744 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3745 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3746 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3747 amdgpu_encoder->rmx_type = RMX_FULL;
3748 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3749 DRM_MODE_ENCODER_LVDS);
3750 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3751 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3752 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3753 DRM_MODE_ENCODER_DAC);
3754 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3755 } else {
3756 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3757 DRM_MODE_ENCODER_TMDS);
3758 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3759 }
3760 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3761 break;
3762 case ENCODER_OBJECT_ID_SI170B:
3763 case ENCODER_OBJECT_ID_CH7303:
3764 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3765 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3766 case ENCODER_OBJECT_ID_TITFP513:
3767 case ENCODER_OBJECT_ID_VT1623:
3768 case ENCODER_OBJECT_ID_HDMI_SI1930:
3769 case ENCODER_OBJECT_ID_TRAVIS:
3770 case ENCODER_OBJECT_ID_NUTMEG:
3771 /* these are handled by the primary encoders */
3772 amdgpu_encoder->is_ext_encoder = true;
3773 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3774 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3775 DRM_MODE_ENCODER_LVDS);
3776 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3777 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3778 DRM_MODE_ENCODER_DAC);
3779 else
3780 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3781 DRM_MODE_ENCODER_TMDS);
3782 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3783 break;
3784 }
3785 }
3786
3787 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3788 .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3789 .bandwidth_update = &dce_v11_0_bandwidth_update,
3790 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3791 .vblank_wait = &dce_v11_0_vblank_wait,
3792 .is_display_hung = &dce_v11_0_is_display_hung,
3793 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3794 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3795 .hpd_sense = &dce_v11_0_hpd_sense,
3796 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3797 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3798 .page_flip = &dce_v11_0_page_flip,
3799 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3800 .add_encoder = &dce_v11_0_encoder_add,
3801 .add_connector = &amdgpu_connector_add,
3802 .stop_mc_access = &dce_v11_0_stop_mc_access,
3803 .resume_mc_access = &dce_v11_0_resume_mc_access,
3804 };
3805
3806 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3807 {
3808 if (adev->mode_info.funcs == NULL)
3809 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3810 }
3811
3812 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3813 .set = dce_v11_0_set_crtc_irq_state,
3814 .process = dce_v11_0_crtc_irq,
3815 };
3816
3817 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3818 .set = dce_v11_0_set_pageflip_irq_state,
3819 .process = dce_v11_0_pageflip_irq,
3820 };
3821
3822 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3823 .set = dce_v11_0_set_hpd_irq_state,
3824 .process = dce_v11_0_hpd_irq,
3825 };
3826
3827 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3828 {
3829 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3830 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3831
3832 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3833 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3834
3835 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3836 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3837 }
Linux kernel - Deliverables
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