2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_11_0_d.h"
36 #include "dce/dce_11_0_sh_mask.h"
37 #include "dce/dce_11_0_enum.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
43 static void dce_v11_0_set_display_funcs(struct amdgpu_device
*adev
);
44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device
*adev
);
46 static const u32 crtc_offsets
[] =
48 CRTC0_REGISTER_OFFSET
,
49 CRTC1_REGISTER_OFFSET
,
50 CRTC2_REGISTER_OFFSET
,
51 CRTC3_REGISTER_OFFSET
,
52 CRTC4_REGISTER_OFFSET
,
53 CRTC5_REGISTER_OFFSET
,
57 static const u32 hpd_offsets
[] =
67 static const uint32_t dig_offsets
[] = {
85 } interrupt_status_offsets
[] = { {
86 .reg
= mmDISP_INTERRUPT_STATUS
,
87 .vblank
= DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK
,
88 .vline
= DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK
,
89 .hpd
= DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE
,
92 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK
,
93 .vline
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK
,
94 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE2
,
97 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK
,
98 .vline
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK
,
99 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE3
,
102 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK
,
103 .vline
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK
,
104 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE4
,
107 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK
,
108 .vline
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK
,
109 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE5
,
112 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK
,
113 .vline
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK
,
114 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
117 static const u32 cz_golden_settings_a11
[] =
119 mmCRTC_DOUBLE_BUFFER_CONTROL
, 0x00010101, 0x00010000,
120 mmFBC_MISC
, 0x1f311fff, 0x14300000,
123 static const u32 cz_mgcg_cgcg_init
[] =
125 mmXDMA_CLOCK_GATING_CNTL
, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL
, 0x00000101, 0x00000000,
129 static const u32 stoney_golden_settings_a11
[] =
131 mmCRTC_DOUBLE_BUFFER_CONTROL
, 0x00010101, 0x00010000,
132 mmFBC_MISC
, 0x1f311fff, 0x14302000,
136 static void dce_v11_0_init_golden_registers(struct amdgpu_device
*adev
)
138 switch (adev
->asic_type
) {
140 amdgpu_program_register_sequence(adev
,
142 (const u32
)ARRAY_SIZE(cz_mgcg_cgcg_init
));
143 amdgpu_program_register_sequence(adev
,
144 cz_golden_settings_a11
,
145 (const u32
)ARRAY_SIZE(cz_golden_settings_a11
));
148 amdgpu_program_register_sequence(adev
,
149 stoney_golden_settings_a11
,
150 (const u32
)ARRAY_SIZE(stoney_golden_settings_a11
));
157 static u32
dce_v11_0_audio_endpt_rreg(struct amdgpu_device
*adev
,
158 u32 block_offset
, u32 reg
)
163 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
164 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
165 r
= RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
);
166 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
171 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device
*adev
,
172 u32 block_offset
, u32 reg
, u32 v
)
176 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
177 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
178 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
, v
);
179 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
182 static bool dce_v11_0_is_in_vblank(struct amdgpu_device
*adev
, int crtc
)
184 if (RREG32(mmCRTC_STATUS
+ crtc_offsets
[crtc
]) &
185 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK
)
191 static bool dce_v11_0_is_counter_moving(struct amdgpu_device
*adev
, int crtc
)
195 pos1
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
196 pos2
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
205 * dce_v11_0_vblank_wait - vblank wait asic callback.
207 * @adev: amdgpu_device pointer
208 * @crtc: crtc to wait for vblank on
210 * Wait for vblank on the requested crtc (evergreen+).
212 static void dce_v11_0_vblank_wait(struct amdgpu_device
*adev
, int crtc
)
216 if (crtc
>= adev
->mode_info
.num_crtc
)
219 if (!(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[crtc
]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK
))
222 /* depending on when we hit vblank, we may be close to active; if so,
223 * wait for another frame.
225 while (dce_v11_0_is_in_vblank(adev
, crtc
)) {
226 if (i
++ % 100 == 0) {
227 if (!dce_v11_0_is_counter_moving(adev
, crtc
))
232 while (!dce_v11_0_is_in_vblank(adev
, crtc
)) {
233 if (i
++ % 100 == 0) {
234 if (!dce_v11_0_is_counter_moving(adev
, crtc
))
240 static u32
dce_v11_0_vblank_get_counter(struct amdgpu_device
*adev
, int crtc
)
242 if (crtc
>= adev
->mode_info
.num_crtc
)
245 return RREG32(mmCRTC_STATUS_FRAME_COUNT
+ crtc_offsets
[crtc
]);
248 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device
*adev
)
252 /* Enable pflip interrupts */
253 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
254 amdgpu_irq_get(adev
, &adev
->pageflip_irq
, i
);
257 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device
*adev
)
261 /* Disable pflip interrupts */
262 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
263 amdgpu_irq_put(adev
, &adev
->pageflip_irq
, i
);
267 * dce_v11_0_page_flip - pageflip callback.
269 * @adev: amdgpu_device pointer
270 * @crtc_id: crtc to cleanup pageflip on
271 * @crtc_base: new address of the crtc (GPU MC address)
273 * Triggers the actual pageflip by updating the primary
274 * surface base address.
276 static void dce_v11_0_page_flip(struct amdgpu_device
*adev
,
277 int crtc_id
, u64 crtc_base
)
279 struct amdgpu_crtc
*amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
281 /* update the scanout addresses */
282 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
283 upper_32_bits(crtc_base
));
284 /* writing to the low address triggers the update */
285 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
286 lower_32_bits(crtc_base
));
288 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
);
291 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device
*adev
, int crtc
,
292 u32
*vbl
, u32
*position
)
294 if ((crtc
< 0) || (crtc
>= adev
->mode_info
.num_crtc
))
297 *vbl
= RREG32(mmCRTC_V_BLANK_START_END
+ crtc_offsets
[crtc
]);
298 *position
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
304 * dce_v11_0_hpd_sense - hpd sense callback.
306 * @adev: amdgpu_device pointer
307 * @hpd: hpd (hotplug detect) pin
309 * Checks if a digital monitor is connected (evergreen+).
310 * Returns true if connected, false if not connected.
312 static bool dce_v11_0_hpd_sense(struct amdgpu_device
*adev
,
313 enum amdgpu_hpd_id hpd
)
316 bool connected
= false;
341 if (RREG32(mmDC_HPD_INT_STATUS
+ hpd_offsets
[idx
]) &
342 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
)
349 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
351 * @adev: amdgpu_device pointer
352 * @hpd: hpd (hotplug detect) pin
354 * Set the polarity of the hpd pin (evergreen+).
356 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device
*adev
,
357 enum amdgpu_hpd_id hpd
)
360 bool connected
= dce_v11_0_hpd_sense(adev
, hpd
);
386 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[idx
]);
388 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 0);
390 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 1);
391 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[idx
], tmp
);
395 * dce_v11_0_hpd_init - hpd setup callback.
397 * @adev: amdgpu_device pointer
399 * Setup the hpd pins used by the card (evergreen+).
400 * Enable the pin, set the polarity, and enable the hpd interrupts.
402 static void dce_v11_0_hpd_init(struct amdgpu_device
*adev
)
404 struct drm_device
*dev
= adev
->ddev
;
405 struct drm_connector
*connector
;
409 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
410 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
412 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
413 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
414 /* don't try to enable hpd on eDP or LVDS avoid breaking the
415 * aux dp channel on imac and help (but not completely fix)
416 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
417 * also avoid interrupt storms during dpms.
422 switch (amdgpu_connector
->hpd
.hpd
) {
445 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
]);
446 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 1);
447 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
], tmp
);
449 tmp
= RREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[idx
]);
450 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
451 DC_HPD_CONNECT_INT_DELAY
,
452 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS
);
453 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
454 DC_HPD_DISCONNECT_INT_DELAY
,
455 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS
);
456 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[idx
], tmp
);
458 dce_v11_0_hpd_set_polarity(adev
, amdgpu_connector
->hpd
.hpd
);
459 amdgpu_irq_get(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
464 * dce_v11_0_hpd_fini - hpd tear down callback.
466 * @adev: amdgpu_device pointer
468 * Tear down the hpd pins used by the card (evergreen+).
469 * Disable the hpd interrupts.
471 static void dce_v11_0_hpd_fini(struct amdgpu_device
*adev
)
473 struct drm_device
*dev
= adev
->ddev
;
474 struct drm_connector
*connector
;
478 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
479 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
481 switch (amdgpu_connector
->hpd
.hpd
) {
504 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
]);
505 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 0);
506 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
], tmp
);
508 amdgpu_irq_put(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
512 static u32
dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device
*adev
)
514 return mmDC_GPIO_HPD_A
;
517 static bool dce_v11_0_is_display_hung(struct amdgpu_device
*adev
)
523 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
524 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
525 if (REG_GET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
)) {
526 crtc_status
[i
] = RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
527 crtc_hung
|= (1 << i
);
531 for (j
= 0; j
< 10; j
++) {
532 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
533 if (crtc_hung
& (1 << i
)) {
534 tmp
= RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
535 if (tmp
!= crtc_status
[i
])
536 crtc_hung
&= ~(1 << i
);
547 static void dce_v11_0_stop_mc_access(struct amdgpu_device
*adev
,
548 struct amdgpu_mode_mc_save
*save
)
550 u32 crtc_enabled
, tmp
;
553 save
->vga_render_control
= RREG32(mmVGA_RENDER_CONTROL
);
554 save
->vga_hdp_control
= RREG32(mmVGA_HDP_CONTROL
);
556 /* disable VGA render */
557 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
558 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
559 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
561 /* blank the display controllers */
562 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
563 crtc_enabled
= REG_GET_FIELD(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]),
564 CRTC_CONTROL
, CRTC_MASTER_EN
);
570 save
->crtc_enabled
[i
] = true;
571 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
572 if (REG_GET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
) == 0) {
573 amdgpu_display_vblank_wait(adev
, i
);
574 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
575 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 1);
576 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
577 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
579 /* wait for the next frame */
580 frame_count
= amdgpu_display_vblank_get_counter(adev
, i
);
581 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
582 if (amdgpu_display_vblank_get_counter(adev
, i
) != frame_count
)
586 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
587 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
) == 0) {
588 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 1);
589 WREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
591 tmp
= RREG32(mmCRTC_MASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
592 if (REG_GET_FIELD(tmp
, CRTC_MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
) == 0) {
593 tmp
= REG_SET_FIELD(tmp
, CRTC_MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
, 1);
594 WREG32(mmCRTC_MASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
597 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
598 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
599 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
600 tmp
= REG_SET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
, 0);
601 WREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
602 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
603 save
->crtc_enabled
[i
] = false;
607 save
->crtc_enabled
[i
] = false;
612 static void dce_v11_0_resume_mc_access(struct amdgpu_device
*adev
,
613 struct amdgpu_mode_mc_save
*save
)
615 u32 tmp
, frame_count
;
618 /* update crtc base addresses */
619 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
620 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
621 upper_32_bits(adev
->mc
.vram_start
));
622 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
623 upper_32_bits(adev
->mc
.vram_start
));
624 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
625 (u32
)adev
->mc
.vram_start
);
626 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
627 (u32
)adev
->mc
.vram_start
);
629 if (save
->crtc_enabled
[i
]) {
630 tmp
= RREG32(mmCRTC_MASTER_UPDATE_MODE
+ crtc_offsets
[i
]);
631 if (REG_GET_FIELD(tmp
, CRTC_MASTER_UPDATE_MODE
, MASTER_UPDATE_MODE
) != 3) {
632 tmp
= REG_SET_FIELD(tmp
, CRTC_MASTER_UPDATE_MODE
, MASTER_UPDATE_MODE
, 3);
633 WREG32(mmCRTC_MASTER_UPDATE_MODE
+ crtc_offsets
[i
], tmp
);
635 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
636 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
)) {
637 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 0);
638 WREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
640 tmp
= RREG32(mmCRTC_MASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
641 if (REG_GET_FIELD(tmp
, CRTC_MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
)) {
642 tmp
= REG_SET_FIELD(tmp
, CRTC_MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
, 0);
643 WREG32(mmCRTC_MASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
645 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
646 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
647 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_SURFACE_UPDATE_PENDING
) == 0)
651 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
652 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 0);
653 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
654 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
655 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
656 /* wait for the next frame */
657 frame_count
= amdgpu_display_vblank_get_counter(adev
, i
);
658 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
659 if (amdgpu_display_vblank_get_counter(adev
, i
) != frame_count
)
666 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(adev
->mc
.vram_start
));
667 WREG32(mmVGA_MEMORY_BASE_ADDRESS
, lower_32_bits(adev
->mc
.vram_start
));
669 /* Unlock vga access */
670 WREG32(mmVGA_HDP_CONTROL
, save
->vga_hdp_control
);
672 WREG32(mmVGA_RENDER_CONTROL
, save
->vga_render_control
);
675 static void dce_v11_0_set_vga_render_state(struct amdgpu_device
*adev
,
680 /* Lockout access through VGA aperture*/
681 tmp
= RREG32(mmVGA_HDP_CONTROL
);
683 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 0);
685 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 1);
686 WREG32(mmVGA_HDP_CONTROL
, tmp
);
688 /* disable VGA render */
689 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
691 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 1);
693 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
694 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
697 static void dce_v11_0_program_fmt(struct drm_encoder
*encoder
)
699 struct drm_device
*dev
= encoder
->dev
;
700 struct amdgpu_device
*adev
= dev
->dev_private
;
701 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
702 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
703 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
706 enum amdgpu_connector_dither dither
= AMDGPU_FMT_DITHER_DISABLE
;
709 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
710 bpc
= amdgpu_connector_get_monitor_bpc(connector
);
711 dither
= amdgpu_connector
->dither
;
714 /* LVDS/eDP FMT is set up by atom */
715 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD_SUPPORT
)
718 /* not needed for analog */
719 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
) ||
720 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
))
728 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
729 /* XXX sort out optimal dither settings */
730 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
731 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
732 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
733 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 0);
735 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
736 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 0);
740 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
741 /* XXX sort out optimal dither settings */
742 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
743 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
744 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
745 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
746 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 1);
748 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
749 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 1);
753 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
754 /* XXX sort out optimal dither settings */
755 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
756 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
757 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
758 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
759 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 2);
761 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
762 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 2);
770 WREG32(mmFMT_BIT_DEPTH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
774 /* display watermark setup */
776 * dce_v11_0_line_buffer_adjust - Set up the line buffer
778 * @adev: amdgpu_device pointer
779 * @amdgpu_crtc: the selected display controller
780 * @mode: the current display mode on the selected display
783 * Setup up the line buffer allocation for
784 * the selected display controller (CIK).
785 * Returns the line buffer size in pixels.
787 static u32
dce_v11_0_line_buffer_adjust(struct amdgpu_device
*adev
,
788 struct amdgpu_crtc
*amdgpu_crtc
,
789 struct drm_display_mode
*mode
)
791 u32 tmp
, buffer_alloc
, i
, mem_cfg
;
792 u32 pipe_offset
= amdgpu_crtc
->crtc_id
;
795 * There are 6 line buffers, one for each display controllers.
796 * There are 3 partitions per LB. Select the number of partitions
797 * to enable based on the display width. For display widths larger
798 * than 4096, you need use to use 2 display controllers and combine
799 * them using the stereo blender.
801 if (amdgpu_crtc
->base
.enabled
&& mode
) {
802 if (mode
->crtc_hdisplay
< 1920) {
805 } else if (mode
->crtc_hdisplay
< 2560) {
808 } else if (mode
->crtc_hdisplay
< 4096) {
810 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
812 DRM_DEBUG_KMS("Mode too big for LB!\n");
814 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
821 tmp
= RREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
);
822 tmp
= REG_SET_FIELD(tmp
, LB_MEMORY_CTRL
, LB_MEMORY_CONFIG
, mem_cfg
);
823 WREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
, tmp
);
825 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
826 tmp
= REG_SET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATED
, buffer_alloc
);
827 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
, tmp
);
829 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
830 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
831 if (REG_GET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATION_COMPLETED
))
836 if (amdgpu_crtc
->base
.enabled
&& mode
) {
848 /* controller not enabled, so no lb used */
853 * cik_get_number_of_dram_channels - get the number of dram channels
855 * @adev: amdgpu_device pointer
857 * Look up the number of video ram channels (CIK).
858 * Used for display watermark bandwidth calculations
859 * Returns the number of dram channels
861 static u32
cik_get_number_of_dram_channels(struct amdgpu_device
*adev
)
863 u32 tmp
= RREG32(mmMC_SHARED_CHMAP
);
865 switch (REG_GET_FIELD(tmp
, MC_SHARED_CHMAP
, NOOFCHAN
)) {
888 struct dce10_wm_params
{
889 u32 dram_channels
; /* number of dram channels */
890 u32 yclk
; /* bandwidth per dram data pin in kHz */
891 u32 sclk
; /* engine clock in kHz */
892 u32 disp_clk
; /* display clock in kHz */
893 u32 src_width
; /* viewport width */
894 u32 active_time
; /* active display time in ns */
895 u32 blank_time
; /* blank time in ns */
896 bool interlaced
; /* mode is interlaced */
897 fixed20_12 vsc
; /* vertical scale ratio */
898 u32 num_heads
; /* number of active crtcs */
899 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
900 u32 lb_size
; /* line buffer allocated to pipe */
901 u32 vtaps
; /* vertical scaler taps */
905 * dce_v11_0_dram_bandwidth - get the dram bandwidth
907 * @wm: watermark calculation data
909 * Calculate the raw dram bandwidth (CIK).
910 * Used for display watermark bandwidth calculations
911 * Returns the dram bandwidth in MBytes/s
913 static u32
dce_v11_0_dram_bandwidth(struct dce10_wm_params
*wm
)
915 /* Calculate raw DRAM Bandwidth */
916 fixed20_12 dram_efficiency
; /* 0.7 */
917 fixed20_12 yclk
, dram_channels
, bandwidth
;
920 a
.full
= dfixed_const(1000);
921 yclk
.full
= dfixed_const(wm
->yclk
);
922 yclk
.full
= dfixed_div(yclk
, a
);
923 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
924 a
.full
= dfixed_const(10);
925 dram_efficiency
.full
= dfixed_const(7);
926 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
927 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
928 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
930 return dfixed_trunc(bandwidth
);
934 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
936 * @wm: watermark calculation data
938 * Calculate the dram bandwidth used for display (CIK).
939 * Used for display watermark bandwidth calculations
940 * Returns the dram bandwidth for display in MBytes/s
942 static u32
dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
944 /* Calculate DRAM Bandwidth and the part allocated to display. */
945 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
946 fixed20_12 yclk
, dram_channels
, bandwidth
;
949 a
.full
= dfixed_const(1000);
950 yclk
.full
= dfixed_const(wm
->yclk
);
951 yclk
.full
= dfixed_div(yclk
, a
);
952 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
953 a
.full
= dfixed_const(10);
954 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
955 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
956 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
957 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
959 return dfixed_trunc(bandwidth
);
963 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
965 * @wm: watermark calculation data
967 * Calculate the data return bandwidth used for display (CIK).
968 * Used for display watermark bandwidth calculations
969 * Returns the data return bandwidth in MBytes/s
971 static u32
dce_v11_0_data_return_bandwidth(struct dce10_wm_params
*wm
)
973 /* Calculate the display Data return Bandwidth */
974 fixed20_12 return_efficiency
; /* 0.8 */
975 fixed20_12 sclk
, bandwidth
;
978 a
.full
= dfixed_const(1000);
979 sclk
.full
= dfixed_const(wm
->sclk
);
980 sclk
.full
= dfixed_div(sclk
, a
);
981 a
.full
= dfixed_const(10);
982 return_efficiency
.full
= dfixed_const(8);
983 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
984 a
.full
= dfixed_const(32);
985 bandwidth
.full
= dfixed_mul(a
, sclk
);
986 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
988 return dfixed_trunc(bandwidth
);
992 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
994 * @wm: watermark calculation data
996 * Calculate the dmif bandwidth used for display (CIK).
997 * Used for display watermark bandwidth calculations
998 * Returns the dmif bandwidth in MBytes/s
1000 static u32
dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params
*wm
)
1002 /* Calculate the DMIF Request Bandwidth */
1003 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
1004 fixed20_12 disp_clk
, bandwidth
;
1007 a
.full
= dfixed_const(1000);
1008 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
1009 disp_clk
.full
= dfixed_div(disp_clk
, a
);
1010 a
.full
= dfixed_const(32);
1011 b
.full
= dfixed_mul(a
, disp_clk
);
1013 a
.full
= dfixed_const(10);
1014 disp_clk_request_efficiency
.full
= dfixed_const(8);
1015 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
1017 bandwidth
.full
= dfixed_mul(b
, disp_clk_request_efficiency
);
1019 return dfixed_trunc(bandwidth
);
1023 * dce_v11_0_available_bandwidth - get the min available bandwidth
1025 * @wm: watermark calculation data
1027 * Calculate the min available bandwidth used for display (CIK).
1028 * Used for display watermark bandwidth calculations
1029 * Returns the min available bandwidth in MBytes/s
1031 static u32
dce_v11_0_available_bandwidth(struct dce10_wm_params
*wm
)
1033 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1034 u32 dram_bandwidth
= dce_v11_0_dram_bandwidth(wm
);
1035 u32 data_return_bandwidth
= dce_v11_0_data_return_bandwidth(wm
);
1036 u32 dmif_req_bandwidth
= dce_v11_0_dmif_request_bandwidth(wm
);
1038 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
1042 * dce_v11_0_average_bandwidth - get the average available bandwidth
1044 * @wm: watermark calculation data
1046 * Calculate the average available bandwidth used for display (CIK).
1047 * Used for display watermark bandwidth calculations
1048 * Returns the average available bandwidth in MBytes/s
1050 static u32
dce_v11_0_average_bandwidth(struct dce10_wm_params
*wm
)
1052 /* Calculate the display mode Average Bandwidth
1053 * DisplayMode should contain the source and destination dimensions,
1057 fixed20_12 line_time
;
1058 fixed20_12 src_width
;
1059 fixed20_12 bandwidth
;
1062 a
.full
= dfixed_const(1000);
1063 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
1064 line_time
.full
= dfixed_div(line_time
, a
);
1065 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
1066 src_width
.full
= dfixed_const(wm
->src_width
);
1067 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
1068 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
1069 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
1071 return dfixed_trunc(bandwidth
);
1075 * dce_v11_0_latency_watermark - get the latency watermark
1077 * @wm: watermark calculation data
1079 * Calculate the latency watermark (CIK).
1080 * Used for display watermark bandwidth calculations
1081 * Returns the latency watermark in ns
1083 static u32
dce_v11_0_latency_watermark(struct dce10_wm_params
*wm
)
1085 /* First calculate the latency in ns */
1086 u32 mc_latency
= 2000; /* 2000 ns. */
1087 u32 available_bandwidth
= dce_v11_0_available_bandwidth(wm
);
1088 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
1089 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
1090 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
1091 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
1092 (wm
->num_heads
* cursor_line_pair_return_time
);
1093 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
1094 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
1095 u32 tmp
, dmif_size
= 12288;
1098 if (wm
->num_heads
== 0)
1101 a
.full
= dfixed_const(2);
1102 b
.full
= dfixed_const(1);
1103 if ((wm
->vsc
.full
> a
.full
) ||
1104 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
1106 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
1107 max_src_lines_per_dst_line
= 4;
1109 max_src_lines_per_dst_line
= 2;
1111 a
.full
= dfixed_const(available_bandwidth
);
1112 b
.full
= dfixed_const(wm
->num_heads
);
1113 a
.full
= dfixed_div(a
, b
);
1115 b
.full
= dfixed_const(mc_latency
+ 512);
1116 c
.full
= dfixed_const(wm
->disp_clk
);
1117 b
.full
= dfixed_div(b
, c
);
1119 c
.full
= dfixed_const(dmif_size
);
1120 b
.full
= dfixed_div(c
, b
);
1122 tmp
= min(dfixed_trunc(a
), dfixed_trunc(b
));
1124 b
.full
= dfixed_const(1000);
1125 c
.full
= dfixed_const(wm
->disp_clk
);
1126 b
.full
= dfixed_div(c
, b
);
1127 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
1128 b
.full
= dfixed_mul(b
, c
);
1130 lb_fill_bw
= min(tmp
, dfixed_trunc(b
));
1132 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
1133 b
.full
= dfixed_const(1000);
1134 c
.full
= dfixed_const(lb_fill_bw
);
1135 b
.full
= dfixed_div(c
, b
);
1136 a
.full
= dfixed_div(a
, b
);
1137 line_fill_time
= dfixed_trunc(a
);
1139 if (line_fill_time
< wm
->active_time
)
1142 return latency
+ (line_fill_time
- wm
->active_time
);
1147 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1148 * average and available dram bandwidth
1150 * @wm: watermark calculation data
1152 * Check if the display average bandwidth fits in the display
1153 * dram bandwidth (CIK).
1154 * Used for display watermark bandwidth calculations
1155 * Returns true if the display fits, false if not.
1157 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
1159 if (dce_v11_0_average_bandwidth(wm
) <=
1160 (dce_v11_0_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
1167 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1168 * average and available bandwidth
1170 * @wm: watermark calculation data
1172 * Check if the display average bandwidth fits in the display
1173 * available bandwidth (CIK).
1174 * Used for display watermark bandwidth calculations
1175 * Returns true if the display fits, false if not.
1177 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params
*wm
)
1179 if (dce_v11_0_average_bandwidth(wm
) <=
1180 (dce_v11_0_available_bandwidth(wm
) / wm
->num_heads
))
1187 * dce_v11_0_check_latency_hiding - check latency hiding
1189 * @wm: watermark calculation data
1191 * Check latency hiding (CIK).
1192 * Used for display watermark bandwidth calculations
1193 * Returns true if the display fits, false if not.
1195 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params
*wm
)
1197 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
1198 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
1199 u32 latency_tolerant_lines
;
1203 a
.full
= dfixed_const(1);
1204 if (wm
->vsc
.full
> a
.full
)
1205 latency_tolerant_lines
= 1;
1207 if (lb_partitions
<= (wm
->vtaps
+ 1))
1208 latency_tolerant_lines
= 1;
1210 latency_tolerant_lines
= 2;
1213 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
1215 if (dce_v11_0_latency_watermark(wm
) <= latency_hiding
)
1222 * dce_v11_0_program_watermarks - program display watermarks
1224 * @adev: amdgpu_device pointer
1225 * @amdgpu_crtc: the selected display controller
1226 * @lb_size: line buffer size
1227 * @num_heads: number of display controllers in use
1229 * Calculate and program the display watermarks for the
1230 * selected display controller (CIK).
1232 static void dce_v11_0_program_watermarks(struct amdgpu_device
*adev
,
1233 struct amdgpu_crtc
*amdgpu_crtc
,
1234 u32 lb_size
, u32 num_heads
)
1236 struct drm_display_mode
*mode
= &amdgpu_crtc
->base
.mode
;
1237 struct dce10_wm_params wm_low
, wm_high
;
1240 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
1241 u32 tmp
, wm_mask
, lb_vblank_lead_lines
= 0;
1243 if (amdgpu_crtc
->base
.enabled
&& num_heads
&& mode
) {
1244 pixel_period
= 1000000 / (u32
)mode
->clock
;
1245 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
1247 /* watermark for high clocks */
1248 if (adev
->pm
.dpm_enabled
) {
1250 amdgpu_dpm_get_mclk(adev
, false) * 10;
1252 amdgpu_dpm_get_sclk(adev
, false) * 10;
1254 wm_high
.yclk
= adev
->pm
.current_mclk
* 10;
1255 wm_high
.sclk
= adev
->pm
.current_sclk
* 10;
1258 wm_high
.disp_clk
= mode
->clock
;
1259 wm_high
.src_width
= mode
->crtc_hdisplay
;
1260 wm_high
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1261 wm_high
.blank_time
= line_time
- wm_high
.active_time
;
1262 wm_high
.interlaced
= false;
1263 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1264 wm_high
.interlaced
= true;
1265 wm_high
.vsc
= amdgpu_crtc
->vsc
;
1267 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1269 wm_high
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1270 wm_high
.lb_size
= lb_size
;
1271 wm_high
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1272 wm_high
.num_heads
= num_heads
;
1274 /* set for high clocks */
1275 latency_watermark_a
= min(dce_v11_0_latency_watermark(&wm_high
), (u32
)65535);
1277 /* possibly force display priority to high */
1278 /* should really do this at mode validation time... */
1279 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high
) ||
1280 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high
) ||
1281 !dce_v11_0_check_latency_hiding(&wm_high
) ||
1282 (adev
->mode_info
.disp_priority
== 2)) {
1283 DRM_DEBUG_KMS("force priority to high\n");
1286 /* watermark for low clocks */
1287 if (adev
->pm
.dpm_enabled
) {
1289 amdgpu_dpm_get_mclk(adev
, true) * 10;
1291 amdgpu_dpm_get_sclk(adev
, true) * 10;
1293 wm_low
.yclk
= adev
->pm
.current_mclk
* 10;
1294 wm_low
.sclk
= adev
->pm
.current_sclk
* 10;
1297 wm_low
.disp_clk
= mode
->clock
;
1298 wm_low
.src_width
= mode
->crtc_hdisplay
;
1299 wm_low
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1300 wm_low
.blank_time
= line_time
- wm_low
.active_time
;
1301 wm_low
.interlaced
= false;
1302 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1303 wm_low
.interlaced
= true;
1304 wm_low
.vsc
= amdgpu_crtc
->vsc
;
1306 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1308 wm_low
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1309 wm_low
.lb_size
= lb_size
;
1310 wm_low
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1311 wm_low
.num_heads
= num_heads
;
1313 /* set for low clocks */
1314 latency_watermark_b
= min(dce_v11_0_latency_watermark(&wm_low
), (u32
)65535);
1316 /* possibly force display priority to high */
1317 /* should really do this at mode validation time... */
1318 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low
) ||
1319 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low
) ||
1320 !dce_v11_0_check_latency_hiding(&wm_low
) ||
1321 (adev
->mode_info
.disp_priority
== 2)) {
1322 DRM_DEBUG_KMS("force priority to high\n");
1324 lb_vblank_lead_lines
= DIV_ROUND_UP(lb_size
, mode
->crtc_hdisplay
);
1328 wm_mask
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1329 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 1);
1330 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1331 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1332 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_a
);
1333 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1334 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1336 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 2);
1337 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1338 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1339 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_b
);
1340 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1341 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1342 /* restore original selection */
1343 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, wm_mask
);
1345 /* save values for DPM */
1346 amdgpu_crtc
->line_time
= line_time
;
1347 amdgpu_crtc
->wm_high
= latency_watermark_a
;
1348 amdgpu_crtc
->wm_low
= latency_watermark_b
;
1349 /* Save number of lines the linebuffer leads before the scanout */
1350 amdgpu_crtc
->lb_vblank_lead_lines
= lb_vblank_lead_lines
;
1354 * dce_v11_0_bandwidth_update - program display watermarks
1356 * @adev: amdgpu_device pointer
1358 * Calculate and program the display watermarks and line
1359 * buffer allocation (CIK).
1361 static void dce_v11_0_bandwidth_update(struct amdgpu_device
*adev
)
1363 struct drm_display_mode
*mode
= NULL
;
1364 u32 num_heads
= 0, lb_size
;
1367 amdgpu_update_display_priority(adev
);
1369 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1370 if (adev
->mode_info
.crtcs
[i
]->base
.enabled
)
1373 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1374 mode
= &adev
->mode_info
.crtcs
[i
]->base
.mode
;
1375 lb_size
= dce_v11_0_line_buffer_adjust(adev
, adev
->mode_info
.crtcs
[i
], mode
);
1376 dce_v11_0_program_watermarks(adev
, adev
->mode_info
.crtcs
[i
],
1377 lb_size
, num_heads
);
1381 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device
*adev
)
1386 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1387 offset
= adev
->mode_info
.audio
.pin
[i
].offset
;
1388 tmp
= RREG32_AUDIO_ENDPT(offset
,
1389 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
);
1391 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
) >>
1392 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
) == 1)
1393 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1395 adev
->mode_info
.audio
.pin
[i
].connected
= true;
1399 static struct amdgpu_audio_pin
*dce_v11_0_audio_get_pin(struct amdgpu_device
*adev
)
1403 dce_v11_0_audio_get_connected_pins(adev
);
1405 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1406 if (adev
->mode_info
.audio
.pin
[i
].connected
)
1407 return &adev
->mode_info
.audio
.pin
[i
];
1409 DRM_ERROR("No connected audio pins found!\n");
1413 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder
*encoder
)
1415 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1416 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1417 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1420 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1423 tmp
= RREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
);
1424 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_SRC_CONTROL
, AFMT_AUDIO_SRC_SELECT
, dig
->afmt
->pin
->id
);
1425 WREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
, tmp
);
1428 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder
*encoder
,
1429 struct drm_display_mode
*mode
)
1431 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1432 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1433 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1434 struct drm_connector
*connector
;
1435 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1439 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1442 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1443 if (connector
->encoder
== encoder
) {
1444 amdgpu_connector
= to_amdgpu_connector(connector
);
1449 if (!amdgpu_connector
) {
1450 DRM_ERROR("Couldn't find encoder's connector\n");
1454 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1456 if (connector
->latency_present
[interlace
]) {
1457 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1458 VIDEO_LIPSYNC
, connector
->video_latency
[interlace
]);
1459 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1460 AUDIO_LIPSYNC
, connector
->audio_latency
[interlace
]);
1462 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1464 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1467 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1468 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
, tmp
);
1471 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder
*encoder
)
1473 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1474 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1475 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1476 struct drm_connector
*connector
;
1477 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1482 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1485 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1486 if (connector
->encoder
== encoder
) {
1487 amdgpu_connector
= to_amdgpu_connector(connector
);
1492 if (!amdgpu_connector
) {
1493 DRM_ERROR("Couldn't find encoder's connector\n");
1497 sad_count
= drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector
), &sadb
);
1498 if (sad_count
< 0) {
1499 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count
);
1503 /* program the speaker allocation */
1504 tmp
= RREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1505 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
);
1506 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1509 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1510 HDMI_CONNECTION
, 1);
1512 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1513 SPEAKER_ALLOCATION
, sadb
[0]);
1515 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1516 SPEAKER_ALLOCATION
, 5); /* stereo */
1517 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1518 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
, tmp
);
1523 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder
*encoder
)
1525 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1526 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1527 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1528 struct drm_connector
*connector
;
1529 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1530 struct cea_sad
*sads
;
1533 static const u16 eld_reg_to_type
[][2] = {
1534 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
1535 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
1536 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
1537 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
1538 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
1539 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
1540 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
1541 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
1542 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
1543 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
1544 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
1545 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
1548 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1551 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1552 if (connector
->encoder
== encoder
) {
1553 amdgpu_connector
= to_amdgpu_connector(connector
);
1558 if (!amdgpu_connector
) {
1559 DRM_ERROR("Couldn't find encoder's connector\n");
1563 sad_count
= drm_edid_to_sad(amdgpu_connector_edid(connector
), &sads
);
1564 if (sad_count
<= 0) {
1565 DRM_ERROR("Couldn't read SADs: %d\n", sad_count
);
1570 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
1572 u8 stereo_freqs
= 0;
1573 int max_channels
= -1;
1576 for (j
= 0; j
< sad_count
; j
++) {
1577 struct cea_sad
*sad
= &sads
[j
];
1579 if (sad
->format
== eld_reg_to_type
[i
][1]) {
1580 if (sad
->channels
> max_channels
) {
1581 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1582 MAX_CHANNELS
, sad
->channels
);
1583 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1584 DESCRIPTOR_BYTE_2
, sad
->byte2
);
1585 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1586 SUPPORTED_FREQUENCIES
, sad
->freq
);
1587 max_channels
= sad
->channels
;
1590 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
1591 stereo_freqs
|= sad
->freq
;
1597 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1598 SUPPORTED_FREQUENCIES_STEREO
, stereo_freqs
);
1599 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
, eld_reg_to_type
[i
][0], tmp
);
1605 static void dce_v11_0_audio_enable(struct amdgpu_device
*adev
,
1606 struct amdgpu_audio_pin
*pin
,
1612 WREG32_AUDIO_ENDPT(pin
->offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
,
1613 enable
? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
: 0);
1616 static const u32 pin_offsets
[] =
1618 AUD0_REGISTER_OFFSET
,
1619 AUD1_REGISTER_OFFSET
,
1620 AUD2_REGISTER_OFFSET
,
1621 AUD3_REGISTER_OFFSET
,
1622 AUD4_REGISTER_OFFSET
,
1623 AUD5_REGISTER_OFFSET
,
1624 AUD6_REGISTER_OFFSET
,
1627 static int dce_v11_0_audio_init(struct amdgpu_device
*adev
)
1634 adev
->mode_info
.audio
.enabled
= true;
1636 adev
->mode_info
.audio
.num_pins
= 7;
1638 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1639 adev
->mode_info
.audio
.pin
[i
].channels
= -1;
1640 adev
->mode_info
.audio
.pin
[i
].rate
= -1;
1641 adev
->mode_info
.audio
.pin
[i
].bits_per_sample
= -1;
1642 adev
->mode_info
.audio
.pin
[i
].status_bits
= 0;
1643 adev
->mode_info
.audio
.pin
[i
].category_code
= 0;
1644 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1645 adev
->mode_info
.audio
.pin
[i
].offset
= pin_offsets
[i
];
1646 adev
->mode_info
.audio
.pin
[i
].id
= i
;
1647 /* disable audio. it will be set up later */
1648 /* XXX remove once we switch to ip funcs */
1649 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1655 static void dce_v11_0_audio_fini(struct amdgpu_device
*adev
)
1659 if (!adev
->mode_info
.audio
.enabled
)
1662 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++)
1663 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1665 adev
->mode_info
.audio
.enabled
= false;
1669 * update the N and CTS parameters for a given pixel clock rate
1671 static void dce_v11_0_afmt_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
1673 struct drm_device
*dev
= encoder
->dev
;
1674 struct amdgpu_device
*adev
= dev
->dev_private
;
1675 struct amdgpu_afmt_acr acr
= amdgpu_afmt_acr(clock
);
1676 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1677 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1680 tmp
= RREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
);
1681 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_0
, HDMI_ACR_CTS_32
, acr
.cts_32khz
);
1682 WREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
, tmp
);
1683 tmp
= RREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
);
1684 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_1
, HDMI_ACR_N_32
, acr
.n_32khz
);
1685 WREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
, tmp
);
1687 tmp
= RREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
);
1688 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_0
, HDMI_ACR_CTS_44
, acr
.cts_44_1khz
);
1689 WREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
, tmp
);
1690 tmp
= RREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
);
1691 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_1
, HDMI_ACR_N_44
, acr
.n_44_1khz
);
1692 WREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
, tmp
);
1694 tmp
= RREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
);
1695 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_0
, HDMI_ACR_CTS_48
, acr
.cts_48khz
);
1696 WREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
, tmp
);
1697 tmp
= RREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
);
1698 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_1
, HDMI_ACR_N_48
, acr
.n_48khz
);
1699 WREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
, tmp
);
1704 * build a HDMI Video Info Frame
1706 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder
*encoder
,
1707 void *buffer
, size_t size
)
1709 struct drm_device
*dev
= encoder
->dev
;
1710 struct amdgpu_device
*adev
= dev
->dev_private
;
1711 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1712 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1713 uint8_t *frame
= buffer
+ 3;
1714 uint8_t *header
= buffer
;
1716 WREG32(mmAFMT_AVI_INFO0
+ dig
->afmt
->offset
,
1717 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
1718 WREG32(mmAFMT_AVI_INFO1
+ dig
->afmt
->offset
,
1719 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
1720 WREG32(mmAFMT_AVI_INFO2
+ dig
->afmt
->offset
,
1721 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
1722 WREG32(mmAFMT_AVI_INFO3
+ dig
->afmt
->offset
,
1723 frame
[0xC] | (frame
[0xD] << 8) | (header
[1] << 24));
1726 static void dce_v11_0_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
)
1728 struct drm_device
*dev
= encoder
->dev
;
1729 struct amdgpu_device
*adev
= dev
->dev_private
;
1730 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1731 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1732 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1733 u32 dto_phase
= 24 * 1000;
1734 u32 dto_modulo
= clock
;
1737 if (!dig
|| !dig
->afmt
)
1740 /* XXX two dtos; generally use dto0 for hdmi */
1741 /* Express [24MHz / target pixel clock] as an exact rational
1742 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1743 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1745 tmp
= RREG32(mmDCCG_AUDIO_DTO_SOURCE
);
1746 tmp
= REG_SET_FIELD(tmp
, DCCG_AUDIO_DTO_SOURCE
, DCCG_AUDIO_DTO0_SOURCE_SEL
,
1747 amdgpu_crtc
->crtc_id
);
1748 WREG32(mmDCCG_AUDIO_DTO_SOURCE
, tmp
);
1749 WREG32(mmDCCG_AUDIO_DTO0_PHASE
, dto_phase
);
1750 WREG32(mmDCCG_AUDIO_DTO0_MODULE
, dto_modulo
);
1754 * update the info frames with the data from the current display mode
1756 static void dce_v11_0_afmt_setmode(struct drm_encoder
*encoder
,
1757 struct drm_display_mode
*mode
)
1759 struct drm_device
*dev
= encoder
->dev
;
1760 struct amdgpu_device
*adev
= dev
->dev_private
;
1761 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1762 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1763 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1764 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AVI_INFOFRAME_SIZE
];
1765 struct hdmi_avi_infoframe frame
;
1770 if (!dig
|| !dig
->afmt
)
1773 /* Silent, r600_hdmi_enable will raise WARN for us */
1774 if (!dig
->afmt
->enabled
)
1777 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1778 if (encoder
->crtc
) {
1779 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1780 bpc
= amdgpu_crtc
->bpc
;
1783 /* disable audio prior to setting up hw */
1784 dig
->afmt
->pin
= dce_v11_0_audio_get_pin(adev
);
1785 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1787 dce_v11_0_audio_set_dto(encoder
, mode
->clock
);
1789 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1790 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1);
1791 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
); /* send null packets when required */
1793 WREG32(mmAFMT_AUDIO_CRC_CONTROL
+ dig
->afmt
->offset
, 0x1000);
1795 tmp
= RREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
);
1802 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 0);
1803 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 0);
1804 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1805 connector
->name
, bpc
);
1808 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1809 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 1);
1810 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1814 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1815 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 2);
1816 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1820 WREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
, tmp
);
1822 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1823 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1); /* send null packets when required */
1824 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_SEND
, 1); /* send general control packets */
1825 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_CONT
, 1); /* send general control packets every frame */
1826 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1828 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1829 /* enable audio info frames (frames won't be set until audio is enabled) */
1830 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_SEND
, 1);
1831 /* required for audio info values to be updated */
1832 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_CONT
, 1);
1833 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1835 tmp
= RREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1836 /* required for audio info values to be updated */
1837 tmp
= REG_SET_FIELD(tmp
, AFMT_INFOFRAME_CONTROL0
, AFMT_AUDIO_INFO_UPDATE
, 1);
1838 WREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1840 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1841 /* anything other than 0 */
1842 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AUDIO_INFO_LINE
, 2);
1843 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1845 WREG32(mmHDMI_GC
+ dig
->afmt
->offset
, 0); /* unset HDMI_GC_AVMUTE */
1847 tmp
= RREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1848 /* set the default audio delay */
1849 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_DELAY_EN
, 1);
1850 /* should be suffient for all audio modes and small enough for all hblanks */
1851 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_PACKETS_PER_LINE
, 3);
1852 WREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1854 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1855 /* allow 60958 channel status fields to be updated */
1856 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_60958_CS_UPDATE
, 1);
1857 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1859 tmp
= RREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
);
1861 /* clear SW CTS value */
1862 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 0);
1864 /* select SW CTS value */
1865 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 1);
1866 /* allow hw to sent ACR packets when required */
1867 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_AUTO_SEND
, 1);
1868 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1870 dce_v11_0_afmt_update_ACR(encoder
, mode
->clock
);
1872 tmp
= RREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
);
1873 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_0
, AFMT_60958_CS_CHANNEL_NUMBER_L
, 1);
1874 WREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
, tmp
);
1876 tmp
= RREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
);
1877 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_1
, AFMT_60958_CS_CHANNEL_NUMBER_R
, 2);
1878 WREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
, tmp
);
1880 tmp
= RREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
);
1881 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_2
, 3);
1882 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_3
, 4);
1883 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_4
, 5);
1884 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_5
, 6);
1885 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_6
, 7);
1886 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_7
, 8);
1887 WREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
, tmp
);
1889 dce_v11_0_audio_write_speaker_allocation(encoder
);
1891 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2
+ dig
->afmt
->offset
,
1892 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
));
1894 dce_v11_0_afmt_audio_select_pin(encoder
);
1895 dce_v11_0_audio_write_sad_regs(encoder
);
1896 dce_v11_0_audio_write_latency_fields(encoder
, mode
);
1898 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, mode
);
1900 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err
);
1904 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1906 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err
);
1910 dce_v11_0_afmt_update_avi_infoframe(encoder
, buffer
, sizeof(buffer
));
1912 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1913 /* enable AVI info frames */
1914 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_SEND
, 1);
1915 /* required for audio info values to be updated */
1916 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_CONT
, 1);
1917 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1919 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1920 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AVI_INFO_LINE
, 2);
1921 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1923 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1924 /* send audio packets */
1925 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_AUDIO_SAMPLE_SEND
, 1);
1926 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1928 WREG32(mmAFMT_RAMP_CONTROL0
+ dig
->afmt
->offset
, 0x00FFFFFF);
1929 WREG32(mmAFMT_RAMP_CONTROL1
+ dig
->afmt
->offset
, 0x007FFFFF);
1930 WREG32(mmAFMT_RAMP_CONTROL2
+ dig
->afmt
->offset
, 0x00000001);
1931 WREG32(mmAFMT_RAMP_CONTROL3
+ dig
->afmt
->offset
, 0x00000001);
1933 /* enable audio after to setting up hw */
1934 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, true);
1937 static void dce_v11_0_afmt_enable(struct drm_encoder
*encoder
, bool enable
)
1939 struct drm_device
*dev
= encoder
->dev
;
1940 struct amdgpu_device
*adev
= dev
->dev_private
;
1941 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1942 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1944 if (!dig
|| !dig
->afmt
)
1947 /* Silent, r600_hdmi_enable will raise WARN for us */
1948 if (enable
&& dig
->afmt
->enabled
)
1950 if (!enable
&& !dig
->afmt
->enabled
)
1953 if (!enable
&& dig
->afmt
->pin
) {
1954 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1955 dig
->afmt
->pin
= NULL
;
1958 dig
->afmt
->enabled
= enable
;
1960 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1961 enable
? "En" : "Dis", dig
->afmt
->offset
, amdgpu_encoder
->encoder_id
);
1964 static void dce_v11_0_afmt_init(struct amdgpu_device
*adev
)
1968 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++)
1969 adev
->mode_info
.afmt
[i
] = NULL
;
1971 /* DCE11 has audio blocks tied to DIG encoders */
1972 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1973 adev
->mode_info
.afmt
[i
] = kzalloc(sizeof(struct amdgpu_afmt
), GFP_KERNEL
);
1974 if (adev
->mode_info
.afmt
[i
]) {
1975 adev
->mode_info
.afmt
[i
]->offset
= dig_offsets
[i
];
1976 adev
->mode_info
.afmt
[i
]->id
= i
;
1981 static void dce_v11_0_afmt_fini(struct amdgpu_device
*adev
)
1985 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1986 kfree(adev
->mode_info
.afmt
[i
]);
1987 adev
->mode_info
.afmt
[i
] = NULL
;
1991 static const u32 vga_control_regs
[6] =
2001 static void dce_v11_0_vga_enable(struct drm_crtc
*crtc
, bool enable
)
2003 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2004 struct drm_device
*dev
= crtc
->dev
;
2005 struct amdgpu_device
*adev
= dev
->dev_private
;
2008 vga_control
= RREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
]) & ~1;
2010 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
| 1);
2012 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
);
2015 static void dce_v11_0_grph_enable(struct drm_crtc
*crtc
, bool enable
)
2017 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2018 struct drm_device
*dev
= crtc
->dev
;
2019 struct amdgpu_device
*adev
= dev
->dev_private
;
2022 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 1);
2024 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 0);
2027 static int dce_v11_0_crtc_do_set_base(struct drm_crtc
*crtc
,
2028 struct drm_framebuffer
*fb
,
2029 int x
, int y
, int atomic
)
2031 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2032 struct drm_device
*dev
= crtc
->dev
;
2033 struct amdgpu_device
*adev
= dev
->dev_private
;
2034 struct amdgpu_framebuffer
*amdgpu_fb
;
2035 struct drm_framebuffer
*target_fb
;
2036 struct drm_gem_object
*obj
;
2037 struct amdgpu_bo
*rbo
;
2038 uint64_t fb_location
, tiling_flags
;
2039 uint32_t fb_format
, fb_pitch_pixels
;
2040 u32 fb_swap
= REG_SET_FIELD(0, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
, ENDIAN_NONE
);
2042 u32 tmp
, viewport_w
, viewport_h
;
2044 bool bypass_lut
= false;
2047 if (!atomic
&& !crtc
->primary
->fb
) {
2048 DRM_DEBUG_KMS("No FB bound\n");
2053 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2057 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2058 target_fb
= crtc
->primary
->fb
;
2061 /* If atomic, assume fb object is pinned & idle & fenced and
2062 * just update base pointers
2064 obj
= amdgpu_fb
->obj
;
2065 rbo
= gem_to_amdgpu_bo(obj
);
2066 r
= amdgpu_bo_reserve(rbo
, false);
2067 if (unlikely(r
!= 0))
2071 fb_location
= amdgpu_bo_gpu_offset(rbo
);
2073 r
= amdgpu_bo_pin(rbo
, AMDGPU_GEM_DOMAIN_VRAM
, &fb_location
);
2074 if (unlikely(r
!= 0)) {
2075 amdgpu_bo_unreserve(rbo
);
2080 amdgpu_bo_get_tiling_flags(rbo
, &tiling_flags
);
2081 amdgpu_bo_unreserve(rbo
);
2083 pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
2085 switch (target_fb
->pixel_format
) {
2087 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 0);
2088 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2090 case DRM_FORMAT_XRGB4444
:
2091 case DRM_FORMAT_ARGB4444
:
2092 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2093 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 2);
2095 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2099 case DRM_FORMAT_XRGB1555
:
2100 case DRM_FORMAT_ARGB1555
:
2101 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2102 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2104 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2108 case DRM_FORMAT_BGRX5551
:
2109 case DRM_FORMAT_BGRA5551
:
2110 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2111 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 5);
2113 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2117 case DRM_FORMAT_RGB565
:
2118 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2119 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
2121 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2125 case DRM_FORMAT_XRGB8888
:
2126 case DRM_FORMAT_ARGB8888
:
2127 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2128 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2130 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2134 case DRM_FORMAT_XRGB2101010
:
2135 case DRM_FORMAT_ARGB2101010
:
2136 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2137 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
2139 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2142 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2145 case DRM_FORMAT_BGRX1010102
:
2146 case DRM_FORMAT_BGRA1010102
:
2147 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2148 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 4);
2150 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2153 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2157 DRM_ERROR("Unsupported screen format %s\n",
2158 drm_get_format_name(target_fb
->pixel_format
));
2162 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_2D_TILED_THIN1
) {
2163 unsigned bankw
, bankh
, mtaspect
, tile_split
, num_banks
;
2165 bankw
= AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
2166 bankh
= AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
2167 mtaspect
= AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
2168 tile_split
= AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
);
2169 num_banks
= AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
2171 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_NUM_BANKS
, num_banks
);
2172 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2173 ARRAY_2D_TILED_THIN1
);
2174 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_TILE_SPLIT
,
2176 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_WIDTH
, bankw
);
2177 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_HEIGHT
, bankh
);
2178 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MACRO_TILE_ASPECT
,
2180 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MICRO_TILE_MODE
,
2181 ADDR_SURF_MICRO_TILING_DISPLAY
);
2182 } else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_1D_TILED_THIN1
) {
2183 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2184 ARRAY_1D_TILED_THIN1
);
2187 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_PIPE_CONFIG
,
2190 dce_v11_0_vga_enable(crtc
, false);
2192 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2193 upper_32_bits(fb_location
));
2194 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2195 upper_32_bits(fb_location
));
2196 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2197 (u32
)fb_location
& GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
);
2198 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2199 (u32
) fb_location
& GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
);
2200 WREG32(mmGRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, fb_format
);
2201 WREG32(mmGRPH_SWAP_CNTL
+ amdgpu_crtc
->crtc_offset
, fb_swap
);
2204 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2205 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2206 * retain the full precision throughout the pipeline.
2208 tmp
= RREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
);
2210 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 1);
2212 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 0);
2213 WREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
, tmp
);
2216 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2218 WREG32(mmGRPH_SURFACE_OFFSET_X
+ amdgpu_crtc
->crtc_offset
, 0);
2219 WREG32(mmGRPH_SURFACE_OFFSET_Y
+ amdgpu_crtc
->crtc_offset
, 0);
2220 WREG32(mmGRPH_X_START
+ amdgpu_crtc
->crtc_offset
, 0);
2221 WREG32(mmGRPH_Y_START
+ amdgpu_crtc
->crtc_offset
, 0);
2222 WREG32(mmGRPH_X_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->width
);
2223 WREG32(mmGRPH_Y_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->height
);
2225 fb_pitch_pixels
= target_fb
->pitches
[0] / (target_fb
->bits_per_pixel
/ 8);
2226 WREG32(mmGRPH_PITCH
+ amdgpu_crtc
->crtc_offset
, fb_pitch_pixels
);
2228 dce_v11_0_grph_enable(crtc
, true);
2230 WREG32(mmLB_DESKTOP_HEIGHT
+ amdgpu_crtc
->crtc_offset
,
2235 WREG32(mmVIEWPORT_START
+ amdgpu_crtc
->crtc_offset
,
2237 viewport_w
= crtc
->mode
.hdisplay
;
2238 viewport_h
= (crtc
->mode
.vdisplay
+ 1) & ~1;
2239 WREG32(mmVIEWPORT_SIZE
+ amdgpu_crtc
->crtc_offset
,
2240 (viewport_w
<< 16) | viewport_h
);
2242 /* pageflip setup */
2243 /* make sure flip is at vb rather than hb */
2244 tmp
= RREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2245 tmp
= REG_SET_FIELD(tmp
, GRPH_FLIP_CONTROL
,
2246 GRPH_SURFACE_UPDATE_H_RETRACE_EN
, 0);
2247 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2249 /* set pageflip to happen only at start of vblank interval (front porch) */
2250 WREG32(mmCRTC_MASTER_UPDATE_MODE
+ amdgpu_crtc
->crtc_offset
, 3);
2252 if (!atomic
&& fb
&& fb
!= crtc
->primary
->fb
) {
2253 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2254 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2255 r
= amdgpu_bo_reserve(rbo
, false);
2256 if (unlikely(r
!= 0))
2258 amdgpu_bo_unpin(rbo
);
2259 amdgpu_bo_unreserve(rbo
);
2262 /* Bytes per pixel may have changed */
2263 dce_v11_0_bandwidth_update(adev
);
2268 static void dce_v11_0_set_interleave(struct drm_crtc
*crtc
,
2269 struct drm_display_mode
*mode
)
2271 struct drm_device
*dev
= crtc
->dev
;
2272 struct amdgpu_device
*adev
= dev
->dev_private
;
2273 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2276 tmp
= RREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
);
2277 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2278 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 1);
2280 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 0);
2281 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
, tmp
);
2284 static void dce_v11_0_crtc_load_lut(struct drm_crtc
*crtc
)
2286 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2287 struct drm_device
*dev
= crtc
->dev
;
2288 struct amdgpu_device
*adev
= dev
->dev_private
;
2292 DRM_DEBUG_KMS("%d\n", amdgpu_crtc
->crtc_id
);
2294 tmp
= RREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2295 tmp
= REG_SET_FIELD(tmp
, INPUT_CSC_CONTROL
, INPUT_CSC_GRPH_MODE
, 0);
2296 WREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2298 tmp
= RREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2299 tmp
= REG_SET_FIELD(tmp
, PRESCALE_GRPH_CONTROL
, GRPH_PRESCALE_BYPASS
, 1);
2300 WREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2302 tmp
= RREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2303 tmp
= REG_SET_FIELD(tmp
, INPUT_GAMMA_CONTROL
, GRPH_INPUT_GAMMA_MODE
, 0);
2304 WREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2306 WREG32(mmDC_LUT_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2308 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0);
2309 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0);
2310 WREG32(mmDC_LUT_BLACK_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0);
2312 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2313 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2314 WREG32(mmDC_LUT_WHITE_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2316 WREG32(mmDC_LUT_RW_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2317 WREG32(mmDC_LUT_WRITE_EN_MASK
+ amdgpu_crtc
->crtc_offset
, 0x00000007);
2319 WREG32(mmDC_LUT_RW_INDEX
+ amdgpu_crtc
->crtc_offset
, 0);
2320 for (i
= 0; i
< 256; i
++) {
2321 WREG32(mmDC_LUT_30_COLOR
+ amdgpu_crtc
->crtc_offset
,
2322 (amdgpu_crtc
->lut_r
[i
] << 20) |
2323 (amdgpu_crtc
->lut_g
[i
] << 10) |
2324 (amdgpu_crtc
->lut_b
[i
] << 0));
2327 tmp
= RREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2328 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, GRPH_DEGAMMA_MODE
, 0);
2329 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, CURSOR_DEGAMMA_MODE
, 0);
2330 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, CURSOR2_DEGAMMA_MODE
, 0);
2331 WREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2333 tmp
= RREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2334 tmp
= REG_SET_FIELD(tmp
, GAMUT_REMAP_CONTROL
, GRPH_GAMUT_REMAP_MODE
, 0);
2335 WREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2337 tmp
= RREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2338 tmp
= REG_SET_FIELD(tmp
, REGAMMA_CONTROL
, GRPH_REGAMMA_MODE
, 0);
2339 WREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2341 tmp
= RREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2342 tmp
= REG_SET_FIELD(tmp
, OUTPUT_CSC_CONTROL
, OUTPUT_CSC_GRPH_MODE
, 0);
2343 WREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2345 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2346 WREG32(mmDENORM_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2347 /* XXX this only needs to be programmed once per crtc at startup,
2348 * not sure where the best place for it is
2350 tmp
= RREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2351 tmp
= REG_SET_FIELD(tmp
, ALPHA_CONTROL
, CURSOR_ALPHA_BLND_ENA
, 1);
2352 WREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2355 static int dce_v11_0_pick_dig_encoder(struct drm_encoder
*encoder
)
2357 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
2358 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2360 switch (amdgpu_encoder
->encoder_id
) {
2361 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2367 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2373 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2379 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2383 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2389 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2393 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2394 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2395 * monitors a dedicated PPLL must be used. If a particular board has
2396 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2397 * as there is no need to program the PLL itself. If we are not able to
2398 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2399 * avoid messing up an existing monitor.
2401 * Asic specific PLL information
2405 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2407 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2410 static u32
dce_v11_0_pick_pll(struct drm_crtc
*crtc
)
2412 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2413 struct drm_device
*dev
= crtc
->dev
;
2414 struct amdgpu_device
*adev
= dev
->dev_private
;
2418 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
))) {
2419 if (adev
->clock
.dp_extclk
)
2420 /* skip PPLL programming if using ext clock */
2421 return ATOM_PPLL_INVALID
;
2423 /* use the same PPLL for all DP monitors */
2424 pll
= amdgpu_pll_get_shared_dp_ppll(crtc
);
2425 if (pll
!= ATOM_PPLL_INVALID
)
2429 /* use the same PPLL for all monitors with the same clock */
2430 pll
= amdgpu_pll_get_shared_nondp_ppll(crtc
);
2431 if (pll
!= ATOM_PPLL_INVALID
)
2435 /* XXX need to determine what plls are available on each DCE11 part */
2436 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2437 if (adev
->asic_type
== CHIP_CARRIZO
|| adev
->asic_type
== CHIP_STONEY
) {
2438 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2440 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2442 DRM_ERROR("unable to allocate a PPLL\n");
2443 return ATOM_PPLL_INVALID
;
2445 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2447 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2449 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2451 DRM_ERROR("unable to allocate a PPLL\n");
2452 return ATOM_PPLL_INVALID
;
2454 return ATOM_PPLL_INVALID
;
2457 static void dce_v11_0_lock_cursor(struct drm_crtc
*crtc
, bool lock
)
2459 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2460 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2463 cur_lock
= RREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
);
2465 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 1);
2467 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 0);
2468 WREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
, cur_lock
);
2471 static void dce_v11_0_hide_cursor(struct drm_crtc
*crtc
)
2473 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2474 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2477 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2478 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 0);
2479 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2482 static void dce_v11_0_show_cursor(struct drm_crtc
*crtc
)
2484 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2485 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2488 WREG32(mmCUR_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2489 upper_32_bits(amdgpu_crtc
->cursor_addr
));
2490 WREG32(mmCUR_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2491 lower_32_bits(amdgpu_crtc
->cursor_addr
));
2493 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2494 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 1);
2495 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_MODE
, 2);
2496 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2499 static int dce_v11_0_cursor_move_locked(struct drm_crtc
*crtc
,
2502 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2503 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2504 int xorigin
= 0, yorigin
= 0;
2506 /* avivo cursor are offset into the total surface */
2509 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x
, y
, crtc
->x
, crtc
->y
);
2512 xorigin
= min(-x
, amdgpu_crtc
->max_cursor_width
- 1);
2516 yorigin
= min(-y
, amdgpu_crtc
->max_cursor_height
- 1);
2520 WREG32(mmCUR_POSITION
+ amdgpu_crtc
->crtc_offset
, (x
<< 16) | y
);
2521 WREG32(mmCUR_HOT_SPOT
+ amdgpu_crtc
->crtc_offset
, (xorigin
<< 16) | yorigin
);
2522 WREG32(mmCUR_SIZE
+ amdgpu_crtc
->crtc_offset
,
2523 ((amdgpu_crtc
->cursor_width
- 1) << 16) | (amdgpu_crtc
->cursor_height
- 1));
2525 amdgpu_crtc
->cursor_x
= x
;
2526 amdgpu_crtc
->cursor_y
= y
;
2531 static int dce_v11_0_crtc_cursor_move(struct drm_crtc
*crtc
,
2536 dce_v11_0_lock_cursor(crtc
, true);
2537 ret
= dce_v11_0_cursor_move_locked(crtc
, x
, y
);
2538 dce_v11_0_lock_cursor(crtc
, false);
2543 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc
*crtc
,
2544 struct drm_file
*file_priv
,
2551 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2552 struct drm_gem_object
*obj
;
2553 struct amdgpu_bo
*aobj
;
2557 /* turn off cursor */
2558 dce_v11_0_hide_cursor(crtc
);
2563 if ((width
> amdgpu_crtc
->max_cursor_width
) ||
2564 (height
> amdgpu_crtc
->max_cursor_height
)) {
2565 DRM_ERROR("bad cursor width or height %d x %d\n", width
, height
);
2569 obj
= drm_gem_object_lookup(crtc
->dev
, file_priv
, handle
);
2571 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle
, amdgpu_crtc
->crtc_id
);
2575 aobj
= gem_to_amdgpu_bo(obj
);
2576 ret
= amdgpu_bo_reserve(aobj
, false);
2578 drm_gem_object_unreference_unlocked(obj
);
2582 ret
= amdgpu_bo_pin(aobj
, AMDGPU_GEM_DOMAIN_VRAM
, &amdgpu_crtc
->cursor_addr
);
2583 amdgpu_bo_unreserve(aobj
);
2585 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret
);
2586 drm_gem_object_unreference_unlocked(obj
);
2590 amdgpu_crtc
->cursor_width
= width
;
2591 amdgpu_crtc
->cursor_height
= height
;
2593 dce_v11_0_lock_cursor(crtc
, true);
2595 if (hot_x
!= amdgpu_crtc
->cursor_hot_x
||
2596 hot_y
!= amdgpu_crtc
->cursor_hot_y
) {
2599 x
= amdgpu_crtc
->cursor_x
+ amdgpu_crtc
->cursor_hot_x
- hot_x
;
2600 y
= amdgpu_crtc
->cursor_y
+ amdgpu_crtc
->cursor_hot_y
- hot_y
;
2602 dce_v11_0_cursor_move_locked(crtc
, x
, y
);
2604 amdgpu_crtc
->cursor_hot_x
= hot_x
;
2605 amdgpu_crtc
->cursor_hot_y
= hot_y
;
2608 dce_v11_0_show_cursor(crtc
);
2609 dce_v11_0_lock_cursor(crtc
, false);
2612 if (amdgpu_crtc
->cursor_bo
) {
2613 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2614 ret
= amdgpu_bo_reserve(aobj
, false);
2615 if (likely(ret
== 0)) {
2616 amdgpu_bo_unpin(aobj
);
2617 amdgpu_bo_unreserve(aobj
);
2619 drm_gem_object_unreference_unlocked(amdgpu_crtc
->cursor_bo
);
2622 amdgpu_crtc
->cursor_bo
= obj
;
2626 static void dce_v11_0_cursor_reset(struct drm_crtc
*crtc
)
2628 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2630 if (amdgpu_crtc
->cursor_bo
) {
2631 dce_v11_0_lock_cursor(crtc
, true);
2633 dce_v11_0_cursor_move_locked(crtc
, amdgpu_crtc
->cursor_x
,
2634 amdgpu_crtc
->cursor_y
);
2636 dce_v11_0_show_cursor(crtc
);
2638 dce_v11_0_lock_cursor(crtc
, false);
2642 static void dce_v11_0_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
2643 u16
*blue
, uint32_t start
, uint32_t size
)
2645 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2646 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
2648 /* userspace palettes are always correct as is */
2649 for (i
= start
; i
< end
; i
++) {
2650 amdgpu_crtc
->lut_r
[i
] = red
[i
] >> 6;
2651 amdgpu_crtc
->lut_g
[i
] = green
[i
] >> 6;
2652 amdgpu_crtc
->lut_b
[i
] = blue
[i
] >> 6;
2654 dce_v11_0_crtc_load_lut(crtc
);
2657 static void dce_v11_0_crtc_destroy(struct drm_crtc
*crtc
)
2659 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2661 drm_crtc_cleanup(crtc
);
2662 destroy_workqueue(amdgpu_crtc
->pflip_queue
);
2666 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs
= {
2667 .cursor_set2
= dce_v11_0_crtc_cursor_set2
,
2668 .cursor_move
= dce_v11_0_crtc_cursor_move
,
2669 .gamma_set
= dce_v11_0_crtc_gamma_set
,
2670 .set_config
= amdgpu_crtc_set_config
,
2671 .destroy
= dce_v11_0_crtc_destroy
,
2672 .page_flip
= amdgpu_crtc_page_flip
,
2675 static void dce_v11_0_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2677 struct drm_device
*dev
= crtc
->dev
;
2678 struct amdgpu_device
*adev
= dev
->dev_private
;
2679 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2683 case DRM_MODE_DPMS_ON
:
2684 amdgpu_crtc
->enabled
= true;
2685 amdgpu_atombios_crtc_enable(crtc
, ATOM_ENABLE
);
2686 dce_v11_0_vga_enable(crtc
, true);
2687 amdgpu_atombios_crtc_blank(crtc
, ATOM_DISABLE
);
2688 dce_v11_0_vga_enable(crtc
, false);
2689 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2690 type
= amdgpu_crtc_idx_to_irq_type(adev
, amdgpu_crtc
->crtc_id
);
2691 amdgpu_irq_update(adev
, &adev
->crtc_irq
, type
);
2692 amdgpu_irq_update(adev
, &adev
->pageflip_irq
, type
);
2693 drm_vblank_post_modeset(dev
, amdgpu_crtc
->crtc_id
);
2694 dce_v11_0_crtc_load_lut(crtc
);
2696 case DRM_MODE_DPMS_STANDBY
:
2697 case DRM_MODE_DPMS_SUSPEND
:
2698 case DRM_MODE_DPMS_OFF
:
2699 drm_vblank_pre_modeset(dev
, amdgpu_crtc
->crtc_id
);
2700 if (amdgpu_crtc
->enabled
) {
2701 dce_v11_0_vga_enable(crtc
, true);
2702 amdgpu_atombios_crtc_blank(crtc
, ATOM_ENABLE
);
2703 dce_v11_0_vga_enable(crtc
, false);
2705 amdgpu_atombios_crtc_enable(crtc
, ATOM_DISABLE
);
2706 amdgpu_crtc
->enabled
= false;
2709 /* adjust pm to dpms */
2710 amdgpu_pm_compute_clocks(adev
);
2713 static void dce_v11_0_crtc_prepare(struct drm_crtc
*crtc
)
2715 /* disable crtc pair power gating before programming */
2716 amdgpu_atombios_crtc_powergate(crtc
, ATOM_DISABLE
);
2717 amdgpu_atombios_crtc_lock(crtc
, ATOM_ENABLE
);
2718 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2721 static void dce_v11_0_crtc_commit(struct drm_crtc
*crtc
)
2723 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
2724 amdgpu_atombios_crtc_lock(crtc
, ATOM_DISABLE
);
2727 static void dce_v11_0_crtc_disable(struct drm_crtc
*crtc
)
2729 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2730 struct drm_device
*dev
= crtc
->dev
;
2731 struct amdgpu_device
*adev
= dev
->dev_private
;
2732 struct amdgpu_atom_ss ss
;
2735 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2736 if (crtc
->primary
->fb
) {
2738 struct amdgpu_framebuffer
*amdgpu_fb
;
2739 struct amdgpu_bo
*rbo
;
2741 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2742 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2743 r
= amdgpu_bo_reserve(rbo
, false);
2745 DRM_ERROR("failed to reserve rbo before unpin\n");
2747 amdgpu_bo_unpin(rbo
);
2748 amdgpu_bo_unreserve(rbo
);
2751 /* disable the GRPH */
2752 dce_v11_0_grph_enable(crtc
, false);
2754 amdgpu_atombios_crtc_powergate(crtc
, ATOM_ENABLE
);
2756 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2757 if (adev
->mode_info
.crtcs
[i
] &&
2758 adev
->mode_info
.crtcs
[i
]->enabled
&&
2759 i
!= amdgpu_crtc
->crtc_id
&&
2760 amdgpu_crtc
->pll_id
== adev
->mode_info
.crtcs
[i
]->pll_id
) {
2761 /* one other crtc is using this pll don't turn
2768 switch (amdgpu_crtc
->pll_id
) {
2772 /* disable the ppll */
2773 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2774 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2780 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2781 amdgpu_crtc
->adjusted_clock
= 0;
2782 amdgpu_crtc
->encoder
= NULL
;
2783 amdgpu_crtc
->connector
= NULL
;
2786 static int dce_v11_0_crtc_mode_set(struct drm_crtc
*crtc
,
2787 struct drm_display_mode
*mode
,
2788 struct drm_display_mode
*adjusted_mode
,
2789 int x
, int y
, struct drm_framebuffer
*old_fb
)
2791 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2793 if (!amdgpu_crtc
->adjusted_clock
)
2796 amdgpu_atombios_crtc_set_pll(crtc
, adjusted_mode
);
2797 amdgpu_atombios_crtc_set_dtd_timing(crtc
, adjusted_mode
);
2798 dce_v11_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2799 amdgpu_atombios_crtc_overscan_setup(crtc
, mode
, adjusted_mode
);
2800 amdgpu_atombios_crtc_scaler_setup(crtc
);
2801 dce_v11_0_cursor_reset(crtc
);
2802 /* update the hw version fpr dpm */
2803 amdgpu_crtc
->hw_mode
= *adjusted_mode
;
2808 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc
*crtc
,
2809 const struct drm_display_mode
*mode
,
2810 struct drm_display_mode
*adjusted_mode
)
2812 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2813 struct drm_device
*dev
= crtc
->dev
;
2814 struct drm_encoder
*encoder
;
2816 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2817 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2818 if (encoder
->crtc
== crtc
) {
2819 amdgpu_crtc
->encoder
= encoder
;
2820 amdgpu_crtc
->connector
= amdgpu_get_connector_for_encoder(encoder
);
2824 if ((amdgpu_crtc
->encoder
== NULL
) || (amdgpu_crtc
->connector
== NULL
)) {
2825 amdgpu_crtc
->encoder
= NULL
;
2826 amdgpu_crtc
->connector
= NULL
;
2829 if (!amdgpu_crtc_scaling_mode_fixup(crtc
, mode
, adjusted_mode
))
2831 if (amdgpu_atombios_crtc_prepare_pll(crtc
, adjusted_mode
))
2834 amdgpu_crtc
->pll_id
= dce_v11_0_pick_pll(crtc
);
2835 /* if we can't get a PPLL for a non-DP encoder, fail */
2836 if ((amdgpu_crtc
->pll_id
== ATOM_PPLL_INVALID
) &&
2837 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2843 static int dce_v11_0_crtc_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2844 struct drm_framebuffer
*old_fb
)
2846 return dce_v11_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2849 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc
*crtc
,
2850 struct drm_framebuffer
*fb
,
2851 int x
, int y
, enum mode_set_atomic state
)
2853 return dce_v11_0_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
2856 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs
= {
2857 .dpms
= dce_v11_0_crtc_dpms
,
2858 .mode_fixup
= dce_v11_0_crtc_mode_fixup
,
2859 .mode_set
= dce_v11_0_crtc_mode_set
,
2860 .mode_set_base
= dce_v11_0_crtc_set_base
,
2861 .mode_set_base_atomic
= dce_v11_0_crtc_set_base_atomic
,
2862 .prepare
= dce_v11_0_crtc_prepare
,
2863 .commit
= dce_v11_0_crtc_commit
,
2864 .load_lut
= dce_v11_0_crtc_load_lut
,
2865 .disable
= dce_v11_0_crtc_disable
,
2868 static int dce_v11_0_crtc_init(struct amdgpu_device
*adev
, int index
)
2870 struct amdgpu_crtc
*amdgpu_crtc
;
2873 amdgpu_crtc
= kzalloc(sizeof(struct amdgpu_crtc
) +
2874 (AMDGPUFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
2875 if (amdgpu_crtc
== NULL
)
2878 drm_crtc_init(adev
->ddev
, &amdgpu_crtc
->base
, &dce_v11_0_crtc_funcs
);
2880 drm_mode_crtc_set_gamma_size(&amdgpu_crtc
->base
, 256);
2881 amdgpu_crtc
->crtc_id
= index
;
2882 amdgpu_crtc
->pflip_queue
= create_singlethread_workqueue("amdgpu-pageflip-queue");
2883 adev
->mode_info
.crtcs
[index
] = amdgpu_crtc
;
2885 amdgpu_crtc
->max_cursor_width
= 128;
2886 amdgpu_crtc
->max_cursor_height
= 128;
2887 adev
->ddev
->mode_config
.cursor_width
= amdgpu_crtc
->max_cursor_width
;
2888 adev
->ddev
->mode_config
.cursor_height
= amdgpu_crtc
->max_cursor_height
;
2890 for (i
= 0; i
< 256; i
++) {
2891 amdgpu_crtc
->lut_r
[i
] = i
<< 2;
2892 amdgpu_crtc
->lut_g
[i
] = i
<< 2;
2893 amdgpu_crtc
->lut_b
[i
] = i
<< 2;
2896 switch (amdgpu_crtc
->crtc_id
) {
2899 amdgpu_crtc
->crtc_offset
= CRTC0_REGISTER_OFFSET
;
2902 amdgpu_crtc
->crtc_offset
= CRTC1_REGISTER_OFFSET
;
2905 amdgpu_crtc
->crtc_offset
= CRTC2_REGISTER_OFFSET
;
2908 amdgpu_crtc
->crtc_offset
= CRTC3_REGISTER_OFFSET
;
2911 amdgpu_crtc
->crtc_offset
= CRTC4_REGISTER_OFFSET
;
2914 amdgpu_crtc
->crtc_offset
= CRTC5_REGISTER_OFFSET
;
2918 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2919 amdgpu_crtc
->adjusted_clock
= 0;
2920 amdgpu_crtc
->encoder
= NULL
;
2921 amdgpu_crtc
->connector
= NULL
;
2922 drm_crtc_helper_add(&amdgpu_crtc
->base
, &dce_v11_0_crtc_helper_funcs
);
2927 static int dce_v11_0_early_init(void *handle
)
2929 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2931 adev
->audio_endpt_rreg
= &dce_v11_0_audio_endpt_rreg
;
2932 adev
->audio_endpt_wreg
= &dce_v11_0_audio_endpt_wreg
;
2934 dce_v11_0_set_display_funcs(adev
);
2935 dce_v11_0_set_irq_funcs(adev
);
2937 switch (adev
->asic_type
) {
2939 adev
->mode_info
.num_crtc
= 3;
2940 adev
->mode_info
.num_hpd
= 6;
2941 adev
->mode_info
.num_dig
= 9;
2944 adev
->mode_info
.num_crtc
= 2;
2945 adev
->mode_info
.num_hpd
= 6;
2946 adev
->mode_info
.num_dig
= 9;
2949 /* FIXME: not supported yet */
2956 static int dce_v11_0_sw_init(void *handle
)
2959 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2961 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2962 r
= amdgpu_irq_add_id(adev
, i
+ 1, &adev
->crtc_irq
);
2967 for (i
= 8; i
< 20; i
+= 2) {
2968 r
= amdgpu_irq_add_id(adev
, i
, &adev
->pageflip_irq
);
2974 r
= amdgpu_irq_add_id(adev
, 42, &adev
->hpd_irq
);
2978 adev
->mode_info
.mode_config_initialized
= true;
2980 adev
->ddev
->mode_config
.funcs
= &amdgpu_mode_funcs
;
2982 adev
->ddev
->mode_config
.max_width
= 16384;
2983 adev
->ddev
->mode_config
.max_height
= 16384;
2985 adev
->ddev
->mode_config
.preferred_depth
= 24;
2986 adev
->ddev
->mode_config
.prefer_shadow
= 1;
2988 adev
->ddev
->mode_config
.fb_base
= adev
->mc
.aper_base
;
2990 r
= amdgpu_modeset_create_props(adev
);
2994 adev
->ddev
->mode_config
.max_width
= 16384;
2995 adev
->ddev
->mode_config
.max_height
= 16384;
2997 /* allocate crtcs */
2998 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2999 r
= dce_v11_0_crtc_init(adev
, i
);
3004 if (amdgpu_atombios_get_connector_info_from_object_table(adev
))
3005 amdgpu_print_display_setup(adev
->ddev
);
3010 dce_v11_0_afmt_init(adev
);
3012 r
= dce_v11_0_audio_init(adev
);
3016 drm_kms_helper_poll_init(adev
->ddev
);
3021 static int dce_v11_0_sw_fini(void *handle
)
3023 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3025 kfree(adev
->mode_info
.bios_hardcoded_edid
);
3027 drm_kms_helper_poll_fini(adev
->ddev
);
3029 dce_v11_0_audio_fini(adev
);
3031 dce_v11_0_afmt_fini(adev
);
3033 adev
->mode_info
.mode_config_initialized
= false;
3038 static int dce_v11_0_hw_init(void *handle
)
3041 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3043 dce_v11_0_init_golden_registers(adev
);
3045 /* init dig PHYs, disp eng pll */
3046 amdgpu_atombios_crtc_powergate_init(adev
);
3047 amdgpu_atombios_encoder_init_dig(adev
);
3048 amdgpu_atombios_crtc_set_disp_eng_pll(adev
, adev
->clock
.default_dispclk
);
3050 /* initialize hpd */
3051 dce_v11_0_hpd_init(adev
);
3053 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
3054 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
3057 dce_v11_0_pageflip_interrupt_init(adev
);
3062 static int dce_v11_0_hw_fini(void *handle
)
3065 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3067 dce_v11_0_hpd_fini(adev
);
3069 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
3070 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
3073 dce_v11_0_pageflip_interrupt_fini(adev
);
3078 static int dce_v11_0_suspend(void *handle
)
3080 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3082 amdgpu_atombios_scratch_regs_save(adev
);
3084 return dce_v11_0_hw_fini(handle
);
3087 static int dce_v11_0_resume(void *handle
)
3089 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3092 ret
= dce_v11_0_hw_init(handle
);
3094 amdgpu_atombios_scratch_regs_restore(adev
);
3096 /* turn on the BL */
3097 if (adev
->mode_info
.bl_encoder
) {
3098 u8 bl_level
= amdgpu_display_backlight_get_level(adev
,
3099 adev
->mode_info
.bl_encoder
);
3100 amdgpu_display_backlight_set_level(adev
, adev
->mode_info
.bl_encoder
,
3107 static bool dce_v11_0_is_idle(void *handle
)
3112 static int dce_v11_0_wait_for_idle(void *handle
)
3117 static void dce_v11_0_print_status(void *handle
)
3119 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3121 dev_info(adev
->dev
, "DCE 10.x registers\n");
3125 static int dce_v11_0_soft_reset(void *handle
)
3127 u32 srbm_soft_reset
= 0, tmp
;
3128 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3130 if (dce_v11_0_is_display_hung(adev
))
3131 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK
;
3133 if (srbm_soft_reset
) {
3134 dce_v11_0_print_status((void *)adev
);
3136 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3137 tmp
|= srbm_soft_reset
;
3138 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
3139 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3140 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3144 tmp
&= ~srbm_soft_reset
;
3145 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3146 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3148 /* Wait a little for things to settle down */
3150 dce_v11_0_print_status((void *)adev
);
3155 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device
*adev
,
3157 enum amdgpu_interrupt_state state
)
3159 u32 lb_interrupt_mask
;
3161 if (crtc
>= adev
->mode_info
.num_crtc
) {
3162 DRM_DEBUG("invalid crtc %d\n", crtc
);
3167 case AMDGPU_IRQ_STATE_DISABLE
:
3168 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3169 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3170 VBLANK_INTERRUPT_MASK
, 0);
3171 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3173 case AMDGPU_IRQ_STATE_ENABLE
:
3174 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3175 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3176 VBLANK_INTERRUPT_MASK
, 1);
3177 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3184 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device
*adev
,
3186 enum amdgpu_interrupt_state state
)
3188 u32 lb_interrupt_mask
;
3190 if (crtc
>= adev
->mode_info
.num_crtc
) {
3191 DRM_DEBUG("invalid crtc %d\n", crtc
);
3196 case AMDGPU_IRQ_STATE_DISABLE
:
3197 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3198 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3199 VLINE_INTERRUPT_MASK
, 0);
3200 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3202 case AMDGPU_IRQ_STATE_ENABLE
:
3203 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3204 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3205 VLINE_INTERRUPT_MASK
, 1);
3206 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3213 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device
*adev
,
3214 struct amdgpu_irq_src
*source
,
3216 enum amdgpu_interrupt_state state
)
3220 if (hpd
>= adev
->mode_info
.num_hpd
) {
3221 DRM_DEBUG("invalid hdp %d\n", hpd
);
3226 case AMDGPU_IRQ_STATE_DISABLE
:
3227 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3228 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 0);
3229 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3231 case AMDGPU_IRQ_STATE_ENABLE
:
3232 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3233 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 1);
3234 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3243 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device
*adev
,
3244 struct amdgpu_irq_src
*source
,
3246 enum amdgpu_interrupt_state state
)
3249 case AMDGPU_CRTC_IRQ_VBLANK1
:
3250 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 0, state
);
3252 case AMDGPU_CRTC_IRQ_VBLANK2
:
3253 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 1, state
);
3255 case AMDGPU_CRTC_IRQ_VBLANK3
:
3256 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 2, state
);
3258 case AMDGPU_CRTC_IRQ_VBLANK4
:
3259 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 3, state
);
3261 case AMDGPU_CRTC_IRQ_VBLANK5
:
3262 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 4, state
);
3264 case AMDGPU_CRTC_IRQ_VBLANK6
:
3265 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 5, state
);
3267 case AMDGPU_CRTC_IRQ_VLINE1
:
3268 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 0, state
);
3270 case AMDGPU_CRTC_IRQ_VLINE2
:
3271 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 1, state
);
3273 case AMDGPU_CRTC_IRQ_VLINE3
:
3274 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 2, state
);
3276 case AMDGPU_CRTC_IRQ_VLINE4
:
3277 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 3, state
);
3279 case AMDGPU_CRTC_IRQ_VLINE5
:
3280 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 4, state
);
3282 case AMDGPU_CRTC_IRQ_VLINE6
:
3283 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 5, state
);
3291 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device
*adev
,
3292 struct amdgpu_irq_src
*src
,
3294 enum amdgpu_interrupt_state state
)
3298 if (type
>= adev
->mode_info
.num_crtc
) {
3299 DRM_ERROR("invalid pageflip crtc %d\n", type
);
3303 reg
= RREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
]);
3304 if (state
== AMDGPU_IRQ_STATE_DISABLE
)
3305 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3306 reg
& ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3308 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3309 reg
| GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3314 static int dce_v11_0_pageflip_irq(struct amdgpu_device
*adev
,
3315 struct amdgpu_irq_src
*source
,
3316 struct amdgpu_iv_entry
*entry
)
3318 unsigned long flags
;
3320 struct amdgpu_crtc
*amdgpu_crtc
;
3321 struct amdgpu_flip_work
*works
;
3323 crtc_id
= (entry
->src_id
- 8) >> 1;
3324 amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
3326 if (crtc_id
>= adev
->mode_info
.num_crtc
) {
3327 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id
);
3331 if (RREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
]) &
3332 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
)
3333 WREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
],
3334 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
);
3336 /* IRQ could occur when in initial stage */
3337 if(amdgpu_crtc
== NULL
)
3340 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
3341 works
= amdgpu_crtc
->pflip_works
;
3342 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_SUBMITTED
){
3343 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3344 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3345 amdgpu_crtc
->pflip_status
,
3346 AMDGPU_FLIP_SUBMITTED
);
3347 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3351 /* page flip completed. clean up */
3352 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_NONE
;
3353 amdgpu_crtc
->pflip_works
= NULL
;
3355 /* wakeup usersapce */
3357 drm_send_vblank_event(adev
->ddev
, crtc_id
, works
->event
);
3359 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3361 drm_vblank_put(adev
->ddev
, amdgpu_crtc
->crtc_id
);
3362 queue_work(amdgpu_crtc
->pflip_queue
, &works
->unpin_work
);
3367 static void dce_v11_0_hpd_int_ack(struct amdgpu_device
*adev
,
3372 if (hpd
>= adev
->mode_info
.num_hpd
) {
3373 DRM_DEBUG("invalid hdp %d\n", hpd
);
3377 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3378 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_ACK
, 1);
3379 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3382 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device
*adev
,
3387 if (crtc
>= adev
->mode_info
.num_crtc
) {
3388 DRM_DEBUG("invalid crtc %d\n", crtc
);
3392 tmp
= RREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
]);
3393 tmp
= REG_SET_FIELD(tmp
, LB_VBLANK_STATUS
, VBLANK_ACK
, 1);
3394 WREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
], tmp
);
3397 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device
*adev
,
3402 if (crtc
>= adev
->mode_info
.num_crtc
) {
3403 DRM_DEBUG("invalid crtc %d\n", crtc
);
3407 tmp
= RREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
]);
3408 tmp
= REG_SET_FIELD(tmp
, LB_VLINE_STATUS
, VLINE_ACK
, 1);
3409 WREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
], tmp
);
3412 static int dce_v11_0_crtc_irq(struct amdgpu_device
*adev
,
3413 struct amdgpu_irq_src
*source
,
3414 struct amdgpu_iv_entry
*entry
)
3416 unsigned crtc
= entry
->src_id
- 1;
3417 uint32_t disp_int
= RREG32(interrupt_status_offsets
[crtc
].reg
);
3418 unsigned irq_type
= amdgpu_crtc_idx_to_irq_type(adev
, crtc
);
3420 switch (entry
->src_data
) {
3421 case 0: /* vblank */
3422 if (disp_int
& interrupt_status_offsets
[crtc
].vblank
)
3423 dce_v11_0_crtc_vblank_int_ack(adev
, crtc
);
3425 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3427 if (amdgpu_irq_enabled(adev
, source
, irq_type
)) {
3428 drm_handle_vblank(adev
->ddev
, crtc
);
3430 DRM_DEBUG("IH: D%d vblank\n", crtc
+ 1);
3434 if (disp_int
& interrupt_status_offsets
[crtc
].vline
)
3435 dce_v11_0_crtc_vline_int_ack(adev
, crtc
);
3437 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3439 DRM_DEBUG("IH: D%d vline\n", crtc
+ 1);
3443 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3450 static int dce_v11_0_hpd_irq(struct amdgpu_device
*adev
,
3451 struct amdgpu_irq_src
*source
,
3452 struct amdgpu_iv_entry
*entry
)
3454 uint32_t disp_int
, mask
;
3457 if (entry
->src_data
>= adev
->mode_info
.num_hpd
) {
3458 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3462 hpd
= entry
->src_data
;
3463 disp_int
= RREG32(interrupt_status_offsets
[hpd
].reg
);
3464 mask
= interrupt_status_offsets
[hpd
].hpd
;
3466 if (disp_int
& mask
) {
3467 dce_v11_0_hpd_int_ack(adev
, hpd
);
3468 schedule_work(&adev
->hotplug_work
);
3469 DRM_DEBUG("IH: HPD%d\n", hpd
+ 1);
3475 static int dce_v11_0_set_clockgating_state(void *handle
,
3476 enum amd_clockgating_state state
)
3481 static int dce_v11_0_set_powergating_state(void *handle
,
3482 enum amd_powergating_state state
)
3487 const struct amd_ip_funcs dce_v11_0_ip_funcs
= {
3488 .early_init
= dce_v11_0_early_init
,
3490 .sw_init
= dce_v11_0_sw_init
,
3491 .sw_fini
= dce_v11_0_sw_fini
,
3492 .hw_init
= dce_v11_0_hw_init
,
3493 .hw_fini
= dce_v11_0_hw_fini
,
3494 .suspend
= dce_v11_0_suspend
,
3495 .resume
= dce_v11_0_resume
,
3496 .is_idle
= dce_v11_0_is_idle
,
3497 .wait_for_idle
= dce_v11_0_wait_for_idle
,
3498 .soft_reset
= dce_v11_0_soft_reset
,
3499 .print_status
= dce_v11_0_print_status
,
3500 .set_clockgating_state
= dce_v11_0_set_clockgating_state
,
3501 .set_powergating_state
= dce_v11_0_set_powergating_state
,
3505 dce_v11_0_encoder_mode_set(struct drm_encoder
*encoder
,
3506 struct drm_display_mode
*mode
,
3507 struct drm_display_mode
*adjusted_mode
)
3509 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3511 amdgpu_encoder
->pixel_clock
= adjusted_mode
->clock
;
3513 /* need to call this here rather than in prepare() since we need some crtc info */
3514 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3516 /* set scaler clears this on some chips */
3517 dce_v11_0_set_interleave(encoder
->crtc
, mode
);
3519 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
3520 dce_v11_0_afmt_enable(encoder
, true);
3521 dce_v11_0_afmt_setmode(encoder
, adjusted_mode
);
3525 static void dce_v11_0_encoder_prepare(struct drm_encoder
*encoder
)
3527 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
3528 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3529 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
3531 if ((amdgpu_encoder
->active_device
&
3532 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
3533 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) !=
3534 ENCODER_OBJECT_ID_NONE
)) {
3535 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
3537 dig
->dig_encoder
= dce_v11_0_pick_dig_encoder(encoder
);
3538 if (amdgpu_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
)
3539 dig
->afmt
= adev
->mode_info
.afmt
[dig
->dig_encoder
];
3543 amdgpu_atombios_scratch_regs_lock(adev
, true);
3546 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
3548 /* select the clock/data port if it uses a router */
3549 if (amdgpu_connector
->router
.cd_valid
)
3550 amdgpu_i2c_router_select_cd_port(amdgpu_connector
);
3552 /* turn eDP panel on for mode set */
3553 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3554 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
3555 ATOM_TRANSMITTER_ACTION_POWER_ON
);
3558 /* this is needed for the pll/ss setup to work correctly in some cases */
3559 amdgpu_atombios_encoder_set_crtc_source(encoder
);
3560 /* set up the FMT blocks */
3561 dce_v11_0_program_fmt(encoder
);
3564 static void dce_v11_0_encoder_commit(struct drm_encoder
*encoder
)
3566 struct drm_device
*dev
= encoder
->dev
;
3567 struct amdgpu_device
*adev
= dev
->dev_private
;
3569 /* need to call this here as we need the crtc set up */
3570 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
3571 amdgpu_atombios_scratch_regs_lock(adev
, false);
3574 static void dce_v11_0_encoder_disable(struct drm_encoder
*encoder
)
3576 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3577 struct amdgpu_encoder_atom_dig
*dig
;
3579 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3581 if (amdgpu_atombios_encoder_is_digital(encoder
)) {
3582 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
3583 dce_v11_0_afmt_enable(encoder
, false);
3584 dig
= amdgpu_encoder
->enc_priv
;
3585 dig
->dig_encoder
= -1;
3587 amdgpu_encoder
->active_device
= 0;
3590 /* these are handled by the primary encoders */
3591 static void dce_v11_0_ext_prepare(struct drm_encoder
*encoder
)
3596 static void dce_v11_0_ext_commit(struct drm_encoder
*encoder
)
3602 dce_v11_0_ext_mode_set(struct drm_encoder
*encoder
,
3603 struct drm_display_mode
*mode
,
3604 struct drm_display_mode
*adjusted_mode
)
3609 static void dce_v11_0_ext_disable(struct drm_encoder
*encoder
)
3615 dce_v11_0_ext_dpms(struct drm_encoder
*encoder
, int mode
)
3620 static bool dce_v11_0_ext_mode_fixup(struct drm_encoder
*encoder
,
3621 const struct drm_display_mode
*mode
,
3622 struct drm_display_mode
*adjusted_mode
)
3627 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs
= {
3628 .dpms
= dce_v11_0_ext_dpms
,
3629 .mode_fixup
= dce_v11_0_ext_mode_fixup
,
3630 .prepare
= dce_v11_0_ext_prepare
,
3631 .mode_set
= dce_v11_0_ext_mode_set
,
3632 .commit
= dce_v11_0_ext_commit
,
3633 .disable
= dce_v11_0_ext_disable
,
3634 /* no detect for TMDS/LVDS yet */
3637 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs
= {
3638 .dpms
= amdgpu_atombios_encoder_dpms
,
3639 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3640 .prepare
= dce_v11_0_encoder_prepare
,
3641 .mode_set
= dce_v11_0_encoder_mode_set
,
3642 .commit
= dce_v11_0_encoder_commit
,
3643 .disable
= dce_v11_0_encoder_disable
,
3644 .detect
= amdgpu_atombios_encoder_dig_detect
,
3647 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs
= {
3648 .dpms
= amdgpu_atombios_encoder_dpms
,
3649 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3650 .prepare
= dce_v11_0_encoder_prepare
,
3651 .mode_set
= dce_v11_0_encoder_mode_set
,
3652 .commit
= dce_v11_0_encoder_commit
,
3653 .detect
= amdgpu_atombios_encoder_dac_detect
,
3656 static void dce_v11_0_encoder_destroy(struct drm_encoder
*encoder
)
3658 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3659 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3660 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder
);
3661 kfree(amdgpu_encoder
->enc_priv
);
3662 drm_encoder_cleanup(encoder
);
3663 kfree(amdgpu_encoder
);
3666 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs
= {
3667 .destroy
= dce_v11_0_encoder_destroy
,
3670 static void dce_v11_0_encoder_add(struct amdgpu_device
*adev
,
3671 uint32_t encoder_enum
,
3672 uint32_t supported_device
,
3675 struct drm_device
*dev
= adev
->ddev
;
3676 struct drm_encoder
*encoder
;
3677 struct amdgpu_encoder
*amdgpu_encoder
;
3679 /* see if we already added it */
3680 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3681 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3682 if (amdgpu_encoder
->encoder_enum
== encoder_enum
) {
3683 amdgpu_encoder
->devices
|= supported_device
;
3690 amdgpu_encoder
= kzalloc(sizeof(struct amdgpu_encoder
), GFP_KERNEL
);
3691 if (!amdgpu_encoder
)
3694 encoder
= &amdgpu_encoder
->base
;
3695 switch (adev
->mode_info
.num_crtc
) {
3697 encoder
->possible_crtcs
= 0x1;
3701 encoder
->possible_crtcs
= 0x3;
3704 encoder
->possible_crtcs
= 0xf;
3707 encoder
->possible_crtcs
= 0x3f;
3711 amdgpu_encoder
->enc_priv
= NULL
;
3713 amdgpu_encoder
->encoder_enum
= encoder_enum
;
3714 amdgpu_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
3715 amdgpu_encoder
->devices
= supported_device
;
3716 amdgpu_encoder
->rmx_type
= RMX_OFF
;
3717 amdgpu_encoder
->underscan_type
= UNDERSCAN_OFF
;
3718 amdgpu_encoder
->is_ext_encoder
= false;
3719 amdgpu_encoder
->caps
= caps
;
3721 switch (amdgpu_encoder
->encoder_id
) {
3722 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
3723 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
3724 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3725 DRM_MODE_ENCODER_DAC
, NULL
);
3726 drm_encoder_helper_add(encoder
, &dce_v11_0_dac_helper_funcs
);
3728 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
3729 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
3730 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
3731 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
3732 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
3733 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3734 amdgpu_encoder
->rmx_type
= RMX_FULL
;
3735 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3736 DRM_MODE_ENCODER_LVDS
, NULL
);
3737 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder
);
3738 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3739 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3740 DRM_MODE_ENCODER_DAC
, NULL
);
3741 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3743 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3744 DRM_MODE_ENCODER_TMDS
, NULL
);
3745 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3747 drm_encoder_helper_add(encoder
, &dce_v11_0_dig_helper_funcs
);
3749 case ENCODER_OBJECT_ID_SI170B
:
3750 case ENCODER_OBJECT_ID_CH7303
:
3751 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
3752 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
3753 case ENCODER_OBJECT_ID_TITFP513
:
3754 case ENCODER_OBJECT_ID_VT1623
:
3755 case ENCODER_OBJECT_ID_HDMI_SI1930
:
3756 case ENCODER_OBJECT_ID_TRAVIS
:
3757 case ENCODER_OBJECT_ID_NUTMEG
:
3758 /* these are handled by the primary encoders */
3759 amdgpu_encoder
->is_ext_encoder
= true;
3760 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3761 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3762 DRM_MODE_ENCODER_LVDS
, NULL
);
3763 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
3764 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3765 DRM_MODE_ENCODER_DAC
, NULL
);
3767 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3768 DRM_MODE_ENCODER_TMDS
, NULL
);
3769 drm_encoder_helper_add(encoder
, &dce_v11_0_ext_helper_funcs
);
3774 static const struct amdgpu_display_funcs dce_v11_0_display_funcs
= {
3775 .set_vga_render_state
= &dce_v11_0_set_vga_render_state
,
3776 .bandwidth_update
= &dce_v11_0_bandwidth_update
,
3777 .vblank_get_counter
= &dce_v11_0_vblank_get_counter
,
3778 .vblank_wait
= &dce_v11_0_vblank_wait
,
3779 .is_display_hung
= &dce_v11_0_is_display_hung
,
3780 .backlight_set_level
= &amdgpu_atombios_encoder_set_backlight_level
,
3781 .backlight_get_level
= &amdgpu_atombios_encoder_get_backlight_level
,
3782 .hpd_sense
= &dce_v11_0_hpd_sense
,
3783 .hpd_set_polarity
= &dce_v11_0_hpd_set_polarity
,
3784 .hpd_get_gpio_reg
= &dce_v11_0_hpd_get_gpio_reg
,
3785 .page_flip
= &dce_v11_0_page_flip
,
3786 .page_flip_get_scanoutpos
= &dce_v11_0_crtc_get_scanoutpos
,
3787 .add_encoder
= &dce_v11_0_encoder_add
,
3788 .add_connector
= &amdgpu_connector_add
,
3789 .stop_mc_access
= &dce_v11_0_stop_mc_access
,
3790 .resume_mc_access
= &dce_v11_0_resume_mc_access
,
3793 static void dce_v11_0_set_display_funcs(struct amdgpu_device
*adev
)
3795 if (adev
->mode_info
.funcs
== NULL
)
3796 adev
->mode_info
.funcs
= &dce_v11_0_display_funcs
;
3799 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs
= {
3800 .set
= dce_v11_0_set_crtc_irq_state
,
3801 .process
= dce_v11_0_crtc_irq
,
3804 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs
= {
3805 .set
= dce_v11_0_set_pageflip_irq_state
,
3806 .process
= dce_v11_0_pageflip_irq
,
3809 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs
= {
3810 .set
= dce_v11_0_set_hpd_irq_state
,
3811 .process
= dce_v11_0_hpd_irq
,
3814 static void dce_v11_0_set_irq_funcs(struct amdgpu_device
*adev
)
3816 adev
->crtc_irq
.num_types
= AMDGPU_CRTC_IRQ_LAST
;
3817 adev
->crtc_irq
.funcs
= &dce_v11_0_crtc_irq_funcs
;
3819 adev
->pageflip_irq
.num_types
= AMDGPU_PAGEFLIP_IRQ_LAST
;
3820 adev
->pageflip_irq
.funcs
= &dce_v11_0_pageflip_irq_funcs
;
3822 adev
->hpd_irq
.num_types
= AMDGPU_HPD_LAST
;
3823 adev
->hpd_irq
.funcs
= &dce_v11_0_hpd_irq_funcs
;