2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
29 #include "gmc/gmc_8_1_d.h"
30 #include "gmc/gmc_8_1_sh_mask.h"
32 #include "bif/bif_5_0_d.h"
33 #include "bif/bif_5_0_sh_mask.h"
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device
*adev
);
43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device
*adev
);
44 static int gmc_v8_0_wait_for_idle(void *handle
);
46 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
47 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
48 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
50 static const u32 golden_settings_tonga_a11
[] =
52 mmMC_ARB_WTM_GRPWT_RD
, 0x00000003, 0x00000000,
53 mmMC_HUB_RDREQ_DMIF_LIMIT
, 0x0000007f, 0x00000028,
54 mmMC_HUB_WDP_UMC
, 0x00007fb6, 0x00000991,
55 mmVM_PRT_APERTURE0_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
56 mmVM_PRT_APERTURE1_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
57 mmVM_PRT_APERTURE2_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
58 mmVM_PRT_APERTURE3_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
61 static const u32 tonga_mgcg_cgcg_init
[] =
63 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
66 static const u32 golden_settings_fiji_a10
[] =
68 mmVM_PRT_APERTURE0_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
69 mmVM_PRT_APERTURE1_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
70 mmVM_PRT_APERTURE2_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
71 mmVM_PRT_APERTURE3_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
74 static const u32 fiji_mgcg_cgcg_init
[] =
76 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
79 static const u32 golden_settings_polaris11_a11
[] =
81 mmVM_PRT_APERTURE0_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
82 mmVM_PRT_APERTURE1_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE2_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
84 mmVM_PRT_APERTURE3_LOW_ADDR
, 0x0fffffff, 0x0fffffff
87 static const u32 golden_settings_polaris10_a11
[] =
89 mmMC_ARB_WTM_GRPWT_RD
, 0x00000003, 0x00000000,
90 mmVM_PRT_APERTURE0_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
91 mmVM_PRT_APERTURE1_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
92 mmVM_PRT_APERTURE2_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
93 mmVM_PRT_APERTURE3_LOW_ADDR
, 0x0fffffff, 0x0fffffff
96 static const u32 cz_mgcg_cgcg_init
[] =
98 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
101 static const u32 stoney_mgcg_cgcg_init
[] =
103 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
107 static void gmc_v8_0_init_golden_registers(struct amdgpu_device
*adev
)
109 switch (adev
->asic_type
) {
111 amdgpu_program_register_sequence(adev
,
113 (const u32
)ARRAY_SIZE(fiji_mgcg_cgcg_init
));
114 amdgpu_program_register_sequence(adev
,
115 golden_settings_fiji_a10
,
116 (const u32
)ARRAY_SIZE(golden_settings_fiji_a10
));
119 amdgpu_program_register_sequence(adev
,
120 tonga_mgcg_cgcg_init
,
121 (const u32
)ARRAY_SIZE(tonga_mgcg_cgcg_init
));
122 amdgpu_program_register_sequence(adev
,
123 golden_settings_tonga_a11
,
124 (const u32
)ARRAY_SIZE(golden_settings_tonga_a11
));
127 amdgpu_program_register_sequence(adev
,
128 golden_settings_polaris11_a11
,
129 (const u32
)ARRAY_SIZE(golden_settings_polaris11_a11
));
132 amdgpu_program_register_sequence(adev
,
133 golden_settings_polaris10_a11
,
134 (const u32
)ARRAY_SIZE(golden_settings_polaris10_a11
));
137 amdgpu_program_register_sequence(adev
,
139 (const u32
)ARRAY_SIZE(cz_mgcg_cgcg_init
));
142 amdgpu_program_register_sequence(adev
,
143 stoney_mgcg_cgcg_init
,
144 (const u32
)ARRAY_SIZE(stoney_mgcg_cgcg_init
));
151 static void gmc_v8_0_mc_stop(struct amdgpu_device
*adev
,
152 struct amdgpu_mode_mc_save
*save
)
156 if (adev
->mode_info
.num_crtc
)
157 amdgpu_display_stop_mc_access(adev
, save
);
159 gmc_v8_0_wait_for_idle(adev
);
161 blackout
= RREG32(mmMC_SHARED_BLACKOUT_CNTL
);
162 if (REG_GET_FIELD(blackout
, MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
) != 1) {
163 /* Block CPU access */
164 WREG32(mmBIF_FB_EN
, 0);
165 /* blackout the MC */
166 blackout
= REG_SET_FIELD(blackout
,
167 MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
, 1);
168 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, blackout
);
170 /* wait for the MC to settle */
174 static void gmc_v8_0_mc_resume(struct amdgpu_device
*adev
,
175 struct amdgpu_mode_mc_save
*save
)
179 /* unblackout the MC */
180 tmp
= RREG32(mmMC_SHARED_BLACKOUT_CNTL
);
181 tmp
= REG_SET_FIELD(tmp
, MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
, 0);
182 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, tmp
);
183 /* allow CPU access */
184 tmp
= REG_SET_FIELD(0, BIF_FB_EN
, FB_READ_EN
, 1);
185 tmp
= REG_SET_FIELD(tmp
, BIF_FB_EN
, FB_WRITE_EN
, 1);
186 WREG32(mmBIF_FB_EN
, tmp
);
188 if (adev
->mode_info
.num_crtc
)
189 amdgpu_display_resume_mc_access(adev
, save
);
193 * gmc_v8_0_init_microcode - load ucode images from disk
195 * @adev: amdgpu_device pointer
197 * Use the firmware interface to load the ucode images into
198 * the driver (not loaded into hw).
199 * Returns 0 on success, error on failure.
201 static int gmc_v8_0_init_microcode(struct amdgpu_device
*adev
)
203 const char *chip_name
;
209 switch (adev
->asic_type
) {
214 chip_name
= "polaris11";
217 chip_name
= "polaris10";
226 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_mc.bin", chip_name
);
227 err
= request_firmware(&adev
->mc
.fw
, fw_name
, adev
->dev
);
230 err
= amdgpu_ucode_validate(adev
->mc
.fw
);
235 "mc: Failed to load firmware \"%s\"\n",
237 release_firmware(adev
->mc
.fw
);
244 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
246 * @adev: amdgpu_device pointer
248 * Load the GDDR MC ucode into the hw (CIK).
249 * Returns 0 on success, error on failure.
251 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device
*adev
)
253 const struct mc_firmware_header_v1_0
*hdr
;
254 const __le32
*fw_data
= NULL
;
255 const __le32
*io_mc_regs
= NULL
;
256 u32 running
, blackout
= 0;
257 int i
, ucode_size
, regs_size
;
262 /* Skip MC ucode loading on SR-IOV capable boards.
263 * vbios does this for us in asic_init in that case.
265 if (adev
->virtualization
.supports_sr_iov
)
268 hdr
= (const struct mc_firmware_header_v1_0
*)adev
->mc
.fw
->data
;
269 amdgpu_ucode_print_mc_hdr(&hdr
->header
);
271 adev
->mc
.fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
272 regs_size
= le32_to_cpu(hdr
->io_debug_size_bytes
) / (4 * 2);
273 io_mc_regs
= (const __le32
*)
274 (adev
->mc
.fw
->data
+ le32_to_cpu(hdr
->io_debug_array_offset_bytes
));
275 ucode_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
276 fw_data
= (const __le32
*)
277 (adev
->mc
.fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
279 running
= REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL
), MC_SEQ_SUP_CNTL
, RUN
);
283 blackout
= RREG32(mmMC_SHARED_BLACKOUT_CNTL
);
284 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, blackout
| 1);
287 /* reset the engine and set to writable */
288 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000008);
289 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000010);
291 /* load mc io regs */
292 for (i
= 0; i
< regs_size
; i
++) {
293 WREG32(mmMC_SEQ_IO_DEBUG_INDEX
, le32_to_cpup(io_mc_regs
++));
294 WREG32(mmMC_SEQ_IO_DEBUG_DATA
, le32_to_cpup(io_mc_regs
++));
296 /* load the MC ucode */
297 for (i
= 0; i
< ucode_size
; i
++)
298 WREG32(mmMC_SEQ_SUP_PGM
, le32_to_cpup(fw_data
++));
300 /* put the engine back into the active state */
301 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000008);
302 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000004);
303 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000001);
305 /* wait for training to complete */
306 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
307 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL
),
308 MC_SEQ_TRAIN_WAKEUP_CNTL
, TRAIN_DONE_D0
))
312 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
313 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL
),
314 MC_SEQ_TRAIN_WAKEUP_CNTL
, TRAIN_DONE_D1
))
320 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, blackout
);
326 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device
*adev
,
327 struct amdgpu_mc
*mc
)
329 if (mc
->mc_vram_size
> 0xFFC0000000ULL
) {
330 /* leave room for at least 1024M GTT */
331 dev_warn(adev
->dev
, "limiting VRAM\n");
332 mc
->real_vram_size
= 0xFFC0000000ULL
;
333 mc
->mc_vram_size
= 0xFFC0000000ULL
;
335 amdgpu_vram_location(adev
, &adev
->mc
, 0);
336 adev
->mc
.gtt_base_align
= 0;
337 amdgpu_gtt_location(adev
, mc
);
341 * gmc_v8_0_mc_program - program the GPU memory controller
343 * @adev: amdgpu_device pointer
345 * Set the location of vram, gart, and AGP in the GPU's
346 * physical address space (CIK).
348 static void gmc_v8_0_mc_program(struct amdgpu_device
*adev
)
350 struct amdgpu_mode_mc_save save
;
355 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x6) {
356 WREG32((0xb05 + j
), 0x00000000);
357 WREG32((0xb06 + j
), 0x00000000);
358 WREG32((0xb07 + j
), 0x00000000);
359 WREG32((0xb08 + j
), 0x00000000);
360 WREG32((0xb09 + j
), 0x00000000);
362 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL
, 0);
364 if (adev
->mode_info
.num_crtc
)
365 amdgpu_display_set_vga_render_state(adev
, false);
367 gmc_v8_0_mc_stop(adev
, &save
);
368 if (gmc_v8_0_wait_for_idle((void *)adev
)) {
369 dev_warn(adev
->dev
, "Wait for MC idle timedout !\n");
371 /* Update configuration */
372 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR
,
373 adev
->mc
.vram_start
>> 12);
374 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
375 adev
->mc
.vram_end
>> 12);
376 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
,
377 adev
->vram_scratch
.gpu_addr
>> 12);
378 tmp
= ((adev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
379 tmp
|= ((adev
->mc
.vram_start
>> 24) & 0xFFFF);
380 WREG32(mmMC_VM_FB_LOCATION
, tmp
);
381 /* XXX double check these! */
382 WREG32(mmHDP_NONSURFACE_BASE
, (adev
->mc
.vram_start
>> 8));
383 WREG32(mmHDP_NONSURFACE_INFO
, (2 << 7) | (1 << 30));
384 WREG32(mmHDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
385 WREG32(mmMC_VM_AGP_BASE
, 0);
386 WREG32(mmMC_VM_AGP_TOP
, 0x0FFFFFFF);
387 WREG32(mmMC_VM_AGP_BOT
, 0x0FFFFFFF);
388 if (gmc_v8_0_wait_for_idle((void *)adev
)) {
389 dev_warn(adev
->dev
, "Wait for MC idle timedout !\n");
391 gmc_v8_0_mc_resume(adev
, &save
);
393 WREG32(mmBIF_FB_EN
, BIF_FB_EN__FB_READ_EN_MASK
| BIF_FB_EN__FB_WRITE_EN_MASK
);
395 tmp
= RREG32(mmHDP_MISC_CNTL
);
396 tmp
= REG_SET_FIELD(tmp
, HDP_MISC_CNTL
, FLUSH_INVALIDATE_CACHE
, 0);
397 WREG32(mmHDP_MISC_CNTL
, tmp
);
399 tmp
= RREG32(mmHDP_HOST_PATH_CNTL
);
400 WREG32(mmHDP_HOST_PATH_CNTL
, tmp
);
404 * gmc_v8_0_mc_init - initialize the memory controller driver params
406 * @adev: amdgpu_device pointer
408 * Look up the amount of vram, vram width, and decide how to place
409 * vram and gart within the GPU's physical address space (CIK).
410 * Returns 0 for success.
412 static int gmc_v8_0_mc_init(struct amdgpu_device
*adev
)
415 int chansize
, numchan
;
417 /* Get VRAM informations */
418 tmp
= RREG32(mmMC_ARB_RAMCFG
);
419 if (REG_GET_FIELD(tmp
, MC_ARB_RAMCFG
, CHANSIZE
)) {
424 tmp
= RREG32(mmMC_SHARED_CHMAP
);
425 switch (REG_GET_FIELD(tmp
, MC_SHARED_CHMAP
, NOOFCHAN
)) {
455 adev
->mc
.vram_width
= numchan
* chansize
;
456 /* Could aper size report 0 ? */
457 adev
->mc
.aper_base
= pci_resource_start(adev
->pdev
, 0);
458 adev
->mc
.aper_size
= pci_resource_len(adev
->pdev
, 0);
459 /* size in MB on si */
460 adev
->mc
.mc_vram_size
= RREG32(mmCONFIG_MEMSIZE
) * 1024ULL * 1024ULL;
461 adev
->mc
.real_vram_size
= RREG32(mmCONFIG_MEMSIZE
) * 1024ULL * 1024ULL;
462 adev
->mc
.visible_vram_size
= adev
->mc
.aper_size
;
464 /* In case the PCI BAR is larger than the actual amount of vram */
465 if (adev
->mc
.visible_vram_size
> adev
->mc
.real_vram_size
)
466 adev
->mc
.visible_vram_size
= adev
->mc
.real_vram_size
;
468 /* unless the user had overridden it, set the gart
469 * size equal to the 1024 or vram, whichever is larger.
471 if (amdgpu_gart_size
== -1)
472 adev
->mc
.gtt_size
= max((1024ULL << 20), adev
->mc
.mc_vram_size
);
474 adev
->mc
.gtt_size
= (uint64_t)amdgpu_gart_size
<< 20;
476 gmc_v8_0_vram_gtt_location(adev
, &adev
->mc
);
483 * VMID 0 is the physical GPU addresses as used by the kernel.
484 * VMIDs 1-15 are used for userspace clients and are handled
485 * by the amdgpu vm/hsa code.
489 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
491 * @adev: amdgpu_device pointer
492 * @vmid: vm instance to flush
494 * Flush the TLB for the requested page table (CIK).
496 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device
*adev
,
499 /* flush hdp cache */
500 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL
, 0);
502 /* bits 0-15 are the VM contexts0-15 */
503 WREG32(mmVM_INVALIDATE_REQUEST
, 1 << vmid
);
507 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
509 * @adev: amdgpu_device pointer
510 * @cpu_pt_addr: cpu address of the page table
511 * @gpu_page_idx: entry in the page table to update
512 * @addr: dst addr to write into pte/pde
513 * @flags: access flags
515 * Update the page tables using the CPU.
517 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device
*adev
,
519 uint32_t gpu_page_idx
,
523 void __iomem
*ptr
= (void *)cpu_pt_addr
;
529 * 39:12 4k physical page base address
540 * 63:59 block fragment size
542 * 39:1 physical base address of PTE
543 * bits 5:1 must be 0.
546 value
= addr
& 0x000000FFFFFFF000ULL
;
548 writeq(value
, ptr
+ (gpu_page_idx
* 8));
554 * gmc_v8_0_set_fault_enable_default - update VM fault handling
556 * @adev: amdgpu_device pointer
557 * @value: true redirects VM faults to the default page
559 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device
*adev
,
564 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
565 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
566 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
567 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
568 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
569 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
570 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
571 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
572 VALID_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
573 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
574 READ_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
575 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
576 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
577 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
578 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
579 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
583 * gmc_v8_0_gart_enable - gart enable
585 * @adev: amdgpu_device pointer
587 * This sets up the TLBs, programs the page tables for VMID0,
588 * sets up the hw for VMIDs 1-15 which are allocated on
589 * demand, and sets up the global locations for the LDS, GDS,
590 * and GPUVM for FSA64 clients (CIK).
591 * Returns 0 for success, errors for failure.
593 static int gmc_v8_0_gart_enable(struct amdgpu_device
*adev
)
598 if (adev
->gart
.robj
== NULL
) {
599 dev_err(adev
->dev
, "No VRAM object for PCIE GART.\n");
602 r
= amdgpu_gart_table_vram_pin(adev
);
605 /* Setup TLB control */
606 tmp
= RREG32(mmMC_VM_MX_L1_TLB_CNTL
);
607 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_TLB
, 1);
608 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_FRAGMENT_PROCESSING
, 1);
609 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, SYSTEM_ACCESS_MODE
, 3);
610 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_ADVANCED_DRIVER_MODEL
, 1);
611 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, SYSTEM_APERTURE_UNMAPPED_ACCESS
, 0);
612 WREG32(mmMC_VM_MX_L1_TLB_CNTL
, tmp
);
614 tmp
= RREG32(mmVM_L2_CNTL
);
615 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_CACHE
, 1);
616 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
, 1);
617 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
, 1);
618 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
, 1);
619 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, EFFECTIVE_L2_QUEUE_SIZE
, 7);
620 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, CONTEXT1_IDENTITY_ACCESS_MODE
, 1);
621 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY
, 1);
622 WREG32(mmVM_L2_CNTL
, tmp
);
623 tmp
= RREG32(mmVM_L2_CNTL2
);
624 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL2
, INVALIDATE_ALL_L1_TLBS
, 1);
625 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL2
, INVALIDATE_L2_CACHE
, 1);
626 WREG32(mmVM_L2_CNTL2
, tmp
);
627 tmp
= RREG32(mmVM_L2_CNTL3
);
628 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL3
, L2_CACHE_BIGK_ASSOCIATIVITY
, 1);
629 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL3
, BANK_SELECT
, 4);
630 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL3
, L2_CACHE_BIGK_FRAGMENT_SIZE
, 4);
631 WREG32(mmVM_L2_CNTL3
, tmp
);
632 /* XXX: set to enable PTE/PDE in system memory */
633 tmp
= RREG32(mmVM_L2_CNTL4
);
634 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL
, 0);
635 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED
, 0);
636 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP
, 0);
637 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL
, 0);
638 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED
, 0);
639 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP
, 0);
640 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL
, 0);
641 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED
, 0);
642 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP
, 0);
643 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL
, 0);
644 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED
, 0);
645 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP
, 0);
646 WREG32(mmVM_L2_CNTL4
, tmp
);
648 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR
, adev
->mc
.gtt_start
>> 12);
649 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR
, adev
->mc
.gtt_end
>> 12);
650 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, adev
->gart
.table_addr
>> 12);
651 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
652 (u32
)(adev
->dummy_page
.addr
>> 12));
653 WREG32(mmVM_CONTEXT0_CNTL2
, 0);
654 tmp
= RREG32(mmVM_CONTEXT0_CNTL
);
655 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
, 1);
656 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT0_CNTL
, PAGE_TABLE_DEPTH
, 0);
657 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT0_CNTL
, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
658 WREG32(mmVM_CONTEXT0_CNTL
, tmp
);
660 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR
, 0);
661 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR
, 0);
662 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET
, 0);
664 /* empty context1-15 */
665 /* FIXME start with 4G, once using 2 level pt switch to full
668 /* set vm size, must be a multiple of 4 */
669 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR
, 0);
670 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR
, adev
->vm_manager
.max_pfn
- 1);
671 for (i
= 1; i
< 16; i
++) {
673 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ i
,
674 adev
->gart
.table_addr
>> 12);
676 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ i
- 8,
677 adev
->gart
.table_addr
>> 12);
680 /* enable context1-15 */
681 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
,
682 (u32
)(adev
->dummy_page
.addr
>> 12));
683 WREG32(mmVM_CONTEXT1_CNTL2
, 4);
684 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
685 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, ENABLE_CONTEXT
, 1);
686 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, PAGE_TABLE_DEPTH
, 1);
687 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
688 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
689 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
690 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, VALID_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
691 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, READ_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
692 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
693 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
694 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, PAGE_TABLE_BLOCK_SIZE
,
695 amdgpu_vm_block_size
- 9);
696 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
697 if (amdgpu_vm_fault_stop
== AMDGPU_VM_FAULT_STOP_ALWAYS
)
698 gmc_v8_0_set_fault_enable_default(adev
, false);
700 gmc_v8_0_set_fault_enable_default(adev
, true);
702 gmc_v8_0_gart_flush_gpu_tlb(adev
, 0);
703 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
704 (unsigned)(adev
->mc
.gtt_size
>> 20),
705 (unsigned long long)adev
->gart
.table_addr
);
706 adev
->gart
.ready
= true;
710 static int gmc_v8_0_gart_init(struct amdgpu_device
*adev
)
714 if (adev
->gart
.robj
) {
715 WARN(1, "R600 PCIE GART already initialized\n");
718 /* Initialize common gart structure */
719 r
= amdgpu_gart_init(adev
);
722 adev
->gart
.table_size
= adev
->gart
.num_gpu_pages
* 8;
723 return amdgpu_gart_table_vram_alloc(adev
);
727 * gmc_v8_0_gart_disable - gart disable
729 * @adev: amdgpu_device pointer
731 * This disables all VM page table (CIK).
733 static void gmc_v8_0_gart_disable(struct amdgpu_device
*adev
)
737 /* Disable all tables */
738 WREG32(mmVM_CONTEXT0_CNTL
, 0);
739 WREG32(mmVM_CONTEXT1_CNTL
, 0);
740 /* Setup TLB control */
741 tmp
= RREG32(mmMC_VM_MX_L1_TLB_CNTL
);
742 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_TLB
, 0);
743 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_FRAGMENT_PROCESSING
, 0);
744 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_ADVANCED_DRIVER_MODEL
, 0);
745 WREG32(mmMC_VM_MX_L1_TLB_CNTL
, tmp
);
747 tmp
= RREG32(mmVM_L2_CNTL
);
748 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_CACHE
, 0);
749 WREG32(mmVM_L2_CNTL
, tmp
);
750 WREG32(mmVM_L2_CNTL2
, 0);
751 amdgpu_gart_table_vram_unpin(adev
);
755 * gmc_v8_0_gart_fini - vm fini callback
757 * @adev: amdgpu_device pointer
759 * Tears down the driver GART/VM setup (CIK).
761 static void gmc_v8_0_gart_fini(struct amdgpu_device
*adev
)
763 amdgpu_gart_table_vram_free(adev
);
764 amdgpu_gart_fini(adev
);
769 * VMID 0 is the physical GPU addresses as used by the kernel.
770 * VMIDs 1-15 are used for userspace clients and are handled
771 * by the amdgpu vm/hsa code.
774 * gmc_v8_0_vm_init - cik vm init callback
776 * @adev: amdgpu_device pointer
778 * Inits cik specific vm parameters (number of VMs, base of vram for
780 * Returns 0 for success.
782 static int gmc_v8_0_vm_init(struct amdgpu_device
*adev
)
786 * VMID 0 is reserved for System
787 * amdgpu graphics/compute will use VMIDs 1-7
788 * amdkfd will use VMIDs 8-15
790 adev
->vm_manager
.num_ids
= AMDGPU_NUM_OF_VMIDS
;
791 amdgpu_vm_manager_init(adev
);
793 /* base offset of vram pages */
794 if (adev
->flags
& AMD_IS_APU
) {
795 u64 tmp
= RREG32(mmMC_VM_FB_OFFSET
);
797 adev
->vm_manager
.vram_base_offset
= tmp
;
799 adev
->vm_manager
.vram_base_offset
= 0;
805 * gmc_v8_0_vm_fini - cik vm fini callback
807 * @adev: amdgpu_device pointer
809 * Tear down any asic specific VM setup (CIK).
811 static void gmc_v8_0_vm_fini(struct amdgpu_device
*adev
)
816 * gmc_v8_0_vm_decode_fault - print human readable fault info
818 * @adev: amdgpu_device pointer
819 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
820 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
822 * Print human readable fault information (CIK).
824 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device
*adev
,
825 u32 status
, u32 addr
, u32 mc_client
)
828 u32 vmid
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
, VMID
);
829 u32 protections
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
831 char block
[5] = { mc_client
>> 24, (mc_client
>> 16) & 0xff,
832 (mc_client
>> 8) & 0xff, mc_client
& 0xff, 0 };
834 mc_id
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
837 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
838 protections
, vmid
, addr
,
839 REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
841 "write" : "read", block
, mc_client
, mc_id
);
844 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type
)
846 switch (mc_seq_vram_type
) {
847 case MC_SEQ_MISC0__MT__GDDR1
:
848 return AMDGPU_VRAM_TYPE_GDDR1
;
849 case MC_SEQ_MISC0__MT__DDR2
:
850 return AMDGPU_VRAM_TYPE_DDR2
;
851 case MC_SEQ_MISC0__MT__GDDR3
:
852 return AMDGPU_VRAM_TYPE_GDDR3
;
853 case MC_SEQ_MISC0__MT__GDDR4
:
854 return AMDGPU_VRAM_TYPE_GDDR4
;
855 case MC_SEQ_MISC0__MT__GDDR5
:
856 return AMDGPU_VRAM_TYPE_GDDR5
;
857 case MC_SEQ_MISC0__MT__HBM
:
858 return AMDGPU_VRAM_TYPE_HBM
;
859 case MC_SEQ_MISC0__MT__DDR3
:
860 return AMDGPU_VRAM_TYPE_DDR3
;
862 return AMDGPU_VRAM_TYPE_UNKNOWN
;
866 static int gmc_v8_0_early_init(void *handle
)
868 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
870 gmc_v8_0_set_gart_funcs(adev
);
871 gmc_v8_0_set_irq_funcs(adev
);
876 static int gmc_v8_0_late_init(void *handle
)
878 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
880 if (amdgpu_vm_fault_stop
!= AMDGPU_VM_FAULT_STOP_ALWAYS
)
881 return amdgpu_irq_get(adev
, &adev
->mc
.vm_fault
, 0);
886 #define mmMC_SEQ_MISC0_FIJI 0xA71
888 static int gmc_v8_0_sw_init(void *handle
)
892 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
894 if (adev
->flags
& AMD_IS_APU
) {
895 adev
->mc
.vram_type
= AMDGPU_VRAM_TYPE_UNKNOWN
;
899 if (adev
->asic_type
== CHIP_FIJI
)
900 tmp
= RREG32(mmMC_SEQ_MISC0_FIJI
);
902 tmp
= RREG32(mmMC_SEQ_MISC0
);
903 tmp
&= MC_SEQ_MISC0__MT__MASK
;
904 adev
->mc
.vram_type
= gmc_v8_0_convert_vram_type(tmp
);
907 r
= amdgpu_irq_add_id(adev
, 146, &adev
->mc
.vm_fault
);
911 r
= amdgpu_irq_add_id(adev
, 147, &adev
->mc
.vm_fault
);
915 /* Adjust VM size here.
916 * Currently set to 4GB ((1 << 20) 4k pages).
917 * Max GPUVM size for cayman and SI is 40 bits.
919 adev
->vm_manager
.max_pfn
= amdgpu_vm_size
<< 18;
921 /* Set the internal MC address mask
922 * This is the max address of the GPU's
923 * internal address space.
925 adev
->mc
.mc_mask
= 0xffffffffffULL
; /* 40 bit MC */
927 /* set DMA mask + need_dma32 flags.
928 * PCIE - can handle 40-bits.
929 * IGP - can handle 40-bits
930 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
932 adev
->need_dma32
= false;
933 dma_bits
= adev
->need_dma32
? 32 : 40;
934 r
= pci_set_dma_mask(adev
->pdev
, DMA_BIT_MASK(dma_bits
));
936 adev
->need_dma32
= true;
938 printk(KERN_WARNING
"amdgpu: No suitable DMA available.\n");
940 r
= pci_set_consistent_dma_mask(adev
->pdev
, DMA_BIT_MASK(dma_bits
));
942 pci_set_consistent_dma_mask(adev
->pdev
, DMA_BIT_MASK(32));
943 printk(KERN_WARNING
"amdgpu: No coherent DMA available.\n");
946 r
= gmc_v8_0_init_microcode(adev
);
948 DRM_ERROR("Failed to load mc firmware!\n");
952 r
= gmc_v8_0_mc_init(adev
);
957 r
= amdgpu_bo_init(adev
);
961 r
= gmc_v8_0_gart_init(adev
);
965 if (!adev
->vm_manager
.enabled
) {
966 r
= gmc_v8_0_vm_init(adev
);
968 dev_err(adev
->dev
, "vm manager initialization failed (%d).\n", r
);
971 adev
->vm_manager
.enabled
= true;
977 static int gmc_v8_0_sw_fini(void *handle
)
979 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
981 if (adev
->vm_manager
.enabled
) {
982 amdgpu_vm_manager_fini(adev
);
983 gmc_v8_0_vm_fini(adev
);
984 adev
->vm_manager
.enabled
= false;
986 gmc_v8_0_gart_fini(adev
);
987 amdgpu_gem_force_release(adev
);
988 amdgpu_bo_fini(adev
);
993 static int gmc_v8_0_hw_init(void *handle
)
996 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
998 gmc_v8_0_init_golden_registers(adev
);
1000 gmc_v8_0_mc_program(adev
);
1002 if (adev
->asic_type
== CHIP_TONGA
) {
1003 r
= gmc_v8_0_mc_load_microcode(adev
);
1005 DRM_ERROR("Failed to load MC firmware!\n");
1010 r
= gmc_v8_0_gart_enable(adev
);
1017 static int gmc_v8_0_hw_fini(void *handle
)
1019 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1021 amdgpu_irq_put(adev
, &adev
->mc
.vm_fault
, 0);
1022 gmc_v8_0_gart_disable(adev
);
1027 static int gmc_v8_0_suspend(void *handle
)
1029 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1031 if (adev
->vm_manager
.enabled
) {
1032 gmc_v8_0_vm_fini(adev
);
1033 adev
->vm_manager
.enabled
= false;
1035 gmc_v8_0_hw_fini(adev
);
1040 static int gmc_v8_0_resume(void *handle
)
1043 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1045 r
= gmc_v8_0_hw_init(adev
);
1049 if (!adev
->vm_manager
.enabled
) {
1050 r
= gmc_v8_0_vm_init(adev
);
1052 dev_err(adev
->dev
, "vm manager initialization failed (%d).\n", r
);
1055 adev
->vm_manager
.enabled
= true;
1061 static bool gmc_v8_0_is_idle(void *handle
)
1063 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1064 u32 tmp
= RREG32(mmSRBM_STATUS
);
1066 if (tmp
& (SRBM_STATUS__MCB_BUSY_MASK
| SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
1067 SRBM_STATUS__MCC_BUSY_MASK
| SRBM_STATUS__MCD_BUSY_MASK
| SRBM_STATUS__VMC_BUSY_MASK
))
1073 static int gmc_v8_0_wait_for_idle(void *handle
)
1077 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1079 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1080 /* read MC_STATUS */
1081 tmp
= RREG32(mmSRBM_STATUS
) & (SRBM_STATUS__MCB_BUSY_MASK
|
1082 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
1083 SRBM_STATUS__MCC_BUSY_MASK
|
1084 SRBM_STATUS__MCD_BUSY_MASK
|
1085 SRBM_STATUS__VMC_BUSY_MASK
|
1086 SRBM_STATUS__VMC1_BUSY_MASK
);
1095 static int gmc_v8_0_soft_reset(void *handle
)
1097 struct amdgpu_mode_mc_save save
;
1098 u32 srbm_soft_reset
= 0;
1099 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1100 u32 tmp
= RREG32(mmSRBM_STATUS
);
1102 if (tmp
& SRBM_STATUS__VMC_BUSY_MASK
)
1103 srbm_soft_reset
= REG_SET_FIELD(srbm_soft_reset
,
1104 SRBM_SOFT_RESET
, SOFT_RESET_VMC
, 1);
1106 if (tmp
& (SRBM_STATUS__MCB_BUSY_MASK
| SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
1107 SRBM_STATUS__MCC_BUSY_MASK
| SRBM_STATUS__MCD_BUSY_MASK
)) {
1108 if (!(adev
->flags
& AMD_IS_APU
))
1109 srbm_soft_reset
= REG_SET_FIELD(srbm_soft_reset
,
1110 SRBM_SOFT_RESET
, SOFT_RESET_MC
, 1);
1113 if (srbm_soft_reset
) {
1114 gmc_v8_0_mc_stop(adev
, &save
);
1115 if (gmc_v8_0_wait_for_idle((void *)adev
)) {
1116 dev_warn(adev
->dev
, "Wait for GMC idle timed out !\n");
1120 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1121 tmp
|= srbm_soft_reset
;
1122 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1123 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1124 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1128 tmp
&= ~srbm_soft_reset
;
1129 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1130 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1132 /* Wait a little for things to settle down */
1135 gmc_v8_0_mc_resume(adev
, &save
);
1142 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device
*adev
,
1143 struct amdgpu_irq_src
*src
,
1145 enum amdgpu_interrupt_state state
)
1148 u32 bits
= (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1149 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1150 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1151 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1152 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1153 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1154 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
);
1157 case AMDGPU_IRQ_STATE_DISABLE
:
1158 /* system context */
1159 tmp
= RREG32(mmVM_CONTEXT0_CNTL
);
1161 WREG32(mmVM_CONTEXT0_CNTL
, tmp
);
1163 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
1165 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
1167 case AMDGPU_IRQ_STATE_ENABLE
:
1168 /* system context */
1169 tmp
= RREG32(mmVM_CONTEXT0_CNTL
);
1171 WREG32(mmVM_CONTEXT0_CNTL
, tmp
);
1173 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
1175 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
1184 static int gmc_v8_0_process_interrupt(struct amdgpu_device
*adev
,
1185 struct amdgpu_irq_src
*source
,
1186 struct amdgpu_iv_entry
*entry
)
1188 u32 addr
, status
, mc_client
;
1190 addr
= RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR
);
1191 status
= RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS
);
1192 mc_client
= RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT
);
1193 /* reset addr and status */
1194 WREG32_P(mmVM_CONTEXT1_CNTL2
, 1, ~1);
1196 if (!addr
&& !status
)
1199 if (amdgpu_vm_fault_stop
== AMDGPU_VM_FAULT_STOP_FIRST
)
1200 gmc_v8_0_set_fault_enable_default(adev
, false);
1202 dev_err(adev
->dev
, "GPU fault detected: %d 0x%08x\n",
1203 entry
->src_id
, entry
->src_data
);
1204 dev_err(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1206 dev_err(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1208 gmc_v8_0_vm_decode_fault(adev
, status
, addr
, mc_client
);
1213 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device
*adev
,
1218 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_MC_MGCG
)) {
1219 data
= RREG32(mmMC_HUB_MISC_HUB_CG
);
1220 data
|= MC_HUB_MISC_HUB_CG__ENABLE_MASK
;
1221 WREG32(mmMC_HUB_MISC_HUB_CG
, data
);
1223 data
= RREG32(mmMC_HUB_MISC_SIP_CG
);
1224 data
|= MC_HUB_MISC_SIP_CG__ENABLE_MASK
;
1225 WREG32(mmMC_HUB_MISC_SIP_CG
, data
);
1227 data
= RREG32(mmMC_HUB_MISC_VM_CG
);
1228 data
|= MC_HUB_MISC_VM_CG__ENABLE_MASK
;
1229 WREG32(mmMC_HUB_MISC_VM_CG
, data
);
1231 data
= RREG32(mmMC_XPB_CLK_GAT
);
1232 data
|= MC_XPB_CLK_GAT__ENABLE_MASK
;
1233 WREG32(mmMC_XPB_CLK_GAT
, data
);
1235 data
= RREG32(mmATC_MISC_CG
);
1236 data
|= ATC_MISC_CG__ENABLE_MASK
;
1237 WREG32(mmATC_MISC_CG
, data
);
1239 data
= RREG32(mmMC_CITF_MISC_WR_CG
);
1240 data
|= MC_CITF_MISC_WR_CG__ENABLE_MASK
;
1241 WREG32(mmMC_CITF_MISC_WR_CG
, data
);
1243 data
= RREG32(mmMC_CITF_MISC_RD_CG
);
1244 data
|= MC_CITF_MISC_RD_CG__ENABLE_MASK
;
1245 WREG32(mmMC_CITF_MISC_RD_CG
, data
);
1247 data
= RREG32(mmMC_CITF_MISC_VM_CG
);
1248 data
|= MC_CITF_MISC_VM_CG__ENABLE_MASK
;
1249 WREG32(mmMC_CITF_MISC_VM_CG
, data
);
1251 data
= RREG32(mmVM_L2_CG
);
1252 data
|= VM_L2_CG__ENABLE_MASK
;
1253 WREG32(mmVM_L2_CG
, data
);
1255 data
= RREG32(mmMC_HUB_MISC_HUB_CG
);
1256 data
&= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK
;
1257 WREG32(mmMC_HUB_MISC_HUB_CG
, data
);
1259 data
= RREG32(mmMC_HUB_MISC_SIP_CG
);
1260 data
&= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK
;
1261 WREG32(mmMC_HUB_MISC_SIP_CG
, data
);
1263 data
= RREG32(mmMC_HUB_MISC_VM_CG
);
1264 data
&= ~MC_HUB_MISC_VM_CG__ENABLE_MASK
;
1265 WREG32(mmMC_HUB_MISC_VM_CG
, data
);
1267 data
= RREG32(mmMC_XPB_CLK_GAT
);
1268 data
&= ~MC_XPB_CLK_GAT__ENABLE_MASK
;
1269 WREG32(mmMC_XPB_CLK_GAT
, data
);
1271 data
= RREG32(mmATC_MISC_CG
);
1272 data
&= ~ATC_MISC_CG__ENABLE_MASK
;
1273 WREG32(mmATC_MISC_CG
, data
);
1275 data
= RREG32(mmMC_CITF_MISC_WR_CG
);
1276 data
&= ~MC_CITF_MISC_WR_CG__ENABLE_MASK
;
1277 WREG32(mmMC_CITF_MISC_WR_CG
, data
);
1279 data
= RREG32(mmMC_CITF_MISC_RD_CG
);
1280 data
&= ~MC_CITF_MISC_RD_CG__ENABLE_MASK
;
1281 WREG32(mmMC_CITF_MISC_RD_CG
, data
);
1283 data
= RREG32(mmMC_CITF_MISC_VM_CG
);
1284 data
&= ~MC_CITF_MISC_VM_CG__ENABLE_MASK
;
1285 WREG32(mmMC_CITF_MISC_VM_CG
, data
);
1287 data
= RREG32(mmVM_L2_CG
);
1288 data
&= ~VM_L2_CG__ENABLE_MASK
;
1289 WREG32(mmVM_L2_CG
, data
);
1293 static void fiji_update_mc_light_sleep(struct amdgpu_device
*adev
,
1298 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_MC_LS
)) {
1299 data
= RREG32(mmMC_HUB_MISC_HUB_CG
);
1300 data
|= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK
;
1301 WREG32(mmMC_HUB_MISC_HUB_CG
, data
);
1303 data
= RREG32(mmMC_HUB_MISC_SIP_CG
);
1304 data
|= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK
;
1305 WREG32(mmMC_HUB_MISC_SIP_CG
, data
);
1307 data
= RREG32(mmMC_HUB_MISC_VM_CG
);
1308 data
|= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK
;
1309 WREG32(mmMC_HUB_MISC_VM_CG
, data
);
1311 data
= RREG32(mmMC_XPB_CLK_GAT
);
1312 data
|= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK
;
1313 WREG32(mmMC_XPB_CLK_GAT
, data
);
1315 data
= RREG32(mmATC_MISC_CG
);
1316 data
|= ATC_MISC_CG__MEM_LS_ENABLE_MASK
;
1317 WREG32(mmATC_MISC_CG
, data
);
1319 data
= RREG32(mmMC_CITF_MISC_WR_CG
);
1320 data
|= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK
;
1321 WREG32(mmMC_CITF_MISC_WR_CG
, data
);
1323 data
= RREG32(mmMC_CITF_MISC_RD_CG
);
1324 data
|= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK
;
1325 WREG32(mmMC_CITF_MISC_RD_CG
, data
);
1327 data
= RREG32(mmMC_CITF_MISC_VM_CG
);
1328 data
|= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK
;
1329 WREG32(mmMC_CITF_MISC_VM_CG
, data
);
1331 data
= RREG32(mmVM_L2_CG
);
1332 data
|= VM_L2_CG__MEM_LS_ENABLE_MASK
;
1333 WREG32(mmVM_L2_CG
, data
);
1335 data
= RREG32(mmMC_HUB_MISC_HUB_CG
);
1336 data
&= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK
;
1337 WREG32(mmMC_HUB_MISC_HUB_CG
, data
);
1339 data
= RREG32(mmMC_HUB_MISC_SIP_CG
);
1340 data
&= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK
;
1341 WREG32(mmMC_HUB_MISC_SIP_CG
, data
);
1343 data
= RREG32(mmMC_HUB_MISC_VM_CG
);
1344 data
&= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK
;
1345 WREG32(mmMC_HUB_MISC_VM_CG
, data
);
1347 data
= RREG32(mmMC_XPB_CLK_GAT
);
1348 data
&= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK
;
1349 WREG32(mmMC_XPB_CLK_GAT
, data
);
1351 data
= RREG32(mmATC_MISC_CG
);
1352 data
&= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK
;
1353 WREG32(mmATC_MISC_CG
, data
);
1355 data
= RREG32(mmMC_CITF_MISC_WR_CG
);
1356 data
&= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK
;
1357 WREG32(mmMC_CITF_MISC_WR_CG
, data
);
1359 data
= RREG32(mmMC_CITF_MISC_RD_CG
);
1360 data
&= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK
;
1361 WREG32(mmMC_CITF_MISC_RD_CG
, data
);
1363 data
= RREG32(mmMC_CITF_MISC_VM_CG
);
1364 data
&= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK
;
1365 WREG32(mmMC_CITF_MISC_VM_CG
, data
);
1367 data
= RREG32(mmVM_L2_CG
);
1368 data
&= ~VM_L2_CG__MEM_LS_ENABLE_MASK
;
1369 WREG32(mmVM_L2_CG
, data
);
1373 static int gmc_v8_0_set_clockgating_state(void *handle
,
1374 enum amd_clockgating_state state
)
1376 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1378 switch (adev
->asic_type
) {
1380 fiji_update_mc_medium_grain_clock_gating(adev
,
1381 state
== AMD_CG_STATE_GATE
? true : false);
1382 fiji_update_mc_light_sleep(adev
,
1383 state
== AMD_CG_STATE_GATE
? true : false);
1391 static int gmc_v8_0_set_powergating_state(void *handle
,
1392 enum amd_powergating_state state
)
1397 const struct amd_ip_funcs gmc_v8_0_ip_funcs
= {
1399 .early_init
= gmc_v8_0_early_init
,
1400 .late_init
= gmc_v8_0_late_init
,
1401 .sw_init
= gmc_v8_0_sw_init
,
1402 .sw_fini
= gmc_v8_0_sw_fini
,
1403 .hw_init
= gmc_v8_0_hw_init
,
1404 .hw_fini
= gmc_v8_0_hw_fini
,
1405 .suspend
= gmc_v8_0_suspend
,
1406 .resume
= gmc_v8_0_resume
,
1407 .is_idle
= gmc_v8_0_is_idle
,
1408 .wait_for_idle
= gmc_v8_0_wait_for_idle
,
1409 .soft_reset
= gmc_v8_0_soft_reset
,
1410 .set_clockgating_state
= gmc_v8_0_set_clockgating_state
,
1411 .set_powergating_state
= gmc_v8_0_set_powergating_state
,
1414 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs
= {
1415 .flush_gpu_tlb
= gmc_v8_0_gart_flush_gpu_tlb
,
1416 .set_pte_pde
= gmc_v8_0_gart_set_pte_pde
,
1419 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs
= {
1420 .set
= gmc_v8_0_vm_fault_interrupt_state
,
1421 .process
= gmc_v8_0_process_interrupt
,
1424 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device
*adev
)
1426 if (adev
->gart
.gart_funcs
== NULL
)
1427 adev
->gart
.gart_funcs
= &gmc_v8_0_gart_funcs
;
1430 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device
*adev
)
1432 adev
->mc
.vm_fault
.num_types
= 1;
1433 adev
->mc
.vm_fault
.funcs
= &gmc_v8_0_irq_funcs
;