2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "amdgpu_pm.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_dpm.h"
33 #include <linux/seq_file.h>
35 #include "smu/smu_7_0_0_d.h"
36 #include "smu/smu_7_0_0_sh_mask.h"
38 #include "gca/gfx_7_2_d.h"
39 #include "gca/gfx_7_2_sh_mask.h"
41 #define KV_MAX_DEEPSLEEP_DIVIDER_ID 5
42 #define KV_MINIMUM_ENGINE_CLOCK 800
43 #define SMC_RAM_END 0x40000
45 static void kv_dpm_set_dpm_funcs(struct amdgpu_device
*adev
);
46 static void kv_dpm_set_irq_funcs(struct amdgpu_device
*adev
);
47 static int kv_enable_nb_dpm(struct amdgpu_device
*adev
,
49 static void kv_init_graphics_levels(struct amdgpu_device
*adev
);
50 static int kv_calculate_ds_divider(struct amdgpu_device
*adev
);
51 static int kv_calculate_nbps_level_settings(struct amdgpu_device
*adev
);
52 static int kv_calculate_dpm_settings(struct amdgpu_device
*adev
);
53 static void kv_enable_new_levels(struct amdgpu_device
*adev
);
54 static void kv_program_nbps_index_settings(struct amdgpu_device
*adev
,
55 struct amdgpu_ps
*new_rps
);
56 static int kv_set_enabled_level(struct amdgpu_device
*adev
, u32 level
);
57 static int kv_set_enabled_levels(struct amdgpu_device
*adev
);
58 static int kv_force_dpm_highest(struct amdgpu_device
*adev
);
59 static int kv_force_dpm_lowest(struct amdgpu_device
*adev
);
60 static void kv_apply_state_adjust_rules(struct amdgpu_device
*adev
,
61 struct amdgpu_ps
*new_rps
,
62 struct amdgpu_ps
*old_rps
);
63 static int kv_set_thermal_temperature_range(struct amdgpu_device
*adev
,
64 int min_temp
, int max_temp
);
65 static int kv_init_fps_limits(struct amdgpu_device
*adev
);
67 static void kv_dpm_powergate_uvd(struct amdgpu_device
*adev
, bool gate
);
68 static void kv_dpm_powergate_vce(struct amdgpu_device
*adev
, bool gate
);
69 static void kv_dpm_powergate_samu(struct amdgpu_device
*adev
, bool gate
);
70 static void kv_dpm_powergate_acp(struct amdgpu_device
*adev
, bool gate
);
73 static u32
kv_convert_vid2_to_vid7(struct amdgpu_device
*adev
,
74 struct sumo_vid_mapping_table
*vid_mapping_table
,
77 struct amdgpu_clock_voltage_dependency_table
*vddc_sclk_table
=
78 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
;
81 if (vddc_sclk_table
&& vddc_sclk_table
->count
) {
82 if (vid_2bit
< vddc_sclk_table
->count
)
83 return vddc_sclk_table
->entries
[vid_2bit
].v
;
85 return vddc_sclk_table
->entries
[vddc_sclk_table
->count
- 1].v
;
87 for (i
= 0; i
< vid_mapping_table
->num_entries
; i
++) {
88 if (vid_mapping_table
->entries
[i
].vid_2bit
== vid_2bit
)
89 return vid_mapping_table
->entries
[i
].vid_7bit
;
91 return vid_mapping_table
->entries
[vid_mapping_table
->num_entries
- 1].vid_7bit
;
95 static u32
kv_convert_vid7_to_vid2(struct amdgpu_device
*adev
,
96 struct sumo_vid_mapping_table
*vid_mapping_table
,
99 struct amdgpu_clock_voltage_dependency_table
*vddc_sclk_table
=
100 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
;
103 if (vddc_sclk_table
&& vddc_sclk_table
->count
) {
104 for (i
= 0; i
< vddc_sclk_table
->count
; i
++) {
105 if (vddc_sclk_table
->entries
[i
].v
== vid_7bit
)
108 return vddc_sclk_table
->count
- 1;
110 for (i
= 0; i
< vid_mapping_table
->num_entries
; i
++) {
111 if (vid_mapping_table
->entries
[i
].vid_7bit
== vid_7bit
)
112 return vid_mapping_table
->entries
[i
].vid_2bit
;
115 return vid_mapping_table
->entries
[vid_mapping_table
->num_entries
- 1].vid_2bit
;
119 static void sumo_take_smu_control(struct amdgpu_device
*adev
, bool enable
)
121 /* This bit selects who handles display phy powergating.
122 * Clear the bit to let atom handle it.
123 * Set it to let the driver handle it.
124 * For now we just let atom handle it.
127 u32 v
= RREG32(mmDOUT_SCRATCH3
);
134 WREG32(mmDOUT_SCRATCH3
, v
);
138 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device
*adev
,
139 struct sumo_sclk_voltage_mapping_table
*sclk_voltage_mapping_table
,
140 ATOM_AVAILABLE_SCLK_LIST
*table
)
146 for (i
= 0; i
< SUMO_MAX_HARDWARE_POWERLEVELS
; i
++) {
147 if (table
[i
].ulSupportedSCLK
> prev_sclk
) {
148 sclk_voltage_mapping_table
->entries
[n
].sclk_frequency
=
149 table
[i
].ulSupportedSCLK
;
150 sclk_voltage_mapping_table
->entries
[n
].vid_2bit
=
151 table
[i
].usVoltageIndex
;
152 prev_sclk
= table
[i
].ulSupportedSCLK
;
157 sclk_voltage_mapping_table
->num_max_dpm_entries
= n
;
160 static void sumo_construct_vid_mapping_table(struct amdgpu_device
*adev
,
161 struct sumo_vid_mapping_table
*vid_mapping_table
,
162 ATOM_AVAILABLE_SCLK_LIST
*table
)
166 for (i
= 0; i
< SUMO_MAX_HARDWARE_POWERLEVELS
; i
++) {
167 if (table
[i
].ulSupportedSCLK
!= 0) {
168 vid_mapping_table
->entries
[table
[i
].usVoltageIndex
].vid_7bit
=
169 table
[i
].usVoltageID
;
170 vid_mapping_table
->entries
[table
[i
].usVoltageIndex
].vid_2bit
=
171 table
[i
].usVoltageIndex
;
175 for (i
= 0; i
< SUMO_MAX_NUMBER_VOLTAGES
; i
++) {
176 if (vid_mapping_table
->entries
[i
].vid_7bit
== 0) {
177 for (j
= i
+ 1; j
< SUMO_MAX_NUMBER_VOLTAGES
; j
++) {
178 if (vid_mapping_table
->entries
[j
].vid_7bit
!= 0) {
179 vid_mapping_table
->entries
[i
] =
180 vid_mapping_table
->entries
[j
];
181 vid_mapping_table
->entries
[j
].vid_7bit
= 0;
186 if (j
== SUMO_MAX_NUMBER_VOLTAGES
)
191 vid_mapping_table
->num_entries
= i
;
195 static const struct kv_lcac_config_values sx_local_cac_cfg_kv
[] =
208 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv
[] =
214 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv
[] =
220 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv
[] =
226 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv
[] =
232 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv
[] =
264 static const struct kv_lcac_config_reg sx0_cac_config_reg
[] =
266 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
269 static const struct kv_lcac_config_reg mc0_cac_config_reg
[] =
271 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
274 static const struct kv_lcac_config_reg mc1_cac_config_reg
[] =
276 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
279 static const struct kv_lcac_config_reg mc2_cac_config_reg
[] =
281 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
284 static const struct kv_lcac_config_reg mc3_cac_config_reg
[] =
286 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
289 static const struct kv_lcac_config_reg cpl_cac_config_reg
[] =
291 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
295 static const struct kv_pt_config_reg didt_config_kv
[] =
297 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
298 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
299 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
300 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
301 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
302 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
303 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
304 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
305 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
306 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
307 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
308 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
309 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND
},
310 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND
},
311 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND
},
312 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND
},
313 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND
},
314 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
315 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
316 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
317 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
318 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
319 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
320 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
321 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
322 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
323 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
324 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
325 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
326 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
327 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND
},
328 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND
},
329 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND
},
330 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND
},
331 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND
},
332 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
333 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
334 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
335 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
336 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
337 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
338 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
339 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
340 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
341 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
342 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
343 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
344 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
345 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND
},
346 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND
},
347 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND
},
348 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND
},
349 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND
},
350 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
351 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
352 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
353 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
354 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
355 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
356 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
357 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
358 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
359 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
360 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND
},
361 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND
},
362 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND
},
363 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND
},
364 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND
},
365 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND
},
366 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND
},
367 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND
},
368 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND
},
372 static struct kv_ps
*kv_get_ps(struct amdgpu_ps
*rps
)
374 struct kv_ps
*ps
= rps
->ps_priv
;
379 static struct kv_power_info
*kv_get_pi(struct amdgpu_device
*adev
)
381 struct kv_power_info
*pi
= adev
->pm
.dpm
.priv
;
387 static void kv_program_local_cac_table(struct amdgpu_device
*adev
,
388 const struct kv_lcac_config_values
*local_cac_table
,
389 const struct kv_lcac_config_reg
*local_cac_reg
)
392 const struct kv_lcac_config_values
*values
= local_cac_table
;
394 while (values
->block_id
!= 0xffffffff) {
395 count
= values
->signal_id
;
396 for (i
= 0; i
< count
; i
++) {
397 data
= ((values
->block_id
<< local_cac_reg
->block_shift
) &
398 local_cac_reg
->block_mask
);
399 data
|= ((i
<< local_cac_reg
->signal_shift
) &
400 local_cac_reg
->signal_mask
);
401 data
|= ((values
->t
<< local_cac_reg
->t_shift
) &
402 local_cac_reg
->t_mask
);
403 data
|= ((1 << local_cac_reg
->enable_shift
) &
404 local_cac_reg
->enable_mask
);
405 WREG32_SMC(local_cac_reg
->cntl
, data
);
412 static int kv_program_pt_config_registers(struct amdgpu_device
*adev
,
413 const struct kv_pt_config_reg
*cac_config_regs
)
415 const struct kv_pt_config_reg
*config_regs
= cac_config_regs
;
419 if (config_regs
== NULL
)
422 while (config_regs
->offset
!= 0xFFFFFFFF) {
423 if (config_regs
->type
== KV_CONFIGREG_CACHE
) {
424 cache
|= ((config_regs
->value
<< config_regs
->shift
) & config_regs
->mask
);
426 switch (config_regs
->type
) {
427 case KV_CONFIGREG_SMC_IND
:
428 data
= RREG32_SMC(config_regs
->offset
);
430 case KV_CONFIGREG_DIDT_IND
:
431 data
= RREG32_DIDT(config_regs
->offset
);
434 data
= RREG32(config_regs
->offset
);
438 data
&= ~config_regs
->mask
;
439 data
|= ((config_regs
->value
<< config_regs
->shift
) & config_regs
->mask
);
443 switch (config_regs
->type
) {
444 case KV_CONFIGREG_SMC_IND
:
445 WREG32_SMC(config_regs
->offset
, data
);
447 case KV_CONFIGREG_DIDT_IND
:
448 WREG32_DIDT(config_regs
->offset
, data
);
451 WREG32(config_regs
->offset
, data
);
461 static void kv_do_enable_didt(struct amdgpu_device
*adev
, bool enable
)
463 struct kv_power_info
*pi
= kv_get_pi(adev
);
466 if (pi
->caps_sq_ramping
) {
467 data
= RREG32_DIDT(ixDIDT_SQ_CTRL0
);
469 data
|= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK
;
471 data
&= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK
;
472 WREG32_DIDT(ixDIDT_SQ_CTRL0
, data
);
475 if (pi
->caps_db_ramping
) {
476 data
= RREG32_DIDT(ixDIDT_DB_CTRL0
);
478 data
|= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK
;
480 data
&= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK
;
481 WREG32_DIDT(ixDIDT_DB_CTRL0
, data
);
484 if (pi
->caps_td_ramping
) {
485 data
= RREG32_DIDT(ixDIDT_TD_CTRL0
);
487 data
|= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK
;
489 data
&= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK
;
490 WREG32_DIDT(ixDIDT_TD_CTRL0
, data
);
493 if (pi
->caps_tcp_ramping
) {
494 data
= RREG32_DIDT(ixDIDT_TCP_CTRL0
);
496 data
|= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK
;
498 data
&= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK
;
499 WREG32_DIDT(ixDIDT_TCP_CTRL0
, data
);
503 static int kv_enable_didt(struct amdgpu_device
*adev
, bool enable
)
505 struct kv_power_info
*pi
= kv_get_pi(adev
);
508 if (pi
->caps_sq_ramping
||
509 pi
->caps_db_ramping
||
510 pi
->caps_td_ramping
||
511 pi
->caps_tcp_ramping
) {
512 adev
->gfx
.rlc
.funcs
->enter_safe_mode(adev
);
515 ret
= kv_program_pt_config_registers(adev
, didt_config_kv
);
517 adev
->gfx
.rlc
.funcs
->exit_safe_mode(adev
);
522 kv_do_enable_didt(adev
, enable
);
524 adev
->gfx
.rlc
.funcs
->exit_safe_mode(adev
);
531 static void kv_initialize_hardware_cac_manager(struct amdgpu_device
*adev
)
533 struct kv_power_info
*pi
= kv_get_pi(adev
);
536 WREG32_SMC(ixLCAC_SX0_OVR_SEL
, 0);
537 WREG32_SMC(ixLCAC_SX0_OVR_VAL
, 0);
538 kv_program_local_cac_table(adev
, sx_local_cac_cfg_kv
, sx0_cac_config_reg
);
540 WREG32_SMC(ixLCAC_MC0_OVR_SEL
, 0);
541 WREG32_SMC(ixLCAC_MC0_OVR_VAL
, 0);
542 kv_program_local_cac_table(adev
, mc0_local_cac_cfg_kv
, mc0_cac_config_reg
);
544 WREG32_SMC(ixLCAC_MC1_OVR_SEL
, 0);
545 WREG32_SMC(ixLCAC_MC1_OVR_VAL
, 0);
546 kv_program_local_cac_table(adev
, mc1_local_cac_cfg_kv
, mc1_cac_config_reg
);
548 WREG32_SMC(ixLCAC_MC2_OVR_SEL
, 0);
549 WREG32_SMC(ixLCAC_MC2_OVR_VAL
, 0);
550 kv_program_local_cac_table(adev
, mc2_local_cac_cfg_kv
, mc2_cac_config_reg
);
552 WREG32_SMC(ixLCAC_MC3_OVR_SEL
, 0);
553 WREG32_SMC(ixLCAC_MC3_OVR_VAL
, 0);
554 kv_program_local_cac_table(adev
, mc3_local_cac_cfg_kv
, mc3_cac_config_reg
);
556 WREG32_SMC(ixLCAC_CPL_OVR_SEL
, 0);
557 WREG32_SMC(ixLCAC_CPL_OVR_VAL
, 0);
558 kv_program_local_cac_table(adev
, cpl_local_cac_cfg_kv
, cpl_cac_config_reg
);
563 static int kv_enable_smc_cac(struct amdgpu_device
*adev
, bool enable
)
565 struct kv_power_info
*pi
= kv_get_pi(adev
);
570 ret
= amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_EnableCac
);
572 pi
->cac_enabled
= false;
574 pi
->cac_enabled
= true;
575 } else if (pi
->cac_enabled
) {
576 amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_DisableCac
);
577 pi
->cac_enabled
= false;
584 static int kv_process_firmware_header(struct amdgpu_device
*adev
)
586 struct kv_power_info
*pi
= kv_get_pi(adev
);
590 ret
= amdgpu_kv_read_smc_sram_dword(adev
, SMU7_FIRMWARE_HEADER_LOCATION
+
591 offsetof(SMU7_Firmware_Header
, DpmTable
),
595 pi
->dpm_table_start
= tmp
;
597 ret
= amdgpu_kv_read_smc_sram_dword(adev
, SMU7_FIRMWARE_HEADER_LOCATION
+
598 offsetof(SMU7_Firmware_Header
, SoftRegisters
),
602 pi
->soft_regs_start
= tmp
;
607 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device
*adev
)
609 struct kv_power_info
*pi
= kv_get_pi(adev
);
612 pi
->graphics_voltage_change_enable
= 1;
614 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
615 pi
->dpm_table_start
+
616 offsetof(SMU7_Fusion_DpmTable
, GraphicsVoltageChangeEnable
),
617 &pi
->graphics_voltage_change_enable
,
618 sizeof(u8
), pi
->sram_end
);
623 static int kv_set_dpm_interval(struct amdgpu_device
*adev
)
625 struct kv_power_info
*pi
= kv_get_pi(adev
);
628 pi
->graphics_interval
= 1;
630 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
631 pi
->dpm_table_start
+
632 offsetof(SMU7_Fusion_DpmTable
, GraphicsInterval
),
633 &pi
->graphics_interval
,
634 sizeof(u8
), pi
->sram_end
);
639 static int kv_set_dpm_boot_state(struct amdgpu_device
*adev
)
641 struct kv_power_info
*pi
= kv_get_pi(adev
);
644 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
645 pi
->dpm_table_start
+
646 offsetof(SMU7_Fusion_DpmTable
, GraphicsBootLevel
),
647 &pi
->graphics_boot_level
,
648 sizeof(u8
), pi
->sram_end
);
653 static void kv_program_vc(struct amdgpu_device
*adev
)
655 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0
, 0x3FFFC100);
658 static void kv_clear_vc(struct amdgpu_device
*adev
)
660 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0
, 0);
663 static int kv_set_divider_value(struct amdgpu_device
*adev
,
666 struct kv_power_info
*pi
= kv_get_pi(adev
);
667 struct atom_clock_dividers dividers
;
670 ret
= amdgpu_atombios_get_clock_dividers(adev
, COMPUTE_ENGINE_PLL_PARAM
,
671 sclk
, false, ÷rs
);
675 pi
->graphics_level
[index
].SclkDid
= (u8
)dividers
.post_div
;
676 pi
->graphics_level
[index
].SclkFrequency
= cpu_to_be32(sclk
);
681 static u16
kv_convert_8bit_index_to_voltage(struct amdgpu_device
*adev
,
684 return 6200 - (voltage
* 25);
687 static u16
kv_convert_2bit_index_to_voltage(struct amdgpu_device
*adev
,
690 struct kv_power_info
*pi
= kv_get_pi(adev
);
691 u32 vid_8bit
= kv_convert_vid2_to_vid7(adev
,
692 &pi
->sys_info
.vid_mapping_table
,
695 return kv_convert_8bit_index_to_voltage(adev
, (u16
)vid_8bit
);
699 static int kv_set_vid(struct amdgpu_device
*adev
, u32 index
, u32 vid
)
701 struct kv_power_info
*pi
= kv_get_pi(adev
);
703 pi
->graphics_level
[index
].VoltageDownH
= (u8
)pi
->voltage_drop_t
;
704 pi
->graphics_level
[index
].MinVddNb
=
705 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev
, vid
));
710 static int kv_set_at(struct amdgpu_device
*adev
, u32 index
, u32 at
)
712 struct kv_power_info
*pi
= kv_get_pi(adev
);
714 pi
->graphics_level
[index
].AT
= cpu_to_be16((u16
)at
);
719 static void kv_dpm_power_level_enable(struct amdgpu_device
*adev
,
720 u32 index
, bool enable
)
722 struct kv_power_info
*pi
= kv_get_pi(adev
);
724 pi
->graphics_level
[index
].EnabledForActivity
= enable
? 1 : 0;
727 static void kv_start_dpm(struct amdgpu_device
*adev
)
729 u32 tmp
= RREG32_SMC(ixGENERAL_PWRMGT
);
731 tmp
|= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK
;
732 WREG32_SMC(ixGENERAL_PWRMGT
, tmp
);
734 amdgpu_kv_smc_dpm_enable(adev
, true);
737 static void kv_stop_dpm(struct amdgpu_device
*adev
)
739 amdgpu_kv_smc_dpm_enable(adev
, false);
742 static void kv_start_am(struct amdgpu_device
*adev
)
744 u32 sclk_pwrmgt_cntl
= RREG32_SMC(ixSCLK_PWRMGT_CNTL
);
746 sclk_pwrmgt_cntl
&= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK
|
747 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK
);
748 sclk_pwrmgt_cntl
|= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK
;
750 WREG32_SMC(ixSCLK_PWRMGT_CNTL
, sclk_pwrmgt_cntl
);
753 static void kv_reset_am(struct amdgpu_device
*adev
)
755 u32 sclk_pwrmgt_cntl
= RREG32_SMC(ixSCLK_PWRMGT_CNTL
);
757 sclk_pwrmgt_cntl
|= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK
|
758 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK
);
760 WREG32_SMC(ixSCLK_PWRMGT_CNTL
, sclk_pwrmgt_cntl
);
763 static int kv_freeze_sclk_dpm(struct amdgpu_device
*adev
, bool freeze
)
765 return amdgpu_kv_notify_message_to_smu(adev
, freeze
?
766 PPSMC_MSG_SCLKDPM_FreezeLevel
: PPSMC_MSG_SCLKDPM_UnfreezeLevel
);
769 static int kv_force_lowest_valid(struct amdgpu_device
*adev
)
771 return kv_force_dpm_lowest(adev
);
774 static int kv_unforce_levels(struct amdgpu_device
*adev
)
776 if (adev
->asic_type
== CHIP_KABINI
|| adev
->asic_type
== CHIP_MULLINS
)
777 return amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_NoForcedLevel
);
779 return kv_set_enabled_levels(adev
);
782 static int kv_update_sclk_t(struct amdgpu_device
*adev
)
784 struct kv_power_info
*pi
= kv_get_pi(adev
);
785 u32 low_sclk_interrupt_t
= 0;
788 if (pi
->caps_sclk_throttle_low_notification
) {
789 low_sclk_interrupt_t
= cpu_to_be32(pi
->low_sclk_interrupt_t
);
791 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
792 pi
->dpm_table_start
+
793 offsetof(SMU7_Fusion_DpmTable
, LowSclkInterruptT
),
794 (u8
*)&low_sclk_interrupt_t
,
795 sizeof(u32
), pi
->sram_end
);
800 static int kv_program_bootup_state(struct amdgpu_device
*adev
)
802 struct kv_power_info
*pi
= kv_get_pi(adev
);
804 struct amdgpu_clock_voltage_dependency_table
*table
=
805 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
;
807 if (table
&& table
->count
) {
808 for (i
= pi
->graphics_dpm_level_count
- 1; i
> 0; i
--) {
809 if (table
->entries
[i
].clk
== pi
->boot_pl
.sclk
)
813 pi
->graphics_boot_level
= (u8
)i
;
814 kv_dpm_power_level_enable(adev
, i
, true);
816 struct sumo_sclk_voltage_mapping_table
*table
=
817 &pi
->sys_info
.sclk_voltage_mapping_table
;
819 if (table
->num_max_dpm_entries
== 0)
822 for (i
= pi
->graphics_dpm_level_count
- 1; i
> 0; i
--) {
823 if (table
->entries
[i
].sclk_frequency
== pi
->boot_pl
.sclk
)
827 pi
->graphics_boot_level
= (u8
)i
;
828 kv_dpm_power_level_enable(adev
, i
, true);
833 static int kv_enable_auto_thermal_throttling(struct amdgpu_device
*adev
)
835 struct kv_power_info
*pi
= kv_get_pi(adev
);
838 pi
->graphics_therm_throttle_enable
= 1;
840 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
841 pi
->dpm_table_start
+
842 offsetof(SMU7_Fusion_DpmTable
, GraphicsThermThrottleEnable
),
843 &pi
->graphics_therm_throttle_enable
,
844 sizeof(u8
), pi
->sram_end
);
849 static int kv_upload_dpm_settings(struct amdgpu_device
*adev
)
851 struct kv_power_info
*pi
= kv_get_pi(adev
);
854 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
855 pi
->dpm_table_start
+
856 offsetof(SMU7_Fusion_DpmTable
, GraphicsLevel
),
857 (u8
*)&pi
->graphics_level
,
858 sizeof(SMU7_Fusion_GraphicsLevel
) * SMU7_MAX_LEVELS_GRAPHICS
,
864 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
865 pi
->dpm_table_start
+
866 offsetof(SMU7_Fusion_DpmTable
, GraphicsDpmLevelCount
),
867 &pi
->graphics_dpm_level_count
,
868 sizeof(u8
), pi
->sram_end
);
873 static u32
kv_get_clock_difference(u32 a
, u32 b
)
875 return (a
>= b
) ? a
- b
: b
- a
;
878 static u32
kv_get_clk_bypass(struct amdgpu_device
*adev
, u32 clk
)
880 struct kv_power_info
*pi
= kv_get_pi(adev
);
883 if (pi
->caps_enable_dfs_bypass
) {
884 if (kv_get_clock_difference(clk
, 40000) < 200)
886 else if (kv_get_clock_difference(clk
, 30000) < 200)
888 else if (kv_get_clock_difference(clk
, 20000) < 200)
890 else if (kv_get_clock_difference(clk
, 15000) < 200)
892 else if (kv_get_clock_difference(clk
, 10000) < 200)
903 static int kv_populate_uvd_table(struct amdgpu_device
*adev
)
905 struct kv_power_info
*pi
= kv_get_pi(adev
);
906 struct amdgpu_uvd_clock_voltage_dependency_table
*table
=
907 &adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
;
908 struct atom_clock_dividers dividers
;
912 if (table
== NULL
|| table
->count
== 0)
915 pi
->uvd_level_count
= 0;
916 for (i
= 0; i
< table
->count
; i
++) {
917 if (pi
->high_voltage_t
&&
918 (pi
->high_voltage_t
< table
->entries
[i
].v
))
921 pi
->uvd_level
[i
].VclkFrequency
= cpu_to_be32(table
->entries
[i
].vclk
);
922 pi
->uvd_level
[i
].DclkFrequency
= cpu_to_be32(table
->entries
[i
].dclk
);
923 pi
->uvd_level
[i
].MinVddNb
= cpu_to_be16(table
->entries
[i
].v
);
925 pi
->uvd_level
[i
].VClkBypassCntl
=
926 (u8
)kv_get_clk_bypass(adev
, table
->entries
[i
].vclk
);
927 pi
->uvd_level
[i
].DClkBypassCntl
=
928 (u8
)kv_get_clk_bypass(adev
, table
->entries
[i
].dclk
);
930 ret
= amdgpu_atombios_get_clock_dividers(adev
, COMPUTE_ENGINE_PLL_PARAM
,
931 table
->entries
[i
].vclk
, false, ÷rs
);
934 pi
->uvd_level
[i
].VclkDivider
= (u8
)dividers
.post_div
;
936 ret
= amdgpu_atombios_get_clock_dividers(adev
, COMPUTE_ENGINE_PLL_PARAM
,
937 table
->entries
[i
].dclk
, false, ÷rs
);
940 pi
->uvd_level
[i
].DclkDivider
= (u8
)dividers
.post_div
;
942 pi
->uvd_level_count
++;
945 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
946 pi
->dpm_table_start
+
947 offsetof(SMU7_Fusion_DpmTable
, UvdLevelCount
),
948 (u8
*)&pi
->uvd_level_count
,
949 sizeof(u8
), pi
->sram_end
);
953 pi
->uvd_interval
= 1;
955 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
956 pi
->dpm_table_start
+
957 offsetof(SMU7_Fusion_DpmTable
, UVDInterval
),
959 sizeof(u8
), pi
->sram_end
);
963 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
964 pi
->dpm_table_start
+
965 offsetof(SMU7_Fusion_DpmTable
, UvdLevel
),
966 (u8
*)&pi
->uvd_level
,
967 sizeof(SMU7_Fusion_UvdLevel
) * SMU7_MAX_LEVELS_UVD
,
974 static int kv_populate_vce_table(struct amdgpu_device
*adev
)
976 struct kv_power_info
*pi
= kv_get_pi(adev
);
979 struct amdgpu_vce_clock_voltage_dependency_table
*table
=
980 &adev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
;
981 struct atom_clock_dividers dividers
;
983 if (table
== NULL
|| table
->count
== 0)
986 pi
->vce_level_count
= 0;
987 for (i
= 0; i
< table
->count
; i
++) {
988 if (pi
->high_voltage_t
&&
989 pi
->high_voltage_t
< table
->entries
[i
].v
)
992 pi
->vce_level
[i
].Frequency
= cpu_to_be32(table
->entries
[i
].evclk
);
993 pi
->vce_level
[i
].MinVoltage
= cpu_to_be16(table
->entries
[i
].v
);
995 pi
->vce_level
[i
].ClkBypassCntl
=
996 (u8
)kv_get_clk_bypass(adev
, table
->entries
[i
].evclk
);
998 ret
= amdgpu_atombios_get_clock_dividers(adev
, COMPUTE_ENGINE_PLL_PARAM
,
999 table
->entries
[i
].evclk
, false, ÷rs
);
1002 pi
->vce_level
[i
].Divider
= (u8
)dividers
.post_div
;
1004 pi
->vce_level_count
++;
1007 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1008 pi
->dpm_table_start
+
1009 offsetof(SMU7_Fusion_DpmTable
, VceLevelCount
),
1010 (u8
*)&pi
->vce_level_count
,
1016 pi
->vce_interval
= 1;
1018 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1019 pi
->dpm_table_start
+
1020 offsetof(SMU7_Fusion_DpmTable
, VCEInterval
),
1021 (u8
*)&pi
->vce_interval
,
1027 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1028 pi
->dpm_table_start
+
1029 offsetof(SMU7_Fusion_DpmTable
, VceLevel
),
1030 (u8
*)&pi
->vce_level
,
1031 sizeof(SMU7_Fusion_ExtClkLevel
) * SMU7_MAX_LEVELS_VCE
,
1037 static int kv_populate_samu_table(struct amdgpu_device
*adev
)
1039 struct kv_power_info
*pi
= kv_get_pi(adev
);
1040 struct amdgpu_clock_voltage_dependency_table
*table
=
1041 &adev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
;
1042 struct atom_clock_dividers dividers
;
1046 if (table
== NULL
|| table
->count
== 0)
1049 pi
->samu_level_count
= 0;
1050 for (i
= 0; i
< table
->count
; i
++) {
1051 if (pi
->high_voltage_t
&&
1052 pi
->high_voltage_t
< table
->entries
[i
].v
)
1055 pi
->samu_level
[i
].Frequency
= cpu_to_be32(table
->entries
[i
].clk
);
1056 pi
->samu_level
[i
].MinVoltage
= cpu_to_be16(table
->entries
[i
].v
);
1058 pi
->samu_level
[i
].ClkBypassCntl
=
1059 (u8
)kv_get_clk_bypass(adev
, table
->entries
[i
].clk
);
1061 ret
= amdgpu_atombios_get_clock_dividers(adev
, COMPUTE_ENGINE_PLL_PARAM
,
1062 table
->entries
[i
].clk
, false, ÷rs
);
1065 pi
->samu_level
[i
].Divider
= (u8
)dividers
.post_div
;
1067 pi
->samu_level_count
++;
1070 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1071 pi
->dpm_table_start
+
1072 offsetof(SMU7_Fusion_DpmTable
, SamuLevelCount
),
1073 (u8
*)&pi
->samu_level_count
,
1079 pi
->samu_interval
= 1;
1081 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1082 pi
->dpm_table_start
+
1083 offsetof(SMU7_Fusion_DpmTable
, SAMUInterval
),
1084 (u8
*)&pi
->samu_interval
,
1090 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1091 pi
->dpm_table_start
+
1092 offsetof(SMU7_Fusion_DpmTable
, SamuLevel
),
1093 (u8
*)&pi
->samu_level
,
1094 sizeof(SMU7_Fusion_ExtClkLevel
) * SMU7_MAX_LEVELS_SAMU
,
1103 static int kv_populate_acp_table(struct amdgpu_device
*adev
)
1105 struct kv_power_info
*pi
= kv_get_pi(adev
);
1106 struct amdgpu_clock_voltage_dependency_table
*table
=
1107 &adev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
;
1108 struct atom_clock_dividers dividers
;
1112 if (table
== NULL
|| table
->count
== 0)
1115 pi
->acp_level_count
= 0;
1116 for (i
= 0; i
< table
->count
; i
++) {
1117 pi
->acp_level
[i
].Frequency
= cpu_to_be32(table
->entries
[i
].clk
);
1118 pi
->acp_level
[i
].MinVoltage
= cpu_to_be16(table
->entries
[i
].v
);
1120 ret
= amdgpu_atombios_get_clock_dividers(adev
, COMPUTE_ENGINE_PLL_PARAM
,
1121 table
->entries
[i
].clk
, false, ÷rs
);
1124 pi
->acp_level
[i
].Divider
= (u8
)dividers
.post_div
;
1126 pi
->acp_level_count
++;
1129 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1130 pi
->dpm_table_start
+
1131 offsetof(SMU7_Fusion_DpmTable
, AcpLevelCount
),
1132 (u8
*)&pi
->acp_level_count
,
1138 pi
->acp_interval
= 1;
1140 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1141 pi
->dpm_table_start
+
1142 offsetof(SMU7_Fusion_DpmTable
, ACPInterval
),
1143 (u8
*)&pi
->acp_interval
,
1149 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1150 pi
->dpm_table_start
+
1151 offsetof(SMU7_Fusion_DpmTable
, AcpLevel
),
1152 (u8
*)&pi
->acp_level
,
1153 sizeof(SMU7_Fusion_ExtClkLevel
) * SMU7_MAX_LEVELS_ACP
,
1161 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device
*adev
)
1163 struct kv_power_info
*pi
= kv_get_pi(adev
);
1165 struct amdgpu_clock_voltage_dependency_table
*table
=
1166 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
;
1168 if (table
&& table
->count
) {
1169 for (i
= 0; i
< pi
->graphics_dpm_level_count
; i
++) {
1170 if (pi
->caps_enable_dfs_bypass
) {
1171 if (kv_get_clock_difference(table
->entries
[i
].clk
, 40000) < 200)
1172 pi
->graphics_level
[i
].ClkBypassCntl
= 3;
1173 else if (kv_get_clock_difference(table
->entries
[i
].clk
, 30000) < 200)
1174 pi
->graphics_level
[i
].ClkBypassCntl
= 2;
1175 else if (kv_get_clock_difference(table
->entries
[i
].clk
, 26600) < 200)
1176 pi
->graphics_level
[i
].ClkBypassCntl
= 7;
1177 else if (kv_get_clock_difference(table
->entries
[i
].clk
, 20000) < 200)
1178 pi
->graphics_level
[i
].ClkBypassCntl
= 6;
1179 else if (kv_get_clock_difference(table
->entries
[i
].clk
, 10000) < 200)
1180 pi
->graphics_level
[i
].ClkBypassCntl
= 8;
1182 pi
->graphics_level
[i
].ClkBypassCntl
= 0;
1184 pi
->graphics_level
[i
].ClkBypassCntl
= 0;
1188 struct sumo_sclk_voltage_mapping_table
*table
=
1189 &pi
->sys_info
.sclk_voltage_mapping_table
;
1190 for (i
= 0; i
< pi
->graphics_dpm_level_count
; i
++) {
1191 if (pi
->caps_enable_dfs_bypass
) {
1192 if (kv_get_clock_difference(table
->entries
[i
].sclk_frequency
, 40000) < 200)
1193 pi
->graphics_level
[i
].ClkBypassCntl
= 3;
1194 else if (kv_get_clock_difference(table
->entries
[i
].sclk_frequency
, 30000) < 200)
1195 pi
->graphics_level
[i
].ClkBypassCntl
= 2;
1196 else if (kv_get_clock_difference(table
->entries
[i
].sclk_frequency
, 26600) < 200)
1197 pi
->graphics_level
[i
].ClkBypassCntl
= 7;
1198 else if (kv_get_clock_difference(table
->entries
[i
].sclk_frequency
, 20000) < 200)
1199 pi
->graphics_level
[i
].ClkBypassCntl
= 6;
1200 else if (kv_get_clock_difference(table
->entries
[i
].sclk_frequency
, 10000) < 200)
1201 pi
->graphics_level
[i
].ClkBypassCntl
= 8;
1203 pi
->graphics_level
[i
].ClkBypassCntl
= 0;
1205 pi
->graphics_level
[i
].ClkBypassCntl
= 0;
1211 static int kv_enable_ulv(struct amdgpu_device
*adev
, bool enable
)
1213 return amdgpu_kv_notify_message_to_smu(adev
, enable
?
1214 PPSMC_MSG_EnableULV
: PPSMC_MSG_DisableULV
);
1217 static void kv_reset_acp_boot_level(struct amdgpu_device
*adev
)
1219 struct kv_power_info
*pi
= kv_get_pi(adev
);
1221 pi
->acp_boot_level
= 0xff;
1224 static void kv_update_current_ps(struct amdgpu_device
*adev
,
1225 struct amdgpu_ps
*rps
)
1227 struct kv_ps
*new_ps
= kv_get_ps(rps
);
1228 struct kv_power_info
*pi
= kv_get_pi(adev
);
1230 pi
->current_rps
= *rps
;
1231 pi
->current_ps
= *new_ps
;
1232 pi
->current_rps
.ps_priv
= &pi
->current_ps
;
1235 static void kv_update_requested_ps(struct amdgpu_device
*adev
,
1236 struct amdgpu_ps
*rps
)
1238 struct kv_ps
*new_ps
= kv_get_ps(rps
);
1239 struct kv_power_info
*pi
= kv_get_pi(adev
);
1241 pi
->requested_rps
= *rps
;
1242 pi
->requested_ps
= *new_ps
;
1243 pi
->requested_rps
.ps_priv
= &pi
->requested_ps
;
1246 static void kv_dpm_enable_bapm(struct amdgpu_device
*adev
, bool enable
)
1248 struct kv_power_info
*pi
= kv_get_pi(adev
);
1251 if (pi
->bapm_enable
) {
1252 ret
= amdgpu_kv_smc_bapm_enable(adev
, enable
);
1254 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1258 static int kv_dpm_enable(struct amdgpu_device
*adev
)
1260 struct kv_power_info
*pi
= kv_get_pi(adev
);
1263 ret
= kv_process_firmware_header(adev
);
1265 DRM_ERROR("kv_process_firmware_header failed\n");
1268 kv_init_fps_limits(adev
);
1269 kv_init_graphics_levels(adev
);
1270 ret
= kv_program_bootup_state(adev
);
1272 DRM_ERROR("kv_program_bootup_state failed\n");
1275 kv_calculate_dfs_bypass_settings(adev
);
1276 ret
= kv_upload_dpm_settings(adev
);
1278 DRM_ERROR("kv_upload_dpm_settings failed\n");
1281 ret
= kv_populate_uvd_table(adev
);
1283 DRM_ERROR("kv_populate_uvd_table failed\n");
1286 ret
= kv_populate_vce_table(adev
);
1288 DRM_ERROR("kv_populate_vce_table failed\n");
1291 ret
= kv_populate_samu_table(adev
);
1293 DRM_ERROR("kv_populate_samu_table failed\n");
1296 ret
= kv_populate_acp_table(adev
);
1298 DRM_ERROR("kv_populate_acp_table failed\n");
1301 kv_program_vc(adev
);
1303 kv_initialize_hardware_cac_manager(adev
);
1306 if (pi
->enable_auto_thermal_throttling
) {
1307 ret
= kv_enable_auto_thermal_throttling(adev
);
1309 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1313 ret
= kv_enable_dpm_voltage_scaling(adev
);
1315 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1318 ret
= kv_set_dpm_interval(adev
);
1320 DRM_ERROR("kv_set_dpm_interval failed\n");
1323 ret
= kv_set_dpm_boot_state(adev
);
1325 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1328 ret
= kv_enable_ulv(adev
, true);
1330 DRM_ERROR("kv_enable_ulv failed\n");
1334 ret
= kv_enable_didt(adev
, true);
1336 DRM_ERROR("kv_enable_didt failed\n");
1339 ret
= kv_enable_smc_cac(adev
, true);
1341 DRM_ERROR("kv_enable_smc_cac failed\n");
1345 kv_reset_acp_boot_level(adev
);
1347 ret
= amdgpu_kv_smc_bapm_enable(adev
, false);
1349 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1353 kv_update_current_ps(adev
, adev
->pm
.dpm
.boot_ps
);
1355 if (adev
->irq
.installed
&&
1356 amdgpu_is_internal_thermal_sensor(adev
->pm
.int_thermal_type
)) {
1357 ret
= kv_set_thermal_temperature_range(adev
, KV_TEMP_RANGE_MIN
, KV_TEMP_RANGE_MAX
);
1359 DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1362 amdgpu_irq_get(adev
, &adev
->pm
.dpm
.thermal
.irq
,
1363 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
);
1364 amdgpu_irq_get(adev
, &adev
->pm
.dpm
.thermal
.irq
,
1365 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
);
1371 static void kv_dpm_disable(struct amdgpu_device
*adev
)
1373 amdgpu_irq_put(adev
, &adev
->pm
.dpm
.thermal
.irq
,
1374 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
);
1375 amdgpu_irq_put(adev
, &adev
->pm
.dpm
.thermal
.irq
,
1376 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
);
1378 amdgpu_kv_smc_bapm_enable(adev
, false);
1380 if (adev
->asic_type
== CHIP_MULLINS
)
1381 kv_enable_nb_dpm(adev
, false);
1383 /* powerup blocks */
1384 kv_dpm_powergate_acp(adev
, false);
1385 kv_dpm_powergate_samu(adev
, false);
1386 kv_dpm_powergate_vce(adev
, false);
1387 kv_dpm_powergate_uvd(adev
, false);
1389 kv_enable_smc_cac(adev
, false);
1390 kv_enable_didt(adev
, false);
1393 kv_enable_ulv(adev
, false);
1396 kv_update_current_ps(adev
, adev
->pm
.dpm
.boot_ps
);
1400 static int kv_write_smc_soft_register(struct amdgpu_device
*adev
,
1401 u16 reg_offset
, u32 value
)
1403 struct kv_power_info
*pi
= kv_get_pi(adev
);
1405 return amdgpu_kv_copy_bytes_to_smc(adev
, pi
->soft_regs_start
+ reg_offset
,
1406 (u8
*)&value
, sizeof(u16
), pi
->sram_end
);
1409 static int kv_read_smc_soft_register(struct amdgpu_device
*adev
,
1410 u16 reg_offset
, u32
*value
)
1412 struct kv_power_info
*pi
= kv_get_pi(adev
);
1414 return amdgpu_kv_read_smc_sram_dword(adev
, pi
->soft_regs_start
+ reg_offset
,
1415 value
, pi
->sram_end
);
1419 static void kv_init_sclk_t(struct amdgpu_device
*adev
)
1421 struct kv_power_info
*pi
= kv_get_pi(adev
);
1423 pi
->low_sclk_interrupt_t
= 0;
1426 static int kv_init_fps_limits(struct amdgpu_device
*adev
)
1428 struct kv_power_info
*pi
= kv_get_pi(adev
);
1435 pi
->fps_high_t
= cpu_to_be16(tmp
);
1436 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1437 pi
->dpm_table_start
+
1438 offsetof(SMU7_Fusion_DpmTable
, FpsHighT
),
1439 (u8
*)&pi
->fps_high_t
,
1440 sizeof(u16
), pi
->sram_end
);
1443 pi
->fps_low_t
= cpu_to_be16(tmp
);
1445 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1446 pi
->dpm_table_start
+
1447 offsetof(SMU7_Fusion_DpmTable
, FpsLowT
),
1448 (u8
*)&pi
->fps_low_t
,
1449 sizeof(u16
), pi
->sram_end
);
1455 static void kv_init_powergate_state(struct amdgpu_device
*adev
)
1457 struct kv_power_info
*pi
= kv_get_pi(adev
);
1459 pi
->uvd_power_gated
= false;
1460 pi
->vce_power_gated
= false;
1461 pi
->samu_power_gated
= false;
1462 pi
->acp_power_gated
= false;
1466 static int kv_enable_uvd_dpm(struct amdgpu_device
*adev
, bool enable
)
1468 return amdgpu_kv_notify_message_to_smu(adev
, enable
?
1469 PPSMC_MSG_UVDDPM_Enable
: PPSMC_MSG_UVDDPM_Disable
);
1472 static int kv_enable_vce_dpm(struct amdgpu_device
*adev
, bool enable
)
1474 return amdgpu_kv_notify_message_to_smu(adev
, enable
?
1475 PPSMC_MSG_VCEDPM_Enable
: PPSMC_MSG_VCEDPM_Disable
);
1478 static int kv_enable_samu_dpm(struct amdgpu_device
*adev
, bool enable
)
1480 return amdgpu_kv_notify_message_to_smu(adev
, enable
?
1481 PPSMC_MSG_SAMUDPM_Enable
: PPSMC_MSG_SAMUDPM_Disable
);
1484 static int kv_enable_acp_dpm(struct amdgpu_device
*adev
, bool enable
)
1486 return amdgpu_kv_notify_message_to_smu(adev
, enable
?
1487 PPSMC_MSG_ACPDPM_Enable
: PPSMC_MSG_ACPDPM_Disable
);
1490 static int kv_update_uvd_dpm(struct amdgpu_device
*adev
, bool gate
)
1492 struct kv_power_info
*pi
= kv_get_pi(adev
);
1493 struct amdgpu_uvd_clock_voltage_dependency_table
*table
=
1494 &adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
;
1500 pi
->uvd_boot_level
= table
->count
- 1;
1502 pi
->uvd_boot_level
= 0;
1504 if (!pi
->caps_uvd_dpm
|| pi
->caps_stable_p_state
) {
1505 mask
= 1 << pi
->uvd_boot_level
;
1510 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1511 pi
->dpm_table_start
+
1512 offsetof(SMU7_Fusion_DpmTable
, UvdBootLevel
),
1513 (uint8_t *)&pi
->uvd_boot_level
,
1514 sizeof(u8
), pi
->sram_end
);
1518 amdgpu_kv_send_msg_to_smc_with_parameter(adev
,
1519 PPSMC_MSG_UVDDPM_SetEnabledMask
,
1523 return kv_enable_uvd_dpm(adev
, !gate
);
1526 static u8
kv_get_vce_boot_level(struct amdgpu_device
*adev
, u32 evclk
)
1529 struct amdgpu_vce_clock_voltage_dependency_table
*table
=
1530 &adev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
;
1532 for (i
= 0; i
< table
->count
; i
++) {
1533 if (table
->entries
[i
].evclk
>= evclk
)
1540 static int kv_update_vce_dpm(struct amdgpu_device
*adev
,
1541 struct amdgpu_ps
*amdgpu_new_state
,
1542 struct amdgpu_ps
*amdgpu_current_state
)
1544 struct kv_power_info
*pi
= kv_get_pi(adev
);
1545 struct amdgpu_vce_clock_voltage_dependency_table
*table
=
1546 &adev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
;
1549 if (amdgpu_new_state
->evclk
> 0 && amdgpu_current_state
->evclk
== 0) {
1550 kv_dpm_powergate_vce(adev
, false);
1551 /* turn the clocks on when encoding */
1552 ret
= amdgpu_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1553 AMD_CG_STATE_UNGATE
);
1556 if (pi
->caps_stable_p_state
)
1557 pi
->vce_boot_level
= table
->count
- 1;
1559 pi
->vce_boot_level
= kv_get_vce_boot_level(adev
, amdgpu_new_state
->evclk
);
1561 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1562 pi
->dpm_table_start
+
1563 offsetof(SMU7_Fusion_DpmTable
, VceBootLevel
),
1564 (u8
*)&pi
->vce_boot_level
,
1570 if (pi
->caps_stable_p_state
)
1571 amdgpu_kv_send_msg_to_smc_with_parameter(adev
,
1572 PPSMC_MSG_VCEDPM_SetEnabledMask
,
1573 (1 << pi
->vce_boot_level
));
1575 kv_enable_vce_dpm(adev
, true);
1576 } else if (amdgpu_new_state
->evclk
== 0 && amdgpu_current_state
->evclk
> 0) {
1577 kv_enable_vce_dpm(adev
, false);
1578 /* turn the clocks off when not encoding */
1579 ret
= amdgpu_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1583 kv_dpm_powergate_vce(adev
, true);
1589 static int kv_update_samu_dpm(struct amdgpu_device
*adev
, bool gate
)
1591 struct kv_power_info
*pi
= kv_get_pi(adev
);
1592 struct amdgpu_clock_voltage_dependency_table
*table
=
1593 &adev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
;
1597 if (pi
->caps_stable_p_state
)
1598 pi
->samu_boot_level
= table
->count
- 1;
1600 pi
->samu_boot_level
= 0;
1602 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1603 pi
->dpm_table_start
+
1604 offsetof(SMU7_Fusion_DpmTable
, SamuBootLevel
),
1605 (u8
*)&pi
->samu_boot_level
,
1611 if (pi
->caps_stable_p_state
)
1612 amdgpu_kv_send_msg_to_smc_with_parameter(adev
,
1613 PPSMC_MSG_SAMUDPM_SetEnabledMask
,
1614 (1 << pi
->samu_boot_level
));
1617 return kv_enable_samu_dpm(adev
, !gate
);
1620 static u8
kv_get_acp_boot_level(struct amdgpu_device
*adev
)
1623 struct amdgpu_clock_voltage_dependency_table
*table
=
1624 &adev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
;
1626 for (i
= 0; i
< table
->count
; i
++) {
1627 if (table
->entries
[i
].clk
>= 0) /* XXX */
1631 if (i
>= table
->count
)
1632 i
= table
->count
- 1;
1637 static void kv_update_acp_boot_level(struct amdgpu_device
*adev
)
1639 struct kv_power_info
*pi
= kv_get_pi(adev
);
1642 if (!pi
->caps_stable_p_state
) {
1643 acp_boot_level
= kv_get_acp_boot_level(adev
);
1644 if (acp_boot_level
!= pi
->acp_boot_level
) {
1645 pi
->acp_boot_level
= acp_boot_level
;
1646 amdgpu_kv_send_msg_to_smc_with_parameter(adev
,
1647 PPSMC_MSG_ACPDPM_SetEnabledMask
,
1648 (1 << pi
->acp_boot_level
));
1653 static int kv_update_acp_dpm(struct amdgpu_device
*adev
, bool gate
)
1655 struct kv_power_info
*pi
= kv_get_pi(adev
);
1656 struct amdgpu_clock_voltage_dependency_table
*table
=
1657 &adev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
;
1661 if (pi
->caps_stable_p_state
)
1662 pi
->acp_boot_level
= table
->count
- 1;
1664 pi
->acp_boot_level
= kv_get_acp_boot_level(adev
);
1666 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1667 pi
->dpm_table_start
+
1668 offsetof(SMU7_Fusion_DpmTable
, AcpBootLevel
),
1669 (u8
*)&pi
->acp_boot_level
,
1675 if (pi
->caps_stable_p_state
)
1676 amdgpu_kv_send_msg_to_smc_with_parameter(adev
,
1677 PPSMC_MSG_ACPDPM_SetEnabledMask
,
1678 (1 << pi
->acp_boot_level
));
1681 return kv_enable_acp_dpm(adev
, !gate
);
1684 static void kv_dpm_powergate_uvd(struct amdgpu_device
*adev
, bool gate
)
1686 struct kv_power_info
*pi
= kv_get_pi(adev
);
1689 if (pi
->uvd_power_gated
== gate
)
1692 pi
->uvd_power_gated
= gate
;
1695 if (pi
->caps_uvd_pg
) {
1696 /* disable clockgating so we can properly shut down the block */
1697 ret
= amdgpu_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_UVD
,
1698 AMD_CG_STATE_UNGATE
);
1699 /* shutdown the UVD block */
1700 ret
= amdgpu_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_UVD
,
1702 /* XXX: check for errors */
1704 kv_update_uvd_dpm(adev
, gate
);
1705 if (pi
->caps_uvd_pg
)
1706 /* power off the UVD block */
1707 amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_UVDPowerOFF
);
1709 if (pi
->caps_uvd_pg
) {
1710 /* power on the UVD block */
1711 amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_UVDPowerON
);
1712 /* re-init the UVD block */
1713 ret
= amdgpu_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_UVD
,
1714 AMD_PG_STATE_UNGATE
);
1715 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
1716 ret
= amdgpu_set_clockgating_state(adev
, AMD_IP_BLOCK_TYPE_UVD
,
1718 /* XXX: check for errors */
1720 kv_update_uvd_dpm(adev
, gate
);
1724 static void kv_dpm_powergate_vce(struct amdgpu_device
*adev
, bool gate
)
1726 struct kv_power_info
*pi
= kv_get_pi(adev
);
1729 if (pi
->vce_power_gated
== gate
)
1732 pi
->vce_power_gated
= gate
;
1735 if (pi
->caps_vce_pg
) {
1736 /* shutdown the VCE block */
1737 ret
= amdgpu_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1739 /* XXX: check for errors */
1740 /* power off the VCE block */
1741 amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_VCEPowerOFF
);
1744 if (pi
->caps_vce_pg
) {
1745 /* power on the VCE block */
1746 amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_VCEPowerON
);
1747 /* re-init the VCE block */
1748 ret
= amdgpu_set_powergating_state(adev
, AMD_IP_BLOCK_TYPE_VCE
,
1749 AMD_PG_STATE_UNGATE
);
1750 /* XXX: check for errors */
1755 static void kv_dpm_powergate_samu(struct amdgpu_device
*adev
, bool gate
)
1757 struct kv_power_info
*pi
= kv_get_pi(adev
);
1759 if (pi
->samu_power_gated
== gate
)
1762 pi
->samu_power_gated
= gate
;
1765 kv_update_samu_dpm(adev
, true);
1766 if (pi
->caps_samu_pg
)
1767 amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_SAMPowerOFF
);
1769 if (pi
->caps_samu_pg
)
1770 amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_SAMPowerON
);
1771 kv_update_samu_dpm(adev
, false);
1775 static void kv_dpm_powergate_acp(struct amdgpu_device
*adev
, bool gate
)
1777 struct kv_power_info
*pi
= kv_get_pi(adev
);
1779 if (pi
->acp_power_gated
== gate
)
1782 if (adev
->asic_type
== CHIP_KABINI
|| adev
->asic_type
== CHIP_MULLINS
)
1785 pi
->acp_power_gated
= gate
;
1788 kv_update_acp_dpm(adev
, true);
1789 if (pi
->caps_acp_pg
)
1790 amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_ACPPowerOFF
);
1792 if (pi
->caps_acp_pg
)
1793 amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_ACPPowerON
);
1794 kv_update_acp_dpm(adev
, false);
1798 static void kv_set_valid_clock_range(struct amdgpu_device
*adev
,
1799 struct amdgpu_ps
*new_rps
)
1801 struct kv_ps
*new_ps
= kv_get_ps(new_rps
);
1802 struct kv_power_info
*pi
= kv_get_pi(adev
);
1804 struct amdgpu_clock_voltage_dependency_table
*table
=
1805 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
;
1807 if (table
&& table
->count
) {
1808 for (i
= 0; i
< pi
->graphics_dpm_level_count
; i
++) {
1809 if ((table
->entries
[i
].clk
>= new_ps
->levels
[0].sclk
) ||
1810 (i
== (pi
->graphics_dpm_level_count
- 1))) {
1811 pi
->lowest_valid
= i
;
1816 for (i
= pi
->graphics_dpm_level_count
- 1; i
> 0; i
--) {
1817 if (table
->entries
[i
].clk
<= new_ps
->levels
[new_ps
->num_levels
- 1].sclk
)
1820 pi
->highest_valid
= i
;
1822 if (pi
->lowest_valid
> pi
->highest_valid
) {
1823 if ((new_ps
->levels
[0].sclk
- table
->entries
[pi
->highest_valid
].clk
) >
1824 (table
->entries
[pi
->lowest_valid
].clk
- new_ps
->levels
[new_ps
->num_levels
- 1].sclk
))
1825 pi
->highest_valid
= pi
->lowest_valid
;
1827 pi
->lowest_valid
= pi
->highest_valid
;
1830 struct sumo_sclk_voltage_mapping_table
*table
=
1831 &pi
->sys_info
.sclk_voltage_mapping_table
;
1833 for (i
= 0; i
< (int)pi
->graphics_dpm_level_count
; i
++) {
1834 if (table
->entries
[i
].sclk_frequency
>= new_ps
->levels
[0].sclk
||
1835 i
== (int)(pi
->graphics_dpm_level_count
- 1)) {
1836 pi
->lowest_valid
= i
;
1841 for (i
= pi
->graphics_dpm_level_count
- 1; i
> 0; i
--) {
1842 if (table
->entries
[i
].sclk_frequency
<=
1843 new_ps
->levels
[new_ps
->num_levels
- 1].sclk
)
1846 pi
->highest_valid
= i
;
1848 if (pi
->lowest_valid
> pi
->highest_valid
) {
1849 if ((new_ps
->levels
[0].sclk
-
1850 table
->entries
[pi
->highest_valid
].sclk_frequency
) >
1851 (table
->entries
[pi
->lowest_valid
].sclk_frequency
-
1852 new_ps
->levels
[new_ps
->num_levels
-1].sclk
))
1853 pi
->highest_valid
= pi
->lowest_valid
;
1855 pi
->lowest_valid
= pi
->highest_valid
;
1860 static int kv_update_dfs_bypass_settings(struct amdgpu_device
*adev
,
1861 struct amdgpu_ps
*new_rps
)
1863 struct kv_ps
*new_ps
= kv_get_ps(new_rps
);
1864 struct kv_power_info
*pi
= kv_get_pi(adev
);
1868 if (pi
->caps_enable_dfs_bypass
) {
1869 clk_bypass_cntl
= new_ps
->need_dfs_bypass
?
1870 pi
->graphics_level
[pi
->graphics_boot_level
].ClkBypassCntl
: 0;
1871 ret
= amdgpu_kv_copy_bytes_to_smc(adev
,
1872 (pi
->dpm_table_start
+
1873 offsetof(SMU7_Fusion_DpmTable
, GraphicsLevel
) +
1874 (pi
->graphics_boot_level
* sizeof(SMU7_Fusion_GraphicsLevel
)) +
1875 offsetof(SMU7_Fusion_GraphicsLevel
, ClkBypassCntl
)),
1877 sizeof(u8
), pi
->sram_end
);
1883 static int kv_enable_nb_dpm(struct amdgpu_device
*adev
,
1886 struct kv_power_info
*pi
= kv_get_pi(adev
);
1890 if (pi
->enable_nb_dpm
&& !pi
->nb_dpm_enabled
) {
1891 ret
= amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_NBDPM_Enable
);
1893 pi
->nb_dpm_enabled
= true;
1896 if (pi
->enable_nb_dpm
&& pi
->nb_dpm_enabled
) {
1897 ret
= amdgpu_kv_notify_message_to_smu(adev
, PPSMC_MSG_NBDPM_Disable
);
1899 pi
->nb_dpm_enabled
= false;
1906 static int kv_dpm_force_performance_level(struct amdgpu_device
*adev
,
1907 enum amdgpu_dpm_forced_level level
)
1911 if (level
== AMDGPU_DPM_FORCED_LEVEL_HIGH
) {
1912 ret
= kv_force_dpm_highest(adev
);
1915 } else if (level
== AMDGPU_DPM_FORCED_LEVEL_LOW
) {
1916 ret
= kv_force_dpm_lowest(adev
);
1919 } else if (level
== AMDGPU_DPM_FORCED_LEVEL_AUTO
) {
1920 ret
= kv_unforce_levels(adev
);
1925 adev
->pm
.dpm
.forced_level
= level
;
1930 static int kv_dpm_pre_set_power_state(struct amdgpu_device
*adev
)
1932 struct kv_power_info
*pi
= kv_get_pi(adev
);
1933 struct amdgpu_ps requested_ps
= *adev
->pm
.dpm
.requested_ps
;
1934 struct amdgpu_ps
*new_ps
= &requested_ps
;
1936 kv_update_requested_ps(adev
, new_ps
);
1938 kv_apply_state_adjust_rules(adev
,
1945 static int kv_dpm_set_power_state(struct amdgpu_device
*adev
)
1947 struct kv_power_info
*pi
= kv_get_pi(adev
);
1948 struct amdgpu_ps
*new_ps
= &pi
->requested_rps
;
1949 struct amdgpu_ps
*old_ps
= &pi
->current_rps
;
1952 if (pi
->bapm_enable
) {
1953 ret
= amdgpu_kv_smc_bapm_enable(adev
, adev
->pm
.dpm
.ac_power
);
1955 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1960 if (adev
->asic_type
== CHIP_KABINI
|| adev
->asic_type
== CHIP_MULLINS
) {
1961 if (pi
->enable_dpm
) {
1962 kv_set_valid_clock_range(adev
, new_ps
);
1963 kv_update_dfs_bypass_settings(adev
, new_ps
);
1964 ret
= kv_calculate_ds_divider(adev
);
1966 DRM_ERROR("kv_calculate_ds_divider failed\n");
1969 kv_calculate_nbps_level_settings(adev
);
1970 kv_calculate_dpm_settings(adev
);
1971 kv_force_lowest_valid(adev
);
1972 kv_enable_new_levels(adev
);
1973 kv_upload_dpm_settings(adev
);
1974 kv_program_nbps_index_settings(adev
, new_ps
);
1975 kv_unforce_levels(adev
);
1976 kv_set_enabled_levels(adev
);
1977 kv_force_lowest_valid(adev
);
1978 kv_unforce_levels(adev
);
1980 ret
= kv_update_vce_dpm(adev
, new_ps
, old_ps
);
1982 DRM_ERROR("kv_update_vce_dpm failed\n");
1985 kv_update_sclk_t(adev
);
1986 if (adev
->asic_type
== CHIP_MULLINS
)
1987 kv_enable_nb_dpm(adev
, true);
1990 if (pi
->enable_dpm
) {
1991 kv_set_valid_clock_range(adev
, new_ps
);
1992 kv_update_dfs_bypass_settings(adev
, new_ps
);
1993 ret
= kv_calculate_ds_divider(adev
);
1995 DRM_ERROR("kv_calculate_ds_divider failed\n");
1998 kv_calculate_nbps_level_settings(adev
);
1999 kv_calculate_dpm_settings(adev
);
2000 kv_freeze_sclk_dpm(adev
, true);
2001 kv_upload_dpm_settings(adev
);
2002 kv_program_nbps_index_settings(adev
, new_ps
);
2003 kv_freeze_sclk_dpm(adev
, false);
2004 kv_set_enabled_levels(adev
);
2005 ret
= kv_update_vce_dpm(adev
, new_ps
, old_ps
);
2007 DRM_ERROR("kv_update_vce_dpm failed\n");
2010 kv_update_acp_boot_level(adev
);
2011 kv_update_sclk_t(adev
);
2012 kv_enable_nb_dpm(adev
, true);
2019 static void kv_dpm_post_set_power_state(struct amdgpu_device
*adev
)
2021 struct kv_power_info
*pi
= kv_get_pi(adev
);
2022 struct amdgpu_ps
*new_ps
= &pi
->requested_rps
;
2024 kv_update_current_ps(adev
, new_ps
);
2027 static void kv_dpm_setup_asic(struct amdgpu_device
*adev
)
2029 sumo_take_smu_control(adev
, true);
2030 kv_init_powergate_state(adev
);
2031 kv_init_sclk_t(adev
);
2035 static void kv_dpm_reset_asic(struct amdgpu_device
*adev
)
2037 struct kv_power_info
*pi
= kv_get_pi(adev
);
2039 if (adev
->asic_type
== CHIP_KABINI
|| adev
->asic_type
== CHIP_MULLINS
) {
2040 kv_force_lowest_valid(adev
);
2041 kv_init_graphics_levels(adev
);
2042 kv_program_bootup_state(adev
);
2043 kv_upload_dpm_settings(adev
);
2044 kv_force_lowest_valid(adev
);
2045 kv_unforce_levels(adev
);
2047 kv_init_graphics_levels(adev
);
2048 kv_program_bootup_state(adev
);
2049 kv_freeze_sclk_dpm(adev
, true);
2050 kv_upload_dpm_settings(adev
);
2051 kv_freeze_sclk_dpm(adev
, false);
2052 kv_set_enabled_level(adev
, pi
->graphics_boot_level
);
2057 static void kv_construct_max_power_limits_table(struct amdgpu_device
*adev
,
2058 struct amdgpu_clock_and_voltage_limits
*table
)
2060 struct kv_power_info
*pi
= kv_get_pi(adev
);
2062 if (pi
->sys_info
.sclk_voltage_mapping_table
.num_max_dpm_entries
> 0) {
2063 int idx
= pi
->sys_info
.sclk_voltage_mapping_table
.num_max_dpm_entries
- 1;
2065 pi
->sys_info
.sclk_voltage_mapping_table
.entries
[idx
].sclk_frequency
;
2067 kv_convert_2bit_index_to_voltage(adev
,
2068 pi
->sys_info
.sclk_voltage_mapping_table
.entries
[idx
].vid_2bit
);
2071 table
->mclk
= pi
->sys_info
.nbp_memory_clock
[0];
2074 static void kv_patch_voltage_values(struct amdgpu_device
*adev
)
2077 struct amdgpu_uvd_clock_voltage_dependency_table
*uvd_table
=
2078 &adev
->pm
.dpm
.dyn_state
.uvd_clock_voltage_dependency_table
;
2079 struct amdgpu_vce_clock_voltage_dependency_table
*vce_table
=
2080 &adev
->pm
.dpm
.dyn_state
.vce_clock_voltage_dependency_table
;
2081 struct amdgpu_clock_voltage_dependency_table
*samu_table
=
2082 &adev
->pm
.dpm
.dyn_state
.samu_clock_voltage_dependency_table
;
2083 struct amdgpu_clock_voltage_dependency_table
*acp_table
=
2084 &adev
->pm
.dpm
.dyn_state
.acp_clock_voltage_dependency_table
;
2086 if (uvd_table
->count
) {
2087 for (i
= 0; i
< uvd_table
->count
; i
++)
2088 uvd_table
->entries
[i
].v
=
2089 kv_convert_8bit_index_to_voltage(adev
,
2090 uvd_table
->entries
[i
].v
);
2093 if (vce_table
->count
) {
2094 for (i
= 0; i
< vce_table
->count
; i
++)
2095 vce_table
->entries
[i
].v
=
2096 kv_convert_8bit_index_to_voltage(adev
,
2097 vce_table
->entries
[i
].v
);
2100 if (samu_table
->count
) {
2101 for (i
= 0; i
< samu_table
->count
; i
++)
2102 samu_table
->entries
[i
].v
=
2103 kv_convert_8bit_index_to_voltage(adev
,
2104 samu_table
->entries
[i
].v
);
2107 if (acp_table
->count
) {
2108 for (i
= 0; i
< acp_table
->count
; i
++)
2109 acp_table
->entries
[i
].v
=
2110 kv_convert_8bit_index_to_voltage(adev
,
2111 acp_table
->entries
[i
].v
);
2116 static void kv_construct_boot_state(struct amdgpu_device
*adev
)
2118 struct kv_power_info
*pi
= kv_get_pi(adev
);
2120 pi
->boot_pl
.sclk
= pi
->sys_info
.bootup_sclk
;
2121 pi
->boot_pl
.vddc_index
= pi
->sys_info
.bootup_nb_voltage_index
;
2122 pi
->boot_pl
.ds_divider_index
= 0;
2123 pi
->boot_pl
.ss_divider_index
= 0;
2124 pi
->boot_pl
.allow_gnb_slow
= 1;
2125 pi
->boot_pl
.force_nbp_state
= 0;
2126 pi
->boot_pl
.display_wm
= 0;
2127 pi
->boot_pl
.vce_wm
= 0;
2130 static int kv_force_dpm_highest(struct amdgpu_device
*adev
)
2135 ret
= amdgpu_kv_dpm_get_enable_mask(adev
, &enable_mask
);
2139 for (i
= SMU7_MAX_LEVELS_GRAPHICS
- 1; i
> 0; i
--) {
2140 if (enable_mask
& (1 << i
))
2144 if (adev
->asic_type
== CHIP_KABINI
|| adev
->asic_type
== CHIP_MULLINS
)
2145 return amdgpu_kv_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_DPM_ForceState
, i
);
2147 return kv_set_enabled_level(adev
, i
);
2150 static int kv_force_dpm_lowest(struct amdgpu_device
*adev
)
2155 ret
= amdgpu_kv_dpm_get_enable_mask(adev
, &enable_mask
);
2159 for (i
= 0; i
< SMU7_MAX_LEVELS_GRAPHICS
; i
++) {
2160 if (enable_mask
& (1 << i
))
2164 if (adev
->asic_type
== CHIP_KABINI
|| adev
->asic_type
== CHIP_MULLINS
)
2165 return amdgpu_kv_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_DPM_ForceState
, i
);
2167 return kv_set_enabled_level(adev
, i
);
2170 static u8
kv_get_sleep_divider_id_from_clock(struct amdgpu_device
*adev
,
2171 u32 sclk
, u32 min_sclk_in_sr
)
2173 struct kv_power_info
*pi
= kv_get_pi(adev
);
2176 u32 min
= max(min_sclk_in_sr
, (u32
)KV_MINIMUM_ENGINE_CLOCK
);
2181 if (!pi
->caps_sclk_ds
)
2184 for (i
= KV_MAX_DEEPSLEEP_DIVIDER_ID
; i
> 0; i
--) {
2193 static int kv_get_high_voltage_limit(struct amdgpu_device
*adev
, int *limit
)
2195 struct kv_power_info
*pi
= kv_get_pi(adev
);
2196 struct amdgpu_clock_voltage_dependency_table
*table
=
2197 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
;
2200 if (table
&& table
->count
) {
2201 for (i
= table
->count
- 1; i
>= 0; i
--) {
2202 if (pi
->high_voltage_t
&&
2203 (kv_convert_8bit_index_to_voltage(adev
, table
->entries
[i
].v
) <=
2204 pi
->high_voltage_t
)) {
2210 struct sumo_sclk_voltage_mapping_table
*table
=
2211 &pi
->sys_info
.sclk_voltage_mapping_table
;
2213 for (i
= table
->num_max_dpm_entries
- 1; i
>= 0; i
--) {
2214 if (pi
->high_voltage_t
&&
2215 (kv_convert_2bit_index_to_voltage(adev
, table
->entries
[i
].vid_2bit
) <=
2216 pi
->high_voltage_t
)) {
2227 static void kv_apply_state_adjust_rules(struct amdgpu_device
*adev
,
2228 struct amdgpu_ps
*new_rps
,
2229 struct amdgpu_ps
*old_rps
)
2231 struct kv_ps
*ps
= kv_get_ps(new_rps
);
2232 struct kv_power_info
*pi
= kv_get_pi(adev
);
2233 u32 min_sclk
= 10000; /* ??? */
2237 struct amdgpu_clock_voltage_dependency_table
*table
=
2238 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
;
2239 u32 stable_p_state_sclk
= 0;
2240 struct amdgpu_clock_and_voltage_limits
*max_limits
=
2241 &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
;
2243 if (new_rps
->vce_active
) {
2244 new_rps
->evclk
= adev
->pm
.dpm
.vce_states
[adev
->pm
.dpm
.vce_level
].evclk
;
2245 new_rps
->ecclk
= adev
->pm
.dpm
.vce_states
[adev
->pm
.dpm
.vce_level
].ecclk
;
2251 mclk
= max_limits
->mclk
;
2254 if (pi
->caps_stable_p_state
) {
2255 stable_p_state_sclk
= (max_limits
->sclk
* 75) / 100;
2257 for (i
= table
->count
- 1; i
>= 0; i
--) {
2258 if (stable_p_state_sclk
>= table
->entries
[i
].clk
) {
2259 stable_p_state_sclk
= table
->entries
[i
].clk
;
2265 stable_p_state_sclk
= table
->entries
[0].clk
;
2267 sclk
= stable_p_state_sclk
;
2270 if (new_rps
->vce_active
) {
2271 if (sclk
< adev
->pm
.dpm
.vce_states
[adev
->pm
.dpm
.vce_level
].sclk
)
2272 sclk
= adev
->pm
.dpm
.vce_states
[adev
->pm
.dpm
.vce_level
].sclk
;
2275 ps
->need_dfs_bypass
= true;
2277 for (i
= 0; i
< ps
->num_levels
; i
++) {
2278 if (ps
->levels
[i
].sclk
< sclk
)
2279 ps
->levels
[i
].sclk
= sclk
;
2282 if (table
&& table
->count
) {
2283 for (i
= 0; i
< ps
->num_levels
; i
++) {
2284 if (pi
->high_voltage_t
&&
2285 (pi
->high_voltage_t
<
2286 kv_convert_8bit_index_to_voltage(adev
, ps
->levels
[i
].vddc_index
))) {
2287 kv_get_high_voltage_limit(adev
, &limit
);
2288 ps
->levels
[i
].sclk
= table
->entries
[limit
].clk
;
2292 struct sumo_sclk_voltage_mapping_table
*table
=
2293 &pi
->sys_info
.sclk_voltage_mapping_table
;
2295 for (i
= 0; i
< ps
->num_levels
; i
++) {
2296 if (pi
->high_voltage_t
&&
2297 (pi
->high_voltage_t
<
2298 kv_convert_8bit_index_to_voltage(adev
, ps
->levels
[i
].vddc_index
))) {
2299 kv_get_high_voltage_limit(adev
, &limit
);
2300 ps
->levels
[i
].sclk
= table
->entries
[limit
].sclk_frequency
;
2305 if (pi
->caps_stable_p_state
) {
2306 for (i
= 0; i
< ps
->num_levels
; i
++) {
2307 ps
->levels
[i
].sclk
= stable_p_state_sclk
;
2311 pi
->video_start
= new_rps
->dclk
|| new_rps
->vclk
||
2312 new_rps
->evclk
|| new_rps
->ecclk
;
2314 if ((new_rps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
) ==
2315 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
)
2316 pi
->battery_state
= true;
2318 pi
->battery_state
= false;
2320 if (adev
->asic_type
== CHIP_KABINI
|| adev
->asic_type
== CHIP_MULLINS
) {
2321 ps
->dpm0_pg_nb_ps_lo
= 0x1;
2322 ps
->dpm0_pg_nb_ps_hi
= 0x0;
2323 ps
->dpmx_nb_ps_lo
= 0x1;
2324 ps
->dpmx_nb_ps_hi
= 0x0;
2326 ps
->dpm0_pg_nb_ps_lo
= 0x3;
2327 ps
->dpm0_pg_nb_ps_hi
= 0x0;
2328 ps
->dpmx_nb_ps_lo
= 0x3;
2329 ps
->dpmx_nb_ps_hi
= 0x0;
2331 if (pi
->sys_info
.nb_dpm_enable
) {
2332 force_high
= (mclk
>= pi
->sys_info
.nbp_memory_clock
[3]) ||
2333 pi
->video_start
|| (adev
->pm
.dpm
.new_active_crtc_count
>= 3) ||
2334 pi
->disable_nb_ps3_in_battery
;
2335 ps
->dpm0_pg_nb_ps_lo
= force_high
? 0x2 : 0x3;
2336 ps
->dpm0_pg_nb_ps_hi
= 0x2;
2337 ps
->dpmx_nb_ps_lo
= force_high
? 0x2 : 0x3;
2338 ps
->dpmx_nb_ps_hi
= 0x2;
2343 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device
*adev
,
2344 u32 index
, bool enable
)
2346 struct kv_power_info
*pi
= kv_get_pi(adev
);
2348 pi
->graphics_level
[index
].EnabledForThrottle
= enable
? 1 : 0;
2351 static int kv_calculate_ds_divider(struct amdgpu_device
*adev
)
2353 struct kv_power_info
*pi
= kv_get_pi(adev
);
2354 u32 sclk_in_sr
= 10000; /* ??? */
2357 if (pi
->lowest_valid
> pi
->highest_valid
)
2360 for (i
= pi
->lowest_valid
; i
<= pi
->highest_valid
; i
++) {
2361 pi
->graphics_level
[i
].DeepSleepDivId
=
2362 kv_get_sleep_divider_id_from_clock(adev
,
2363 be32_to_cpu(pi
->graphics_level
[i
].SclkFrequency
),
2369 static int kv_calculate_nbps_level_settings(struct amdgpu_device
*adev
)
2371 struct kv_power_info
*pi
= kv_get_pi(adev
);
2374 struct amdgpu_clock_and_voltage_limits
*max_limits
=
2375 &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
;
2376 u32 mclk
= max_limits
->mclk
;
2378 if (pi
->lowest_valid
> pi
->highest_valid
)
2381 if (adev
->asic_type
== CHIP_KABINI
|| adev
->asic_type
== CHIP_MULLINS
) {
2382 for (i
= pi
->lowest_valid
; i
<= pi
->highest_valid
; i
++) {
2383 pi
->graphics_level
[i
].GnbSlow
= 1;
2384 pi
->graphics_level
[i
].ForceNbPs1
= 0;
2385 pi
->graphics_level
[i
].UpH
= 0;
2388 if (!pi
->sys_info
.nb_dpm_enable
)
2391 force_high
= ((mclk
>= pi
->sys_info
.nbp_memory_clock
[3]) ||
2392 (adev
->pm
.dpm
.new_active_crtc_count
>= 3) || pi
->video_start
);
2395 for (i
= pi
->lowest_valid
; i
<= pi
->highest_valid
; i
++)
2396 pi
->graphics_level
[i
].GnbSlow
= 0;
2398 if (pi
->battery_state
)
2399 pi
->graphics_level
[0].ForceNbPs1
= 1;
2401 pi
->graphics_level
[1].GnbSlow
= 0;
2402 pi
->graphics_level
[2].GnbSlow
= 0;
2403 pi
->graphics_level
[3].GnbSlow
= 0;
2404 pi
->graphics_level
[4].GnbSlow
= 0;
2407 for (i
= pi
->lowest_valid
; i
<= pi
->highest_valid
; i
++) {
2408 pi
->graphics_level
[i
].GnbSlow
= 1;
2409 pi
->graphics_level
[i
].ForceNbPs1
= 0;
2410 pi
->graphics_level
[i
].UpH
= 0;
2413 if (pi
->sys_info
.nb_dpm_enable
&& pi
->battery_state
) {
2414 pi
->graphics_level
[pi
->lowest_valid
].UpH
= 0x28;
2415 pi
->graphics_level
[pi
->lowest_valid
].GnbSlow
= 0;
2416 if (pi
->lowest_valid
!= pi
->highest_valid
)
2417 pi
->graphics_level
[pi
->lowest_valid
].ForceNbPs1
= 1;
2423 static int kv_calculate_dpm_settings(struct amdgpu_device
*adev
)
2425 struct kv_power_info
*pi
= kv_get_pi(adev
);
2428 if (pi
->lowest_valid
> pi
->highest_valid
)
2431 for (i
= pi
->lowest_valid
; i
<= pi
->highest_valid
; i
++)
2432 pi
->graphics_level
[i
].DisplayWatermark
= (i
== pi
->highest_valid
) ? 1 : 0;
2437 static void kv_init_graphics_levels(struct amdgpu_device
*adev
)
2439 struct kv_power_info
*pi
= kv_get_pi(adev
);
2441 struct amdgpu_clock_voltage_dependency_table
*table
=
2442 &adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
;
2444 if (table
&& table
->count
) {
2447 pi
->graphics_dpm_level_count
= 0;
2448 for (i
= 0; i
< table
->count
; i
++) {
2449 if (pi
->high_voltage_t
&&
2450 (pi
->high_voltage_t
<
2451 kv_convert_8bit_index_to_voltage(adev
, table
->entries
[i
].v
)))
2454 kv_set_divider_value(adev
, i
, table
->entries
[i
].clk
);
2455 vid_2bit
= kv_convert_vid7_to_vid2(adev
,
2456 &pi
->sys_info
.vid_mapping_table
,
2457 table
->entries
[i
].v
);
2458 kv_set_vid(adev
, i
, vid_2bit
);
2459 kv_set_at(adev
, i
, pi
->at
[i
]);
2460 kv_dpm_power_level_enabled_for_throttle(adev
, i
, true);
2461 pi
->graphics_dpm_level_count
++;
2464 struct sumo_sclk_voltage_mapping_table
*table
=
2465 &pi
->sys_info
.sclk_voltage_mapping_table
;
2467 pi
->graphics_dpm_level_count
= 0;
2468 for (i
= 0; i
< table
->num_max_dpm_entries
; i
++) {
2469 if (pi
->high_voltage_t
&&
2470 pi
->high_voltage_t
<
2471 kv_convert_2bit_index_to_voltage(adev
, table
->entries
[i
].vid_2bit
))
2474 kv_set_divider_value(adev
, i
, table
->entries
[i
].sclk_frequency
);
2475 kv_set_vid(adev
, i
, table
->entries
[i
].vid_2bit
);
2476 kv_set_at(adev
, i
, pi
->at
[i
]);
2477 kv_dpm_power_level_enabled_for_throttle(adev
, i
, true);
2478 pi
->graphics_dpm_level_count
++;
2482 for (i
= 0; i
< SMU7_MAX_LEVELS_GRAPHICS
; i
++)
2483 kv_dpm_power_level_enable(adev
, i
, false);
2486 static void kv_enable_new_levels(struct amdgpu_device
*adev
)
2488 struct kv_power_info
*pi
= kv_get_pi(adev
);
2491 for (i
= 0; i
< SMU7_MAX_LEVELS_GRAPHICS
; i
++) {
2492 if (i
>= pi
->lowest_valid
&& i
<= pi
->highest_valid
)
2493 kv_dpm_power_level_enable(adev
, i
, true);
2497 static int kv_set_enabled_level(struct amdgpu_device
*adev
, u32 level
)
2499 u32 new_mask
= (1 << level
);
2501 return amdgpu_kv_send_msg_to_smc_with_parameter(adev
,
2502 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
2506 static int kv_set_enabled_levels(struct amdgpu_device
*adev
)
2508 struct kv_power_info
*pi
= kv_get_pi(adev
);
2509 u32 i
, new_mask
= 0;
2511 for (i
= pi
->lowest_valid
; i
<= pi
->highest_valid
; i
++)
2512 new_mask
|= (1 << i
);
2514 return amdgpu_kv_send_msg_to_smc_with_parameter(adev
,
2515 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
2519 static void kv_program_nbps_index_settings(struct amdgpu_device
*adev
,
2520 struct amdgpu_ps
*new_rps
)
2522 struct kv_ps
*new_ps
= kv_get_ps(new_rps
);
2523 struct kv_power_info
*pi
= kv_get_pi(adev
);
2526 if (adev
->asic_type
== CHIP_KABINI
|| adev
->asic_type
== CHIP_MULLINS
)
2529 if (pi
->sys_info
.nb_dpm_enable
) {
2530 nbdpmconfig1
= RREG32_SMC(ixNB_DPM_CONFIG_1
);
2531 nbdpmconfig1
&= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK
|
2532 NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK
|
2533 NB_DPM_CONFIG_1__DpmXNbPsLo_MASK
|
2534 NB_DPM_CONFIG_1__DpmXNbPsHi_MASK
);
2535 nbdpmconfig1
|= (new_ps
->dpm0_pg_nb_ps_lo
<< NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT
) |
2536 (new_ps
->dpm0_pg_nb_ps_hi
<< NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT
) |
2537 (new_ps
->dpmx_nb_ps_lo
<< NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT
) |
2538 (new_ps
->dpmx_nb_ps_hi
<< NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT
);
2539 WREG32_SMC(ixNB_DPM_CONFIG_1
, nbdpmconfig1
);
2543 static int kv_set_thermal_temperature_range(struct amdgpu_device
*adev
,
2544 int min_temp
, int max_temp
)
2546 int low_temp
= 0 * 1000;
2547 int high_temp
= 255 * 1000;
2550 if (low_temp
< min_temp
)
2551 low_temp
= min_temp
;
2552 if (high_temp
> max_temp
)
2553 high_temp
= max_temp
;
2554 if (high_temp
< low_temp
) {
2555 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp
, high_temp
);
2559 tmp
= RREG32_SMC(ixCG_THERMAL_INT_CTRL
);
2560 tmp
&= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK
|
2561 CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK
);
2562 tmp
|= ((49 + (high_temp
/ 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT
) |
2563 ((49 + (low_temp
/ 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT
);
2564 WREG32_SMC(ixCG_THERMAL_INT_CTRL
, tmp
);
2566 adev
->pm
.dpm
.thermal
.min_temp
= low_temp
;
2567 adev
->pm
.dpm
.thermal
.max_temp
= high_temp
;
2573 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
2574 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
2575 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5
;
2576 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6
;
2577 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7
;
2578 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8
;
2581 static int kv_parse_sys_info_table(struct amdgpu_device
*adev
)
2583 struct kv_power_info
*pi
= kv_get_pi(adev
);
2584 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
2585 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
2586 union igp_info
*igp_info
;
2591 if (amdgpu_atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2592 &frev
, &crev
, &data_offset
)) {
2593 igp_info
= (union igp_info
*)(mode_info
->atom_context
->bios
+
2597 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
2600 pi
->sys_info
.bootup_sclk
= le32_to_cpu(igp_info
->info_8
.ulBootUpEngineClock
);
2601 pi
->sys_info
.bootup_uma_clk
= le32_to_cpu(igp_info
->info_8
.ulBootUpUMAClock
);
2602 pi
->sys_info
.bootup_nb_voltage_index
=
2603 le16_to_cpu(igp_info
->info_8
.usBootUpNBVoltage
);
2604 if (igp_info
->info_8
.ucHtcTmpLmt
== 0)
2605 pi
->sys_info
.htc_tmp_lmt
= 203;
2607 pi
->sys_info
.htc_tmp_lmt
= igp_info
->info_8
.ucHtcTmpLmt
;
2608 if (igp_info
->info_8
.ucHtcHystLmt
== 0)
2609 pi
->sys_info
.htc_hyst_lmt
= 5;
2611 pi
->sys_info
.htc_hyst_lmt
= igp_info
->info_8
.ucHtcHystLmt
;
2612 if (pi
->sys_info
.htc_tmp_lmt
<= pi
->sys_info
.htc_hyst_lmt
) {
2613 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2616 if (le32_to_cpu(igp_info
->info_8
.ulSystemConfig
) & (1 << 3))
2617 pi
->sys_info
.nb_dpm_enable
= true;
2619 pi
->sys_info
.nb_dpm_enable
= false;
2621 for (i
= 0; i
< KV_NUM_NBPSTATES
; i
++) {
2622 pi
->sys_info
.nbp_memory_clock
[i
] =
2623 le32_to_cpu(igp_info
->info_8
.ulNbpStateMemclkFreq
[i
]);
2624 pi
->sys_info
.nbp_n_clock
[i
] =
2625 le32_to_cpu(igp_info
->info_8
.ulNbpStateNClkFreq
[i
]);
2627 if (le32_to_cpu(igp_info
->info_8
.ulGPUCapInfo
) &
2628 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS
)
2629 pi
->caps_enable_dfs_bypass
= true;
2631 sumo_construct_sclk_voltage_mapping_table(adev
,
2632 &pi
->sys_info
.sclk_voltage_mapping_table
,
2633 igp_info
->info_8
.sAvail_SCLK
);
2635 sumo_construct_vid_mapping_table(adev
,
2636 &pi
->sys_info
.vid_mapping_table
,
2637 igp_info
->info_8
.sAvail_SCLK
);
2639 kv_construct_max_power_limits_table(adev
,
2640 &adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
);
2646 struct _ATOM_POWERPLAY_INFO info
;
2647 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
2648 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
2649 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
2650 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
2651 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
2654 union pplib_clock_info
{
2655 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
2656 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
2657 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
2658 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
2661 union pplib_power_state
{
2662 struct _ATOM_PPLIB_STATE v1
;
2663 struct _ATOM_PPLIB_STATE_V2 v2
;
2666 static void kv_patch_boot_state(struct amdgpu_device
*adev
,
2669 struct kv_power_info
*pi
= kv_get_pi(adev
);
2672 ps
->levels
[0] = pi
->boot_pl
;
2675 static void kv_parse_pplib_non_clock_info(struct amdgpu_device
*adev
,
2676 struct amdgpu_ps
*rps
,
2677 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
,
2680 struct kv_ps
*ps
= kv_get_ps(rps
);
2682 rps
->caps
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
2683 rps
->class = le16_to_cpu(non_clock_info
->usClassification
);
2684 rps
->class2
= le16_to_cpu(non_clock_info
->usClassification2
);
2686 if (ATOM_PPLIB_NONCLOCKINFO_VER1
< table_rev
) {
2687 rps
->vclk
= le32_to_cpu(non_clock_info
->ulVCLK
);
2688 rps
->dclk
= le32_to_cpu(non_clock_info
->ulDCLK
);
2694 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_BOOT
) {
2695 adev
->pm
.dpm
.boot_ps
= rps
;
2696 kv_patch_boot_state(adev
, ps
);
2698 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE
)
2699 adev
->pm
.dpm
.uvd_ps
= rps
;
2702 static void kv_parse_pplib_clock_info(struct amdgpu_device
*adev
,
2703 struct amdgpu_ps
*rps
, int index
,
2704 union pplib_clock_info
*clock_info
)
2706 struct kv_power_info
*pi
= kv_get_pi(adev
);
2707 struct kv_ps
*ps
= kv_get_ps(rps
);
2708 struct kv_pl
*pl
= &ps
->levels
[index
];
2711 sclk
= le16_to_cpu(clock_info
->sumo
.usEngineClockLow
);
2712 sclk
|= clock_info
->sumo
.ucEngineClockHigh
<< 16;
2714 pl
->vddc_index
= clock_info
->sumo
.vddcIndex
;
2716 ps
->num_levels
= index
+ 1;
2718 if (pi
->caps_sclk_ds
) {
2719 pl
->ds_divider_index
= 5;
2720 pl
->ss_divider_index
= 5;
2724 static int kv_parse_power_table(struct amdgpu_device
*adev
)
2726 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
2727 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2728 union pplib_power_state
*power_state
;
2729 int i
, j
, k
, non_clock_array_index
, clock_array_index
;
2730 union pplib_clock_info
*clock_info
;
2731 struct _StateArray
*state_array
;
2732 struct _ClockInfoArray
*clock_info_array
;
2733 struct _NonClockInfoArray
*non_clock_info_array
;
2734 union power_info
*power_info
;
2735 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2738 u8
*power_state_offset
;
2741 if (!amdgpu_atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2742 &frev
, &crev
, &data_offset
))
2744 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2746 amdgpu_add_thermal_controller(adev
);
2748 state_array
= (struct _StateArray
*)
2749 (mode_info
->atom_context
->bios
+ data_offset
+
2750 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
));
2751 clock_info_array
= (struct _ClockInfoArray
*)
2752 (mode_info
->atom_context
->bios
+ data_offset
+
2753 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
));
2754 non_clock_info_array
= (struct _NonClockInfoArray
*)
2755 (mode_info
->atom_context
->bios
+ data_offset
+
2756 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
));
2758 adev
->pm
.dpm
.ps
= kzalloc(sizeof(struct amdgpu_ps
) *
2759 state_array
->ucNumEntries
, GFP_KERNEL
);
2760 if (!adev
->pm
.dpm
.ps
)
2762 power_state_offset
= (u8
*)state_array
->states
;
2763 for (i
= 0; i
< state_array
->ucNumEntries
; i
++) {
2765 power_state
= (union pplib_power_state
*)power_state_offset
;
2766 non_clock_array_index
= power_state
->v2
.nonClockInfoIndex
;
2767 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2768 &non_clock_info_array
->nonClockInfo
[non_clock_array_index
];
2769 ps
= kzalloc(sizeof(struct kv_ps
), GFP_KERNEL
);
2771 kfree(adev
->pm
.dpm
.ps
);
2774 adev
->pm
.dpm
.ps
[i
].ps_priv
= ps
;
2776 idx
= (u8
*)&power_state
->v2
.clockInfoIndex
[0];
2777 for (j
= 0; j
< power_state
->v2
.ucNumDPMLevels
; j
++) {
2778 clock_array_index
= idx
[j
];
2779 if (clock_array_index
>= clock_info_array
->ucNumEntries
)
2781 if (k
>= SUMO_MAX_HARDWARE_POWERLEVELS
)
2783 clock_info
= (union pplib_clock_info
*)
2784 ((u8
*)&clock_info_array
->clockInfo
[0] +
2785 (clock_array_index
* clock_info_array
->ucEntrySize
));
2786 kv_parse_pplib_clock_info(adev
,
2787 &adev
->pm
.dpm
.ps
[i
], k
,
2791 kv_parse_pplib_non_clock_info(adev
, &adev
->pm
.dpm
.ps
[i
],
2793 non_clock_info_array
->ucEntrySize
);
2794 power_state_offset
+= 2 + power_state
->v2
.ucNumDPMLevels
;
2796 adev
->pm
.dpm
.num_ps
= state_array
->ucNumEntries
;
2798 /* fill in the vce power states */
2799 for (i
= 0; i
< AMDGPU_MAX_VCE_LEVELS
; i
++) {
2801 clock_array_index
= adev
->pm
.dpm
.vce_states
[i
].clk_idx
;
2802 clock_info
= (union pplib_clock_info
*)
2803 &clock_info_array
->clockInfo
[clock_array_index
* clock_info_array
->ucEntrySize
];
2804 sclk
= le16_to_cpu(clock_info
->sumo
.usEngineClockLow
);
2805 sclk
|= clock_info
->sumo
.ucEngineClockHigh
<< 16;
2806 adev
->pm
.dpm
.vce_states
[i
].sclk
= sclk
;
2807 adev
->pm
.dpm
.vce_states
[i
].mclk
= 0;
2813 static int kv_dpm_init(struct amdgpu_device
*adev
)
2815 struct kv_power_info
*pi
;
2818 pi
= kzalloc(sizeof(struct kv_power_info
), GFP_KERNEL
);
2821 adev
->pm
.dpm
.priv
= pi
;
2823 ret
= amdgpu_get_platform_caps(adev
);
2827 ret
= amdgpu_parse_extended_power_table(adev
);
2831 for (i
= 0; i
< SUMO_MAX_HARDWARE_POWERLEVELS
; i
++)
2832 pi
->at
[i
] = TRINITY_AT_DFLT
;
2834 pi
->sram_end
= SMC_RAM_END
;
2836 pi
->enable_nb_dpm
= true;
2838 pi
->caps_power_containment
= true;
2839 pi
->caps_cac
= true;
2840 pi
->enable_didt
= false;
2841 if (pi
->enable_didt
) {
2842 pi
->caps_sq_ramping
= true;
2843 pi
->caps_db_ramping
= true;
2844 pi
->caps_td_ramping
= true;
2845 pi
->caps_tcp_ramping
= true;
2848 if (amdgpu_sclk_deep_sleep_en
)
2849 pi
->caps_sclk_ds
= true;
2851 pi
->caps_sclk_ds
= false;
2853 pi
->enable_auto_thermal_throttling
= true;
2854 pi
->disable_nb_ps3_in_battery
= false;
2855 if (amdgpu_bapm
== 0)
2856 pi
->bapm_enable
= false;
2858 pi
->bapm_enable
= true;
2859 pi
->voltage_drop_t
= 0;
2860 pi
->caps_sclk_throttle_low_notification
= false;
2861 pi
->caps_fps
= false; /* true? */
2862 pi
->caps_uvd_pg
= (adev
->pg_flags
& AMD_PG_SUPPORT_UVD
) ? true : false;
2863 pi
->caps_uvd_dpm
= true;
2864 pi
->caps_vce_pg
= (adev
->pg_flags
& AMD_PG_SUPPORT_VCE
) ? true : false;
2865 pi
->caps_samu_pg
= (adev
->pg_flags
& AMD_PG_SUPPORT_SAMU
) ? true : false;
2866 pi
->caps_acp_pg
= (adev
->pg_flags
& AMD_PG_SUPPORT_ACP
) ? true : false;
2867 pi
->caps_stable_p_state
= false;
2869 ret
= kv_parse_sys_info_table(adev
);
2873 kv_patch_voltage_values(adev
);
2874 kv_construct_boot_state(adev
);
2876 ret
= kv_parse_power_table(adev
);
2880 pi
->enable_dpm
= true;
2886 kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device
*adev
,
2889 struct kv_power_info
*pi
= kv_get_pi(adev
);
2891 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX
) &
2892 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK
) >>
2893 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT
;
2897 if (current_index
>= SMU__NUM_SCLK_DPM_STATE
) {
2898 seq_printf(m
, "invalid dpm profile %d\n", current_index
);
2900 sclk
= be32_to_cpu(pi
->graphics_level
[current_index
].SclkFrequency
);
2901 tmp
= (RREG32_SMC(ixSMU_VOLTAGE_STATUS
) &
2902 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK
) >>
2903 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT
;
2904 vddc
= kv_convert_8bit_index_to_voltage(adev
, (u16
)tmp
);
2905 seq_printf(m
, "uvd %sabled\n", pi
->uvd_power_gated
? "dis" : "en");
2906 seq_printf(m
, "vce %sabled\n", pi
->vce_power_gated
? "dis" : "en");
2907 seq_printf(m
, "power level %d sclk: %u vddc: %u\n",
2908 current_index
, sclk
, vddc
);
2913 kv_dpm_print_power_state(struct amdgpu_device
*adev
,
2914 struct amdgpu_ps
*rps
)
2917 struct kv_ps
*ps
= kv_get_ps(rps
);
2919 amdgpu_dpm_print_class_info(rps
->class, rps
->class2
);
2920 amdgpu_dpm_print_cap_info(rps
->caps
);
2921 printk("\tuvd vclk: %d dclk: %d\n", rps
->vclk
, rps
->dclk
);
2922 for (i
= 0; i
< ps
->num_levels
; i
++) {
2923 struct kv_pl
*pl
= &ps
->levels
[i
];
2924 printk("\t\tpower level %d sclk: %u vddc: %u\n",
2926 kv_convert_8bit_index_to_voltage(adev
, pl
->vddc_index
));
2928 amdgpu_dpm_print_ps_status(adev
, rps
);
2931 static void kv_dpm_fini(struct amdgpu_device
*adev
)
2935 for (i
= 0; i
< adev
->pm
.dpm
.num_ps
; i
++) {
2936 kfree(adev
->pm
.dpm
.ps
[i
].ps_priv
);
2938 kfree(adev
->pm
.dpm
.ps
);
2939 kfree(adev
->pm
.dpm
.priv
);
2940 amdgpu_free_extended_power_table(adev
);
2943 static void kv_dpm_display_configuration_changed(struct amdgpu_device
*adev
)
2948 static u32
kv_dpm_get_sclk(struct amdgpu_device
*adev
, bool low
)
2950 struct kv_power_info
*pi
= kv_get_pi(adev
);
2951 struct kv_ps
*requested_state
= kv_get_ps(&pi
->requested_rps
);
2954 return requested_state
->levels
[0].sclk
;
2956 return requested_state
->levels
[requested_state
->num_levels
- 1].sclk
;
2959 static u32
kv_dpm_get_mclk(struct amdgpu_device
*adev
, bool low
)
2961 struct kv_power_info
*pi
= kv_get_pi(adev
);
2963 return pi
->sys_info
.bootup_uma_clk
;
2966 /* get temperature in millidegrees */
2967 static int kv_dpm_get_temp(struct amdgpu_device
*adev
)
2970 int actual_temp
= 0;
2972 temp
= RREG32_SMC(0xC0300E0C);
2975 actual_temp
= (temp
/ 8) - 49;
2979 actual_temp
= actual_temp
* 1000;
2984 static int kv_dpm_early_init(void *handle
)
2986 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2988 kv_dpm_set_dpm_funcs(adev
);
2989 kv_dpm_set_irq_funcs(adev
);
2994 static int kv_dpm_late_init(void *handle
)
2996 /* powerdown unused blocks for now */
2997 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3003 /* init the sysfs and debugfs files late */
3004 ret
= amdgpu_pm_sysfs_init(adev
);
3008 kv_dpm_powergate_acp(adev
, true);
3009 kv_dpm_powergate_samu(adev
, true);
3010 kv_dpm_powergate_vce(adev
, true);
3011 kv_dpm_powergate_uvd(adev
, true);
3016 static int kv_dpm_sw_init(void *handle
)
3019 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3021 ret
= amdgpu_irq_add_id(adev
, 230, &adev
->pm
.dpm
.thermal
.irq
);
3025 ret
= amdgpu_irq_add_id(adev
, 231, &adev
->pm
.dpm
.thermal
.irq
);
3029 /* default to balanced state */
3030 adev
->pm
.dpm
.state
= POWER_STATE_TYPE_BALANCED
;
3031 adev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BALANCED
;
3032 adev
->pm
.dpm
.forced_level
= AMDGPU_DPM_FORCED_LEVEL_AUTO
;
3033 adev
->pm
.default_sclk
= adev
->clock
.default_sclk
;
3034 adev
->pm
.default_mclk
= adev
->clock
.default_mclk
;
3035 adev
->pm
.current_sclk
= adev
->clock
.default_sclk
;
3036 adev
->pm
.current_mclk
= adev
->clock
.default_mclk
;
3037 adev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
3039 if (amdgpu_dpm
== 0)
3042 INIT_WORK(&adev
->pm
.dpm
.thermal
.work
, amdgpu_dpm_thermal_work_handler
);
3043 mutex_lock(&adev
->pm
.mutex
);
3044 ret
= kv_dpm_init(adev
);
3047 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.requested_ps
= adev
->pm
.dpm
.boot_ps
;
3048 if (amdgpu_dpm
== 1)
3049 amdgpu_pm_print_power_states(adev
);
3050 mutex_unlock(&adev
->pm
.mutex
);
3051 DRM_INFO("amdgpu: dpm initialized\n");
3057 mutex_unlock(&adev
->pm
.mutex
);
3058 DRM_ERROR("amdgpu: dpm initialization failed\n");
3062 static int kv_dpm_sw_fini(void *handle
)
3064 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3066 mutex_lock(&adev
->pm
.mutex
);
3067 amdgpu_pm_sysfs_fini(adev
);
3069 mutex_unlock(&adev
->pm
.mutex
);
3074 static int kv_dpm_hw_init(void *handle
)
3077 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3079 mutex_lock(&adev
->pm
.mutex
);
3080 kv_dpm_setup_asic(adev
);
3081 ret
= kv_dpm_enable(adev
);
3083 adev
->pm
.dpm_enabled
= false;
3085 adev
->pm
.dpm_enabled
= true;
3086 mutex_unlock(&adev
->pm
.mutex
);
3091 static int kv_dpm_hw_fini(void *handle
)
3093 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3095 if (adev
->pm
.dpm_enabled
) {
3096 mutex_lock(&adev
->pm
.mutex
);
3097 kv_dpm_disable(adev
);
3098 mutex_unlock(&adev
->pm
.mutex
);
3104 static int kv_dpm_suspend(void *handle
)
3106 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3108 if (adev
->pm
.dpm_enabled
) {
3109 mutex_lock(&adev
->pm
.mutex
);
3111 kv_dpm_disable(adev
);
3112 /* reset the power state */
3113 adev
->pm
.dpm
.current_ps
= adev
->pm
.dpm
.requested_ps
= adev
->pm
.dpm
.boot_ps
;
3114 mutex_unlock(&adev
->pm
.mutex
);
3119 static int kv_dpm_resume(void *handle
)
3122 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3124 if (adev
->pm
.dpm_enabled
) {
3125 /* asic init will reset to the boot state */
3126 mutex_lock(&adev
->pm
.mutex
);
3127 kv_dpm_setup_asic(adev
);
3128 ret
= kv_dpm_enable(adev
);
3130 adev
->pm
.dpm_enabled
= false;
3132 adev
->pm
.dpm_enabled
= true;
3133 mutex_unlock(&adev
->pm
.mutex
);
3134 if (adev
->pm
.dpm_enabled
)
3135 amdgpu_pm_compute_clocks(adev
);
3140 static bool kv_dpm_is_idle(void *handle
)
3145 static int kv_dpm_wait_for_idle(void *handle
)
3151 static int kv_dpm_soft_reset(void *handle
)
3156 static int kv_dpm_set_interrupt_state(struct amdgpu_device
*adev
,
3157 struct amdgpu_irq_src
*src
,
3159 enum amdgpu_interrupt_state state
)
3164 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
:
3166 case AMDGPU_IRQ_STATE_DISABLE
:
3167 cg_thermal_int
= RREG32_SMC(ixCG_THERMAL_INT_CTRL
);
3168 cg_thermal_int
&= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK
;
3169 WREG32_SMC(ixCG_THERMAL_INT_CTRL
, cg_thermal_int
);
3171 case AMDGPU_IRQ_STATE_ENABLE
:
3172 cg_thermal_int
= RREG32_SMC(ixCG_THERMAL_INT_CTRL
);
3173 cg_thermal_int
|= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK
;
3174 WREG32_SMC(ixCG_THERMAL_INT_CTRL
, cg_thermal_int
);
3181 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
:
3183 case AMDGPU_IRQ_STATE_DISABLE
:
3184 cg_thermal_int
= RREG32_SMC(ixCG_THERMAL_INT_CTRL
);
3185 cg_thermal_int
&= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK
;
3186 WREG32_SMC(ixCG_THERMAL_INT_CTRL
, cg_thermal_int
);
3188 case AMDGPU_IRQ_STATE_ENABLE
:
3189 cg_thermal_int
= RREG32_SMC(ixCG_THERMAL_INT_CTRL
);
3190 cg_thermal_int
|= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK
;
3191 WREG32_SMC(ixCG_THERMAL_INT_CTRL
, cg_thermal_int
);
3204 static int kv_dpm_process_interrupt(struct amdgpu_device
*adev
,
3205 struct amdgpu_irq_src
*source
,
3206 struct amdgpu_iv_entry
*entry
)
3208 bool queue_thermal
= false;
3213 switch (entry
->src_id
) {
3214 case 230: /* thermal low to high */
3215 DRM_DEBUG("IH: thermal low to high\n");
3216 adev
->pm
.dpm
.thermal
.high_to_low
= false;
3217 queue_thermal
= true;
3219 case 231: /* thermal high to low */
3220 DRM_DEBUG("IH: thermal high to low\n");
3221 adev
->pm
.dpm
.thermal
.high_to_low
= true;
3222 queue_thermal
= true;
3229 schedule_work(&adev
->pm
.dpm
.thermal
.work
);
3234 static int kv_dpm_set_clockgating_state(void *handle
,
3235 enum amd_clockgating_state state
)
3240 static int kv_dpm_set_powergating_state(void *handle
,
3241 enum amd_powergating_state state
)
3246 const struct amd_ip_funcs kv_dpm_ip_funcs
= {
3248 .early_init
= kv_dpm_early_init
,
3249 .late_init
= kv_dpm_late_init
,
3250 .sw_init
= kv_dpm_sw_init
,
3251 .sw_fini
= kv_dpm_sw_fini
,
3252 .hw_init
= kv_dpm_hw_init
,
3253 .hw_fini
= kv_dpm_hw_fini
,
3254 .suspend
= kv_dpm_suspend
,
3255 .resume
= kv_dpm_resume
,
3256 .is_idle
= kv_dpm_is_idle
,
3257 .wait_for_idle
= kv_dpm_wait_for_idle
,
3258 .soft_reset
= kv_dpm_soft_reset
,
3259 .set_clockgating_state
= kv_dpm_set_clockgating_state
,
3260 .set_powergating_state
= kv_dpm_set_powergating_state
,
3263 static const struct amdgpu_dpm_funcs kv_dpm_funcs
= {
3264 .get_temperature
= &kv_dpm_get_temp
,
3265 .pre_set_power_state
= &kv_dpm_pre_set_power_state
,
3266 .set_power_state
= &kv_dpm_set_power_state
,
3267 .post_set_power_state
= &kv_dpm_post_set_power_state
,
3268 .display_configuration_changed
= &kv_dpm_display_configuration_changed
,
3269 .get_sclk
= &kv_dpm_get_sclk
,
3270 .get_mclk
= &kv_dpm_get_mclk
,
3271 .print_power_state
= &kv_dpm_print_power_state
,
3272 .debugfs_print_current_performance_level
= &kv_dpm_debugfs_print_current_performance_level
,
3273 .force_performance_level
= &kv_dpm_force_performance_level
,
3274 .powergate_uvd
= &kv_dpm_powergate_uvd
,
3275 .enable_bapm
= &kv_dpm_enable_bapm
,
3278 static void kv_dpm_set_dpm_funcs(struct amdgpu_device
*adev
)
3280 if (adev
->pm
.funcs
== NULL
)
3281 adev
->pm
.funcs
= &kv_dpm_funcs
;
3284 static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs
= {
3285 .set
= kv_dpm_set_interrupt_state
,
3286 .process
= kv_dpm_process_interrupt
,
3289 static void kv_dpm_set_irq_funcs(struct amdgpu_device
*adev
)
3291 adev
->pm
.dpm
.thermal
.irq
.num_types
= AMDGPU_THERMAL_IRQ_LAST
;
3292 adev
->pm
.dpm
.thermal
.irq
.funcs
= &kv_dpm_irq_funcs
;