2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_2_4_d.h"
33 #include "oss/oss_2_4_sh_mask.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "iceland_sdma_pkt_open.h"
47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device
*adev
);
48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device
*adev
);
49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device
*adev
);
50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device
*adev
);
52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
55 static const u32 sdma_offsets
[SDMA_MAX_INSTANCE
] =
57 SDMA0_REGISTER_OFFSET
,
61 static const u32 golden_settings_iceland_a11
[] =
63 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
64 mmSDMA0_CLK_CTRL
, 0xff000fff, 0x00000000,
65 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
66 mmSDMA1_CLK_CTRL
, 0xff000fff, 0x00000000,
69 static const u32 iceland_mgcg_cgcg_init
[] =
71 mmSDMA0_CLK_CTRL
, 0xff000ff0, 0x00000100,
72 mmSDMA1_CLK_CTRL
, 0xff000ff0, 0x00000100
77 * Starting with CIK, the GPU has new asynchronous
78 * DMA engines. These engines are used for compute
79 * and gfx. There are two DMA engines (SDMA0, SDMA1)
80 * and each one supports 1 ring buffer used for gfx
81 * and 2 queues used for compute.
83 * The programming model is very similar to the CP
84 * (ring buffer, IBs, etc.), but sDMA has it's own
85 * packet format that is different from the PM4 format
86 * used by the CP. sDMA supports copying data, writing
87 * embedded data, solid fills, and a number of other
88 * things. It also has support for tiling/detiling of
92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device
*adev
)
94 switch (adev
->asic_type
) {
96 amdgpu_program_register_sequence(adev
,
97 iceland_mgcg_cgcg_init
,
98 (const u32
)ARRAY_SIZE(iceland_mgcg_cgcg_init
));
99 amdgpu_program_register_sequence(adev
,
100 golden_settings_iceland_a11
,
101 (const u32
)ARRAY_SIZE(golden_settings_iceland_a11
));
109 * sdma_v2_4_init_microcode - load ucode images from disk
111 * @adev: amdgpu_device pointer
113 * Use the firmware interface to load the ucode images into
114 * the driver (not loaded into hw).
115 * Returns 0 on success, error on failure.
117 static int sdma_v2_4_init_microcode(struct amdgpu_device
*adev
)
119 const char *chip_name
;
122 struct amdgpu_firmware_info
*info
= NULL
;
123 const struct common_firmware_header
*header
= NULL
;
124 const struct sdma_firmware_header_v1_0
*hdr
;
128 switch (adev
->asic_type
) {
135 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
137 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma.bin", chip_name
);
139 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma1.bin", chip_name
);
140 err
= request_firmware(&adev
->sdma
[i
].fw
, fw_name
, adev
->dev
);
143 err
= amdgpu_ucode_validate(adev
->sdma
[i
].fw
);
146 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
[i
].fw
->data
;
147 adev
->sdma
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
148 adev
->sdma
[i
].feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
149 if (adev
->sdma
[i
].feature_version
>= 20)
150 adev
->sdma
[i
].burst_nop
= true;
152 if (adev
->firmware
.smu_load
) {
153 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_SDMA0
+ i
];
154 info
->ucode_id
= AMDGPU_UCODE_ID_SDMA0
+ i
;
155 info
->fw
= adev
->sdma
[i
].fw
;
156 header
= (const struct common_firmware_header
*)info
->fw
->data
;
157 adev
->firmware
.fw_size
+=
158 ALIGN(le32_to_cpu(header
->ucode_size_bytes
), PAGE_SIZE
);
165 "sdma_v2_4: Failed to load firmware \"%s\"\n",
167 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
168 release_firmware(adev
->sdma
[i
].fw
);
169 adev
->sdma
[i
].fw
= NULL
;
176 * sdma_v2_4_ring_get_rptr - get the current read pointer
178 * @ring: amdgpu ring pointer
180 * Get the current rptr from the hardware (VI+).
182 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring
*ring
)
186 /* XXX check if swapping is necessary on BE */
187 rptr
= ring
->adev
->wb
.wb
[ring
->rptr_offs
] >> 2;
193 * sdma_v2_4_ring_get_wptr - get the current write pointer
195 * @ring: amdgpu ring pointer
197 * Get the current wptr from the hardware (VI+).
199 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring
*ring
)
201 struct amdgpu_device
*adev
= ring
->adev
;
202 int me
= (ring
== &ring
->adev
->sdma
[0].ring
) ? 0 : 1;
203 u32 wptr
= RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
]) >> 2;
209 * sdma_v2_4_ring_set_wptr - commit the write pointer
211 * @ring: amdgpu ring pointer
213 * Write the wptr back to the hardware (VI+).
215 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring
*ring
)
217 struct amdgpu_device
*adev
= ring
->adev
;
218 int me
= (ring
== &ring
->adev
->sdma
[0].ring
) ? 0 : 1;
220 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
], ring
->wptr
<< 2);
223 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
225 struct amdgpu_sdma
*sdma
= amdgpu_get_sdma_instance(ring
);
228 for (i
= 0; i
< count
; i
++)
229 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
230 amdgpu_ring_write(ring
, ring
->nop
|
231 SDMA_PKT_NOP_HEADER_COUNT(count
- 1));
233 amdgpu_ring_write(ring
, ring
->nop
);
237 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
239 * @ring: amdgpu ring pointer
240 * @ib: IB object to schedule
242 * Schedule an IB in the DMA ring (VI).
244 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring
*ring
,
245 struct amdgpu_ib
*ib
)
247 u32 vmid
= (ib
->vm
? ib
->vm
->ids
[ring
->idx
].id
: 0) & 0xf;
248 u32 next_rptr
= ring
->wptr
+ 5;
250 while ((next_rptr
& 7) != 2)
255 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
256 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
));
257 amdgpu_ring_write(ring
, lower_32_bits(ring
->next_rptr_gpu_addr
) & 0xfffffffc);
258 amdgpu_ring_write(ring
, upper_32_bits(ring
->next_rptr_gpu_addr
));
259 amdgpu_ring_write(ring
, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
260 amdgpu_ring_write(ring
, next_rptr
);
262 /* IB packet must end on a 8 DW boundary */
263 sdma_v2_4_ring_insert_nop(ring
, (10 - (ring
->wptr
& 7)) % 8);
265 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT
) |
266 SDMA_PKT_INDIRECT_HEADER_VMID(vmid
));
267 /* base must be 32 byte aligned */
268 amdgpu_ring_write(ring
, lower_32_bits(ib
->gpu_addr
) & 0xffffffe0);
269 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
270 amdgpu_ring_write(ring
, ib
->length_dw
);
271 amdgpu_ring_write(ring
, 0);
272 amdgpu_ring_write(ring
, 0);
277 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
279 * @ring: amdgpu ring pointer
281 * Emit an hdp flush packet on the requested DMA ring.
283 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
285 u32 ref_and_mask
= 0;
287 if (ring
== &ring
->adev
->sdma
[0].ring
)
288 ref_and_mask
= REG_SET_FIELD(ref_and_mask
, GPU_HDP_FLUSH_DONE
, SDMA0
, 1);
290 ref_and_mask
= REG_SET_FIELD(ref_and_mask
, GPU_HDP_FLUSH_DONE
, SDMA1
, 1);
292 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
293 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
294 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
295 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
<< 2);
296 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
<< 2);
297 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
298 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
299 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
300 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
304 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
306 * @ring: amdgpu ring pointer
307 * @fence: amdgpu fence object
309 * Add a DMA fence packet to the ring to write
310 * the fence seq number and DMA trap packet to generate
311 * an interrupt if needed (VI).
313 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
316 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
317 /* write the fence */
318 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
));
319 amdgpu_ring_write(ring
, lower_32_bits(addr
));
320 amdgpu_ring_write(ring
, upper_32_bits(addr
));
321 amdgpu_ring_write(ring
, lower_32_bits(seq
));
323 /* optionally write high bits as well */
326 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
));
327 amdgpu_ring_write(ring
, lower_32_bits(addr
));
328 amdgpu_ring_write(ring
, upper_32_bits(addr
));
329 amdgpu_ring_write(ring
, upper_32_bits(seq
));
332 /* generate an interrupt */
333 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP
));
334 amdgpu_ring_write(ring
, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
338 * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring
340 * @ring: amdgpu_ring structure holding ring information
341 * @semaphore: amdgpu semaphore object
342 * @emit_wait: wait or signal semaphore
344 * Add a DMA semaphore packet to the ring wait on or signal
347 static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring
*ring
,
348 struct amdgpu_semaphore
*semaphore
,
351 u64 addr
= semaphore
->gpu_addr
;
352 u32 sig
= emit_wait
? 0 : 1;
354 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SEM
) |
355 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig
));
356 amdgpu_ring_write(ring
, lower_32_bits(addr
) & 0xfffffff8);
357 amdgpu_ring_write(ring
, upper_32_bits(addr
));
363 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
365 * @adev: amdgpu_device pointer
367 * Stop the gfx async dma ring buffers (VI).
369 static void sdma_v2_4_gfx_stop(struct amdgpu_device
*adev
)
371 struct amdgpu_ring
*sdma0
= &adev
->sdma
[0].ring
;
372 struct amdgpu_ring
*sdma1
= &adev
->sdma
[1].ring
;
373 u32 rb_cntl
, ib_cntl
;
376 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
377 (adev
->mman
.buffer_funcs_ring
== sdma1
))
378 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
380 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
381 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
382 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 0);
383 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
384 ib_cntl
= RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]);
385 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 0);
386 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
388 sdma0
->ready
= false;
389 sdma1
->ready
= false;
393 * sdma_v2_4_rlc_stop - stop the compute async dma engines
395 * @adev: amdgpu_device pointer
397 * Stop the compute async dma queues (VI).
399 static void sdma_v2_4_rlc_stop(struct amdgpu_device
*adev
)
405 * sdma_v2_4_enable - stop the async dma engines
407 * @adev: amdgpu_device pointer
408 * @enable: enable/disable the DMA MEs.
410 * Halt or unhalt the async dma engines (VI).
412 static void sdma_v2_4_enable(struct amdgpu_device
*adev
, bool enable
)
417 if (enable
== false) {
418 sdma_v2_4_gfx_stop(adev
);
419 sdma_v2_4_rlc_stop(adev
);
422 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
423 f32_cntl
= RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]);
425 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_F32_CNTL
, HALT
, 0);
427 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_F32_CNTL
, HALT
, 1);
428 WREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
], f32_cntl
);
433 * sdma_v2_4_gfx_resume - setup and start the async dma engines
435 * @adev: amdgpu_device pointer
437 * Set up the gfx DMA ring buffers and enable them (VI).
438 * Returns 0 for success, error for failure.
440 static int sdma_v2_4_gfx_resume(struct amdgpu_device
*adev
)
442 struct amdgpu_ring
*ring
;
443 u32 rb_cntl
, ib_cntl
;
448 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
449 ring
= &adev
->sdma
[i
].ring
;
450 wb_offset
= (ring
->rptr_offs
* 4);
452 mutex_lock(&adev
->srbm_mutex
);
453 for (j
= 0; j
< 16; j
++) {
454 vi_srbm_select(adev
, 0, 0, 0, j
);
456 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
], 0);
457 WREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
], 0);
459 vi_srbm_select(adev
, 0, 0, 0, 0);
460 mutex_unlock(&adev
->srbm_mutex
);
462 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
], 0);
464 /* Set ring buffer size in dwords */
465 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
466 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
467 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SIZE
, rb_bufsz
);
469 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SWAP_ENABLE
, 1);
470 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
,
471 RPTR_WRITEBACK_SWAP_ENABLE
, 1);
473 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
475 /* Initialize the ring buffer's read and write pointers */
476 WREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
], 0);
477 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], 0);
479 /* set the wb address whether it's enabled or not */
480 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
],
481 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
482 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
],
483 lower_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC);
485 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RPTR_WRITEBACK_ENABLE
, 1);
487 WREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
], ring
->gpu_addr
>> 8);
488 WREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
], ring
->gpu_addr
>> 40);
491 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], ring
->wptr
<< 2);
494 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 1);
495 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
497 ib_cntl
= RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]);
498 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 1);
500 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_SWAP_ENABLE
, 1);
503 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
507 r
= amdgpu_ring_test_ring(ring
);
513 if (adev
->mman
.buffer_funcs_ring
== ring
)
514 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.real_vram_size
);
521 * sdma_v2_4_rlc_resume - setup and start the async dma engines
523 * @adev: amdgpu_device pointer
525 * Set up the compute DMA queues and enable them (VI).
526 * Returns 0 for success, error for failure.
528 static int sdma_v2_4_rlc_resume(struct amdgpu_device
*adev
)
535 * sdma_v2_4_load_microcode - load the sDMA ME ucode
537 * @adev: amdgpu_device pointer
539 * Loads the sDMA0/1 ucode.
540 * Returns 0 for success, -EINVAL if the ucode is not available.
542 static int sdma_v2_4_load_microcode(struct amdgpu_device
*adev
)
544 const struct sdma_firmware_header_v1_0
*hdr
;
545 const __le32
*fw_data
;
548 bool smc_loads_fw
= false; /* XXX fix me */
550 if (!adev
->sdma
[0].fw
|| !adev
->sdma
[1].fw
)
554 sdma_v2_4_enable(adev
, false);
557 /* XXX query SMC for fw load complete */
559 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
560 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
[i
].fw
->data
;
561 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
562 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
563 fw_data
= (const __le32
*)
564 (adev
->sdma
[i
].fw
->data
+
565 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
566 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], 0);
567 for (j
= 0; j
< fw_size
; j
++)
568 WREG32(mmSDMA0_UCODE_DATA
+ sdma_offsets
[i
], le32_to_cpup(fw_data
++));
569 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], adev
->sdma
[i
].fw_version
);
577 * sdma_v2_4_start - setup and start the async dma engines
579 * @adev: amdgpu_device pointer
581 * Set up the DMA engines and enable them (VI).
582 * Returns 0 for success, error for failure.
584 static int sdma_v2_4_start(struct amdgpu_device
*adev
)
588 if (!adev
->firmware
.smu_load
) {
589 r
= sdma_v2_4_load_microcode(adev
);
593 r
= adev
->smu
.smumgr_funcs
->check_fw_load_finish(adev
,
594 AMDGPU_UCODE_ID_SDMA0
);
597 r
= adev
->smu
.smumgr_funcs
->check_fw_load_finish(adev
,
598 AMDGPU_UCODE_ID_SDMA1
);
604 sdma_v2_4_enable(adev
, true);
606 /* start the gfx rings and rlc compute queues */
607 r
= sdma_v2_4_gfx_resume(adev
);
610 r
= sdma_v2_4_rlc_resume(adev
);
618 * sdma_v2_4_ring_test_ring - simple async dma engine test
620 * @ring: amdgpu_ring structure holding ring information
622 * Test the DMA engine by writing using it to write an
623 * value to memory. (VI).
624 * Returns 0 for success, error for failure.
626 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring
*ring
)
628 struct amdgpu_device
*adev
= ring
->adev
;
635 r
= amdgpu_wb_get(adev
, &index
);
637 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
641 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
643 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
645 r
= amdgpu_ring_lock(ring
, 5);
647 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
648 amdgpu_wb_free(adev
, index
);
652 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
653 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
));
654 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
655 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
656 amdgpu_ring_write(ring
, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
657 amdgpu_ring_write(ring
, 0xDEADBEEF);
658 amdgpu_ring_unlock_commit(ring
);
660 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
661 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
662 if (tmp
== 0xDEADBEEF)
667 if (i
< adev
->usec_timeout
) {
668 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
670 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
674 amdgpu_wb_free(adev
, index
);
680 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
682 * @ring: amdgpu_ring structure holding ring information
684 * Test a simple IB in the DMA ring (VI).
685 * Returns 0 on success, error on failure.
687 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring
*ring
)
689 struct amdgpu_device
*adev
= ring
->adev
;
691 struct fence
*f
= NULL
;
698 r
= amdgpu_wb_get(adev
, &index
);
700 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
704 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
706 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
707 memset(&ib
, 0, sizeof(ib
));
708 r
= amdgpu_ib_get(ring
, NULL
, 256, &ib
);
710 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r
);
714 ib
.ptr
[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
715 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
);
716 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
717 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
718 ib
.ptr
[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
719 ib
.ptr
[4] = 0xDEADBEEF;
720 ib
.ptr
[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
721 ib
.ptr
[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
722 ib
.ptr
[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
725 r
= amdgpu_sched_ib_submit_kernel_helper(adev
, ring
, &ib
, 1, NULL
,
726 AMDGPU_FENCE_OWNER_UNDEFINED
,
731 r
= fence_wait(f
, false);
733 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r
);
736 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
737 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
738 if (tmp
== 0xDEADBEEF)
742 if (i
< adev
->usec_timeout
) {
743 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
747 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp
);
753 amdgpu_ib_free(adev
, &ib
);
755 amdgpu_wb_free(adev
, index
);
760 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
762 * @ib: indirect buffer to fill with commands
763 * @pe: addr of the page entry
764 * @src: src addr to copy from
765 * @count: number of page entries to update
767 * Update PTEs by copying them from the GART using sDMA (CIK).
769 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib
*ib
,
770 uint64_t pe
, uint64_t src
,
774 unsigned bytes
= count
* 8;
775 if (bytes
> 0x1FFFF8)
778 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
779 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
780 ib
->ptr
[ib
->length_dw
++] = bytes
;
781 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
782 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
783 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
784 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
785 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
794 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
796 * @ib: indirect buffer to fill with commands
797 * @pe: addr of the page entry
798 * @addr: dst addr to write into pe
799 * @count: number of page entries to update
800 * @incr: increase next addr by incr bytes
801 * @flags: access flags
803 * Update PTEs by writing them manually using sDMA (CIK).
805 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib
*ib
,
807 uint64_t addr
, unsigned count
,
808 uint32_t incr
, uint32_t flags
)
818 /* for non-physically contiguous pages (system) */
819 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
820 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
821 ib
->ptr
[ib
->length_dw
++] = pe
;
822 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
823 ib
->ptr
[ib
->length_dw
++] = ndw
;
824 for (; ndw
> 0; ndw
-= 2, --count
, pe
+= 8) {
825 if (flags
& AMDGPU_PTE_SYSTEM
) {
826 value
= amdgpu_vm_map_gart(ib
->ring
->adev
, addr
);
827 value
&= 0xFFFFFFFFFFFFF000ULL
;
828 } else if (flags
& AMDGPU_PTE_VALID
) {
835 ib
->ptr
[ib
->length_dw
++] = value
;
836 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
842 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
844 * @ib: indirect buffer to fill with commands
845 * @pe: addr of the page entry
846 * @addr: dst addr to write into pe
847 * @count: number of page entries to update
848 * @incr: increase next addr by incr bytes
849 * @flags: access flags
851 * Update the page tables using sDMA (CIK).
853 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib
*ib
,
855 uint64_t addr
, unsigned count
,
856 uint32_t incr
, uint32_t flags
)
866 if (flags
& AMDGPU_PTE_VALID
)
871 /* for physically contiguous pages (vram) */
872 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE
);
873 ib
->ptr
[ib
->length_dw
++] = pe
; /* dst addr */
874 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
875 ib
->ptr
[ib
->length_dw
++] = flags
; /* mask */
876 ib
->ptr
[ib
->length_dw
++] = 0;
877 ib
->ptr
[ib
->length_dw
++] = value
; /* value */
878 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
879 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
880 ib
->ptr
[ib
->length_dw
++] = 0;
881 ib
->ptr
[ib
->length_dw
++] = ndw
; /* number of entries */
890 * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw
892 * @ib: indirect buffer to fill with padding
895 static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib
*ib
)
897 struct amdgpu_sdma
*sdma
= amdgpu_get_sdma_instance(ib
->ring
);
901 pad_count
= (8 - (ib
->length_dw
& 0x7)) % 8;
902 for (i
= 0; i
< pad_count
; i
++)
903 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
904 ib
->ptr
[ib
->length_dw
++] =
905 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
) |
906 SDMA_PKT_NOP_HEADER_COUNT(pad_count
- 1);
908 ib
->ptr
[ib
->length_dw
++] =
909 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
913 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
915 * @ring: amdgpu_ring pointer
916 * @vm: amdgpu_vm pointer
918 * Update the page table base and flush the VM TLB
921 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
922 unsigned vm_id
, uint64_t pd_addr
)
924 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
925 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
927 amdgpu_ring_write(ring
, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
929 amdgpu_ring_write(ring
, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
931 amdgpu_ring_write(ring
, pd_addr
>> 12);
934 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
935 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
936 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
937 amdgpu_ring_write(ring
, 1 << vm_id
);
940 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
941 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
942 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
943 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
<< 2);
944 amdgpu_ring_write(ring
, 0);
945 amdgpu_ring_write(ring
, 0); /* reference */
946 amdgpu_ring_write(ring
, 0); /* mask */
947 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
948 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
951 static int sdma_v2_4_early_init(void *handle
)
953 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
955 sdma_v2_4_set_ring_funcs(adev
);
956 sdma_v2_4_set_buffer_funcs(adev
);
957 sdma_v2_4_set_vm_pte_funcs(adev
);
958 sdma_v2_4_set_irq_funcs(adev
);
963 static int sdma_v2_4_sw_init(void *handle
)
965 struct amdgpu_ring
*ring
;
967 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
969 /* SDMA trap event */
970 r
= amdgpu_irq_add_id(adev
, 224, &adev
->sdma_trap_irq
);
974 /* SDMA Privileged inst */
975 r
= amdgpu_irq_add_id(adev
, 241, &adev
->sdma_illegal_inst_irq
);
979 /* SDMA Privileged inst */
980 r
= amdgpu_irq_add_id(adev
, 247, &adev
->sdma_illegal_inst_irq
);
984 r
= sdma_v2_4_init_microcode(adev
);
986 DRM_ERROR("Failed to load sdma firmware!\n");
990 ring
= &adev
->sdma
[0].ring
;
991 ring
->ring_obj
= NULL
;
992 ring
->use_doorbell
= false;
994 ring
= &adev
->sdma
[1].ring
;
995 ring
->ring_obj
= NULL
;
996 ring
->use_doorbell
= false;
998 ring
= &adev
->sdma
[0].ring
;
999 sprintf(ring
->name
, "sdma0");
1000 r
= amdgpu_ring_init(adev
, ring
, 256 * 1024,
1001 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
), 0xf,
1002 &adev
->sdma_trap_irq
, AMDGPU_SDMA_IRQ_TRAP0
,
1003 AMDGPU_RING_TYPE_SDMA
);
1007 ring
= &adev
->sdma
[1].ring
;
1008 sprintf(ring
->name
, "sdma1");
1009 r
= amdgpu_ring_init(adev
, ring
, 256 * 1024,
1010 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
), 0xf,
1011 &adev
->sdma_trap_irq
, AMDGPU_SDMA_IRQ_TRAP1
,
1012 AMDGPU_RING_TYPE_SDMA
);
1019 static int sdma_v2_4_sw_fini(void *handle
)
1021 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1023 amdgpu_ring_fini(&adev
->sdma
[0].ring
);
1024 amdgpu_ring_fini(&adev
->sdma
[1].ring
);
1029 static int sdma_v2_4_hw_init(void *handle
)
1032 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1034 sdma_v2_4_init_golden_registers(adev
);
1036 r
= sdma_v2_4_start(adev
);
1043 static int sdma_v2_4_hw_fini(void *handle
)
1045 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1047 sdma_v2_4_enable(adev
, false);
1052 static int sdma_v2_4_suspend(void *handle
)
1054 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1056 return sdma_v2_4_hw_fini(adev
);
1059 static int sdma_v2_4_resume(void *handle
)
1061 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1063 return sdma_v2_4_hw_init(adev
);
1066 static bool sdma_v2_4_is_idle(void *handle
)
1068 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1069 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1071 if (tmp
& (SRBM_STATUS2__SDMA_BUSY_MASK
|
1072 SRBM_STATUS2__SDMA1_BUSY_MASK
))
1078 static int sdma_v2_4_wait_for_idle(void *handle
)
1082 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1084 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1085 tmp
= RREG32(mmSRBM_STATUS2
) & (SRBM_STATUS2__SDMA_BUSY_MASK
|
1086 SRBM_STATUS2__SDMA1_BUSY_MASK
);
1095 static void sdma_v2_4_print_status(void *handle
)
1098 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1100 dev_info(adev
->dev
, "VI SDMA registers\n");
1101 dev_info(adev
->dev
, " SRBM_STATUS2=0x%08X\n",
1102 RREG32(mmSRBM_STATUS2
));
1103 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
1104 dev_info(adev
->dev
, " SDMA%d_STATUS_REG=0x%08X\n",
1105 i
, RREG32(mmSDMA0_STATUS_REG
+ sdma_offsets
[i
]));
1106 dev_info(adev
->dev
, " SDMA%d_F32_CNTL=0x%08X\n",
1107 i
, RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]));
1108 dev_info(adev
->dev
, " SDMA%d_CNTL=0x%08X\n",
1109 i
, RREG32(mmSDMA0_CNTL
+ sdma_offsets
[i
]));
1110 dev_info(adev
->dev
, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1111 i
, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
]));
1112 dev_info(adev
->dev
, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1113 i
, RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]));
1114 dev_info(adev
->dev
, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1115 i
, RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]));
1116 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1117 i
, RREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
]));
1118 dev_info(adev
->dev
, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1119 i
, RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
]));
1120 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1121 i
, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
]));
1122 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1123 i
, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
]));
1124 dev_info(adev
->dev
, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1125 i
, RREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
]));
1126 dev_info(adev
->dev
, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1127 i
, RREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
]));
1128 mutex_lock(&adev
->srbm_mutex
);
1129 for (j
= 0; j
< 16; j
++) {
1130 vi_srbm_select(adev
, 0, 0, 0, j
);
1131 dev_info(adev
->dev
, " VM %d:\n", j
);
1132 dev_info(adev
->dev
, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1133 i
, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
]));
1134 dev_info(adev
->dev
, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1135 i
, RREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
]));
1137 vi_srbm_select(adev
, 0, 0, 0, 0);
1138 mutex_unlock(&adev
->srbm_mutex
);
1142 static int sdma_v2_4_soft_reset(void *handle
)
1144 u32 srbm_soft_reset
= 0;
1145 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1146 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1148 if (tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
) {
1150 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
1151 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 0);
1152 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
1153 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK
;
1155 if (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
) {
1157 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
1158 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 0);
1159 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
1160 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK
;
1163 if (srbm_soft_reset
) {
1164 sdma_v2_4_print_status((void *)adev
);
1166 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1167 tmp
|= srbm_soft_reset
;
1168 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1169 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1170 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1174 tmp
&= ~srbm_soft_reset
;
1175 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1176 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1178 /* Wait a little for things to settle down */
1181 sdma_v2_4_print_status((void *)adev
);
1187 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device
*adev
,
1188 struct amdgpu_irq_src
*src
,
1190 enum amdgpu_interrupt_state state
)
1195 case AMDGPU_SDMA_IRQ_TRAP0
:
1197 case AMDGPU_IRQ_STATE_DISABLE
:
1198 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1199 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 0);
1200 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1202 case AMDGPU_IRQ_STATE_ENABLE
:
1203 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1204 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 1);
1205 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1211 case AMDGPU_SDMA_IRQ_TRAP1
:
1213 case AMDGPU_IRQ_STATE_DISABLE
:
1214 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1215 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 0);
1216 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1218 case AMDGPU_IRQ_STATE_ENABLE
:
1219 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1220 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 1);
1221 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1233 static int sdma_v2_4_process_trap_irq(struct amdgpu_device
*adev
,
1234 struct amdgpu_irq_src
*source
,
1235 struct amdgpu_iv_entry
*entry
)
1237 u8 instance_id
, queue_id
;
1239 instance_id
= (entry
->ring_id
& 0x3) >> 0;
1240 queue_id
= (entry
->ring_id
& 0xc) >> 2;
1241 DRM_DEBUG("IH: SDMA trap\n");
1242 switch (instance_id
) {
1246 amdgpu_fence_process(&adev
->sdma
[0].ring
);
1259 amdgpu_fence_process(&adev
->sdma
[1].ring
);
1273 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1274 struct amdgpu_irq_src
*source
,
1275 struct amdgpu_iv_entry
*entry
)
1277 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1278 schedule_work(&adev
->reset_work
);
1282 static int sdma_v2_4_set_clockgating_state(void *handle
,
1283 enum amd_clockgating_state state
)
1285 /* XXX handled via the smc on VI */
1289 static int sdma_v2_4_set_powergating_state(void *handle
,
1290 enum amd_powergating_state state
)
1295 const struct amd_ip_funcs sdma_v2_4_ip_funcs
= {
1296 .early_init
= sdma_v2_4_early_init
,
1298 .sw_init
= sdma_v2_4_sw_init
,
1299 .sw_fini
= sdma_v2_4_sw_fini
,
1300 .hw_init
= sdma_v2_4_hw_init
,
1301 .hw_fini
= sdma_v2_4_hw_fini
,
1302 .suspend
= sdma_v2_4_suspend
,
1303 .resume
= sdma_v2_4_resume
,
1304 .is_idle
= sdma_v2_4_is_idle
,
1305 .wait_for_idle
= sdma_v2_4_wait_for_idle
,
1306 .soft_reset
= sdma_v2_4_soft_reset
,
1307 .print_status
= sdma_v2_4_print_status
,
1308 .set_clockgating_state
= sdma_v2_4_set_clockgating_state
,
1309 .set_powergating_state
= sdma_v2_4_set_powergating_state
,
1313 * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up
1315 * @ring: amdgpu_ring structure holding ring information
1317 * Check if the async DMA engine is locked up (VI).
1318 * Returns true if the engine appears to be locked up, false if not.
1320 static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring
*ring
)
1323 if (sdma_v2_4_is_idle(ring
->adev
)) {
1324 amdgpu_ring_lockup_update(ring
);
1327 return amdgpu_ring_test_lockup(ring
);
1330 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs
= {
1331 .get_rptr
= sdma_v2_4_ring_get_rptr
,
1332 .get_wptr
= sdma_v2_4_ring_get_wptr
,
1333 .set_wptr
= sdma_v2_4_ring_set_wptr
,
1335 .emit_ib
= sdma_v2_4_ring_emit_ib
,
1336 .emit_fence
= sdma_v2_4_ring_emit_fence
,
1337 .emit_semaphore
= sdma_v2_4_ring_emit_semaphore
,
1338 .emit_vm_flush
= sdma_v2_4_ring_emit_vm_flush
,
1339 .emit_hdp_flush
= sdma_v2_4_ring_emit_hdp_flush
,
1340 .test_ring
= sdma_v2_4_ring_test_ring
,
1341 .test_ib
= sdma_v2_4_ring_test_ib
,
1342 .is_lockup
= sdma_v2_4_ring_is_lockup
,
1343 .insert_nop
= sdma_v2_4_ring_insert_nop
,
1346 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device
*adev
)
1348 adev
->sdma
[0].ring
.funcs
= &sdma_v2_4_ring_funcs
;
1349 adev
->sdma
[1].ring
.funcs
= &sdma_v2_4_ring_funcs
;
1352 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs
= {
1353 .set
= sdma_v2_4_set_trap_irq_state
,
1354 .process
= sdma_v2_4_process_trap_irq
,
1357 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs
= {
1358 .process
= sdma_v2_4_process_illegal_inst_irq
,
1361 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device
*adev
)
1363 adev
->sdma_trap_irq
.num_types
= AMDGPU_SDMA_IRQ_LAST
;
1364 adev
->sdma_trap_irq
.funcs
= &sdma_v2_4_trap_irq_funcs
;
1365 adev
->sdma_illegal_inst_irq
.funcs
= &sdma_v2_4_illegal_inst_irq_funcs
;
1369 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1371 * @ring: amdgpu_ring structure holding ring information
1372 * @src_offset: src GPU address
1373 * @dst_offset: dst GPU address
1374 * @byte_count: number of bytes to xfer
1376 * Copy GPU buffers using the DMA engine (VI).
1377 * Used by the amdgpu ttm implementation to move pages if
1378 * registered as the asic copy callback.
1380 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib
*ib
,
1381 uint64_t src_offset
,
1382 uint64_t dst_offset
,
1383 uint32_t byte_count
)
1385 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
1386 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
1387 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1388 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1389 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src_offset
);
1390 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src_offset
);
1391 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1392 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1396 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1398 * @ring: amdgpu_ring structure holding ring information
1399 * @src_data: value to write to buffer
1400 * @dst_offset: dst GPU address
1401 * @byte_count: number of bytes to xfer
1403 * Fill GPU buffers using the DMA engine (VI).
1405 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib
*ib
,
1407 uint64_t dst_offset
,
1408 uint32_t byte_count
)
1410 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL
);
1411 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1412 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1413 ib
->ptr
[ib
->length_dw
++] = src_data
;
1414 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1417 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs
= {
1418 .copy_max_bytes
= 0x1fffff,
1420 .emit_copy_buffer
= sdma_v2_4_emit_copy_buffer
,
1422 .fill_max_bytes
= 0x1fffff,
1424 .emit_fill_buffer
= sdma_v2_4_emit_fill_buffer
,
1427 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device
*adev
)
1429 if (adev
->mman
.buffer_funcs
== NULL
) {
1430 adev
->mman
.buffer_funcs
= &sdma_v2_4_buffer_funcs
;
1431 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
[0].ring
;
1435 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs
= {
1436 .copy_pte
= sdma_v2_4_vm_copy_pte
,
1437 .write_pte
= sdma_v2_4_vm_write_pte
,
1438 .set_pte_pde
= sdma_v2_4_vm_set_pte_pde
,
1439 .pad_ib
= sdma_v2_4_vm_pad_ib
,
1442 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1444 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1445 adev
->vm_manager
.vm_pte_funcs
= &sdma_v2_4_vm_pte_funcs
;
1446 adev
->vm_manager
.vm_pte_funcs_ring
= &adev
->sdma
[0].ring
;
1447 adev
->vm_manager
.vm_pte_funcs_ring
->is_pte_ring
= true;