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drm/amdgpu: modify sdma start sequence
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / sdma_v3_0.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
29 #include "vi.h"
30 #include "vid.h"
31
32 #include "oss/oss_3_0_d.h"
33 #include "oss/oss_3_0_sh_mask.h"
34
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
37
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
41
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
44
45 #include "tonga_sdma_pkt_open.h"
46
47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
51
52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
63
64
65 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
66 {
67 SDMA0_REGISTER_OFFSET,
68 SDMA1_REGISTER_OFFSET
69 };
70
71 static const u32 golden_settings_tonga_a11[] =
72 {
73 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
74 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
75 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
76 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
77 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
78 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
79 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
80 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
81 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
82 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
83 };
84
85 static const u32 tonga_mgcg_cgcg_init[] =
86 {
87 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
88 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
89 };
90
91 static const u32 golden_settings_fiji_a10[] =
92 {
93 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
94 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
95 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
96 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
97 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
98 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
99 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
100 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
101 };
102
103 static const u32 fiji_mgcg_cgcg_init[] =
104 {
105 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
106 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
107 };
108
109 static const u32 golden_settings_polaris11_a11[] =
110 {
111 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
112 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
113 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
114 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
115 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
116 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
117 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
118 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
119 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
120 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
121 };
122
123 static const u32 golden_settings_polaris10_a11[] =
124 {
125 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
126 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
127 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
128 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
129 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
130 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
131 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
132 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
133 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
134 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
135 };
136
137 static const u32 cz_golden_settings_a11[] =
138 {
139 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
140 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
141 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
142 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
143 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
144 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
145 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
146 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
147 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
148 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
149 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
150 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
151 };
152
153 static const u32 cz_mgcg_cgcg_init[] =
154 {
155 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
156 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
157 };
158
159 static const u32 stoney_golden_settings_a11[] =
160 {
161 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
162 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
163 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
164 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
165 };
166
167 static const u32 stoney_mgcg_cgcg_init[] =
168 {
169 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
170 };
171
172 /*
173 * sDMA - System DMA
174 * Starting with CIK, the GPU has new asynchronous
175 * DMA engines. These engines are used for compute
176 * and gfx. There are two DMA engines (SDMA0, SDMA1)
177 * and each one supports 1 ring buffer used for gfx
178 * and 2 queues used for compute.
179 *
180 * The programming model is very similar to the CP
181 * (ring buffer, IBs, etc.), but sDMA has it's own
182 * packet format that is different from the PM4 format
183 * used by the CP. sDMA supports copying data, writing
184 * embedded data, solid fills, and a number of other
185 * things. It also has support for tiling/detiling of
186 * buffers.
187 */
188
189 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
190 {
191 switch (adev->asic_type) {
192 case CHIP_FIJI:
193 amdgpu_program_register_sequence(adev,
194 fiji_mgcg_cgcg_init,
195 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
196 amdgpu_program_register_sequence(adev,
197 golden_settings_fiji_a10,
198 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
199 break;
200 case CHIP_TONGA:
201 amdgpu_program_register_sequence(adev,
202 tonga_mgcg_cgcg_init,
203 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
204 amdgpu_program_register_sequence(adev,
205 golden_settings_tonga_a11,
206 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
207 break;
208 case CHIP_POLARIS11:
209 amdgpu_program_register_sequence(adev,
210 golden_settings_polaris11_a11,
211 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
212 break;
213 case CHIP_POLARIS10:
214 amdgpu_program_register_sequence(adev,
215 golden_settings_polaris10_a11,
216 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
217 break;
218 case CHIP_CARRIZO:
219 amdgpu_program_register_sequence(adev,
220 cz_mgcg_cgcg_init,
221 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
222 amdgpu_program_register_sequence(adev,
223 cz_golden_settings_a11,
224 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
225 break;
226 case CHIP_STONEY:
227 amdgpu_program_register_sequence(adev,
228 stoney_mgcg_cgcg_init,
229 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
230 amdgpu_program_register_sequence(adev,
231 stoney_golden_settings_a11,
232 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
233 break;
234 default:
235 break;
236 }
237 }
238
239 /**
240 * sdma_v3_0_init_microcode - load ucode images from disk
241 *
242 * @adev: amdgpu_device pointer
243 *
244 * Use the firmware interface to load the ucode images into
245 * the driver (not loaded into hw).
246 * Returns 0 on success, error on failure.
247 */
248 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
249 {
250 const char *chip_name;
251 char fw_name[30];
252 int err = 0, i;
253 struct amdgpu_firmware_info *info = NULL;
254 const struct common_firmware_header *header = NULL;
255 const struct sdma_firmware_header_v1_0 *hdr;
256
257 DRM_DEBUG("\n");
258
259 switch (adev->asic_type) {
260 case CHIP_TONGA:
261 chip_name = "tonga";
262 break;
263 case CHIP_FIJI:
264 chip_name = "fiji";
265 break;
266 case CHIP_POLARIS11:
267 chip_name = "polaris11";
268 break;
269 case CHIP_POLARIS10:
270 chip_name = "polaris10";
271 break;
272 case CHIP_CARRIZO:
273 chip_name = "carrizo";
274 break;
275 case CHIP_STONEY:
276 chip_name = "stoney";
277 break;
278 default: BUG();
279 }
280
281 for (i = 0; i < adev->sdma.num_instances; i++) {
282 if (i == 0)
283 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
284 else
285 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
286 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
287 if (err)
288 goto out;
289 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
290 if (err)
291 goto out;
292 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
293 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
294 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
295 if (adev->sdma.instance[i].feature_version >= 20)
296 adev->sdma.instance[i].burst_nop = true;
297
298 if (adev->firmware.smu_load) {
299 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
300 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
301 info->fw = adev->sdma.instance[i].fw;
302 header = (const struct common_firmware_header *)info->fw->data;
303 adev->firmware.fw_size +=
304 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
305 }
306 }
307 out:
308 if (err) {
309 printk(KERN_ERR
310 "sdma_v3_0: Failed to load firmware \"%s\"\n",
311 fw_name);
312 for (i = 0; i < adev->sdma.num_instances; i++) {
313 release_firmware(adev->sdma.instance[i].fw);
314 adev->sdma.instance[i].fw = NULL;
315 }
316 }
317 return err;
318 }
319
320 /**
321 * sdma_v3_0_ring_get_rptr - get the current read pointer
322 *
323 * @ring: amdgpu ring pointer
324 *
325 * Get the current rptr from the hardware (VI+).
326 */
327 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
328 {
329 u32 rptr;
330
331 /* XXX check if swapping is necessary on BE */
332 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
333
334 return rptr;
335 }
336
337 /**
338 * sdma_v3_0_ring_get_wptr - get the current write pointer
339 *
340 * @ring: amdgpu ring pointer
341 *
342 * Get the current wptr from the hardware (VI+).
343 */
344 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
345 {
346 struct amdgpu_device *adev = ring->adev;
347 u32 wptr;
348
349 if (ring->use_doorbell) {
350 /* XXX check if swapping is necessary on BE */
351 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
352 } else {
353 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
354
355 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
356 }
357
358 return wptr;
359 }
360
361 /**
362 * sdma_v3_0_ring_set_wptr - commit the write pointer
363 *
364 * @ring: amdgpu ring pointer
365 *
366 * Write the wptr back to the hardware (VI+).
367 */
368 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
369 {
370 struct amdgpu_device *adev = ring->adev;
371
372 if (ring->use_doorbell) {
373 /* XXX check if swapping is necessary on BE */
374 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
375 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
376 } else {
377 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
378
379 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
380 }
381 }
382
383 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
384 {
385 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
386 int i;
387
388 for (i = 0; i < count; i++)
389 if (sdma && sdma->burst_nop && (i == 0))
390 amdgpu_ring_write(ring, ring->nop |
391 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
392 else
393 amdgpu_ring_write(ring, ring->nop);
394 }
395
396 /**
397 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
398 *
399 * @ring: amdgpu ring pointer
400 * @ib: IB object to schedule
401 *
402 * Schedule an IB in the DMA ring (VI).
403 */
404 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
405 struct amdgpu_ib *ib,
406 unsigned vm_id, bool ctx_switch)
407 {
408 u32 vmid = vm_id & 0xf;
409 u32 next_rptr = ring->wptr + 5;
410
411 while ((next_rptr & 7) != 2)
412 next_rptr++;
413 next_rptr += 6;
414
415 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
416 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
417 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
418 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
419 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
420 amdgpu_ring_write(ring, next_rptr);
421
422 /* IB packet must end on a 8 DW boundary */
423 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
424
425 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
426 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
427 /* base must be 32 byte aligned */
428 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
429 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
430 amdgpu_ring_write(ring, ib->length_dw);
431 amdgpu_ring_write(ring, 0);
432 amdgpu_ring_write(ring, 0);
433
434 }
435
436 /**
437 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
438 *
439 * @ring: amdgpu ring pointer
440 *
441 * Emit an hdp flush packet on the requested DMA ring.
442 */
443 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
444 {
445 u32 ref_and_mask = 0;
446
447 if (ring == &ring->adev->sdma.instance[0].ring)
448 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
449 else
450 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
451
452 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
453 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
454 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
455 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
456 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
457 amdgpu_ring_write(ring, ref_and_mask); /* reference */
458 amdgpu_ring_write(ring, ref_and_mask); /* mask */
459 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
460 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
461 }
462
463 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
464 {
465 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
466 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
467 amdgpu_ring_write(ring, mmHDP_DEBUG0);
468 amdgpu_ring_write(ring, 1);
469 }
470
471 /**
472 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
473 *
474 * @ring: amdgpu ring pointer
475 * @fence: amdgpu fence object
476 *
477 * Add a DMA fence packet to the ring to write
478 * the fence seq number and DMA trap packet to generate
479 * an interrupt if needed (VI).
480 */
481 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
482 unsigned flags)
483 {
484 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
485 /* write the fence */
486 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
487 amdgpu_ring_write(ring, lower_32_bits(addr));
488 amdgpu_ring_write(ring, upper_32_bits(addr));
489 amdgpu_ring_write(ring, lower_32_bits(seq));
490
491 /* optionally write high bits as well */
492 if (write64bit) {
493 addr += 4;
494 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
495 amdgpu_ring_write(ring, lower_32_bits(addr));
496 amdgpu_ring_write(ring, upper_32_bits(addr));
497 amdgpu_ring_write(ring, upper_32_bits(seq));
498 }
499
500 /* generate an interrupt */
501 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
502 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
503 }
504
505 unsigned init_cond_exec(struct amdgpu_ring *ring)
506 {
507 unsigned ret;
508 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
509 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
510 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
511 amdgpu_ring_write(ring, 1);
512 ret = ring->wptr;/* this is the offset we need patch later */
513 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
514 return ret;
515 }
516
517 void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
518 {
519 unsigned cur;
520 BUG_ON(ring->ring[offset] != 0x55aa55aa);
521
522 cur = ring->wptr - 1;
523 if (likely(cur > offset))
524 ring->ring[offset] = cur - offset;
525 else
526 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
527 }
528
529
530 /**
531 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
532 *
533 * @adev: amdgpu_device pointer
534 *
535 * Stop the gfx async dma ring buffers (VI).
536 */
537 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
538 {
539 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
540 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
541 u32 rb_cntl, ib_cntl;
542 int i;
543
544 if ((adev->mman.buffer_funcs_ring == sdma0) ||
545 (adev->mman.buffer_funcs_ring == sdma1))
546 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
547
548 for (i = 0; i < adev->sdma.num_instances; i++) {
549 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
550 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
551 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
552 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
553 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
554 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
555 }
556 sdma0->ready = false;
557 sdma1->ready = false;
558 }
559
560 /**
561 * sdma_v3_0_rlc_stop - stop the compute async dma engines
562 *
563 * @adev: amdgpu_device pointer
564 *
565 * Stop the compute async dma queues (VI).
566 */
567 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
568 {
569 /* XXX todo */
570 }
571
572 /**
573 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
574 *
575 * @adev: amdgpu_device pointer
576 * @enable: enable/disable the DMA MEs context switch.
577 *
578 * Halt or unhalt the async dma engines context switch (VI).
579 */
580 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
581 {
582 u32 f32_cntl;
583 int i;
584
585 for (i = 0; i < adev->sdma.num_instances; i++) {
586 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
587 if (enable)
588 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
589 AUTO_CTXSW_ENABLE, 1);
590 else
591 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
592 AUTO_CTXSW_ENABLE, 0);
593 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
594 }
595 }
596
597 /**
598 * sdma_v3_0_enable - stop the async dma engines
599 *
600 * @adev: amdgpu_device pointer
601 * @enable: enable/disable the DMA MEs.
602 *
603 * Halt or unhalt the async dma engines (VI).
604 */
605 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
606 {
607 u32 f32_cntl;
608 int i;
609
610 if (enable == false) {
611 sdma_v3_0_gfx_stop(adev);
612 sdma_v3_0_rlc_stop(adev);
613 }
614
615 for (i = 0; i < adev->sdma.num_instances; i++) {
616 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
617 if (enable)
618 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
619 else
620 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
621 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
622 }
623 }
624
625 /**
626 * sdma_v3_0_gfx_resume - setup and start the async dma engines
627 *
628 * @adev: amdgpu_device pointer
629 *
630 * Set up the gfx DMA ring buffers and enable them (VI).
631 * Returns 0 for success, error for failure.
632 */
633 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
634 {
635 struct amdgpu_ring *ring;
636 u32 rb_cntl, ib_cntl;
637 u32 rb_bufsz;
638 u32 wb_offset;
639 u32 doorbell;
640 int i, j, r;
641
642 for (i = 0; i < adev->sdma.num_instances; i++) {
643 ring = &adev->sdma.instance[i].ring;
644 wb_offset = (ring->rptr_offs * 4);
645
646 mutex_lock(&adev->srbm_mutex);
647 for (j = 0; j < 16; j++) {
648 vi_srbm_select(adev, 0, 0, 0, j);
649 /* SDMA GFX */
650 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
651 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
652 }
653 vi_srbm_select(adev, 0, 0, 0, 0);
654 mutex_unlock(&adev->srbm_mutex);
655
656 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
657 adev->gfx.config.gb_addr_config & 0x70);
658
659 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
660
661 /* Set ring buffer size in dwords */
662 rb_bufsz = order_base_2(ring->ring_size / 4);
663 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
664 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
665 #ifdef __BIG_ENDIAN
666 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
667 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
668 RPTR_WRITEBACK_SWAP_ENABLE, 1);
669 #endif
670 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
671
672 /* Initialize the ring buffer's read and write pointers */
673 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
674 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
675 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
676 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
677
678 /* set the wb address whether it's enabled or not */
679 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
680 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
681 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
682 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
683
684 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
685
686 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
687 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
688
689 ring->wptr = 0;
690 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
691
692 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
693
694 if (ring->use_doorbell) {
695 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
696 OFFSET, ring->doorbell_index);
697 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
698 } else {
699 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
700 }
701 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
702
703 /* enable DMA RB */
704 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
705 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
706
707 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
708 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
709 #ifdef __BIG_ENDIAN
710 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
711 #endif
712 /* enable DMA IBs */
713 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
714
715 ring->ready = true;
716 }
717
718 /* unhalt the MEs */
719 sdma_v3_0_enable(adev, true);
720 /* enable sdma ring preemption */
721 sdma_v3_0_ctx_switch_enable(adev, true);
722
723 for (i = 0; i < adev->sdma.num_instances; i++) {
724 ring = &adev->sdma.instance[i].ring;
725 r = amdgpu_ring_test_ring(ring);
726 if (r) {
727 ring->ready = false;
728 return r;
729 }
730
731 if (adev->mman.buffer_funcs_ring == ring)
732 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
733 }
734
735 return 0;
736 }
737
738 /**
739 * sdma_v3_0_rlc_resume - setup and start the async dma engines
740 *
741 * @adev: amdgpu_device pointer
742 *
743 * Set up the compute DMA queues and enable them (VI).
744 * Returns 0 for success, error for failure.
745 */
746 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
747 {
748 /* XXX todo */
749 return 0;
750 }
751
752 /**
753 * sdma_v3_0_load_microcode - load the sDMA ME ucode
754 *
755 * @adev: amdgpu_device pointer
756 *
757 * Loads the sDMA0/1 ucode.
758 * Returns 0 for success, -EINVAL if the ucode is not available.
759 */
760 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
761 {
762 const struct sdma_firmware_header_v1_0 *hdr;
763 const __le32 *fw_data;
764 u32 fw_size;
765 int i, j;
766
767 /* halt the MEs */
768 sdma_v3_0_enable(adev, false);
769
770 for (i = 0; i < adev->sdma.num_instances; i++) {
771 if (!adev->sdma.instance[i].fw)
772 return -EINVAL;
773 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
774 amdgpu_ucode_print_sdma_hdr(&hdr->header);
775 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
776 fw_data = (const __le32 *)
777 (adev->sdma.instance[i].fw->data +
778 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
779 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
780 for (j = 0; j < fw_size; j++)
781 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
782 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
783 }
784
785 return 0;
786 }
787
788 /**
789 * sdma_v3_0_start - setup and start the async dma engines
790 *
791 * @adev: amdgpu_device pointer
792 *
793 * Set up the DMA engines and enable them (VI).
794 * Returns 0 for success, error for failure.
795 */
796 static int sdma_v3_0_start(struct amdgpu_device *adev)
797 {
798 int r, i;
799
800 if (!adev->pp_enabled) {
801 if (!adev->firmware.smu_load) {
802 r = sdma_v3_0_load_microcode(adev);
803 if (r)
804 return r;
805 } else {
806 for (i = 0; i < adev->sdma.num_instances; i++) {
807 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
808 (i == 0) ?
809 AMDGPU_UCODE_ID_SDMA0 :
810 AMDGPU_UCODE_ID_SDMA1);
811 if (r)
812 return -EINVAL;
813 }
814 }
815 }
816
817 /* disble sdma engine before programing it */
818 sdma_v3_0_ctx_switch_enable(adev, false);
819 sdma_v3_0_enable(adev, false);
820
821 /* start the gfx rings and rlc compute queues */
822 r = sdma_v3_0_gfx_resume(adev);
823 if (r)
824 return r;
825 r = sdma_v3_0_rlc_resume(adev);
826 if (r)
827 return r;
828
829 return 0;
830 }
831
832 /**
833 * sdma_v3_0_ring_test_ring - simple async dma engine test
834 *
835 * @ring: amdgpu_ring structure holding ring information
836 *
837 * Test the DMA engine by writing using it to write an
838 * value to memory. (VI).
839 * Returns 0 for success, error for failure.
840 */
841 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
842 {
843 struct amdgpu_device *adev = ring->adev;
844 unsigned i;
845 unsigned index;
846 int r;
847 u32 tmp;
848 u64 gpu_addr;
849
850 r = amdgpu_wb_get(adev, &index);
851 if (r) {
852 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
853 return r;
854 }
855
856 gpu_addr = adev->wb.gpu_addr + (index * 4);
857 tmp = 0xCAFEDEAD;
858 adev->wb.wb[index] = cpu_to_le32(tmp);
859
860 r = amdgpu_ring_alloc(ring, 5);
861 if (r) {
862 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
863 amdgpu_wb_free(adev, index);
864 return r;
865 }
866
867 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
868 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
869 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
870 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
871 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
872 amdgpu_ring_write(ring, 0xDEADBEEF);
873 amdgpu_ring_commit(ring);
874
875 for (i = 0; i < adev->usec_timeout; i++) {
876 tmp = le32_to_cpu(adev->wb.wb[index]);
877 if (tmp == 0xDEADBEEF)
878 break;
879 DRM_UDELAY(1);
880 }
881
882 if (i < adev->usec_timeout) {
883 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
884 } else {
885 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
886 ring->idx, tmp);
887 r = -EINVAL;
888 }
889 amdgpu_wb_free(adev, index);
890
891 return r;
892 }
893
894 /**
895 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
896 *
897 * @ring: amdgpu_ring structure holding ring information
898 *
899 * Test a simple IB in the DMA ring (VI).
900 * Returns 0 on success, error on failure.
901 */
902 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
903 {
904 struct amdgpu_device *adev = ring->adev;
905 struct amdgpu_ib ib;
906 struct fence *f = NULL;
907 unsigned i;
908 unsigned index;
909 int r;
910 u32 tmp = 0;
911 u64 gpu_addr;
912
913 r = amdgpu_wb_get(adev, &index);
914 if (r) {
915 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
916 return r;
917 }
918
919 gpu_addr = adev->wb.gpu_addr + (index * 4);
920 tmp = 0xCAFEDEAD;
921 adev->wb.wb[index] = cpu_to_le32(tmp);
922 memset(&ib, 0, sizeof(ib));
923 r = amdgpu_ib_get(adev, NULL, 256, &ib);
924 if (r) {
925 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
926 goto err0;
927 }
928
929 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
930 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
931 ib.ptr[1] = lower_32_bits(gpu_addr);
932 ib.ptr[2] = upper_32_bits(gpu_addr);
933 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
934 ib.ptr[4] = 0xDEADBEEF;
935 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
936 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
937 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
938 ib.length_dw = 8;
939
940 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
941 if (r)
942 goto err1;
943
944 r = fence_wait(f, false);
945 if (r) {
946 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
947 goto err1;
948 }
949 for (i = 0; i < adev->usec_timeout; i++) {
950 tmp = le32_to_cpu(adev->wb.wb[index]);
951 if (tmp == 0xDEADBEEF)
952 break;
953 DRM_UDELAY(1);
954 }
955 if (i < adev->usec_timeout) {
956 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
957 ring->idx, i);
958 goto err1;
959 } else {
960 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
961 r = -EINVAL;
962 }
963 err1:
964 fence_put(f);
965 amdgpu_ib_free(adev, &ib, NULL);
966 fence_put(f);
967 err0:
968 amdgpu_wb_free(adev, index);
969 return r;
970 }
971
972 /**
973 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
974 *
975 * @ib: indirect buffer to fill with commands
976 * @pe: addr of the page entry
977 * @src: src addr to copy from
978 * @count: number of page entries to update
979 *
980 * Update PTEs by copying them from the GART using sDMA (CIK).
981 */
982 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
983 uint64_t pe, uint64_t src,
984 unsigned count)
985 {
986 while (count) {
987 unsigned bytes = count * 8;
988 if (bytes > 0x1FFFF8)
989 bytes = 0x1FFFF8;
990
991 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
992 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
993 ib->ptr[ib->length_dw++] = bytes;
994 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
995 ib->ptr[ib->length_dw++] = lower_32_bits(src);
996 ib->ptr[ib->length_dw++] = upper_32_bits(src);
997 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
998 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
999
1000 pe += bytes;
1001 src += bytes;
1002 count -= bytes / 8;
1003 }
1004 }
1005
1006 /**
1007 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
1008 *
1009 * @ib: indirect buffer to fill with commands
1010 * @pe: addr of the page entry
1011 * @addr: dst addr to write into pe
1012 * @count: number of page entries to update
1013 * @incr: increase next addr by incr bytes
1014 * @flags: access flags
1015 *
1016 * Update PTEs by writing them manually using sDMA (CIK).
1017 */
1018 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
1019 const dma_addr_t *pages_addr, uint64_t pe,
1020 uint64_t addr, unsigned count,
1021 uint32_t incr, uint32_t flags)
1022 {
1023 uint64_t value;
1024 unsigned ndw;
1025
1026 while (count) {
1027 ndw = count * 2;
1028 if (ndw > 0xFFFFE)
1029 ndw = 0xFFFFE;
1030
1031 /* for non-physically contiguous pages (system) */
1032 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1033 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1034 ib->ptr[ib->length_dw++] = pe;
1035 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1036 ib->ptr[ib->length_dw++] = ndw;
1037 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
1038 value = amdgpu_vm_map_gart(pages_addr, addr);
1039 addr += incr;
1040 value |= flags;
1041 ib->ptr[ib->length_dw++] = value;
1042 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1043 }
1044 }
1045 }
1046
1047 /**
1048 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1049 *
1050 * @ib: indirect buffer to fill with commands
1051 * @pe: addr of the page entry
1052 * @addr: dst addr to write into pe
1053 * @count: number of page entries to update
1054 * @incr: increase next addr by incr bytes
1055 * @flags: access flags
1056 *
1057 * Update the page tables using sDMA (CIK).
1058 */
1059 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1060 uint64_t pe,
1061 uint64_t addr, unsigned count,
1062 uint32_t incr, uint32_t flags)
1063 {
1064 uint64_t value;
1065 unsigned ndw;
1066
1067 while (count) {
1068 ndw = count;
1069 if (ndw > 0x7FFFF)
1070 ndw = 0x7FFFF;
1071
1072 if (flags & AMDGPU_PTE_VALID)
1073 value = addr;
1074 else
1075 value = 0;
1076
1077 /* for physically contiguous pages (vram) */
1078 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1079 ib->ptr[ib->length_dw++] = pe; /* dst addr */
1080 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1081 ib->ptr[ib->length_dw++] = flags; /* mask */
1082 ib->ptr[ib->length_dw++] = 0;
1083 ib->ptr[ib->length_dw++] = value; /* value */
1084 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1085 ib->ptr[ib->length_dw++] = incr; /* increment size */
1086 ib->ptr[ib->length_dw++] = 0;
1087 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
1088
1089 pe += ndw * 8;
1090 addr += ndw * incr;
1091 count -= ndw;
1092 }
1093 }
1094
1095 /**
1096 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1097 *
1098 * @ib: indirect buffer to fill with padding
1099 *
1100 */
1101 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1102 {
1103 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1104 u32 pad_count;
1105 int i;
1106
1107 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1108 for (i = 0; i < pad_count; i++)
1109 if (sdma && sdma->burst_nop && (i == 0))
1110 ib->ptr[ib->length_dw++] =
1111 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1112 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1113 else
1114 ib->ptr[ib->length_dw++] =
1115 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1116 }
1117
1118 /**
1119 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1120 *
1121 * @ring: amdgpu_ring pointer
1122 *
1123 * Make sure all previous operations are completed (CIK).
1124 */
1125 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1126 {
1127 uint32_t seq = ring->fence_drv.sync_seq;
1128 uint64_t addr = ring->fence_drv.gpu_addr;
1129
1130 /* wait for idle */
1131 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1132 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1133 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1134 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1135 amdgpu_ring_write(ring, addr & 0xfffffffc);
1136 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1137 amdgpu_ring_write(ring, seq); /* reference */
1138 amdgpu_ring_write(ring, 0xfffffff); /* mask */
1139 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1140 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1141 }
1142
1143 /**
1144 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1145 *
1146 * @ring: amdgpu_ring pointer
1147 * @vm: amdgpu_vm pointer
1148 *
1149 * Update the page table base and flush the VM TLB
1150 * using sDMA (VI).
1151 */
1152 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1153 unsigned vm_id, uint64_t pd_addr)
1154 {
1155 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1156 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1157 if (vm_id < 8) {
1158 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1159 } else {
1160 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1161 }
1162 amdgpu_ring_write(ring, pd_addr >> 12);
1163
1164 /* flush TLB */
1165 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1166 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1167 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1168 amdgpu_ring_write(ring, 1 << vm_id);
1169
1170 /* wait for flush */
1171 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1172 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1173 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1174 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1175 amdgpu_ring_write(ring, 0);
1176 amdgpu_ring_write(ring, 0); /* reference */
1177 amdgpu_ring_write(ring, 0); /* mask */
1178 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1179 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1180 }
1181
1182 static int sdma_v3_0_early_init(void *handle)
1183 {
1184 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1185
1186 switch (adev->asic_type) {
1187 case CHIP_STONEY:
1188 adev->sdma.num_instances = 1;
1189 break;
1190 default:
1191 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1192 break;
1193 }
1194
1195 sdma_v3_0_set_ring_funcs(adev);
1196 sdma_v3_0_set_buffer_funcs(adev);
1197 sdma_v3_0_set_vm_pte_funcs(adev);
1198 sdma_v3_0_set_irq_funcs(adev);
1199
1200 return 0;
1201 }
1202
1203 static int sdma_v3_0_sw_init(void *handle)
1204 {
1205 struct amdgpu_ring *ring;
1206 int r, i;
1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208
1209 /* SDMA trap event */
1210 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
1211 if (r)
1212 return r;
1213
1214 /* SDMA Privileged inst */
1215 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
1216 if (r)
1217 return r;
1218
1219 /* SDMA Privileged inst */
1220 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
1221 if (r)
1222 return r;
1223
1224 r = sdma_v3_0_init_microcode(adev);
1225 if (r) {
1226 DRM_ERROR("Failed to load sdma firmware!\n");
1227 return r;
1228 }
1229
1230 for (i = 0; i < adev->sdma.num_instances; i++) {
1231 ring = &adev->sdma.instance[i].ring;
1232 ring->ring_obj = NULL;
1233 ring->use_doorbell = true;
1234 ring->doorbell_index = (i == 0) ?
1235 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1236
1237 sprintf(ring->name, "sdma%d", i);
1238 r = amdgpu_ring_init(adev, ring, 1024,
1239 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1240 &adev->sdma.trap_irq,
1241 (i == 0) ?
1242 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1243 AMDGPU_RING_TYPE_SDMA);
1244 if (r)
1245 return r;
1246 }
1247
1248 return r;
1249 }
1250
1251 static int sdma_v3_0_sw_fini(void *handle)
1252 {
1253 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1254 int i;
1255
1256 for (i = 0; i < adev->sdma.num_instances; i++)
1257 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1258
1259 return 0;
1260 }
1261
1262 static int sdma_v3_0_hw_init(void *handle)
1263 {
1264 int r;
1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1266
1267 sdma_v3_0_init_golden_registers(adev);
1268
1269 r = sdma_v3_0_start(adev);
1270 if (r)
1271 return r;
1272
1273 return r;
1274 }
1275
1276 static int sdma_v3_0_hw_fini(void *handle)
1277 {
1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279
1280 sdma_v3_0_ctx_switch_enable(adev, false);
1281 sdma_v3_0_enable(adev, false);
1282
1283 return 0;
1284 }
1285
1286 static int sdma_v3_0_suspend(void *handle)
1287 {
1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1289
1290 return sdma_v3_0_hw_fini(adev);
1291 }
1292
1293 static int sdma_v3_0_resume(void *handle)
1294 {
1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296
1297 return sdma_v3_0_hw_init(adev);
1298 }
1299
1300 static bool sdma_v3_0_is_idle(void *handle)
1301 {
1302 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1303 u32 tmp = RREG32(mmSRBM_STATUS2);
1304
1305 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1306 SRBM_STATUS2__SDMA1_BUSY_MASK))
1307 return false;
1308
1309 return true;
1310 }
1311
1312 static int sdma_v3_0_wait_for_idle(void *handle)
1313 {
1314 unsigned i;
1315 u32 tmp;
1316 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1317
1318 for (i = 0; i < adev->usec_timeout; i++) {
1319 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1320 SRBM_STATUS2__SDMA1_BUSY_MASK);
1321
1322 if (!tmp)
1323 return 0;
1324 udelay(1);
1325 }
1326 return -ETIMEDOUT;
1327 }
1328
1329 static int sdma_v3_0_soft_reset(void *handle)
1330 {
1331 u32 srbm_soft_reset = 0;
1332 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1333 u32 tmp = RREG32(mmSRBM_STATUS2);
1334
1335 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1336 /* sdma0 */
1337 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1338 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1339 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1340 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1341 }
1342 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1343 /* sdma1 */
1344 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1345 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1346 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1347 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1348 }
1349
1350 if (srbm_soft_reset) {
1351 tmp = RREG32(mmSRBM_SOFT_RESET);
1352 tmp |= srbm_soft_reset;
1353 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1354 WREG32(mmSRBM_SOFT_RESET, tmp);
1355 tmp = RREG32(mmSRBM_SOFT_RESET);
1356
1357 udelay(50);
1358
1359 tmp &= ~srbm_soft_reset;
1360 WREG32(mmSRBM_SOFT_RESET, tmp);
1361 tmp = RREG32(mmSRBM_SOFT_RESET);
1362
1363 /* Wait a little for things to settle down */
1364 udelay(50);
1365 }
1366
1367 return 0;
1368 }
1369
1370 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1371 struct amdgpu_irq_src *source,
1372 unsigned type,
1373 enum amdgpu_interrupt_state state)
1374 {
1375 u32 sdma_cntl;
1376
1377 switch (type) {
1378 case AMDGPU_SDMA_IRQ_TRAP0:
1379 switch (state) {
1380 case AMDGPU_IRQ_STATE_DISABLE:
1381 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1382 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1383 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1384 break;
1385 case AMDGPU_IRQ_STATE_ENABLE:
1386 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1387 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1388 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1389 break;
1390 default:
1391 break;
1392 }
1393 break;
1394 case AMDGPU_SDMA_IRQ_TRAP1:
1395 switch (state) {
1396 case AMDGPU_IRQ_STATE_DISABLE:
1397 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1398 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1399 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1400 break;
1401 case AMDGPU_IRQ_STATE_ENABLE:
1402 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1403 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1404 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1405 break;
1406 default:
1407 break;
1408 }
1409 break;
1410 default:
1411 break;
1412 }
1413 return 0;
1414 }
1415
1416 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1417 struct amdgpu_irq_src *source,
1418 struct amdgpu_iv_entry *entry)
1419 {
1420 u8 instance_id, queue_id;
1421
1422 instance_id = (entry->ring_id & 0x3) >> 0;
1423 queue_id = (entry->ring_id & 0xc) >> 2;
1424 DRM_DEBUG("IH: SDMA trap\n");
1425 switch (instance_id) {
1426 case 0:
1427 switch (queue_id) {
1428 case 0:
1429 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1430 break;
1431 case 1:
1432 /* XXX compute */
1433 break;
1434 case 2:
1435 /* XXX compute */
1436 break;
1437 }
1438 break;
1439 case 1:
1440 switch (queue_id) {
1441 case 0:
1442 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1443 break;
1444 case 1:
1445 /* XXX compute */
1446 break;
1447 case 2:
1448 /* XXX compute */
1449 break;
1450 }
1451 break;
1452 }
1453 return 0;
1454 }
1455
1456 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1457 struct amdgpu_irq_src *source,
1458 struct amdgpu_iv_entry *entry)
1459 {
1460 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1461 schedule_work(&adev->reset_work);
1462 return 0;
1463 }
1464
1465 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1466 struct amdgpu_device *adev,
1467 bool enable)
1468 {
1469 uint32_t temp, data;
1470 int i;
1471
1472 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1473 for (i = 0; i < adev->sdma.num_instances; i++) {
1474 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1475 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1476 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1477 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1478 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1479 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1480 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1481 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1482 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1483 if (data != temp)
1484 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1485 }
1486 } else {
1487 for (i = 0; i < adev->sdma.num_instances; i++) {
1488 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1489 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1490 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1491 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1492 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1493 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1494 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1495 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1496 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1497
1498 if (data != temp)
1499 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1500 }
1501 }
1502 }
1503
1504 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1505 struct amdgpu_device *adev,
1506 bool enable)
1507 {
1508 uint32_t temp, data;
1509 int i;
1510
1511 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1512 for (i = 0; i < adev->sdma.num_instances; i++) {
1513 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1514 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1515
1516 if (temp != data)
1517 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1518 }
1519 } else {
1520 for (i = 0; i < adev->sdma.num_instances; i++) {
1521 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1522 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1523
1524 if (temp != data)
1525 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1526 }
1527 }
1528 }
1529
1530 static int sdma_v3_0_set_clockgating_state(void *handle,
1531 enum amd_clockgating_state state)
1532 {
1533 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1534
1535 switch (adev->asic_type) {
1536 case CHIP_FIJI:
1537 case CHIP_CARRIZO:
1538 case CHIP_STONEY:
1539 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1540 state == AMD_CG_STATE_GATE ? true : false);
1541 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1542 state == AMD_CG_STATE_GATE ? true : false);
1543 break;
1544 default:
1545 break;
1546 }
1547 return 0;
1548 }
1549
1550 static int sdma_v3_0_set_powergating_state(void *handle,
1551 enum amd_powergating_state state)
1552 {
1553 return 0;
1554 }
1555
1556 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1557 .name = "sdma_v3_0",
1558 .early_init = sdma_v3_0_early_init,
1559 .late_init = NULL,
1560 .sw_init = sdma_v3_0_sw_init,
1561 .sw_fini = sdma_v3_0_sw_fini,
1562 .hw_init = sdma_v3_0_hw_init,
1563 .hw_fini = sdma_v3_0_hw_fini,
1564 .suspend = sdma_v3_0_suspend,
1565 .resume = sdma_v3_0_resume,
1566 .is_idle = sdma_v3_0_is_idle,
1567 .wait_for_idle = sdma_v3_0_wait_for_idle,
1568 .soft_reset = sdma_v3_0_soft_reset,
1569 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1570 .set_powergating_state = sdma_v3_0_set_powergating_state,
1571 };
1572
1573 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1574 .get_rptr = sdma_v3_0_ring_get_rptr,
1575 .get_wptr = sdma_v3_0_ring_get_wptr,
1576 .set_wptr = sdma_v3_0_ring_set_wptr,
1577 .parse_cs = NULL,
1578 .emit_ib = sdma_v3_0_ring_emit_ib,
1579 .emit_fence = sdma_v3_0_ring_emit_fence,
1580 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1581 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1582 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1583 .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
1584 .test_ring = sdma_v3_0_ring_test_ring,
1585 .test_ib = sdma_v3_0_ring_test_ib,
1586 .insert_nop = sdma_v3_0_ring_insert_nop,
1587 .pad_ib = sdma_v3_0_ring_pad_ib,
1588 };
1589
1590 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1591 {
1592 int i;
1593
1594 for (i = 0; i < adev->sdma.num_instances; i++)
1595 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1596 }
1597
1598 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1599 .set = sdma_v3_0_set_trap_irq_state,
1600 .process = sdma_v3_0_process_trap_irq,
1601 };
1602
1603 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1604 .process = sdma_v3_0_process_illegal_inst_irq,
1605 };
1606
1607 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1608 {
1609 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1610 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1611 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1612 }
1613
1614 /**
1615 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1616 *
1617 * @ring: amdgpu_ring structure holding ring information
1618 * @src_offset: src GPU address
1619 * @dst_offset: dst GPU address
1620 * @byte_count: number of bytes to xfer
1621 *
1622 * Copy GPU buffers using the DMA engine (VI).
1623 * Used by the amdgpu ttm implementation to move pages if
1624 * registered as the asic copy callback.
1625 */
1626 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1627 uint64_t src_offset,
1628 uint64_t dst_offset,
1629 uint32_t byte_count)
1630 {
1631 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1632 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1633 ib->ptr[ib->length_dw++] = byte_count;
1634 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1635 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1636 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1637 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1638 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1639 }
1640
1641 /**
1642 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1643 *
1644 * @ring: amdgpu_ring structure holding ring information
1645 * @src_data: value to write to buffer
1646 * @dst_offset: dst GPU address
1647 * @byte_count: number of bytes to xfer
1648 *
1649 * Fill GPU buffers using the DMA engine (VI).
1650 */
1651 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1652 uint32_t src_data,
1653 uint64_t dst_offset,
1654 uint32_t byte_count)
1655 {
1656 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1657 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1658 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1659 ib->ptr[ib->length_dw++] = src_data;
1660 ib->ptr[ib->length_dw++] = byte_count;
1661 }
1662
1663 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1664 .copy_max_bytes = 0x1fffff,
1665 .copy_num_dw = 7,
1666 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1667
1668 .fill_max_bytes = 0x1fffff,
1669 .fill_num_dw = 5,
1670 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1671 };
1672
1673 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1674 {
1675 if (adev->mman.buffer_funcs == NULL) {
1676 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1677 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1678 }
1679 }
1680
1681 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1682 .copy_pte = sdma_v3_0_vm_copy_pte,
1683 .write_pte = sdma_v3_0_vm_write_pte,
1684 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1685 };
1686
1687 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1688 {
1689 unsigned i;
1690
1691 if (adev->vm_manager.vm_pte_funcs == NULL) {
1692 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1693 for (i = 0; i < adev->sdma.num_instances; i++)
1694 adev->vm_manager.vm_pte_rings[i] =
1695 &adev->sdma.instance[i].ring;
1696
1697 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1698 }
1699 }
Linux kernel - Deliverables
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