2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_3_0_d.h"
33 #include "oss/oss_3_0_sh_mask.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "tonga_sdma_pkt_open.h"
47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device
*adev
);
48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device
*adev
);
49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device
*adev
);
50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device
*adev
);
52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
65 static const u32 sdma_offsets
[SDMA_MAX_INSTANCE
] =
67 SDMA0_REGISTER_OFFSET
,
71 static const u32 golden_settings_tonga_a11
[] =
73 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
74 mmSDMA0_CLK_CTRL
, 0xff000fff, 0x00000000,
75 mmSDMA0_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
76 mmSDMA0_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
77 mmSDMA0_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
78 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
79 mmSDMA1_CLK_CTRL
, 0xff000fff, 0x00000000,
80 mmSDMA1_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
81 mmSDMA1_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
82 mmSDMA1_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
85 static const u32 tonga_mgcg_cgcg_init
[] =
87 mmSDMA0_CLK_CTRL
, 0xff000ff0, 0x00000100,
88 mmSDMA1_CLK_CTRL
, 0xff000ff0, 0x00000100
91 static const u32 golden_settings_fiji_a10
[] =
93 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
94 mmSDMA0_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
95 mmSDMA0_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
96 mmSDMA0_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
97 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
98 mmSDMA1_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
99 mmSDMA1_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
100 mmSDMA1_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
103 static const u32 fiji_mgcg_cgcg_init
[] =
105 mmSDMA0_CLK_CTRL
, 0xff000ff0, 0x00000100,
106 mmSDMA1_CLK_CTRL
, 0xff000ff0, 0x00000100
109 static const u32 golden_settings_polaris11_a11
[] =
111 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
112 mmSDMA0_CLK_CTRL
, 0xff000fff, 0x00000000,
113 mmSDMA0_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
114 mmSDMA0_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
115 mmSDMA0_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
116 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
117 mmSDMA1_CLK_CTRL
, 0xff000fff, 0x00000000,
118 mmSDMA1_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
119 mmSDMA1_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
120 mmSDMA1_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
123 static const u32 golden_settings_polaris10_a11
[] =
125 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
126 mmSDMA0_CLK_CTRL
, 0xff000fff, 0x00000000,
127 mmSDMA0_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
128 mmSDMA0_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
129 mmSDMA0_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
130 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
131 mmSDMA1_CLK_CTRL
, 0xff000fff, 0x00000000,
132 mmSDMA1_GFX_IB_CNTL
, 0x800f0111, 0x00000100,
133 mmSDMA1_RLC0_IB_CNTL
, 0x800f0111, 0x00000100,
134 mmSDMA1_RLC1_IB_CNTL
, 0x800f0111, 0x00000100,
137 static const u32 cz_golden_settings_a11
[] =
139 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
140 mmSDMA0_CLK_CTRL
, 0xff000fff, 0x00000000,
141 mmSDMA0_GFX_IB_CNTL
, 0x00000100, 0x00000100,
142 mmSDMA0_POWER_CNTL
, 0x00000800, 0x0003c800,
143 mmSDMA0_RLC0_IB_CNTL
, 0x00000100, 0x00000100,
144 mmSDMA0_RLC1_IB_CNTL
, 0x00000100, 0x00000100,
145 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
146 mmSDMA1_CLK_CTRL
, 0xff000fff, 0x00000000,
147 mmSDMA1_GFX_IB_CNTL
, 0x00000100, 0x00000100,
148 mmSDMA1_POWER_CNTL
, 0x00000800, 0x0003c800,
149 mmSDMA1_RLC0_IB_CNTL
, 0x00000100, 0x00000100,
150 mmSDMA1_RLC1_IB_CNTL
, 0x00000100, 0x00000100,
153 static const u32 cz_mgcg_cgcg_init
[] =
155 mmSDMA0_CLK_CTRL
, 0xff000ff0, 0x00000100,
156 mmSDMA1_CLK_CTRL
, 0xff000ff0, 0x00000100
159 static const u32 stoney_golden_settings_a11
[] =
161 mmSDMA0_GFX_IB_CNTL
, 0x00000100, 0x00000100,
162 mmSDMA0_POWER_CNTL
, 0x00000800, 0x0003c800,
163 mmSDMA0_RLC0_IB_CNTL
, 0x00000100, 0x00000100,
164 mmSDMA0_RLC1_IB_CNTL
, 0x00000100, 0x00000100,
167 static const u32 stoney_mgcg_cgcg_init
[] =
169 mmSDMA0_CLK_CTRL
, 0xffffffff, 0x00000100,
174 * Starting with CIK, the GPU has new asynchronous
175 * DMA engines. These engines are used for compute
176 * and gfx. There are two DMA engines (SDMA0, SDMA1)
177 * and each one supports 1 ring buffer used for gfx
178 * and 2 queues used for compute.
180 * The programming model is very similar to the CP
181 * (ring buffer, IBs, etc.), but sDMA has it's own
182 * packet format that is different from the PM4 format
183 * used by the CP. sDMA supports copying data, writing
184 * embedded data, solid fills, and a number of other
185 * things. It also has support for tiling/detiling of
189 static void sdma_v3_0_init_golden_registers(struct amdgpu_device
*adev
)
191 switch (adev
->asic_type
) {
193 amdgpu_program_register_sequence(adev
,
195 (const u32
)ARRAY_SIZE(fiji_mgcg_cgcg_init
));
196 amdgpu_program_register_sequence(adev
,
197 golden_settings_fiji_a10
,
198 (const u32
)ARRAY_SIZE(golden_settings_fiji_a10
));
201 amdgpu_program_register_sequence(adev
,
202 tonga_mgcg_cgcg_init
,
203 (const u32
)ARRAY_SIZE(tonga_mgcg_cgcg_init
));
204 amdgpu_program_register_sequence(adev
,
205 golden_settings_tonga_a11
,
206 (const u32
)ARRAY_SIZE(golden_settings_tonga_a11
));
209 amdgpu_program_register_sequence(adev
,
210 golden_settings_polaris11_a11
,
211 (const u32
)ARRAY_SIZE(golden_settings_polaris11_a11
));
214 amdgpu_program_register_sequence(adev
,
215 golden_settings_polaris10_a11
,
216 (const u32
)ARRAY_SIZE(golden_settings_polaris10_a11
));
219 amdgpu_program_register_sequence(adev
,
221 (const u32
)ARRAY_SIZE(cz_mgcg_cgcg_init
));
222 amdgpu_program_register_sequence(adev
,
223 cz_golden_settings_a11
,
224 (const u32
)ARRAY_SIZE(cz_golden_settings_a11
));
227 amdgpu_program_register_sequence(adev
,
228 stoney_mgcg_cgcg_init
,
229 (const u32
)ARRAY_SIZE(stoney_mgcg_cgcg_init
));
230 amdgpu_program_register_sequence(adev
,
231 stoney_golden_settings_a11
,
232 (const u32
)ARRAY_SIZE(stoney_golden_settings_a11
));
239 static void sdma_v3_0_free_microcode(struct amdgpu_device
*adev
)
242 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
243 release_firmware(adev
->sdma
.instance
[i
].fw
);
244 adev
->sdma
.instance
[i
].fw
= NULL
;
249 * sdma_v3_0_init_microcode - load ucode images from disk
251 * @adev: amdgpu_device pointer
253 * Use the firmware interface to load the ucode images into
254 * the driver (not loaded into hw).
255 * Returns 0 on success, error on failure.
257 static int sdma_v3_0_init_microcode(struct amdgpu_device
*adev
)
259 const char *chip_name
;
262 struct amdgpu_firmware_info
*info
= NULL
;
263 const struct common_firmware_header
*header
= NULL
;
264 const struct sdma_firmware_header_v1_0
*hdr
;
268 switch (adev
->asic_type
) {
276 chip_name
= "polaris11";
279 chip_name
= "polaris10";
282 chip_name
= "carrizo";
285 chip_name
= "stoney";
290 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
292 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma.bin", chip_name
);
294 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma1.bin", chip_name
);
295 err
= request_firmware(&adev
->sdma
.instance
[i
].fw
, fw_name
, adev
->dev
);
298 err
= amdgpu_ucode_validate(adev
->sdma
.instance
[i
].fw
);
301 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
302 adev
->sdma
.instance
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
303 adev
->sdma
.instance
[i
].feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
304 if (adev
->sdma
.instance
[i
].feature_version
>= 20)
305 adev
->sdma
.instance
[i
].burst_nop
= true;
307 if (adev
->firmware
.smu_load
) {
308 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_SDMA0
+ i
];
309 info
->ucode_id
= AMDGPU_UCODE_ID_SDMA0
+ i
;
310 info
->fw
= adev
->sdma
.instance
[i
].fw
;
311 header
= (const struct common_firmware_header
*)info
->fw
->data
;
312 adev
->firmware
.fw_size
+=
313 ALIGN(le32_to_cpu(header
->ucode_size_bytes
), PAGE_SIZE
);
319 "sdma_v3_0: Failed to load firmware \"%s\"\n",
321 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
322 release_firmware(adev
->sdma
.instance
[i
].fw
);
323 adev
->sdma
.instance
[i
].fw
= NULL
;
330 * sdma_v3_0_ring_get_rptr - get the current read pointer
332 * @ring: amdgpu ring pointer
334 * Get the current rptr from the hardware (VI+).
336 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring
*ring
)
340 /* XXX check if swapping is necessary on BE */
341 rptr
= ring
->adev
->wb
.wb
[ring
->rptr_offs
] >> 2;
347 * sdma_v3_0_ring_get_wptr - get the current write pointer
349 * @ring: amdgpu ring pointer
351 * Get the current wptr from the hardware (VI+).
353 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring
*ring
)
355 struct amdgpu_device
*adev
= ring
->adev
;
358 if (ring
->use_doorbell
) {
359 /* XXX check if swapping is necessary on BE */
360 wptr
= ring
->adev
->wb
.wb
[ring
->wptr_offs
] >> 2;
362 int me
= (ring
== &ring
->adev
->sdma
.instance
[0].ring
) ? 0 : 1;
364 wptr
= RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
]) >> 2;
371 * sdma_v3_0_ring_set_wptr - commit the write pointer
373 * @ring: amdgpu ring pointer
375 * Write the wptr back to the hardware (VI+).
377 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring
*ring
)
379 struct amdgpu_device
*adev
= ring
->adev
;
381 if (ring
->use_doorbell
) {
382 /* XXX check if swapping is necessary on BE */
383 adev
->wb
.wb
[ring
->wptr_offs
] = ring
->wptr
<< 2;
384 WDOORBELL32(ring
->doorbell_index
, ring
->wptr
<< 2);
386 int me
= (ring
== &ring
->adev
->sdma
.instance
[0].ring
) ? 0 : 1;
388 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
], ring
->wptr
<< 2);
392 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
394 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
397 for (i
= 0; i
< count
; i
++)
398 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
399 amdgpu_ring_write(ring
, ring
->nop
|
400 SDMA_PKT_NOP_HEADER_COUNT(count
- 1));
402 amdgpu_ring_write(ring
, ring
->nop
);
406 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
408 * @ring: amdgpu ring pointer
409 * @ib: IB object to schedule
411 * Schedule an IB in the DMA ring (VI).
413 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring
*ring
,
414 struct amdgpu_ib
*ib
,
415 unsigned vm_id
, bool ctx_switch
)
417 u32 vmid
= vm_id
& 0xf;
419 /* IB packet must end on a 8 DW boundary */
420 sdma_v3_0_ring_insert_nop(ring
, (10 - (ring
->wptr
& 7)) % 8);
422 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT
) |
423 SDMA_PKT_INDIRECT_HEADER_VMID(vmid
));
424 /* base must be 32 byte aligned */
425 amdgpu_ring_write(ring
, lower_32_bits(ib
->gpu_addr
) & 0xffffffe0);
426 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
427 amdgpu_ring_write(ring
, ib
->length_dw
);
428 amdgpu_ring_write(ring
, 0);
429 amdgpu_ring_write(ring
, 0);
434 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
436 * @ring: amdgpu ring pointer
438 * Emit an hdp flush packet on the requested DMA ring.
440 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
442 u32 ref_and_mask
= 0;
444 if (ring
== &ring
->adev
->sdma
.instance
[0].ring
)
445 ref_and_mask
= REG_SET_FIELD(ref_and_mask
, GPU_HDP_FLUSH_DONE
, SDMA0
, 1);
447 ref_and_mask
= REG_SET_FIELD(ref_and_mask
, GPU_HDP_FLUSH_DONE
, SDMA1
, 1);
449 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
450 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
451 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
452 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
<< 2);
453 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
<< 2);
454 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
455 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
456 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
457 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
460 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring
*ring
)
462 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
463 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
464 amdgpu_ring_write(ring
, mmHDP_DEBUG0
);
465 amdgpu_ring_write(ring
, 1);
469 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
471 * @ring: amdgpu ring pointer
472 * @fence: amdgpu fence object
474 * Add a DMA fence packet to the ring to write
475 * the fence seq number and DMA trap packet to generate
476 * an interrupt if needed (VI).
478 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
481 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
482 /* write the fence */
483 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
));
484 amdgpu_ring_write(ring
, lower_32_bits(addr
));
485 amdgpu_ring_write(ring
, upper_32_bits(addr
));
486 amdgpu_ring_write(ring
, lower_32_bits(seq
));
488 /* optionally write high bits as well */
491 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
));
492 amdgpu_ring_write(ring
, lower_32_bits(addr
));
493 amdgpu_ring_write(ring
, upper_32_bits(addr
));
494 amdgpu_ring_write(ring
, upper_32_bits(seq
));
497 /* generate an interrupt */
498 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP
));
499 amdgpu_ring_write(ring
, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
502 unsigned init_cond_exec(struct amdgpu_ring
*ring
)
505 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE
));
506 amdgpu_ring_write(ring
, lower_32_bits(ring
->cond_exe_gpu_addr
));
507 amdgpu_ring_write(ring
, upper_32_bits(ring
->cond_exe_gpu_addr
));
508 amdgpu_ring_write(ring
, 1);
509 ret
= ring
->wptr
;/* this is the offset we need patch later */
510 amdgpu_ring_write(ring
, 0x55aa55aa);/* insert dummy here and patch it later */
514 void patch_cond_exec(struct amdgpu_ring
*ring
, unsigned offset
)
517 BUG_ON(ring
->ring
[offset
] != 0x55aa55aa);
519 cur
= ring
->wptr
- 1;
520 if (likely(cur
> offset
))
521 ring
->ring
[offset
] = cur
- offset
;
523 ring
->ring
[offset
] = (ring
->ring_size
>>2) - offset
+ cur
;
528 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
530 * @adev: amdgpu_device pointer
532 * Stop the gfx async dma ring buffers (VI).
534 static void sdma_v3_0_gfx_stop(struct amdgpu_device
*adev
)
536 struct amdgpu_ring
*sdma0
= &adev
->sdma
.instance
[0].ring
;
537 struct amdgpu_ring
*sdma1
= &adev
->sdma
.instance
[1].ring
;
538 u32 rb_cntl
, ib_cntl
;
541 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
542 (adev
->mman
.buffer_funcs_ring
== sdma1
))
543 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
545 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
546 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
547 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 0);
548 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
549 ib_cntl
= RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]);
550 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 0);
551 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
553 sdma0
->ready
= false;
554 sdma1
->ready
= false;
558 * sdma_v3_0_rlc_stop - stop the compute async dma engines
560 * @adev: amdgpu_device pointer
562 * Stop the compute async dma queues (VI).
564 static void sdma_v3_0_rlc_stop(struct amdgpu_device
*adev
)
570 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
572 * @adev: amdgpu_device pointer
573 * @enable: enable/disable the DMA MEs context switch.
575 * Halt or unhalt the async dma engines context switch (VI).
577 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device
*adev
, bool enable
)
582 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
583 f32_cntl
= RREG32(mmSDMA0_CNTL
+ sdma_offsets
[i
]);
585 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_CNTL
,
586 AUTO_CTXSW_ENABLE
, 1);
588 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_CNTL
,
589 AUTO_CTXSW_ENABLE
, 0);
590 WREG32(mmSDMA0_CNTL
+ sdma_offsets
[i
], f32_cntl
);
595 * sdma_v3_0_enable - stop the async dma engines
597 * @adev: amdgpu_device pointer
598 * @enable: enable/disable the DMA MEs.
600 * Halt or unhalt the async dma engines (VI).
602 static void sdma_v3_0_enable(struct amdgpu_device
*adev
, bool enable
)
608 sdma_v3_0_gfx_stop(adev
);
609 sdma_v3_0_rlc_stop(adev
);
612 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
613 f32_cntl
= RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]);
615 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_F32_CNTL
, HALT
, 0);
617 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_F32_CNTL
, HALT
, 1);
618 WREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
], f32_cntl
);
623 * sdma_v3_0_gfx_resume - setup and start the async dma engines
625 * @adev: amdgpu_device pointer
627 * Set up the gfx DMA ring buffers and enable them (VI).
628 * Returns 0 for success, error for failure.
630 static int sdma_v3_0_gfx_resume(struct amdgpu_device
*adev
)
632 struct amdgpu_ring
*ring
;
633 u32 rb_cntl
, ib_cntl
;
639 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
640 ring
= &adev
->sdma
.instance
[i
].ring
;
641 wb_offset
= (ring
->rptr_offs
* 4);
643 mutex_lock(&adev
->srbm_mutex
);
644 for (j
= 0; j
< 16; j
++) {
645 vi_srbm_select(adev
, 0, 0, 0, j
);
647 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
], 0);
648 WREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
], 0);
650 vi_srbm_select(adev
, 0, 0, 0, 0);
651 mutex_unlock(&adev
->srbm_mutex
);
653 WREG32(mmSDMA0_TILING_CONFIG
+ sdma_offsets
[i
],
654 adev
->gfx
.config
.gb_addr_config
& 0x70);
656 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
], 0);
658 /* Set ring buffer size in dwords */
659 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
660 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
661 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SIZE
, rb_bufsz
);
663 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SWAP_ENABLE
, 1);
664 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
,
665 RPTR_WRITEBACK_SWAP_ENABLE
, 1);
667 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
669 /* Initialize the ring buffer's read and write pointers */
670 WREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
], 0);
671 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], 0);
672 WREG32(mmSDMA0_GFX_IB_RPTR
+ sdma_offsets
[i
], 0);
673 WREG32(mmSDMA0_GFX_IB_OFFSET
+ sdma_offsets
[i
], 0);
675 /* set the wb address whether it's enabled or not */
676 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
],
677 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
678 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
],
679 lower_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC);
681 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RPTR_WRITEBACK_ENABLE
, 1);
683 WREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
], ring
->gpu_addr
>> 8);
684 WREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
], ring
->gpu_addr
>> 40);
687 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], ring
->wptr
<< 2);
689 doorbell
= RREG32(mmSDMA0_GFX_DOORBELL
+ sdma_offsets
[i
]);
691 if (ring
->use_doorbell
) {
692 doorbell
= REG_SET_FIELD(doorbell
, SDMA0_GFX_DOORBELL
,
693 OFFSET
, ring
->doorbell_index
);
694 doorbell
= REG_SET_FIELD(doorbell
, SDMA0_GFX_DOORBELL
, ENABLE
, 1);
696 doorbell
= REG_SET_FIELD(doorbell
, SDMA0_GFX_DOORBELL
, ENABLE
, 0);
698 WREG32(mmSDMA0_GFX_DOORBELL
+ sdma_offsets
[i
], doorbell
);
701 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 1);
702 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
704 ib_cntl
= RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]);
705 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 1);
707 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_SWAP_ENABLE
, 1);
710 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
716 sdma_v3_0_enable(adev
, true);
717 /* enable sdma ring preemption */
718 sdma_v3_0_ctx_switch_enable(adev
, true);
720 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
721 ring
= &adev
->sdma
.instance
[i
].ring
;
722 r
= amdgpu_ring_test_ring(ring
);
728 if (adev
->mman
.buffer_funcs_ring
== ring
)
729 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.real_vram_size
);
736 * sdma_v3_0_rlc_resume - setup and start the async dma engines
738 * @adev: amdgpu_device pointer
740 * Set up the compute DMA queues and enable them (VI).
741 * Returns 0 for success, error for failure.
743 static int sdma_v3_0_rlc_resume(struct amdgpu_device
*adev
)
750 * sdma_v3_0_load_microcode - load the sDMA ME ucode
752 * @adev: amdgpu_device pointer
754 * Loads the sDMA0/1 ucode.
755 * Returns 0 for success, -EINVAL if the ucode is not available.
757 static int sdma_v3_0_load_microcode(struct amdgpu_device
*adev
)
759 const struct sdma_firmware_header_v1_0
*hdr
;
760 const __le32
*fw_data
;
765 sdma_v3_0_enable(adev
, false);
767 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
768 if (!adev
->sdma
.instance
[i
].fw
)
770 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
771 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
772 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
773 fw_data
= (const __le32
*)
774 (adev
->sdma
.instance
[i
].fw
->data
+
775 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
776 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], 0);
777 for (j
= 0; j
< fw_size
; j
++)
778 WREG32(mmSDMA0_UCODE_DATA
+ sdma_offsets
[i
], le32_to_cpup(fw_data
++));
779 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], adev
->sdma
.instance
[i
].fw_version
);
786 * sdma_v3_0_start - setup and start the async dma engines
788 * @adev: amdgpu_device pointer
790 * Set up the DMA engines and enable them (VI).
791 * Returns 0 for success, error for failure.
793 static int sdma_v3_0_start(struct amdgpu_device
*adev
)
797 if (!adev
->pp_enabled
) {
798 if (!adev
->firmware
.smu_load
) {
799 r
= sdma_v3_0_load_microcode(adev
);
803 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
804 r
= adev
->smu
.smumgr_funcs
->check_fw_load_finish(adev
,
806 AMDGPU_UCODE_ID_SDMA0
:
807 AMDGPU_UCODE_ID_SDMA1
);
814 /* disble sdma engine before programing it */
815 sdma_v3_0_ctx_switch_enable(adev
, false);
816 sdma_v3_0_enable(adev
, false);
818 /* start the gfx rings and rlc compute queues */
819 r
= sdma_v3_0_gfx_resume(adev
);
822 r
= sdma_v3_0_rlc_resume(adev
);
830 * sdma_v3_0_ring_test_ring - simple async dma engine test
832 * @ring: amdgpu_ring structure holding ring information
834 * Test the DMA engine by writing using it to write an
835 * value to memory. (VI).
836 * Returns 0 for success, error for failure.
838 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring
*ring
)
840 struct amdgpu_device
*adev
= ring
->adev
;
847 r
= amdgpu_wb_get(adev
, &index
);
849 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
853 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
855 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
857 r
= amdgpu_ring_alloc(ring
, 5);
859 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
860 amdgpu_wb_free(adev
, index
);
864 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
865 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
));
866 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
867 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
868 amdgpu_ring_write(ring
, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
869 amdgpu_ring_write(ring
, 0xDEADBEEF);
870 amdgpu_ring_commit(ring
);
872 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
873 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
874 if (tmp
== 0xDEADBEEF)
879 if (i
< adev
->usec_timeout
) {
880 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
882 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
886 amdgpu_wb_free(adev
, index
);
892 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
894 * @ring: amdgpu_ring structure holding ring information
896 * Test a simple IB in the DMA ring (VI).
897 * Returns 0 on success, error on failure.
899 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring
*ring
)
901 struct amdgpu_device
*adev
= ring
->adev
;
903 struct fence
*f
= NULL
;
909 r
= amdgpu_wb_get(adev
, &index
);
911 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
915 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
917 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
918 memset(&ib
, 0, sizeof(ib
));
919 r
= amdgpu_ib_get(adev
, NULL
, 256, &ib
);
921 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r
);
925 ib
.ptr
[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
926 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
);
927 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
928 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
929 ib
.ptr
[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
930 ib
.ptr
[4] = 0xDEADBEEF;
931 ib
.ptr
[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
932 ib
.ptr
[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
933 ib
.ptr
[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
);
936 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, NULL
, &f
);
940 r
= fence_wait(f
, false);
942 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r
);
945 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
946 if (tmp
== 0xDEADBEEF) {
947 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
949 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp
);
953 amdgpu_ib_free(adev
, &ib
, NULL
);
956 amdgpu_wb_free(adev
, index
);
961 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
963 * @ib: indirect buffer to fill with commands
964 * @pe: addr of the page entry
965 * @src: src addr to copy from
966 * @count: number of page entries to update
968 * Update PTEs by copying them from the GART using sDMA (CIK).
970 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib
*ib
,
971 uint64_t pe
, uint64_t src
,
975 unsigned bytes
= count
* 8;
976 if (bytes
> 0x1FFFF8)
979 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
980 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
981 ib
->ptr
[ib
->length_dw
++] = bytes
;
982 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
983 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
984 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
985 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
986 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
995 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
997 * @ib: indirect buffer to fill with commands
998 * @pe: addr of the page entry
999 * @addr: dst addr to write into pe
1000 * @count: number of page entries to update
1001 * @incr: increase next addr by incr bytes
1002 * @flags: access flags
1004 * Update PTEs by writing them manually using sDMA (CIK).
1006 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib
*ib
,
1007 const dma_addr_t
*pages_addr
, uint64_t pe
,
1008 uint64_t addr
, unsigned count
,
1009 uint32_t incr
, uint32_t flags
)
1019 /* for non-physically contiguous pages (system) */
1020 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
1021 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
1022 ib
->ptr
[ib
->length_dw
++] = pe
;
1023 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
1024 ib
->ptr
[ib
->length_dw
++] = ndw
;
1025 for (; ndw
> 0; ndw
-= 2, --count
, pe
+= 8) {
1026 value
= amdgpu_vm_map_gart(pages_addr
, addr
);
1029 ib
->ptr
[ib
->length_dw
++] = value
;
1030 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
1036 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1038 * @ib: indirect buffer to fill with commands
1039 * @pe: addr of the page entry
1040 * @addr: dst addr to write into pe
1041 * @count: number of page entries to update
1042 * @incr: increase next addr by incr bytes
1043 * @flags: access flags
1045 * Update the page tables using sDMA (CIK).
1047 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib
*ib
,
1049 uint64_t addr
, unsigned count
,
1050 uint32_t incr
, uint32_t flags
)
1060 if (flags
& AMDGPU_PTE_VALID
)
1065 /* for physically contiguous pages (vram) */
1066 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE
);
1067 ib
->ptr
[ib
->length_dw
++] = pe
; /* dst addr */
1068 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
1069 ib
->ptr
[ib
->length_dw
++] = flags
; /* mask */
1070 ib
->ptr
[ib
->length_dw
++] = 0;
1071 ib
->ptr
[ib
->length_dw
++] = value
; /* value */
1072 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
1073 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
1074 ib
->ptr
[ib
->length_dw
++] = 0;
1075 ib
->ptr
[ib
->length_dw
++] = ndw
; /* number of entries */
1084 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1086 * @ib: indirect buffer to fill with padding
1089 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
)
1091 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
1095 pad_count
= (8 - (ib
->length_dw
& 0x7)) % 8;
1096 for (i
= 0; i
< pad_count
; i
++)
1097 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
1098 ib
->ptr
[ib
->length_dw
++] =
1099 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
) |
1100 SDMA_PKT_NOP_HEADER_COUNT(pad_count
- 1);
1102 ib
->ptr
[ib
->length_dw
++] =
1103 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
1107 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1109 * @ring: amdgpu_ring pointer
1111 * Make sure all previous operations are completed (CIK).
1113 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring
*ring
)
1115 uint32_t seq
= ring
->fence_drv
.sync_seq
;
1116 uint64_t addr
= ring
->fence_drv
.gpu_addr
;
1119 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
1120 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1121 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1122 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1123 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
1124 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
1125 amdgpu_ring_write(ring
, seq
); /* reference */
1126 amdgpu_ring_write(ring
, 0xfffffff); /* mask */
1127 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1128 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1132 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1134 * @ring: amdgpu_ring pointer
1135 * @vm: amdgpu_vm pointer
1137 * Update the page table base and flush the VM TLB
1140 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
1141 unsigned vm_id
, uint64_t pd_addr
)
1143 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
1144 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1146 amdgpu_ring_write(ring
, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
1148 amdgpu_ring_write(ring
, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
1150 amdgpu_ring_write(ring
, pd_addr
>> 12);
1153 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
1154 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1155 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
1156 amdgpu_ring_write(ring
, 1 << vm_id
);
1158 /* wait for flush */
1159 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
1160 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1161 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1162 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
<< 2);
1163 amdgpu_ring_write(ring
, 0);
1164 amdgpu_ring_write(ring
, 0); /* reference */
1165 amdgpu_ring_write(ring
, 0); /* mask */
1166 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1167 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1170 static int sdma_v3_0_early_init(void *handle
)
1172 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1174 switch (adev
->asic_type
) {
1176 adev
->sdma
.num_instances
= 1;
1179 adev
->sdma
.num_instances
= SDMA_MAX_INSTANCE
;
1183 sdma_v3_0_set_ring_funcs(adev
);
1184 sdma_v3_0_set_buffer_funcs(adev
);
1185 sdma_v3_0_set_vm_pte_funcs(adev
);
1186 sdma_v3_0_set_irq_funcs(adev
);
1191 static int sdma_v3_0_sw_init(void *handle
)
1193 struct amdgpu_ring
*ring
;
1195 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1197 /* SDMA trap event */
1198 r
= amdgpu_irq_add_id(adev
, 224, &adev
->sdma
.trap_irq
);
1202 /* SDMA Privileged inst */
1203 r
= amdgpu_irq_add_id(adev
, 241, &adev
->sdma
.illegal_inst_irq
);
1207 /* SDMA Privileged inst */
1208 r
= amdgpu_irq_add_id(adev
, 247, &adev
->sdma
.illegal_inst_irq
);
1212 r
= sdma_v3_0_init_microcode(adev
);
1214 DRM_ERROR("Failed to load sdma firmware!\n");
1218 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1219 ring
= &adev
->sdma
.instance
[i
].ring
;
1220 ring
->ring_obj
= NULL
;
1221 ring
->use_doorbell
= true;
1222 ring
->doorbell_index
= (i
== 0) ?
1223 AMDGPU_DOORBELL_sDMA_ENGINE0
: AMDGPU_DOORBELL_sDMA_ENGINE1
;
1225 sprintf(ring
->name
, "sdma%d", i
);
1226 r
= amdgpu_ring_init(adev
, ring
, 1024,
1227 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
), 0xf,
1228 &adev
->sdma
.trap_irq
,
1230 AMDGPU_SDMA_IRQ_TRAP0
: AMDGPU_SDMA_IRQ_TRAP1
,
1231 AMDGPU_RING_TYPE_SDMA
);
1239 static int sdma_v3_0_sw_fini(void *handle
)
1241 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1244 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1245 amdgpu_ring_fini(&adev
->sdma
.instance
[i
].ring
);
1247 sdma_v3_0_free_microcode(adev
);
1251 static int sdma_v3_0_hw_init(void *handle
)
1254 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1256 sdma_v3_0_init_golden_registers(adev
);
1258 r
= sdma_v3_0_start(adev
);
1265 static int sdma_v3_0_hw_fini(void *handle
)
1267 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1269 sdma_v3_0_ctx_switch_enable(adev
, false);
1270 sdma_v3_0_enable(adev
, false);
1275 static int sdma_v3_0_suspend(void *handle
)
1277 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1279 return sdma_v3_0_hw_fini(adev
);
1282 static int sdma_v3_0_resume(void *handle
)
1284 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1286 return sdma_v3_0_hw_init(adev
);
1289 static bool sdma_v3_0_is_idle(void *handle
)
1291 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1292 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1294 if (tmp
& (SRBM_STATUS2__SDMA_BUSY_MASK
|
1295 SRBM_STATUS2__SDMA1_BUSY_MASK
))
1301 static int sdma_v3_0_wait_for_idle(void *handle
)
1305 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1307 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1308 tmp
= RREG32(mmSRBM_STATUS2
) & (SRBM_STATUS2__SDMA_BUSY_MASK
|
1309 SRBM_STATUS2__SDMA1_BUSY_MASK
);
1318 static int sdma_v3_0_soft_reset(void *handle
)
1320 u32 srbm_soft_reset
= 0;
1321 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1322 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1324 if (tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
) {
1326 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
1327 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 0);
1328 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
1329 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK
;
1331 if (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
) {
1333 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
1334 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 0);
1335 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
1336 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK
;
1339 if (srbm_soft_reset
) {
1340 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1341 tmp
|= srbm_soft_reset
;
1342 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1343 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1344 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1348 tmp
&= ~srbm_soft_reset
;
1349 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1350 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1352 /* Wait a little for things to settle down */
1359 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device
*adev
,
1360 struct amdgpu_irq_src
*source
,
1362 enum amdgpu_interrupt_state state
)
1367 case AMDGPU_SDMA_IRQ_TRAP0
:
1369 case AMDGPU_IRQ_STATE_DISABLE
:
1370 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1371 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 0);
1372 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1374 case AMDGPU_IRQ_STATE_ENABLE
:
1375 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1376 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 1);
1377 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1383 case AMDGPU_SDMA_IRQ_TRAP1
:
1385 case AMDGPU_IRQ_STATE_DISABLE
:
1386 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1387 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 0);
1388 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1390 case AMDGPU_IRQ_STATE_ENABLE
:
1391 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1392 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 1);
1393 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1405 static int sdma_v3_0_process_trap_irq(struct amdgpu_device
*adev
,
1406 struct amdgpu_irq_src
*source
,
1407 struct amdgpu_iv_entry
*entry
)
1409 u8 instance_id
, queue_id
;
1411 instance_id
= (entry
->ring_id
& 0x3) >> 0;
1412 queue_id
= (entry
->ring_id
& 0xc) >> 2;
1413 DRM_DEBUG("IH: SDMA trap\n");
1414 switch (instance_id
) {
1418 amdgpu_fence_process(&adev
->sdma
.instance
[0].ring
);
1431 amdgpu_fence_process(&adev
->sdma
.instance
[1].ring
);
1445 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1446 struct amdgpu_irq_src
*source
,
1447 struct amdgpu_iv_entry
*entry
)
1449 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1450 schedule_work(&adev
->reset_work
);
1454 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1455 struct amdgpu_device
*adev
,
1458 uint32_t temp
, data
;
1461 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_MGCG
)) {
1462 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1463 temp
= data
= RREG32(mmSDMA0_CLK_CTRL
+ sdma_offsets
[i
]);
1464 data
&= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK
|
1465 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK
|
1466 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK
|
1467 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK
|
1468 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK
|
1469 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK
|
1470 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK
|
1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK
);
1473 WREG32(mmSDMA0_CLK_CTRL
+ sdma_offsets
[i
], data
);
1476 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1477 temp
= data
= RREG32(mmSDMA0_CLK_CTRL
+ sdma_offsets
[i
]);
1478 data
|= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK
|
1479 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK
|
1480 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK
|
1481 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK
|
1482 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK
|
1483 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK
|
1484 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK
|
1485 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK
;
1488 WREG32(mmSDMA0_CLK_CTRL
+ sdma_offsets
[i
], data
);
1493 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1494 struct amdgpu_device
*adev
,
1497 uint32_t temp
, data
;
1500 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_LS
)) {
1501 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1502 temp
= data
= RREG32(mmSDMA0_POWER_CNTL
+ sdma_offsets
[i
]);
1503 data
|= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK
;
1506 WREG32(mmSDMA0_POWER_CNTL
+ sdma_offsets
[i
], data
);
1509 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1510 temp
= data
= RREG32(mmSDMA0_POWER_CNTL
+ sdma_offsets
[i
]);
1511 data
&= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK
;
1514 WREG32(mmSDMA0_POWER_CNTL
+ sdma_offsets
[i
], data
);
1519 static int sdma_v3_0_set_clockgating_state(void *handle
,
1520 enum amd_clockgating_state state
)
1522 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1524 switch (adev
->asic_type
) {
1528 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev
,
1529 state
== AMD_CG_STATE_GATE
? true : false);
1530 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev
,
1531 state
== AMD_CG_STATE_GATE
? true : false);
1539 static int sdma_v3_0_set_powergating_state(void *handle
,
1540 enum amd_powergating_state state
)
1545 const struct amd_ip_funcs sdma_v3_0_ip_funcs
= {
1546 .name
= "sdma_v3_0",
1547 .early_init
= sdma_v3_0_early_init
,
1549 .sw_init
= sdma_v3_0_sw_init
,
1550 .sw_fini
= sdma_v3_0_sw_fini
,
1551 .hw_init
= sdma_v3_0_hw_init
,
1552 .hw_fini
= sdma_v3_0_hw_fini
,
1553 .suspend
= sdma_v3_0_suspend
,
1554 .resume
= sdma_v3_0_resume
,
1555 .is_idle
= sdma_v3_0_is_idle
,
1556 .wait_for_idle
= sdma_v3_0_wait_for_idle
,
1557 .soft_reset
= sdma_v3_0_soft_reset
,
1558 .set_clockgating_state
= sdma_v3_0_set_clockgating_state
,
1559 .set_powergating_state
= sdma_v3_0_set_powergating_state
,
1562 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs
= {
1563 .get_rptr
= sdma_v3_0_ring_get_rptr
,
1564 .get_wptr
= sdma_v3_0_ring_get_wptr
,
1565 .set_wptr
= sdma_v3_0_ring_set_wptr
,
1567 .emit_ib
= sdma_v3_0_ring_emit_ib
,
1568 .emit_fence
= sdma_v3_0_ring_emit_fence
,
1569 .emit_pipeline_sync
= sdma_v3_0_ring_emit_pipeline_sync
,
1570 .emit_vm_flush
= sdma_v3_0_ring_emit_vm_flush
,
1571 .emit_hdp_flush
= sdma_v3_0_ring_emit_hdp_flush
,
1572 .emit_hdp_invalidate
= sdma_v3_0_ring_emit_hdp_invalidate
,
1573 .test_ring
= sdma_v3_0_ring_test_ring
,
1574 .test_ib
= sdma_v3_0_ring_test_ib
,
1575 .insert_nop
= sdma_v3_0_ring_insert_nop
,
1576 .pad_ib
= sdma_v3_0_ring_pad_ib
,
1579 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device
*adev
)
1583 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1584 adev
->sdma
.instance
[i
].ring
.funcs
= &sdma_v3_0_ring_funcs
;
1587 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs
= {
1588 .set
= sdma_v3_0_set_trap_irq_state
,
1589 .process
= sdma_v3_0_process_trap_irq
,
1592 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs
= {
1593 .process
= sdma_v3_0_process_illegal_inst_irq
,
1596 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device
*adev
)
1598 adev
->sdma
.trap_irq
.num_types
= AMDGPU_SDMA_IRQ_LAST
;
1599 adev
->sdma
.trap_irq
.funcs
= &sdma_v3_0_trap_irq_funcs
;
1600 adev
->sdma
.illegal_inst_irq
.funcs
= &sdma_v3_0_illegal_inst_irq_funcs
;
1604 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1606 * @ring: amdgpu_ring structure holding ring information
1607 * @src_offset: src GPU address
1608 * @dst_offset: dst GPU address
1609 * @byte_count: number of bytes to xfer
1611 * Copy GPU buffers using the DMA engine (VI).
1612 * Used by the amdgpu ttm implementation to move pages if
1613 * registered as the asic copy callback.
1615 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib
*ib
,
1616 uint64_t src_offset
,
1617 uint64_t dst_offset
,
1618 uint32_t byte_count
)
1620 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
1621 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
1622 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1623 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1624 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src_offset
);
1625 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src_offset
);
1626 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1627 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1631 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1633 * @ring: amdgpu_ring structure holding ring information
1634 * @src_data: value to write to buffer
1635 * @dst_offset: dst GPU address
1636 * @byte_count: number of bytes to xfer
1638 * Fill GPU buffers using the DMA engine (VI).
1640 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib
*ib
,
1642 uint64_t dst_offset
,
1643 uint32_t byte_count
)
1645 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL
);
1646 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1647 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1648 ib
->ptr
[ib
->length_dw
++] = src_data
;
1649 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1652 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs
= {
1653 .copy_max_bytes
= 0x1fffff,
1655 .emit_copy_buffer
= sdma_v3_0_emit_copy_buffer
,
1657 .fill_max_bytes
= 0x1fffff,
1659 .emit_fill_buffer
= sdma_v3_0_emit_fill_buffer
,
1662 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device
*adev
)
1664 if (adev
->mman
.buffer_funcs
== NULL
) {
1665 adev
->mman
.buffer_funcs
= &sdma_v3_0_buffer_funcs
;
1666 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
.instance
[0].ring
;
1670 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs
= {
1671 .copy_pte
= sdma_v3_0_vm_copy_pte
,
1672 .write_pte
= sdma_v3_0_vm_write_pte
,
1673 .set_pte_pde
= sdma_v3_0_vm_set_pte_pde
,
1676 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1680 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1681 adev
->vm_manager
.vm_pte_funcs
= &sdma_v3_0_vm_pte_funcs
;
1682 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1683 adev
->vm_manager
.vm_pte_rings
[i
] =
1684 &adev
->sdma
.instance
[i
].ring
;
1686 adev
->vm_manager
.vm_pte_num_rings
= adev
->sdma
.num_instances
;