2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "tonga_ppsmc.h"
28 #include "tonga_smum.h"
29 #include "smu_ucode_xfer_vi.h"
30 #include "amdgpu_ucode.h"
32 #include "smu/smu_7_1_2_d.h"
33 #include "smu/smu_7_1_2_sh_mask.h"
35 #define TONGA_SMC_SIZE 0x20000
37 static int tonga_set_smc_sram_address(struct amdgpu_device
*adev
, uint32_t smc_address
, uint32_t limit
)
44 if ((smc_address
+ 3) > limit
)
47 WREG32(mmSMC_IND_INDEX_0
, smc_address
);
49 val
= RREG32(mmSMC_IND_ACCESS_CNTL
);
50 val
= REG_SET_FIELD(val
, SMC_IND_ACCESS_CNTL
, AUTO_INCREMENT_IND_0
, 0);
51 WREG32(mmSMC_IND_ACCESS_CNTL
, val
);
56 static int tonga_copy_bytes_to_smc(struct amdgpu_device
*adev
, uint32_t smc_start_address
, const uint8_t *src
, uint32_t byte_count
, uint32_t limit
)
59 uint32_t data
, orig_data
;
64 if (smc_start_address
& 3)
67 if ((smc_start_address
+ byte_count
) > limit
)
70 addr
= smc_start_address
;
72 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
73 while (byte_count
>= 4) {
74 /* Bytes are written into the SMC addres space with the MSB first */
75 data
= (src
[0] << 24) + (src
[1] << 16) + (src
[2] << 8) + src
[3];
77 result
= tonga_set_smc_sram_address(adev
, addr
, limit
);
82 WREG32(mmSMC_IND_DATA_0
, data
);
89 if (0 != byte_count
) {
90 /* Now write odd bytes left, do a read modify write cycle */
93 result
= tonga_set_smc_sram_address(adev
, addr
, limit
);
97 orig_data
= RREG32(mmSMC_IND_DATA_0
);
98 extra_shift
= 8 * (4 - byte_count
);
100 while (byte_count
> 0) {
101 data
= (data
<< 8) + *src
++;
105 data
<<= extra_shift
;
106 data
|= (orig_data
& ~((~0UL) << extra_shift
));
108 result
= tonga_set_smc_sram_address(adev
, addr
, limit
);
112 WREG32(mmSMC_IND_DATA_0
, data
);
116 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
120 static int tonga_program_jump_on_start(struct amdgpu_device
*adev
)
122 static unsigned char data
[] = {0xE0, 0x00, 0x80, 0x40};
123 tonga_copy_bytes_to_smc(adev
, 0x0, data
, 4, sizeof(data
)+1);
128 static bool tonga_is_smc_ram_running(struct amdgpu_device
*adev
)
130 uint32_t val
= RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
);
131 val
= REG_GET_FIELD(val
, SMC_SYSCON_CLOCK_CNTL_0
, ck_disable
);
133 return ((0 == val
) && (0x20100 <= RREG32_SMC(ixSMC_PC_C
)));
136 static int wait_smu_response(struct amdgpu_device
*adev
)
141 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
142 val
= RREG32(mmSMC_RESP_0
);
143 if (REG_GET_FIELD(val
, SMC_RESP_0
, SMC_RESP
))
148 if (i
== adev
->usec_timeout
)
154 static int tonga_send_msg_to_smc_offset(struct amdgpu_device
*adev
)
156 if (wait_smu_response(adev
)) {
157 DRM_ERROR("Failed to send previous message\n");
161 WREG32(mmSMC_MSG_ARG_0
, 0x20000);
162 WREG32(mmSMC_MESSAGE_0
, PPSMC_MSG_Test
);
164 if (wait_smu_response(adev
)) {
165 DRM_ERROR("Failed to send message\n");
172 static int tonga_send_msg_to_smc(struct amdgpu_device
*adev
, PPSMC_Msg msg
)
174 if (!tonga_is_smc_ram_running(adev
))
179 if (wait_smu_response(adev
)) {
180 DRM_ERROR("Failed to send previous message\n");
184 WREG32(mmSMC_MESSAGE_0
, msg
);
186 if (wait_smu_response(adev
)) {
187 DRM_ERROR("Failed to send message\n");
194 static int tonga_send_msg_to_smc_without_waiting(struct amdgpu_device
*adev
,
197 if (wait_smu_response(adev
)) {
198 DRM_ERROR("Failed to send previous message\n");
202 WREG32(mmSMC_MESSAGE_0
, msg
);
207 static int tonga_send_msg_to_smc_with_parameter(struct amdgpu_device
*adev
,
211 if (!tonga_is_smc_ram_running(adev
))
214 if (wait_smu_response(adev
)) {
215 DRM_ERROR("Failed to send previous message\n");
219 WREG32(mmSMC_MSG_ARG_0
, parameter
);
221 return tonga_send_msg_to_smc(adev
, msg
);
224 static int tonga_send_msg_to_smc_with_parameter_without_waiting(
225 struct amdgpu_device
*adev
,
226 PPSMC_Msg msg
, uint32_t parameter
)
228 if (wait_smu_response(adev
)) {
229 DRM_ERROR("Failed to send previous message\n");
233 WREG32(mmSMC_MSG_ARG_0
, parameter
);
235 return tonga_send_msg_to_smc_without_waiting(adev
, msg
);
238 #if 0 /* not used yet */
239 static int tonga_wait_for_smc_inactive(struct amdgpu_device
*adev
)
244 if (!tonga_is_smc_ram_running(adev
))
247 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
248 val
= RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
);
249 if (REG_GET_FIELD(val
, SMC_SYSCON_CLOCK_CNTL_0
, cken
) == 0)
254 if (i
== adev
->usec_timeout
)
261 static int tonga_smu_upload_firmware_image(struct amdgpu_device
*adev
)
263 const struct smc_firmware_header_v1_0
*hdr
;
265 uint32_t ucode_start_address
;
275 /* Skip SMC ucode loading on SR-IOV capable boards.
276 * vbios does this for us in asic_init in that case.
278 if (adev
->virtualization
.supports_sr_iov
)
281 hdr
= (const struct smc_firmware_header_v1_0
*)adev
->pm
.fw
->data
;
282 amdgpu_ucode_print_smc_hdr(&hdr
->header
);
284 adev
->pm
.fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
285 ucode_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
);
286 ucode_start_address
= le32_to_cpu(hdr
->ucode_start_addr
);
287 src
= (const uint8_t *)
288 (adev
->pm
.fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
290 if (ucode_size
& 3) {
291 DRM_ERROR("SMC ucode is not 4 bytes aligned\n");
295 if (ucode_size
> TONGA_SMC_SIZE
) {
296 DRM_ERROR("SMC address is beyond the SMC RAM area\n");
300 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
301 WREG32(mmSMC_IND_INDEX_0
, ucode_start_address
);
303 val
= RREG32(mmSMC_IND_ACCESS_CNTL
);
304 val
= REG_SET_FIELD(val
, SMC_IND_ACCESS_CNTL
, AUTO_INCREMENT_IND_0
, 1);
305 WREG32(mmSMC_IND_ACCESS_CNTL
, val
);
307 byte_count
= ucode_size
;
308 data
= (uint32_t *)src
;
309 for (; byte_count
>= 4; data
++, byte_count
-= 4)
310 WREG32(mmSMC_IND_DATA_0
, data
[0]);
312 val
= RREG32(mmSMC_IND_ACCESS_CNTL
);
313 val
= REG_SET_FIELD(val
, SMC_IND_ACCESS_CNTL
, AUTO_INCREMENT_IND_0
, 0);
314 WREG32(mmSMC_IND_ACCESS_CNTL
, val
);
315 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
320 #if 0 /* not used yet */
321 static int tonga_read_smc_sram_dword(struct amdgpu_device
*adev
,
322 uint32_t smc_address
,
329 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
330 result
= tonga_set_smc_sram_address(adev
, smc_address
, limit
);
332 *value
= RREG32(mmSMC_IND_DATA_0
);
333 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
337 static int tonga_write_smc_sram_dword(struct amdgpu_device
*adev
,
338 uint32_t smc_address
,
345 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
346 result
= tonga_set_smc_sram_address(adev
, smc_address
, limit
);
348 WREG32(mmSMC_IND_DATA_0
, value
);
349 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
353 static int tonga_smu_stop_smc(struct amdgpu_device
*adev
)
355 uint32_t val
= RREG32_SMC(ixSMC_SYSCON_RESET_CNTL
);
356 val
= REG_SET_FIELD(val
, SMC_SYSCON_RESET_CNTL
, rst_reg
, 1);
357 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL
, val
);
359 val
= RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
);
360 val
= REG_SET_FIELD(val
, SMC_SYSCON_CLOCK_CNTL_0
, ck_disable
, 1);
361 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
, val
);
367 static enum AMDGPU_UCODE_ID
tonga_convert_fw_type(uint32_t fw_type
)
371 return AMDGPU_UCODE_ID_SDMA0
;
373 return AMDGPU_UCODE_ID_SDMA1
;
375 return AMDGPU_UCODE_ID_CP_CE
;
376 case UCODE_ID_CP_PFP
:
377 return AMDGPU_UCODE_ID_CP_PFP
;
379 return AMDGPU_UCODE_ID_CP_ME
;
380 case UCODE_ID_CP_MEC
:
381 case UCODE_ID_CP_MEC_JT1
:
382 return AMDGPU_UCODE_ID_CP_MEC1
;
383 case UCODE_ID_CP_MEC_JT2
:
384 return AMDGPU_UCODE_ID_CP_MEC2
;
386 return AMDGPU_UCODE_ID_RLC_G
;
388 DRM_ERROR("ucode type is out of range!\n");
389 return AMDGPU_UCODE_ID_MAXIMUM
;
393 static int tonga_smu_populate_single_firmware_entry(struct amdgpu_device
*adev
,
395 struct SMU_Entry
*entry
)
397 enum AMDGPU_UCODE_ID id
= tonga_convert_fw_type(fw_type
);
398 struct amdgpu_firmware_info
*ucode
= &adev
->firmware
.ucode
[id
];
399 const struct gfx_firmware_header_v1_0
*header
= NULL
;
403 if (ucode
->fw
== NULL
)
406 gpu_addr
= ucode
->mc_addr
;
407 header
= (const struct gfx_firmware_header_v1_0
*)ucode
->fw
->data
;
408 data_size
= le32_to_cpu(header
->header
.ucode_size_bytes
);
410 if ((fw_type
== UCODE_ID_CP_MEC_JT1
) ||
411 (fw_type
== UCODE_ID_CP_MEC_JT2
)) {
412 gpu_addr
+= le32_to_cpu(header
->jt_offset
) << 2;
413 data_size
= le32_to_cpu(header
->jt_size
) << 2;
416 entry
->version
= (uint16_t)le32_to_cpu(header
->header
.ucode_version
);
417 entry
->id
= (uint16_t)fw_type
;
418 entry
->image_addr_high
= upper_32_bits(gpu_addr
);
419 entry
->image_addr_low
= lower_32_bits(gpu_addr
);
420 entry
->meta_data_addr_high
= 0;
421 entry
->meta_data_addr_low
= 0;
422 entry
->data_size_byte
= data_size
;
423 entry
->num_register_entries
= 0;
425 if (fw_type
== UCODE_ID_RLC_G
)
433 static int tonga_smu_request_load_fw(struct amdgpu_device
*adev
)
435 struct tonga_smu_private_data
*private = (struct tonga_smu_private_data
*)adev
->smu
.priv
;
436 struct SMU_DRAMData_TOC
*toc
;
439 WREG32_SMC(ixSOFT_REGISTERS_TABLE_28
, 0);
441 tonga_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_SMU_DRAM_ADDR_HI
, private->smu_buffer_addr_high
);
442 tonga_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_SMU_DRAM_ADDR_LO
, private->smu_buffer_addr_low
);
444 toc
= (struct SMU_DRAMData_TOC
*)private->header
;
445 toc
->num_entries
= 0;
446 toc
->structure_version
= 1;
448 if (!adev
->firmware
.smu_load
)
451 if (tonga_smu_populate_single_firmware_entry(adev
, UCODE_ID_RLC_G
,
452 &toc
->entry
[toc
->num_entries
++])) {
453 DRM_ERROR("Failed to get firmware entry for RLC\n");
457 if (tonga_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_CE
,
458 &toc
->entry
[toc
->num_entries
++])) {
459 DRM_ERROR("Failed to get firmware entry for CE\n");
463 if (tonga_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_PFP
,
464 &toc
->entry
[toc
->num_entries
++])) {
465 DRM_ERROR("Failed to get firmware entry for PFP\n");
469 if (tonga_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_ME
,
470 &toc
->entry
[toc
->num_entries
++])) {
471 DRM_ERROR("Failed to get firmware entry for ME\n");
475 if (tonga_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_MEC
,
476 &toc
->entry
[toc
->num_entries
++])) {
477 DRM_ERROR("Failed to get firmware entry for MEC\n");
481 if (tonga_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_MEC_JT1
,
482 &toc
->entry
[toc
->num_entries
++])) {
483 DRM_ERROR("Failed to get firmware entry for MEC_JT1\n");
487 if (tonga_smu_populate_single_firmware_entry(adev
, UCODE_ID_CP_MEC_JT2
,
488 &toc
->entry
[toc
->num_entries
++])) {
489 DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
493 if (tonga_smu_populate_single_firmware_entry(adev
, UCODE_ID_SDMA0
,
494 &toc
->entry
[toc
->num_entries
++])) {
495 DRM_ERROR("Failed to get firmware entry for SDMA0\n");
499 if (tonga_smu_populate_single_firmware_entry(adev
, UCODE_ID_SDMA1
,
500 &toc
->entry
[toc
->num_entries
++])) {
501 DRM_ERROR("Failed to get firmware entry for SDMA1\n");
505 tonga_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_DRV_DRAM_ADDR_HI
, private->header_addr_high
);
506 tonga_send_msg_to_smc_with_parameter(adev
, PPSMC_MSG_DRV_DRAM_ADDR_LO
, private->header_addr_low
);
508 fw_to_load
= UCODE_ID_RLC_G_MASK
|
509 UCODE_ID_SDMA0_MASK
|
510 UCODE_ID_SDMA1_MASK
|
511 UCODE_ID_CP_CE_MASK
|
512 UCODE_ID_CP_ME_MASK
|
513 UCODE_ID_CP_PFP_MASK
|
514 UCODE_ID_CP_MEC_MASK
;
516 if (tonga_send_msg_to_smc_with_parameter_without_waiting(adev
, PPSMC_MSG_LoadUcodes
, fw_to_load
)) {
517 DRM_ERROR("Fail to request SMU load ucode\n");
524 static uint32_t tonga_smu_get_mask_for_fw_type(uint32_t fw_type
)
527 case AMDGPU_UCODE_ID_SDMA0
:
528 return UCODE_ID_SDMA0_MASK
;
529 case AMDGPU_UCODE_ID_SDMA1
:
530 return UCODE_ID_SDMA1_MASK
;
531 case AMDGPU_UCODE_ID_CP_CE
:
532 return UCODE_ID_CP_CE_MASK
;
533 case AMDGPU_UCODE_ID_CP_PFP
:
534 return UCODE_ID_CP_PFP_MASK
;
535 case AMDGPU_UCODE_ID_CP_ME
:
536 return UCODE_ID_CP_ME_MASK
;
537 case AMDGPU_UCODE_ID_CP_MEC1
:
538 return UCODE_ID_CP_MEC_MASK
;
539 case AMDGPU_UCODE_ID_CP_MEC2
:
540 return UCODE_ID_CP_MEC_MASK
;
541 case AMDGPU_UCODE_ID_RLC_G
:
542 return UCODE_ID_RLC_G_MASK
;
544 DRM_ERROR("ucode type is out of range!\n");
549 static int tonga_smu_check_fw_load_finish(struct amdgpu_device
*adev
,
552 uint32_t fw_mask
= tonga_smu_get_mask_for_fw_type(fw_type
);
555 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
556 if (fw_mask
== (RREG32_SMC(ixSOFT_REGISTERS_TABLE_28
) & fw_mask
))
561 if (i
== adev
->usec_timeout
) {
562 DRM_ERROR("check firmware loading failed\n");
569 static int tonga_smu_start_in_protection_mode(struct amdgpu_device
*adev
)
576 val
= RREG32_SMC(ixSMC_SYSCON_RESET_CNTL
);
577 val
= REG_SET_FIELD(val
, SMC_SYSCON_RESET_CNTL
, rst_reg
, 1);
578 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL
, val
);
580 result
= tonga_smu_upload_firmware_image(adev
);
585 WREG32_SMC(ixSMU_STATUS
, 0);
588 val
= RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
);
589 val
= REG_SET_FIELD(val
, SMC_SYSCON_CLOCK_CNTL_0
, ck_disable
, 0);
590 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
, val
);
592 /* De-assert reset */
593 val
= RREG32_SMC(ixSMC_SYSCON_RESET_CNTL
);
594 val
= REG_SET_FIELD(val
, SMC_SYSCON_RESET_CNTL
, rst_reg
, 0);
595 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL
, val
);
597 /* Set SMU Auto Start */
598 val
= RREG32_SMC(ixSMU_INPUT_DATA
);
599 val
= REG_SET_FIELD(val
, SMU_INPUT_DATA
, AUTO_START
, 1);
600 WREG32_SMC(ixSMU_INPUT_DATA
, val
);
602 /* Clear firmware interrupt enable flag */
603 WREG32_SMC(ixFIRMWARE_FLAGS
, 0);
605 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
606 val
= RREG32_SMC(ixRCU_UC_EVENTS
);
607 if (REG_GET_FIELD(val
, RCU_UC_EVENTS
, INTERRUPTS_ENABLED
))
612 if (i
== adev
->usec_timeout
) {
613 DRM_ERROR("Interrupt is not enabled by firmware\n");
617 /* Call Test SMU message with 0x20000 offset
618 * to trigger SMU start
620 tonga_send_msg_to_smc_offset(adev
);
622 /* Wait for done bit to be set */
623 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
624 val
= RREG32_SMC(ixSMU_STATUS
);
625 if (REG_GET_FIELD(val
, SMU_STATUS
, SMU_DONE
))
630 if (i
== adev
->usec_timeout
) {
631 DRM_ERROR("Timeout for SMU start\n");
635 /* Check pass/failed indicator */
636 val
= RREG32_SMC(ixSMU_STATUS
);
637 if (!REG_GET_FIELD(val
, SMU_STATUS
, SMU_PASS
)) {
638 DRM_ERROR("SMU Firmware start failed\n");
642 /* Wait for firmware to initialize */
643 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
644 val
= RREG32_SMC(ixFIRMWARE_FLAGS
);
645 if(REG_GET_FIELD(val
, FIRMWARE_FLAGS
, INTERRUPTS_ENABLED
))
650 if (i
== adev
->usec_timeout
) {
651 DRM_ERROR("SMU firmware initialization failed\n");
658 static int tonga_smu_start_in_non_protection_mode(struct amdgpu_device
*adev
)
663 /* wait for smc boot up */
664 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
665 val
= RREG32_SMC(ixRCU_UC_EVENTS
);
666 val
= REG_GET_FIELD(val
, RCU_UC_EVENTS
, boot_seq_done
);
672 if (i
== adev
->usec_timeout
) {
673 DRM_ERROR("SMC boot sequence is not completed\n");
677 /* Clear firmware interrupt enable flag */
678 WREG32_SMC(ixFIRMWARE_FLAGS
, 0);
681 val
= RREG32_SMC(ixSMC_SYSCON_RESET_CNTL
);
682 val
= REG_SET_FIELD(val
, SMC_SYSCON_RESET_CNTL
, rst_reg
, 1);
683 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL
, val
);
685 result
= tonga_smu_upload_firmware_image(adev
);
689 /* Set smc instruct start point at 0x0 */
690 tonga_program_jump_on_start(adev
);
693 val
= RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
);
694 val
= REG_SET_FIELD(val
, SMC_SYSCON_CLOCK_CNTL_0
, ck_disable
, 0);
695 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0
, val
);
697 /* De-assert reset */
698 val
= RREG32_SMC(ixSMC_SYSCON_RESET_CNTL
);
699 val
= REG_SET_FIELD(val
, SMC_SYSCON_RESET_CNTL
, rst_reg
, 0);
700 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL
, val
);
702 /* Wait for firmware to initialize */
703 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
704 val
= RREG32_SMC(ixFIRMWARE_FLAGS
);
705 if (REG_GET_FIELD(val
, FIRMWARE_FLAGS
, INTERRUPTS_ENABLED
))
710 if (i
== adev
->usec_timeout
) {
711 DRM_ERROR("Timeout for SMC firmware initialization\n");
718 int tonga_smu_start(struct amdgpu_device
*adev
)
723 if (!tonga_is_smc_ram_running(adev
)) {
724 val
= RREG32_SMC(ixSMU_FIRMWARE
);
725 if (!REG_GET_FIELD(val
, SMU_FIRMWARE
, SMU_MODE
)) {
726 result
= tonga_smu_start_in_non_protection_mode(adev
);
730 result
= tonga_smu_start_in_protection_mode(adev
);
736 return tonga_smu_request_load_fw(adev
);
739 static const struct amdgpu_smumgr_funcs tonga_smumgr_funcs
= {
740 .check_fw_load_finish
= tonga_smu_check_fw_load_finish
,
741 .request_smu_load_fw
= NULL
,
742 .request_smu_specific_fw
= NULL
,
745 int tonga_smu_init(struct amdgpu_device
*adev
)
747 struct tonga_smu_private_data
*private;
748 uint32_t image_size
= ((sizeof(struct SMU_DRAMData_TOC
) / 4096) + 1) * 4096;
749 uint32_t smu_internal_buffer_size
= 200*4096;
750 struct amdgpu_bo
**toc_buf
= &adev
->smu
.toc_buf
;
751 struct amdgpu_bo
**smu_buf
= &adev
->smu
.smu_buf
;
757 private = kzalloc(sizeof(struct tonga_smu_private_data
), GFP_KERNEL
);
761 /* allocate firmware buffers */
762 if (adev
->firmware
.smu_load
)
763 amdgpu_ucode_init_bo(adev
);
765 adev
->smu
.priv
= private;
766 adev
->smu
.fw_flags
= 0;
768 /* Allocate FW image data structure and header buffer */
769 ret
= amdgpu_bo_create(adev
, image_size
, PAGE_SIZE
,
770 true, AMDGPU_GEM_DOMAIN_VRAM
,
771 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
772 NULL
, NULL
, toc_buf
);
774 DRM_ERROR("Failed to allocate memory for TOC buffer\n");
778 /* Allocate buffer for SMU internal buffer */
779 ret
= amdgpu_bo_create(adev
, smu_internal_buffer_size
, PAGE_SIZE
,
780 true, AMDGPU_GEM_DOMAIN_VRAM
,
781 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
782 NULL
, NULL
, smu_buf
);
784 DRM_ERROR("Failed to allocate memory for SMU internal buffer\n");
788 /* Retrieve GPU address for header buffer and internal buffer */
789 ret
= amdgpu_bo_reserve(adev
->smu
.toc_buf
, false);
791 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
792 DRM_ERROR("Failed to reserve the TOC buffer\n");
796 ret
= amdgpu_bo_pin(adev
->smu
.toc_buf
, AMDGPU_GEM_DOMAIN_VRAM
, &mc_addr
);
798 amdgpu_bo_unreserve(adev
->smu
.toc_buf
);
799 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
800 DRM_ERROR("Failed to pin the TOC buffer\n");
804 ret
= amdgpu_bo_kmap(*toc_buf
, &toc_buf_ptr
);
806 amdgpu_bo_unreserve(adev
->smu
.toc_buf
);
807 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
808 DRM_ERROR("Failed to map the TOC buffer\n");
812 amdgpu_bo_unreserve(adev
->smu
.toc_buf
);
813 private->header_addr_low
= lower_32_bits(mc_addr
);
814 private->header_addr_high
= upper_32_bits(mc_addr
);
815 private->header
= toc_buf_ptr
;
817 ret
= amdgpu_bo_reserve(adev
->smu
.smu_buf
, false);
819 amdgpu_bo_unref(&adev
->smu
.smu_buf
);
820 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
821 DRM_ERROR("Failed to reserve the SMU internal buffer\n");
825 ret
= amdgpu_bo_pin(adev
->smu
.smu_buf
, AMDGPU_GEM_DOMAIN_VRAM
, &mc_addr
);
827 amdgpu_bo_unreserve(adev
->smu
.smu_buf
);
828 amdgpu_bo_unref(&adev
->smu
.smu_buf
);
829 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
830 DRM_ERROR("Failed to pin the SMU internal buffer\n");
834 ret
= amdgpu_bo_kmap(*smu_buf
, &smu_buf_ptr
);
836 amdgpu_bo_unreserve(adev
->smu
.smu_buf
);
837 amdgpu_bo_unref(&adev
->smu
.smu_buf
);
838 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
839 DRM_ERROR("Failed to map the SMU internal buffer\n");
843 amdgpu_bo_unreserve(adev
->smu
.smu_buf
);
844 private->smu_buffer_addr_low
= lower_32_bits(mc_addr
);
845 private->smu_buffer_addr_high
= upper_32_bits(mc_addr
);
847 adev
->smu
.smumgr_funcs
= &tonga_smumgr_funcs
;
852 int tonga_smu_fini(struct amdgpu_device
*adev
)
854 amdgpu_bo_unref(&adev
->smu
.toc_buf
);
855 amdgpu_bo_unref(&adev
->smu
.smu_buf
);
856 kfree(adev
->smu
.priv
);
857 adev
->smu
.priv
= NULL
;
858 if (adev
->firmware
.fw_buf
)
859 amdgpu_ucode_fini_bo(adev
);