drivers/gpu/drm/amd/amdgpu/tonga_smc.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "drmP.h"
  26 #include "amdgpu.h"
  27 #include "tonga_ppsmc.h"
  28 #include "tonga_smum.h"
  29 #include "smu_ucode_xfer_vi.h"
  30 #include "amdgpu_ucode.h"
  31
  32 #include "smu/smu_7_1_2_d.h"
  33 #include "smu/smu_7_1_2_sh_mask.h"
  34
  35 #define TONGA_SMC_SIZE 0x20000
  36
  37 static int tonga_set_smc_sram_address(struct amdgpu_device *adev, uint32_t smc_address, uint32_t limit)
  38 {
  39         uint32_t val;
  40
  41         if (smc_address & 3)
  42                 return -EINVAL;
  43
  44         if ((smc_address + 3) > limit)
  45                 return -EINVAL;
  46
  47         WREG32(mmSMC_IND_INDEX_0, smc_address);
  48
  49         val = RREG32(mmSMC_IND_ACCESS_CNTL);
  50         val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
  51         WREG32(mmSMC_IND_ACCESS_CNTL, val);
  52
  53         return 0;
  54 }
  55
  56 static int tonga_copy_bytes_to_smc(struct amdgpu_device *adev, uint32_t smc_start_address, const uint8_t *src, uint32_t byte_count, uint32_t limit)
  57 {
  58         uint32_t addr;
  59         uint32_t data, orig_data;
  60         int result = 0;
  61         uint32_t extra_shift;
  62         unsigned long flags;
  63
  64         if (smc_start_address & 3)
  65                 return -EINVAL;
  66
  67         if ((smc_start_address + byte_count) > limit)
  68                 return -EINVAL;
  69
  70         addr = smc_start_address;
  71
  72         spin_lock_irqsave(&adev->smc_idx_lock, flags);
  73         while (byte_count >= 4) {
  74                 /* Bytes are written into the SMC addres space with the MSB first */
  75                 data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
  76
  77                 result = tonga_set_smc_sram_address(adev, addr, limit);
  78
  79                 if (result)
  80                         goto out;
  81
  82                 WREG32(mmSMC_IND_DATA_0, data);
  83
  84                 src += 4;
  85                 byte_count -= 4;
  86                 addr += 4;
  87         }
  88
  89         if (0 != byte_count) {
  90                 /* Now write odd bytes left, do a read modify write cycle */
  91                 data = 0;
  92
  93                 result = tonga_set_smc_sram_address(adev, addr, limit);
  94                 if (result)
  95                         goto out;
  96
  97                 orig_data = RREG32(mmSMC_IND_DATA_0);
  98                 extra_shift = 8 * (4 - byte_count);
  99
 100                 while (byte_count > 0) {
 101                         data = (data << 8) + *src++;
 102                         byte_count--;
 103                 }
 104
 105                 data <<= extra_shift;
 106                 data |= (orig_data & ~((~0UL) << extra_shift));
 107
 108                 result = tonga_set_smc_sram_address(adev, addr, limit);
 109                 if (result)
 110                         goto out;
 111
 112                 WREG32(mmSMC_IND_DATA_0, data);
 113         }
 114
 115 out:
 116         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 117         return result;
 118 }
 119
 120 static int tonga_program_jump_on_start(struct amdgpu_device *adev)
 121 {
 122         static unsigned char data[] = {0xE0, 0x00, 0x80, 0x40};
 123         tonga_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
 124
 125         return 0;
 126 }
 127
 128 static bool tonga_is_smc_ram_running(struct amdgpu_device *adev)
 129 {
 130         uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
 131         val = REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable);
 132
 133         return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C)));
 134 }
 135
 136 static int wait_smu_response(struct amdgpu_device *adev)
 137 {
 138         int i;
 139         uint32_t val;
 140
 141         for (i = 0; i < adev->usec_timeout; i++) {
 142                 val = RREG32(mmSMC_RESP_0);
 143                 if (REG_GET_FIELD(val, SMC_RESP_0, SMC_RESP))
 144                         break;
 145                 udelay(1);
 146         }
 147
 148         if (i == adev->usec_timeout)
 149                 return -EINVAL;
 150
 151         return 0;
 152 }
 153
 154 static int tonga_send_msg_to_smc_offset(struct amdgpu_device *adev)
 155 {
 156         if (wait_smu_response(adev)) {
 157                 DRM_ERROR("Failed to send previous message\n");
 158                 return -EINVAL;
 159         }
 160
 161         WREG32(mmSMC_MSG_ARG_0, 0x20000);
 162         WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_Test);
 163
 164         if (wait_smu_response(adev)) {
 165                 DRM_ERROR("Failed to send message\n");
 166                 return -EINVAL;
 167         }
 168
 169         return 0;
 170 }
 171
 172 static int tonga_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)
 173 {
 174         if (!tonga_is_smc_ram_running(adev))
 175         {
 176                 return -EINVAL;
 177         }
 178
 179         if (wait_smu_response(adev)) {
 180                 DRM_ERROR("Failed to send previous message\n");
 181                 return -EINVAL;
 182         }
 183
 184         WREG32(mmSMC_MESSAGE_0, msg);
 185
 186         if (wait_smu_response(adev)) {
 187                 DRM_ERROR("Failed to send message\n");
 188                 return -EINVAL;
 189         }
 190
 191         return 0;
 192 }
 193
 194 static int tonga_send_msg_to_smc_without_waiting(struct amdgpu_device *adev,
 195                                                 PPSMC_Msg msg)
 196 {
 197         if (wait_smu_response(adev)) {
 198                 DRM_ERROR("Failed to send previous message\n");
 199                 return -EINVAL;
 200         }
 201
 202         WREG32(mmSMC_MESSAGE_0, msg);
 203
 204         return 0;
 205 }
 206
 207 static int tonga_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
 208                                                 PPSMC_Msg msg,
 209                                                 uint32_t parameter)
 210 {
 211         if (!tonga_is_smc_ram_running(adev))
 212                 return -EINVAL;
 213
 214         if (wait_smu_response(adev)) {
 215                 DRM_ERROR("Failed to send previous message\n");
 216                 return -EINVAL;
 217         }
 218
 219         WREG32(mmSMC_MSG_ARG_0, parameter);
 220
 221         return tonga_send_msg_to_smc(adev, msg);
 222 }
 223
 224 static int tonga_send_msg_to_smc_with_parameter_without_waiting(
 225                                         struct amdgpu_device *adev,
 226                                         PPSMC_Msg msg, uint32_t parameter)
 227 {
 228         if (wait_smu_response(adev)) {
 229                 DRM_ERROR("Failed to send previous message\n");
 230                 return -EINVAL;
 231         }
 232
 233         WREG32(mmSMC_MSG_ARG_0, parameter);
 234
 235         return tonga_send_msg_to_smc_without_waiting(adev, msg);
 236 }
 237
 238 #if 0 /* not used yet */
 239 static int tonga_wait_for_smc_inactive(struct amdgpu_device *adev)
 240 {
 241         int i;
 242         uint32_t val;
 243
 244         if (!tonga_is_smc_ram_running(adev))
 245                 return -EINVAL;
 246
 247         for (i = 0; i < adev->usec_timeout; i++) {
 248                 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
 249                 if (REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, cken) == 0)
 250                         break;
 251                 udelay(1);
 252         }
 253
 254         if (i == adev->usec_timeout)
 255                 return -EINVAL;
 256
 257         return 0;
 258 }
 259 #endif
 260
 261 static int tonga_smu_upload_firmware_image(struct amdgpu_device *adev)
 262 {
 263         const struct smc_firmware_header_v1_0 *hdr;
 264         uint32_t ucode_size;
 265         uint32_t ucode_start_address;
 266         const uint8_t *src;
 267         uint32_t val;
 268         uint32_t byte_count;
 269         uint32_t *data;
 270         unsigned long flags;
 271
 272         if (!adev->pm.fw)
 273                 return -EINVAL;
 274
 275         /* Skip SMC ucode loading on SR-IOV capable boards.
 276          * vbios does this for us in asic_init in that case.
 277          */
 278         if (adev->virtualization.supports_sr_iov)
 279                 return 0;
 280
 281         hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
 282         amdgpu_ucode_print_smc_hdr(&hdr->header);
 283
 284         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 285         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
 286         ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
 287         src = (const uint8_t *)
 288                 (adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 289
 290         if (ucode_size & 3) {
 291                 DRM_ERROR("SMC ucode is not 4 bytes aligned\n");
 292                 return -EINVAL;
 293         }
 294
 295         if (ucode_size > TONGA_SMC_SIZE) {
 296                 DRM_ERROR("SMC address is beyond the SMC RAM area\n");
 297                 return -EINVAL;
 298         }
 299
 300         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 301         WREG32(mmSMC_IND_INDEX_0, ucode_start_address);
 302
 303         val = RREG32(mmSMC_IND_ACCESS_CNTL);
 304         val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
 305         WREG32(mmSMC_IND_ACCESS_CNTL, val);
 306
 307         byte_count = ucode_size;
 308         data = (uint32_t *)src;
 309         for (; byte_count >= 4; data++, byte_count -= 4)
 310                 WREG32(mmSMC_IND_DATA_0, data[0]);
 311
 312         val = RREG32(mmSMC_IND_ACCESS_CNTL);
 313         val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
 314         WREG32(mmSMC_IND_ACCESS_CNTL, val);
 315         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 316
 317         return 0;
 318 }
 319
 320 #if 0 /* not used yet */
 321 static int tonga_read_smc_sram_dword(struct amdgpu_device *adev,
 322                                 uint32_t smc_address,
 323                                 uint32_t *value,
 324                                 uint32_t limit)
 325 {
 326         int result;
 327         unsigned long flags;
 328
 329         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 330         result = tonga_set_smc_sram_address(adev, smc_address, limit);
 331         if (result == 0)
 332                 *value = RREG32(mmSMC_IND_DATA_0);
 333         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 334         return result;
 335 }
 336
 337 static int tonga_write_smc_sram_dword(struct amdgpu_device *adev,
 338                                 uint32_t smc_address,
 339                                 uint32_t value,
 340                                 uint32_t limit)
 341 {
 342         int result;
 343         unsigned long flags;
 344
 345         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 346         result = tonga_set_smc_sram_address(adev, smc_address, limit);
 347         if (result == 0)
 348                 WREG32(mmSMC_IND_DATA_0, value);
 349         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 350         return result;
 351 }
 352
 353 static int tonga_smu_stop_smc(struct amdgpu_device *adev)
 354 {
 355         uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
 356         val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 357         WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
 358
 359         val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
 360         val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
 361         WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
 362
 363         return 0;
 364 }
 365 #endif
 366
 367 static enum AMDGPU_UCODE_ID tonga_convert_fw_type(uint32_t fw_type)
 368 {
 369         switch (fw_type) {
 370                 case UCODE_ID_SDMA0:
 371                         return AMDGPU_UCODE_ID_SDMA0;
 372                 case UCODE_ID_SDMA1:
 373                         return AMDGPU_UCODE_ID_SDMA1;
 374                 case UCODE_ID_CP_CE:
 375                         return AMDGPU_UCODE_ID_CP_CE;
 376                 case UCODE_ID_CP_PFP:
 377                         return AMDGPU_UCODE_ID_CP_PFP;
 378                 case UCODE_ID_CP_ME:
 379                         return AMDGPU_UCODE_ID_CP_ME;
 380                 case UCODE_ID_CP_MEC:
 381                 case UCODE_ID_CP_MEC_JT1:
 382                         return AMDGPU_UCODE_ID_CP_MEC1;
 383                 case UCODE_ID_CP_MEC_JT2:
 384                         return AMDGPU_UCODE_ID_CP_MEC2;
 385                 case UCODE_ID_RLC_G:
 386                         return AMDGPU_UCODE_ID_RLC_G;
 387                 default:
 388                         DRM_ERROR("ucode type is out of range!\n");
 389                         return AMDGPU_UCODE_ID_MAXIMUM;
 390         }
 391 }
 392
 393 static int tonga_smu_populate_single_firmware_entry(struct amdgpu_device *adev,
 394                                                 uint32_t fw_type,
 395                                                 struct SMU_Entry *entry)
 396 {
 397         enum AMDGPU_UCODE_ID id = tonga_convert_fw_type(fw_type);
 398         struct amdgpu_firmware_info *ucode = &adev->firmware.ucode[id];
 399         const struct gfx_firmware_header_v1_0 *header = NULL;
 400         uint64_t gpu_addr;
 401         uint32_t data_size;
 402
 403         if (ucode->fw == NULL)
 404                 return -EINVAL;
 405
 406         gpu_addr  = ucode->mc_addr;
 407         header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 408         data_size = le32_to_cpu(header->header.ucode_size_bytes);
 409
 410         if ((fw_type == UCODE_ID_CP_MEC_JT1) ||
 411                 (fw_type == UCODE_ID_CP_MEC_JT2)) {
 412                 gpu_addr += le32_to_cpu(header->jt_offset) << 2;
 413                 data_size = le32_to_cpu(header->jt_size) << 2;
 414         }
 415
 416         entry->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
 417         entry->id = (uint16_t)fw_type;
 418         entry->image_addr_high = upper_32_bits(gpu_addr);
 419         entry->image_addr_low = lower_32_bits(gpu_addr);
 420         entry->meta_data_addr_high = 0;
 421         entry->meta_data_addr_low = 0;
 422         entry->data_size_byte = data_size;
 423         entry->num_register_entries = 0;
 424
 425         if (fw_type == UCODE_ID_RLC_G)
 426                 entry->flags = 1;
 427         else
 428                 entry->flags = 0;
 429
 430         return 0;
 431 }
 432
 433 static int tonga_smu_request_load_fw(struct amdgpu_device *adev)
 434 {
 435         struct tonga_smu_private_data *private = (struct tonga_smu_private_data *)adev->smu.priv;
 436         struct SMU_DRAMData_TOC *toc;
 437         uint32_t fw_to_load;
 438
 439         WREG32_SMC(ixSOFT_REGISTERS_TABLE_28, 0);
 440
 441         tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_HI, private->smu_buffer_addr_high);
 442         tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_LO, private->smu_buffer_addr_low);
 443
 444         toc = (struct SMU_DRAMData_TOC *)private->header;
 445         toc->num_entries = 0;
 446         toc->structure_version = 1;
 447
 448         if (!adev->firmware.smu_load)
 449                 return 0;
 450
 451         if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_RLC_G,
 452                         &toc->entry[toc->num_entries++])) {
 453                 DRM_ERROR("Failed to get firmware entry for RLC\n");
 454                 return -EINVAL;
 455         }
 456
 457         if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_CE,
 458                         &toc->entry[toc->num_entries++])) {
 459                 DRM_ERROR("Failed to get firmware entry for CE\n");
 460                 return -EINVAL;
 461         }
 462
 463         if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_PFP,
 464                         &toc->entry[toc->num_entries++])) {
 465                 DRM_ERROR("Failed to get firmware entry for PFP\n");
 466                 return -EINVAL;
 467         }
 468
 469         if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_ME,
 470                         &toc->entry[toc->num_entries++])) {
 471                 DRM_ERROR("Failed to get firmware entry for ME\n");
 472                 return -EINVAL;
 473         }
 474
 475         if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC,
 476                         &toc->entry[toc->num_entries++])) {
 477                 DRM_ERROR("Failed to get firmware entry for MEC\n");
 478                 return -EINVAL;
 479         }
 480
 481         if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT1,
 482                         &toc->entry[toc->num_entries++])) {
 483                 DRM_ERROR("Failed to get firmware entry for MEC_JT1\n");
 484                 return -EINVAL;
 485         }
 486
 487         if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,
 488                         &toc->entry[toc->num_entries++])) {
 489                 DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
 490                 return -EINVAL;
 491         }
 492
 493         if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,
 494                         &toc->entry[toc->num_entries++])) {
 495                 DRM_ERROR("Failed to get firmware entry for SDMA0\n");
 496                 return -EINVAL;
 497         }
 498
 499         if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA1,
 500                         &toc->entry[toc->num_entries++])) {
 501                 DRM_ERROR("Failed to get firmware entry for SDMA1\n");
 502                 return -EINVAL;
 503         }
 504
 505         tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_HI, private->header_addr_high);
 506         tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_LO, private->header_addr_low);
 507
 508         fw_to_load = UCODE_ID_RLC_G_MASK |
 509                         UCODE_ID_SDMA0_MASK |
 510                         UCODE_ID_SDMA1_MASK |
 511                         UCODE_ID_CP_CE_MASK |
 512                         UCODE_ID_CP_ME_MASK |
 513                         UCODE_ID_CP_PFP_MASK |
 514                         UCODE_ID_CP_MEC_MASK;
 515
 516         if (tonga_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {
 517                 DRM_ERROR("Fail to request SMU load ucode\n");
 518                 return -EINVAL;
 519         }
 520
 521         return 0;
 522 }
 523
 524 static uint32_t tonga_smu_get_mask_for_fw_type(uint32_t fw_type)
 525 {
 526         switch (fw_type) {
 527                 case AMDGPU_UCODE_ID_SDMA0:
 528                         return UCODE_ID_SDMA0_MASK;
 529                 case AMDGPU_UCODE_ID_SDMA1:
 530                         return UCODE_ID_SDMA1_MASK;
 531                 case AMDGPU_UCODE_ID_CP_CE:
 532                         return UCODE_ID_CP_CE_MASK;
 533                 case AMDGPU_UCODE_ID_CP_PFP:
 534                         return UCODE_ID_CP_PFP_MASK;
 535                 case AMDGPU_UCODE_ID_CP_ME:
 536                         return UCODE_ID_CP_ME_MASK;
 537                 case AMDGPU_UCODE_ID_CP_MEC1:
 538                         return UCODE_ID_CP_MEC_MASK;
 539                 case AMDGPU_UCODE_ID_CP_MEC2:
 540                         return UCODE_ID_CP_MEC_MASK;
 541                 case AMDGPU_UCODE_ID_RLC_G:
 542                         return UCODE_ID_RLC_G_MASK;
 543                 default:
 544                         DRM_ERROR("ucode type is out of range!\n");
 545                         return 0;
 546         }
 547 }
 548
 549 static int tonga_smu_check_fw_load_finish(struct amdgpu_device *adev,
 550                                         uint32_t fw_type)
 551 {
 552         uint32_t fw_mask = tonga_smu_get_mask_for_fw_type(fw_type);
 553         int i;
 554
 555         for (i = 0; i < adev->usec_timeout; i++) {
 556                 if (fw_mask == (RREG32_SMC(ixSOFT_REGISTERS_TABLE_28) & fw_mask))
 557                         break;
 558                 udelay(1);
 559         }
 560
 561         if (i == adev->usec_timeout) {
 562                 DRM_ERROR("check firmware loading failed\n");
 563                 return -EINVAL;
 564         }
 565
 566         return 0;
 567 }
 568
 569 static int tonga_smu_start_in_protection_mode(struct amdgpu_device *adev)
 570 {
 571         int result;
 572         uint32_t val;
 573         int i;
 574
 575         /* Assert reset */
 576         val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
 577         val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 578         WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
 579
 580         result = tonga_smu_upload_firmware_image(adev);
 581         if (result)
 582                 return result;
 583
 584         /* Clear status */
 585         WREG32_SMC(ixSMU_STATUS, 0);
 586
 587         /* Enable clock */
 588         val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
 589         val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 590         WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
 591
 592         /* De-assert reset */
 593         val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
 594         val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 595         WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
 596
 597         /* Set SMU Auto Start */
 598         val = RREG32_SMC(ixSMU_INPUT_DATA);
 599         val = REG_SET_FIELD(val, SMU_INPUT_DATA, AUTO_START, 1);
 600         WREG32_SMC(ixSMU_INPUT_DATA, val);
 601
 602         /* Clear firmware interrupt enable flag */
 603         WREG32_SMC(ixFIRMWARE_FLAGS, 0);
 604
 605         for (i = 0; i < adev->usec_timeout; i++) {
 606                 val = RREG32_SMC(ixRCU_UC_EVENTS);
 607                 if (REG_GET_FIELD(val, RCU_UC_EVENTS, INTERRUPTS_ENABLED))
 608                         break;
 609                 udelay(1);
 610         }
 611
 612         if (i == adev->usec_timeout) {
 613                 DRM_ERROR("Interrupt is not enabled by firmware\n");
 614                 return -EINVAL;
 615         }
 616
 617         /* Call Test SMU message with 0x20000 offset
 618          * to trigger SMU start
 619          */
 620         tonga_send_msg_to_smc_offset(adev);
 621
 622         /* Wait for done bit to be set */
 623         for (i = 0; i < adev->usec_timeout; i++) {
 624                 val = RREG32_SMC(ixSMU_STATUS);
 625                 if (REG_GET_FIELD(val, SMU_STATUS, SMU_DONE))
 626                         break;
 627                 udelay(1);
 628         }
 629
 630         if (i == adev->usec_timeout) {
 631                 DRM_ERROR("Timeout for SMU start\n");
 632                 return -EINVAL;
 633         }
 634
 635         /* Check pass/failed indicator */
 636         val = RREG32_SMC(ixSMU_STATUS);
 637         if (!REG_GET_FIELD(val, SMU_STATUS, SMU_PASS)) {
 638                 DRM_ERROR("SMU Firmware start failed\n");
 639                 return -EINVAL;
 640         }
 641
 642         /* Wait for firmware to initialize */
 643         for (i = 0; i < adev->usec_timeout; i++) {
 644                 val = RREG32_SMC(ixFIRMWARE_FLAGS);
 645                 if(REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED))
 646                         break;
 647                 udelay(1);
 648         }
 649
 650         if (i == adev->usec_timeout) {
 651                 DRM_ERROR("SMU firmware initialization failed\n");
 652                 return -EINVAL;
 653         }
 654
 655         return 0;
 656 }
 657
 658 static int tonga_smu_start_in_non_protection_mode(struct amdgpu_device *adev)
 659 {
 660         int i, result;
 661         uint32_t val;
 662
 663         /* wait for smc boot up */
 664         for (i = 0; i < adev->usec_timeout; i++) {
 665                 val = RREG32_SMC(ixRCU_UC_EVENTS);
 666                 val = REG_GET_FIELD(val, RCU_UC_EVENTS, boot_seq_done);
 667                 if (val)
 668                         break;
 669                 udelay(1);
 670         }
 671
 672         if (i == adev->usec_timeout) {
 673                 DRM_ERROR("SMC boot sequence is not completed\n");
 674                 return -EINVAL;
 675         }
 676
 677         /* Clear firmware interrupt enable flag */
 678         WREG32_SMC(ixFIRMWARE_FLAGS, 0);
 679
 680         /* Assert reset */
 681         val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
 682         val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 683         WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
 684
 685         result = tonga_smu_upload_firmware_image(adev);
 686         if (result)
 687                 return result;
 688
 689         /* Set smc instruct start point at 0x0 */
 690         tonga_program_jump_on_start(adev);
 691
 692         /* Enable clock */
 693         val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
 694         val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 695         WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
 696
 697         /* De-assert reset */
 698         val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
 699         val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 700         WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
 701
 702         /* Wait for firmware to initialize */
 703         for (i = 0; i < adev->usec_timeout; i++) {
 704                 val = RREG32_SMC(ixFIRMWARE_FLAGS);
 705                 if (REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED))
 706                         break;
 707                 udelay(1);
 708         }
 709
 710         if (i == adev->usec_timeout) {
 711                 DRM_ERROR("Timeout for SMC firmware initialization\n");
 712                 return -EINVAL;
 713         }
 714
 715         return 0;
 716 }
 717
 718 int tonga_smu_start(struct amdgpu_device *adev)
 719 {
 720         int result;
 721         uint32_t val;
 722
 723         if (!tonga_is_smc_ram_running(adev)) {
 724                 val = RREG32_SMC(ixSMU_FIRMWARE);
 725                 if (!REG_GET_FIELD(val, SMU_FIRMWARE, SMU_MODE)) {
 726                         result = tonga_smu_start_in_non_protection_mode(adev);
 727                         if (result)
 728                                 return result;
 729                 } else {
 730                         result = tonga_smu_start_in_protection_mode(adev);
 731                         if (result)
 732                                 return result;
 733                 }
 734         }
 735
 736         return tonga_smu_request_load_fw(adev);
 737 }
 738
 739 static const struct amdgpu_smumgr_funcs tonga_smumgr_funcs = {
 740         .check_fw_load_finish = tonga_smu_check_fw_load_finish,
 741         .request_smu_load_fw = NULL,
 742         .request_smu_specific_fw = NULL,
 743 };
 744
 745 int tonga_smu_init(struct amdgpu_device *adev)
 746 {
 747         struct tonga_smu_private_data *private;
 748         uint32_t image_size = ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
 749         uint32_t smu_internal_buffer_size = 200*4096;
 750         struct amdgpu_bo **toc_buf = &adev->smu.toc_buf;
 751         struct amdgpu_bo **smu_buf = &adev->smu.smu_buf;
 752         uint64_t mc_addr;
 753         void *toc_buf_ptr;
 754         void *smu_buf_ptr;
 755         int ret;
 756
 757         private = kzalloc(sizeof(struct tonga_smu_private_data), GFP_KERNEL);
 758         if (NULL == private)
 759                 return -ENOMEM;
 760
 761         /* allocate firmware buffers */
 762         if (adev->firmware.smu_load)
 763                 amdgpu_ucode_init_bo(adev);
 764
 765         adev->smu.priv = private;
 766         adev->smu.fw_flags = 0;
 767
 768         /* Allocate FW image data structure and header buffer */
 769         ret = amdgpu_bo_create(adev, image_size, PAGE_SIZE,
 770                                true, AMDGPU_GEM_DOMAIN_VRAM,
 771                                AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 772                                NULL, NULL, toc_buf);
 773         if (ret) {
 774                 DRM_ERROR("Failed to allocate memory for TOC buffer\n");
 775                 return -ENOMEM;
 776         }
 777
 778         /* Allocate buffer for SMU internal buffer */
 779         ret = amdgpu_bo_create(adev, smu_internal_buffer_size, PAGE_SIZE,
 780                                true, AMDGPU_GEM_DOMAIN_VRAM,
 781                                AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 782                                NULL, NULL, smu_buf);
 783         if (ret) {
 784                 DRM_ERROR("Failed to allocate memory for SMU internal buffer\n");
 785                 return -ENOMEM;
 786         }
 787
 788         /* Retrieve GPU address for header buffer and internal buffer */
 789         ret = amdgpu_bo_reserve(adev->smu.toc_buf, false);
 790         if (ret) {
 791                 amdgpu_bo_unref(&adev->smu.toc_buf);
 792                 DRM_ERROR("Failed to reserve the TOC buffer\n");
 793                 return -EINVAL;
 794         }
 795
 796         ret = amdgpu_bo_pin(adev->smu.toc_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr);
 797         if (ret) {
 798                 amdgpu_bo_unreserve(adev->smu.toc_buf);
 799                 amdgpu_bo_unref(&adev->smu.toc_buf);
 800                 DRM_ERROR("Failed to pin the TOC buffer\n");
 801                 return -EINVAL;
 802         }
 803
 804         ret = amdgpu_bo_kmap(*toc_buf, &toc_buf_ptr);
 805         if (ret) {
 806                 amdgpu_bo_unreserve(adev->smu.toc_buf);
 807                 amdgpu_bo_unref(&adev->smu.toc_buf);
 808                 DRM_ERROR("Failed to map the TOC buffer\n");
 809                 return -EINVAL;
 810         }
 811
 812         amdgpu_bo_unreserve(adev->smu.toc_buf);
 813         private->header_addr_low = lower_32_bits(mc_addr);
 814         private->header_addr_high = upper_32_bits(mc_addr);
 815         private->header = toc_buf_ptr;
 816
 817         ret = amdgpu_bo_reserve(adev->smu.smu_buf, false);
 818         if (ret) {
 819                 amdgpu_bo_unref(&adev->smu.smu_buf);
 820                 amdgpu_bo_unref(&adev->smu.toc_buf);
 821                 DRM_ERROR("Failed to reserve the SMU internal buffer\n");
 822                 return -EINVAL;
 823         }
 824
 825         ret = amdgpu_bo_pin(adev->smu.smu_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr);
 826         if (ret) {
 827                 amdgpu_bo_unreserve(adev->smu.smu_buf);
 828                 amdgpu_bo_unref(&adev->smu.smu_buf);
 829                 amdgpu_bo_unref(&adev->smu.toc_buf);
 830                 DRM_ERROR("Failed to pin the SMU internal buffer\n");
 831                 return -EINVAL;
 832         }
 833
 834         ret = amdgpu_bo_kmap(*smu_buf, &smu_buf_ptr);
 835         if (ret) {
 836                 amdgpu_bo_unreserve(adev->smu.smu_buf);
 837                 amdgpu_bo_unref(&adev->smu.smu_buf);
 838                 amdgpu_bo_unref(&adev->smu.toc_buf);
 839                 DRM_ERROR("Failed to map the SMU internal buffer\n");
 840                 return -EINVAL;
 841         }
 842
 843         amdgpu_bo_unreserve(adev->smu.smu_buf);
 844         private->smu_buffer_addr_low = lower_32_bits(mc_addr);
 845         private->smu_buffer_addr_high = upper_32_bits(mc_addr);
 846
 847         adev->smu.smumgr_funcs = &tonga_smumgr_funcs;
 848
 849         return 0;
 850 }
 851
 852 int tonga_smu_fini(struct amdgpu_device *adev)
 853 {
 854         amdgpu_bo_unref(&adev->smu.toc_buf);
 855         amdgpu_bo_unref(&adev->smu.smu_buf);
 856         kfree(adev->smu.priv);
 857         adev->smu.priv = NULL;
 858         if (adev->firmware.fw_buf)
 859                 amdgpu_ucode_fini_bo(adev);
 860
 861         return 0;
 862 }