2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christian König <christian.koenig@amd.com>
25 #include <linux/firmware.h>
28 #include "amdgpu_uvd.h"
30 #include "uvd/uvd_6_0_d.h"
31 #include "uvd/uvd_6_0_sh_mask.h"
32 #include "oss/oss_2_0_d.h"
33 #include "oss/oss_2_0_sh_mask.h"
34 #include "smu/smu_7_1_3_d.h"
35 #include "smu/smu_7_1_3_sh_mask.h"
38 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device
*adev
);
39 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device
*adev
);
40 static int uvd_v6_0_start(struct amdgpu_device
*adev
);
41 static void uvd_v6_0_stop(struct amdgpu_device
*adev
);
42 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device
*adev
);
45 * uvd_v6_0_ring_get_rptr - get read pointer
47 * @ring: amdgpu_ring pointer
49 * Returns the current hardware read pointer
51 static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring
*ring
)
53 struct amdgpu_device
*adev
= ring
->adev
;
55 return RREG32(mmUVD_RBC_RB_RPTR
);
59 * uvd_v6_0_ring_get_wptr - get write pointer
61 * @ring: amdgpu_ring pointer
63 * Returns the current hardware write pointer
65 static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring
*ring
)
67 struct amdgpu_device
*adev
= ring
->adev
;
69 return RREG32(mmUVD_RBC_RB_WPTR
);
73 * uvd_v6_0_ring_set_wptr - set write pointer
75 * @ring: amdgpu_ring pointer
77 * Commits the write pointer to the hardware
79 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring
*ring
)
81 struct amdgpu_device
*adev
= ring
->adev
;
83 WREG32(mmUVD_RBC_RB_WPTR
, ring
->wptr
);
86 static int uvd_v6_0_early_init(void *handle
)
88 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
90 uvd_v6_0_set_ring_funcs(adev
);
91 uvd_v6_0_set_irq_funcs(adev
);
96 static int uvd_v6_0_sw_init(void *handle
)
98 struct amdgpu_ring
*ring
;
100 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
103 r
= amdgpu_irq_add_id(adev
, 124, &adev
->uvd
.irq
);
107 r
= amdgpu_uvd_sw_init(adev
);
111 r
= amdgpu_uvd_resume(adev
);
115 ring
= &adev
->uvd
.ring
;
116 sprintf(ring
->name
, "uvd");
117 r
= amdgpu_ring_init(adev
, ring
, 512, CP_PACKET2
, 0xf,
118 &adev
->uvd
.irq
, 0, AMDGPU_RING_TYPE_UVD
);
123 static int uvd_v6_0_sw_fini(void *handle
)
126 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
128 r
= amdgpu_uvd_suspend(adev
);
132 r
= amdgpu_uvd_sw_fini(adev
);
140 * uvd_v6_0_hw_init - start and test UVD block
142 * @adev: amdgpu_device pointer
144 * Initialize the hardware, boot up the VCPU and do some testing
146 static int uvd_v6_0_hw_init(void *handle
)
148 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
149 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
153 r
= uvd_v6_0_start(adev
);
158 r
= amdgpu_ring_test_ring(ring
);
164 r
= amdgpu_ring_alloc(ring
, 10);
166 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r
);
170 tmp
= PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
, 0);
171 amdgpu_ring_write(ring
, tmp
);
172 amdgpu_ring_write(ring
, 0xFFFFF);
174 tmp
= PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
, 0);
175 amdgpu_ring_write(ring
, tmp
);
176 amdgpu_ring_write(ring
, 0xFFFFF);
178 tmp
= PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
, 0);
179 amdgpu_ring_write(ring
, tmp
);
180 amdgpu_ring_write(ring
, 0xFFFFF);
182 /* Clear timeout status bits */
183 amdgpu_ring_write(ring
, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS
, 0));
184 amdgpu_ring_write(ring
, 0x8);
186 amdgpu_ring_write(ring
, PACKET0(mmUVD_SEMA_CNTL
, 0));
187 amdgpu_ring_write(ring
, 3);
189 amdgpu_ring_commit(ring
);
193 DRM_INFO("UVD initialized successfully.\n");
199 * uvd_v6_0_hw_fini - stop the hardware block
201 * @adev: amdgpu_device pointer
203 * Stop the UVD block, mark ring as not ready any more
205 static int uvd_v6_0_hw_fini(void *handle
)
207 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
208 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
216 static int uvd_v6_0_suspend(void *handle
)
219 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
221 r
= uvd_v6_0_hw_fini(adev
);
225 /* Skip this for APU for now */
226 if (!(adev
->flags
& AMD_IS_APU
)) {
227 r
= amdgpu_uvd_suspend(adev
);
235 static int uvd_v6_0_resume(void *handle
)
238 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
240 /* Skip this for APU for now */
241 if (!(adev
->flags
& AMD_IS_APU
)) {
242 r
= amdgpu_uvd_resume(adev
);
246 r
= uvd_v6_0_hw_init(adev
);
254 * uvd_v6_0_mc_resume - memory controller programming
256 * @adev: amdgpu_device pointer
258 * Let the UVD memory controller know it's offsets
260 static void uvd_v6_0_mc_resume(struct amdgpu_device
*adev
)
265 /* programm memory controller bits 0-27 */
266 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
,
267 lower_32_bits(adev
->uvd
.gpu_addr
));
268 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
,
269 upper_32_bits(adev
->uvd
.gpu_addr
));
271 offset
= AMDGPU_UVD_FIRMWARE_OFFSET
;
272 size
= AMDGPU_GPU_PAGE_ALIGN(adev
->uvd
.fw
->size
+ 4);
273 WREG32(mmUVD_VCPU_CACHE_OFFSET0
, offset
>> 3);
274 WREG32(mmUVD_VCPU_CACHE_SIZE0
, size
);
277 size
= AMDGPU_UVD_HEAP_SIZE
;
278 WREG32(mmUVD_VCPU_CACHE_OFFSET1
, offset
>> 3);
279 WREG32(mmUVD_VCPU_CACHE_SIZE1
, size
);
282 size
= AMDGPU_UVD_STACK_SIZE
+
283 (AMDGPU_UVD_SESSION_SIZE
* adev
->uvd
.max_handles
);
284 WREG32(mmUVD_VCPU_CACHE_OFFSET2
, offset
>> 3);
285 WREG32(mmUVD_VCPU_CACHE_SIZE2
, size
);
287 WREG32(mmUVD_UDEC_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
288 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
289 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG
, adev
->gfx
.config
.gb_addr_config
);
291 WREG32(mmUVD_GP_SCRATCH4
, adev
->uvd
.max_handles
);
295 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device
*adev
,
300 data
= RREG32(mmUVD_CGC_GATE
);
301 data1
= RREG32(mmUVD_SUVD_CGC_GATE
);
303 data
|= UVD_CGC_GATE__SYS_MASK
|
304 UVD_CGC_GATE__UDEC_MASK
|
305 UVD_CGC_GATE__MPEG2_MASK
|
306 UVD_CGC_GATE__RBC_MASK
|
307 UVD_CGC_GATE__LMI_MC_MASK
|
308 UVD_CGC_GATE__IDCT_MASK
|
309 UVD_CGC_GATE__MPRD_MASK
|
310 UVD_CGC_GATE__MPC_MASK
|
311 UVD_CGC_GATE__LBSI_MASK
|
312 UVD_CGC_GATE__LRBBM_MASK
|
313 UVD_CGC_GATE__UDEC_RE_MASK
|
314 UVD_CGC_GATE__UDEC_CM_MASK
|
315 UVD_CGC_GATE__UDEC_IT_MASK
|
316 UVD_CGC_GATE__UDEC_DB_MASK
|
317 UVD_CGC_GATE__UDEC_MP_MASK
|
318 UVD_CGC_GATE__WCB_MASK
|
319 UVD_CGC_GATE__VCPU_MASK
|
320 UVD_CGC_GATE__SCPU_MASK
;
321 data1
|= UVD_SUVD_CGC_GATE__SRE_MASK
|
322 UVD_SUVD_CGC_GATE__SIT_MASK
|
323 UVD_SUVD_CGC_GATE__SMP_MASK
|
324 UVD_SUVD_CGC_GATE__SCM_MASK
|
325 UVD_SUVD_CGC_GATE__SDB_MASK
|
326 UVD_SUVD_CGC_GATE__SRE_H264_MASK
|
327 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
|
328 UVD_SUVD_CGC_GATE__SIT_H264_MASK
|
329 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
|
330 UVD_SUVD_CGC_GATE__SCM_H264_MASK
|
331 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
|
332 UVD_SUVD_CGC_GATE__SDB_H264_MASK
|
333 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
;
335 data
&= ~(UVD_CGC_GATE__SYS_MASK
|
336 UVD_CGC_GATE__UDEC_MASK
|
337 UVD_CGC_GATE__MPEG2_MASK
|
338 UVD_CGC_GATE__RBC_MASK
|
339 UVD_CGC_GATE__LMI_MC_MASK
|
340 UVD_CGC_GATE__LMI_UMC_MASK
|
341 UVD_CGC_GATE__IDCT_MASK
|
342 UVD_CGC_GATE__MPRD_MASK
|
343 UVD_CGC_GATE__MPC_MASK
|
344 UVD_CGC_GATE__LBSI_MASK
|
345 UVD_CGC_GATE__LRBBM_MASK
|
346 UVD_CGC_GATE__UDEC_RE_MASK
|
347 UVD_CGC_GATE__UDEC_CM_MASK
|
348 UVD_CGC_GATE__UDEC_IT_MASK
|
349 UVD_CGC_GATE__UDEC_DB_MASK
|
350 UVD_CGC_GATE__UDEC_MP_MASK
|
351 UVD_CGC_GATE__WCB_MASK
|
352 UVD_CGC_GATE__VCPU_MASK
|
353 UVD_CGC_GATE__SCPU_MASK
);
354 data1
&= ~(UVD_SUVD_CGC_GATE__SRE_MASK
|
355 UVD_SUVD_CGC_GATE__SIT_MASK
|
356 UVD_SUVD_CGC_GATE__SMP_MASK
|
357 UVD_SUVD_CGC_GATE__SCM_MASK
|
358 UVD_SUVD_CGC_GATE__SDB_MASK
|
359 UVD_SUVD_CGC_GATE__SRE_H264_MASK
|
360 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
|
361 UVD_SUVD_CGC_GATE__SIT_H264_MASK
|
362 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
|
363 UVD_SUVD_CGC_GATE__SCM_H264_MASK
|
364 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
|
365 UVD_SUVD_CGC_GATE__SDB_H264_MASK
|
366 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
);
368 WREG32(mmUVD_CGC_GATE
, data
);
369 WREG32(mmUVD_SUVD_CGC_GATE
, data1
);
374 * uvd_v6_0_start - start UVD block
376 * @adev: amdgpu_device pointer
378 * Setup and start the UVD block
380 static int uvd_v6_0_start(struct amdgpu_device
*adev
)
382 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
383 uint32_t rb_bufsz
, tmp
;
384 uint32_t lmi_swap_cntl
;
385 uint32_t mp_swap_cntl
;
389 WREG32_P(mmUVD_POWER_STATUS
, 0, ~(1 << 2));
391 /* disable byte swapping */
395 uvd_v6_0_mc_resume(adev
);
397 /* Set dynamic clock gating in S/W control mode */
398 if (adev
->cg_flags
& AMD_CG_SUPPORT_UVD_MGCG
) {
399 uvd_v6_0_set_sw_clock_gating(adev
);
401 /* disable clock gating */
402 uint32_t data
= RREG32(mmUVD_CGC_CTRL
);
403 data
&= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
;
404 WREG32(mmUVD_CGC_CTRL
, data
);
407 /* disable interupt */
408 WREG32_P(mmUVD_MASTINT_EN
, 0, ~(1 << 1));
410 /* stall UMC and register bus before resetting VCPU */
411 WREG32_P(mmUVD_LMI_CTRL2
, 1 << 8, ~(1 << 8));
414 /* put LMI, VCPU, RBC etc... into reset */
415 WREG32(mmUVD_SOFT_RESET
, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
|
416 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
| UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK
|
417 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK
| UVD_SOFT_RESET__CSM_SOFT_RESET_MASK
|
418 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK
| UVD_SOFT_RESET__TAP_SOFT_RESET_MASK
|
419 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
);
422 /* take UVD block out of reset */
423 WREG32_P(mmSRBM_SOFT_RESET
, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
);
426 /* initialize UVD memory controller */
427 WREG32(mmUVD_LMI_CTRL
, 0x40 | (1 << 8) | (1 << 13) |
428 (1 << 21) | (1 << 9) | (1 << 20));
431 /* swap (8 in 32) RB and IB */
435 WREG32(mmUVD_LMI_SWAP_CNTL
, lmi_swap_cntl
);
436 WREG32(mmUVD_MP_SWAP_CNTL
, mp_swap_cntl
);
438 WREG32(mmUVD_MPC_SET_MUXA0
, 0x40c2040);
439 WREG32(mmUVD_MPC_SET_MUXA1
, 0x0);
440 WREG32(mmUVD_MPC_SET_MUXB0
, 0x40c2040);
441 WREG32(mmUVD_MPC_SET_MUXB1
, 0x0);
442 WREG32(mmUVD_MPC_SET_ALU
, 0);
443 WREG32(mmUVD_MPC_SET_MUX
, 0x88);
445 /* take all subblocks out of reset, except VCPU */
446 WREG32(mmUVD_SOFT_RESET
, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
);
449 /* enable VCPU clock */
450 WREG32(mmUVD_VCPU_CNTL
, 1 << 9);
453 WREG32_P(mmUVD_LMI_CTRL2
, 0, ~(1 << 8));
455 /* boot up the VCPU */
456 WREG32(mmUVD_SOFT_RESET
, 0);
459 for (i
= 0; i
< 10; ++i
) {
462 for (j
= 0; j
< 100; ++j
) {
463 status
= RREG32(mmUVD_STATUS
);
472 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
473 WREG32_P(mmUVD_SOFT_RESET
, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
,
474 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
);
476 WREG32_P(mmUVD_SOFT_RESET
, 0,
477 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
);
483 DRM_ERROR("UVD not responding, giving up!!!\n");
486 /* enable master interrupt */
487 WREG32_P(mmUVD_MASTINT_EN
, 3 << 1, ~(3 << 1));
489 /* clear the bit 4 of UVD_STATUS */
490 WREG32_P(mmUVD_STATUS
, 0, ~(2 << 1));
492 rb_bufsz
= order_base_2(ring
->ring_size
);
494 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_BUFSZ
, rb_bufsz
);
495 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_BLKSZ
, 1);
496 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_NO_FETCH
, 1);
497 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_WPTR_POLL_EN
, 0);
498 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_NO_UPDATE
, 1);
499 tmp
= REG_SET_FIELD(tmp
, UVD_RBC_RB_CNTL
, RB_RPTR_WR_EN
, 1);
500 /* force RBC into idle state */
501 WREG32(mmUVD_RBC_RB_CNTL
, tmp
);
503 /* set the write pointer delay */
504 WREG32(mmUVD_RBC_RB_WPTR_CNTL
, 0);
506 /* set the wb address */
507 WREG32(mmUVD_RBC_RB_RPTR_ADDR
, (upper_32_bits(ring
->gpu_addr
) >> 2));
509 /* programm the RB_BASE for ring buffer */
510 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
,
511 lower_32_bits(ring
->gpu_addr
));
512 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
,
513 upper_32_bits(ring
->gpu_addr
));
515 /* Initialize the ring buffer's read and write pointers */
516 WREG32(mmUVD_RBC_RB_RPTR
, 0);
518 ring
->wptr
= RREG32(mmUVD_RBC_RB_RPTR
);
519 WREG32(mmUVD_RBC_RB_WPTR
, ring
->wptr
);
521 WREG32_P(mmUVD_RBC_RB_CNTL
, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
);
527 * uvd_v6_0_stop - stop UVD block
529 * @adev: amdgpu_device pointer
533 static void uvd_v6_0_stop(struct amdgpu_device
*adev
)
535 /* force RBC into idle state */
536 WREG32(mmUVD_RBC_RB_CNTL
, 0x11010101);
538 /* Stall UMC and register bus before resetting VCPU */
539 WREG32_P(mmUVD_LMI_CTRL2
, 1 << 8, ~(1 << 8));
542 /* put VCPU into reset */
543 WREG32(mmUVD_SOFT_RESET
, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
);
546 /* disable VCPU clock */
547 WREG32(mmUVD_VCPU_CNTL
, 0x0);
549 /* Unstall UMC and register bus */
550 WREG32_P(mmUVD_LMI_CTRL2
, 0, ~(1 << 8));
554 * uvd_v6_0_ring_emit_fence - emit an fence & trap command
556 * @ring: amdgpu_ring pointer
557 * @fence: fence to emit
559 * Write a fence and a trap command to the ring.
561 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
564 WARN_ON(flags
& AMDGPU_FENCE_FLAG_64BIT
);
566 amdgpu_ring_write(ring
, PACKET0(mmUVD_CONTEXT_ID
, 0));
567 amdgpu_ring_write(ring
, seq
);
568 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA0
, 0));
569 amdgpu_ring_write(ring
, addr
& 0xffffffff);
570 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA1
, 0));
571 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xff);
572 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_CMD
, 0));
573 amdgpu_ring_write(ring
, 0);
575 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA0
, 0));
576 amdgpu_ring_write(ring
, 0);
577 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_DATA1
, 0));
578 amdgpu_ring_write(ring
, 0);
579 amdgpu_ring_write(ring
, PACKET0(mmUVD_GPCOM_VCPU_CMD
, 0));
580 amdgpu_ring_write(ring
, 2);
584 * uvd_v6_0_ring_test_ring - register write test
586 * @ring: amdgpu_ring pointer
588 * Test if we can successfully write to the context register
590 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring
*ring
)
592 struct amdgpu_device
*adev
= ring
->adev
;
597 WREG32(mmUVD_CONTEXT_ID
, 0xCAFEDEAD);
598 r
= amdgpu_ring_alloc(ring
, 3);
600 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
604 amdgpu_ring_write(ring
, PACKET0(mmUVD_CONTEXT_ID
, 0));
605 amdgpu_ring_write(ring
, 0xDEADBEEF);
606 amdgpu_ring_commit(ring
);
607 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
608 tmp
= RREG32(mmUVD_CONTEXT_ID
);
609 if (tmp
== 0xDEADBEEF)
614 if (i
< adev
->usec_timeout
) {
615 DRM_INFO("ring test on %d succeeded in %d usecs\n",
618 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
626 * uvd_v6_0_ring_emit_ib - execute indirect buffer
628 * @ring: amdgpu_ring pointer
629 * @ib: indirect buffer to execute
631 * Write ring commands to execute the indirect buffer
633 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring
*ring
,
634 struct amdgpu_ib
*ib
,
635 unsigned vm_id
, bool ctx_switch
)
637 amdgpu_ring_write(ring
, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW
, 0));
638 amdgpu_ring_write(ring
, lower_32_bits(ib
->gpu_addr
));
639 amdgpu_ring_write(ring
, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH
, 0));
640 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
641 amdgpu_ring_write(ring
, PACKET0(mmUVD_RBC_IB_SIZE
, 0));
642 amdgpu_ring_write(ring
, ib
->length_dw
);
646 * uvd_v6_0_ring_test_ib - test ib execution
648 * @ring: amdgpu_ring pointer
650 * Test if we can successfully execute an IB
652 static int uvd_v6_0_ring_test_ib(struct amdgpu_ring
*ring
)
654 struct fence
*fence
= NULL
;
657 r
= amdgpu_uvd_get_create_msg(ring
, 1, NULL
);
659 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r
);
663 r
= amdgpu_uvd_get_destroy_msg(ring
, 1, true, &fence
);
665 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r
);
669 r
= fence_wait(fence
, false);
671 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r
);
674 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
680 static bool uvd_v6_0_is_idle(void *handle
)
682 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
684 return !(RREG32(mmSRBM_STATUS
) & SRBM_STATUS__UVD_BUSY_MASK
);
687 static int uvd_v6_0_wait_for_idle(void *handle
)
690 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
692 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
693 if (!(RREG32(mmSRBM_STATUS
) & SRBM_STATUS__UVD_BUSY_MASK
))
699 static int uvd_v6_0_soft_reset(void *handle
)
701 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
705 WREG32_P(mmSRBM_SOFT_RESET
, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
,
706 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK
);
709 return uvd_v6_0_start(adev
);
712 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device
*adev
,
713 struct amdgpu_irq_src
*source
,
715 enum amdgpu_interrupt_state state
)
721 static int uvd_v6_0_process_interrupt(struct amdgpu_device
*adev
,
722 struct amdgpu_irq_src
*source
,
723 struct amdgpu_iv_entry
*entry
)
725 DRM_DEBUG("IH: UVD TRAP\n");
726 amdgpu_fence_process(&adev
->uvd
.ring
);
730 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device
*adev
)
732 uint32_t data
, data1
, data2
, suvd_flags
;
734 data
= RREG32(mmUVD_CGC_CTRL
);
735 data1
= RREG32(mmUVD_SUVD_CGC_GATE
);
736 data2
= RREG32(mmUVD_SUVD_CGC_CTRL
);
738 data
&= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK
|
739 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK
);
741 suvd_flags
= UVD_SUVD_CGC_GATE__SRE_MASK
|
742 UVD_SUVD_CGC_GATE__SIT_MASK
|
743 UVD_SUVD_CGC_GATE__SMP_MASK
|
744 UVD_SUVD_CGC_GATE__SCM_MASK
|
745 UVD_SUVD_CGC_GATE__SDB_MASK
;
747 data
|= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
|
748 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL
, CLK_GATE_DLY_TIMER
)) |
749 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL
, CLK_OFF_DELAY
));
751 data
&= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
|
752 UVD_CGC_CTRL__UDEC_CM_MODE_MASK
|
753 UVD_CGC_CTRL__UDEC_IT_MODE_MASK
|
754 UVD_CGC_CTRL__UDEC_DB_MODE_MASK
|
755 UVD_CGC_CTRL__UDEC_MP_MODE_MASK
|
756 UVD_CGC_CTRL__SYS_MODE_MASK
|
757 UVD_CGC_CTRL__UDEC_MODE_MASK
|
758 UVD_CGC_CTRL__MPEG2_MODE_MASK
|
759 UVD_CGC_CTRL__REGS_MODE_MASK
|
760 UVD_CGC_CTRL__RBC_MODE_MASK
|
761 UVD_CGC_CTRL__LMI_MC_MODE_MASK
|
762 UVD_CGC_CTRL__LMI_UMC_MODE_MASK
|
763 UVD_CGC_CTRL__IDCT_MODE_MASK
|
764 UVD_CGC_CTRL__MPRD_MODE_MASK
|
765 UVD_CGC_CTRL__MPC_MODE_MASK
|
766 UVD_CGC_CTRL__LBSI_MODE_MASK
|
767 UVD_CGC_CTRL__LRBBM_MODE_MASK
|
768 UVD_CGC_CTRL__WCB_MODE_MASK
|
769 UVD_CGC_CTRL__VCPU_MODE_MASK
|
770 UVD_CGC_CTRL__JPEG_MODE_MASK
|
771 UVD_CGC_CTRL__SCPU_MODE_MASK
|
772 UVD_CGC_CTRL__JPEG2_MODE_MASK
);
773 data2
&= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
|
774 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
|
775 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
|
776 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
|
777 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
);
780 WREG32(mmUVD_CGC_CTRL
, data
);
781 WREG32(mmUVD_CGC_GATE
, 0);
782 WREG32(mmUVD_SUVD_CGC_GATE
, data1
);
783 WREG32(mmUVD_SUVD_CGC_CTRL
, data2
);
787 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device
*adev
)
789 uint32_t data
, data1
, cgc_flags
, suvd_flags
;
791 data
= RREG32(mmUVD_CGC_GATE
);
792 data1
= RREG32(mmUVD_SUVD_CGC_GATE
);
794 cgc_flags
= UVD_CGC_GATE__SYS_MASK
|
795 UVD_CGC_GATE__UDEC_MASK
|
796 UVD_CGC_GATE__MPEG2_MASK
|
797 UVD_CGC_GATE__RBC_MASK
|
798 UVD_CGC_GATE__LMI_MC_MASK
|
799 UVD_CGC_GATE__IDCT_MASK
|
800 UVD_CGC_GATE__MPRD_MASK
|
801 UVD_CGC_GATE__MPC_MASK
|
802 UVD_CGC_GATE__LBSI_MASK
|
803 UVD_CGC_GATE__LRBBM_MASK
|
804 UVD_CGC_GATE__UDEC_RE_MASK
|
805 UVD_CGC_GATE__UDEC_CM_MASK
|
806 UVD_CGC_GATE__UDEC_IT_MASK
|
807 UVD_CGC_GATE__UDEC_DB_MASK
|
808 UVD_CGC_GATE__UDEC_MP_MASK
|
809 UVD_CGC_GATE__WCB_MASK
|
810 UVD_CGC_GATE__VCPU_MASK
|
811 UVD_CGC_GATE__SCPU_MASK
|
812 UVD_CGC_GATE__JPEG_MASK
|
813 UVD_CGC_GATE__JPEG2_MASK
;
815 suvd_flags
= UVD_SUVD_CGC_GATE__SRE_MASK
|
816 UVD_SUVD_CGC_GATE__SIT_MASK
|
817 UVD_SUVD_CGC_GATE__SMP_MASK
|
818 UVD_SUVD_CGC_GATE__SCM_MASK
|
819 UVD_SUVD_CGC_GATE__SDB_MASK
;
824 WREG32(mmUVD_CGC_GATE
, data
);
825 WREG32(mmUVD_SUVD_CGC_GATE
, data1
);
829 static void uvd_v6_set_bypass_mode(struct amdgpu_device
*adev
, bool enable
)
831 u32 tmp
= RREG32_SMC(ixGCK_DFS_BYPASS_CNTL
);
834 tmp
|= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK
|
835 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK
);
837 tmp
&= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK
|
838 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK
);
840 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL
, tmp
);
843 static int uvd_v6_0_set_clockgating_state(void *handle
,
844 enum amd_clockgating_state state
)
846 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
847 bool enable
= (state
== AMD_CG_STATE_GATE
) ? true : false;
848 static int curstate
= -1;
850 if (adev
->asic_type
== CHIP_FIJI
)
851 uvd_v6_set_bypass_mode(adev
, enable
);
853 if (!(adev
->cg_flags
& AMD_CG_SUPPORT_UVD_MGCG
))
856 if (curstate
== state
)
861 /* disable HW gating and enable Sw gating */
862 uvd_v6_0_set_sw_clock_gating(adev
);
864 /* wait for STATUS to clear */
865 if (uvd_v6_0_wait_for_idle(handle
))
868 /* enable HW gates because UVD is idle */
869 /* uvd_v6_0_set_hw_clock_gating(adev); */
875 static int uvd_v6_0_set_powergating_state(void *handle
,
876 enum amd_powergating_state state
)
878 /* This doesn't actually powergate the UVD block.
879 * That's done in the dpm code via the SMC. This
880 * just re-inits the block as necessary. The actual
881 * gating still happens in the dpm code. We should
882 * revisit this when there is a cleaner line between
883 * the smc and the hw blocks
885 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
887 if (!(adev
->pg_flags
& AMD_PG_SUPPORT_UVD
))
890 if (state
== AMD_PG_STATE_GATE
) {
894 return uvd_v6_0_start(adev
);
898 const struct amd_ip_funcs uvd_v6_0_ip_funcs
= {
900 .early_init
= uvd_v6_0_early_init
,
902 .sw_init
= uvd_v6_0_sw_init
,
903 .sw_fini
= uvd_v6_0_sw_fini
,
904 .hw_init
= uvd_v6_0_hw_init
,
905 .hw_fini
= uvd_v6_0_hw_fini
,
906 .suspend
= uvd_v6_0_suspend
,
907 .resume
= uvd_v6_0_resume
,
908 .is_idle
= uvd_v6_0_is_idle
,
909 .wait_for_idle
= uvd_v6_0_wait_for_idle
,
910 .soft_reset
= uvd_v6_0_soft_reset
,
911 .set_clockgating_state
= uvd_v6_0_set_clockgating_state
,
912 .set_powergating_state
= uvd_v6_0_set_powergating_state
,
915 static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs
= {
916 .get_rptr
= uvd_v6_0_ring_get_rptr
,
917 .get_wptr
= uvd_v6_0_ring_get_wptr
,
918 .set_wptr
= uvd_v6_0_ring_set_wptr
,
919 .parse_cs
= amdgpu_uvd_ring_parse_cs
,
920 .emit_ib
= uvd_v6_0_ring_emit_ib
,
921 .emit_fence
= uvd_v6_0_ring_emit_fence
,
922 .test_ring
= uvd_v6_0_ring_test_ring
,
923 .test_ib
= uvd_v6_0_ring_test_ib
,
924 .insert_nop
= amdgpu_ring_insert_nop
,
925 .pad_ib
= amdgpu_ring_generic_pad_ib
,
928 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device
*adev
)
930 adev
->uvd
.ring
.funcs
= &uvd_v6_0_ring_funcs
;
933 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs
= {
934 .set
= uvd_v6_0_set_interrupt_state
,
935 .process
= uvd_v6_0_process_interrupt
,
938 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device
*adev
)
940 adev
->uvd
.irq
.num_types
= 1;
941 adev
->uvd
.irq
.funcs
= &uvd_v6_0_irq_funcs
;