2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
36 #include "gmc/gmc_8_1_d.h"
37 #include "gmc/gmc_8_1_sh_mask.h"
39 #include "oss/oss_3_0_d.h"
40 #include "oss/oss_3_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "gca/gfx_8_0_d.h"
46 #include "gca/gfx_8_0_sh_mask.h"
48 #include "smu/smu_7_1_1_d.h"
49 #include "smu/smu_7_1_1_sh_mask.h"
51 #include "uvd/uvd_5_0_d.h"
52 #include "uvd/uvd_5_0_sh_mask.h"
54 #include "vce/vce_3_0_d.h"
55 #include "vce/vce_3_0_sh_mask.h"
57 #include "dce/dce_10_0_d.h"
58 #include "dce/dce_10_0_sh_mask.h"
66 #include "sdma_v2_4.h"
67 #include "sdma_v3_0.h"
68 #include "dce_v10_0.h"
69 #include "dce_v11_0.h"
70 #include "iceland_ih.h"
76 #include "amdgpu_powerplay.h"
77 #if defined(CONFIG_DRM_AMD_ACP)
78 #include "amdgpu_acp.h"
82 * Indirect registers accessor
84 static u32
vi_pcie_rreg(struct amdgpu_device
*adev
, u32 reg
)
89 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
90 WREG32(mmPCIE_INDEX
, reg
);
91 (void)RREG32(mmPCIE_INDEX
);
92 r
= RREG32(mmPCIE_DATA
);
93 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
97 static void vi_pcie_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
101 spin_lock_irqsave(&adev
->pcie_idx_lock
, flags
);
102 WREG32(mmPCIE_INDEX
, reg
);
103 (void)RREG32(mmPCIE_INDEX
);
104 WREG32(mmPCIE_DATA
, v
);
105 (void)RREG32(mmPCIE_DATA
);
106 spin_unlock_irqrestore(&adev
->pcie_idx_lock
, flags
);
109 static u32
vi_smc_rreg(struct amdgpu_device
*adev
, u32 reg
)
114 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
115 WREG32(mmSMC_IND_INDEX_0
, (reg
));
116 r
= RREG32(mmSMC_IND_DATA_0
);
117 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
121 static void vi_smc_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
125 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
126 WREG32(mmSMC_IND_INDEX_0
, (reg
));
127 WREG32(mmSMC_IND_DATA_0
, (v
));
128 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
132 #define mmMP0PUB_IND_INDEX 0x180
133 #define mmMP0PUB_IND_DATA 0x181
135 static u32
cz_smc_rreg(struct amdgpu_device
*adev
, u32 reg
)
140 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
141 WREG32(mmMP0PUB_IND_INDEX
, (reg
));
142 r
= RREG32(mmMP0PUB_IND_DATA
);
143 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
147 static void cz_smc_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
151 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
152 WREG32(mmMP0PUB_IND_INDEX
, (reg
));
153 WREG32(mmMP0PUB_IND_DATA
, (v
));
154 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
157 static u32
vi_uvd_ctx_rreg(struct amdgpu_device
*adev
, u32 reg
)
162 spin_lock_irqsave(&adev
->uvd_ctx_idx_lock
, flags
);
163 WREG32(mmUVD_CTX_INDEX
, ((reg
) & 0x1ff));
164 r
= RREG32(mmUVD_CTX_DATA
);
165 spin_unlock_irqrestore(&adev
->uvd_ctx_idx_lock
, flags
);
169 static void vi_uvd_ctx_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
173 spin_lock_irqsave(&adev
->uvd_ctx_idx_lock
, flags
);
174 WREG32(mmUVD_CTX_INDEX
, ((reg
) & 0x1ff));
175 WREG32(mmUVD_CTX_DATA
, (v
));
176 spin_unlock_irqrestore(&adev
->uvd_ctx_idx_lock
, flags
);
179 static u32
vi_didt_rreg(struct amdgpu_device
*adev
, u32 reg
)
184 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
185 WREG32(mmDIDT_IND_INDEX
, (reg
));
186 r
= RREG32(mmDIDT_IND_DATA
);
187 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
191 static void vi_didt_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
)
195 spin_lock_irqsave(&adev
->didt_idx_lock
, flags
);
196 WREG32(mmDIDT_IND_INDEX
, (reg
));
197 WREG32(mmDIDT_IND_DATA
, (v
));
198 spin_unlock_irqrestore(&adev
->didt_idx_lock
, flags
);
201 static const u32 tonga_mgcg_cgcg_init
[] =
203 mmCGTT_DRM_CLK_CTRL0
, 0xffffffff, 0x00600100,
204 mmPCIE_INDEX
, 0xffffffff, 0x0140001c,
205 mmPCIE_DATA
, 0x000f0000, 0x00000000,
206 mmSMC_IND_INDEX_4
, 0xffffffff, 0xC060000C,
207 mmSMC_IND_DATA_4
, 0xc0000fff, 0x00000100,
208 mmCGTT_DRM_CLK_CTRL0
, 0xff000fff, 0x00000100,
209 mmHDP_XDP_CGTT_BLK_CTRL
, 0xc0000fff, 0x00000104,
212 static const u32 fiji_mgcg_cgcg_init
[] =
214 mmCGTT_DRM_CLK_CTRL0
, 0xffffffff, 0x00600100,
215 mmPCIE_INDEX
, 0xffffffff, 0x0140001c,
216 mmPCIE_DATA
, 0x000f0000, 0x00000000,
217 mmSMC_IND_INDEX_4
, 0xffffffff, 0xC060000C,
218 mmSMC_IND_DATA_4
, 0xc0000fff, 0x00000100,
219 mmCGTT_DRM_CLK_CTRL0
, 0xff000fff, 0x00000100,
220 mmHDP_XDP_CGTT_BLK_CTRL
, 0xc0000fff, 0x00000104,
223 static const u32 iceland_mgcg_cgcg_init
[] =
225 mmPCIE_INDEX
, 0xffffffff, ixPCIE_CNTL2
,
226 mmPCIE_DATA
, 0x000f0000, 0x00000000,
227 mmSMC_IND_INDEX_4
, 0xffffffff, ixCGTT_ROM_CLK_CTRL0
,
228 mmSMC_IND_DATA_4
, 0xc0000fff, 0x00000100,
229 mmHDP_XDP_CGTT_BLK_CTRL
, 0xc0000fff, 0x00000104,
232 static const u32 cz_mgcg_cgcg_init
[] =
234 mmCGTT_DRM_CLK_CTRL0
, 0xffffffff, 0x00600100,
235 mmPCIE_INDEX
, 0xffffffff, 0x0140001c,
236 mmPCIE_DATA
, 0x000f0000, 0x00000000,
237 mmCGTT_DRM_CLK_CTRL0
, 0xff000fff, 0x00000100,
238 mmHDP_XDP_CGTT_BLK_CTRL
, 0xc0000fff, 0x00000104,
241 static const u32 stoney_mgcg_cgcg_init
[] =
243 mmCGTT_DRM_CLK_CTRL0
, 0xffffffff, 0x00000100,
244 mmHDP_XDP_CGTT_BLK_CTRL
, 0xffffffff, 0x00000104,
245 mmHDP_HOST_PATH_CNTL
, 0xffffffff, 0x0f000027,
248 static void vi_init_golden_registers(struct amdgpu_device
*adev
)
250 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
251 mutex_lock(&adev
->grbm_idx_mutex
);
253 switch (adev
->asic_type
) {
255 amdgpu_program_register_sequence(adev
,
256 iceland_mgcg_cgcg_init
,
257 (const u32
)ARRAY_SIZE(iceland_mgcg_cgcg_init
));
260 amdgpu_program_register_sequence(adev
,
262 (const u32
)ARRAY_SIZE(fiji_mgcg_cgcg_init
));
265 amdgpu_program_register_sequence(adev
,
266 tonga_mgcg_cgcg_init
,
267 (const u32
)ARRAY_SIZE(tonga_mgcg_cgcg_init
));
270 amdgpu_program_register_sequence(adev
,
272 (const u32
)ARRAY_SIZE(cz_mgcg_cgcg_init
));
275 amdgpu_program_register_sequence(adev
,
276 stoney_mgcg_cgcg_init
,
277 (const u32
)ARRAY_SIZE(stoney_mgcg_cgcg_init
));
282 mutex_unlock(&adev
->grbm_idx_mutex
);
286 * vi_get_xclk - get the xclk
288 * @adev: amdgpu_device pointer
290 * Returns the reference clock used by the gfx engine
293 static u32
vi_get_xclk(struct amdgpu_device
*adev
)
295 u32 reference_clock
= adev
->clock
.spll
.reference_freq
;
298 if (adev
->flags
& AMD_IS_APU
)
299 return reference_clock
;
301 tmp
= RREG32_SMC(ixCG_CLKPIN_CNTL_2
);
302 if (REG_GET_FIELD(tmp
, CG_CLKPIN_CNTL_2
, MUX_TCLK_TO_XCLK
))
305 tmp
= RREG32_SMC(ixCG_CLKPIN_CNTL
);
306 if (REG_GET_FIELD(tmp
, CG_CLKPIN_CNTL
, XTALIN_DIVIDE
))
307 return reference_clock
/ 4;
309 return reference_clock
;
313 * vi_srbm_select - select specific register instances
315 * @adev: amdgpu_device pointer
316 * @me: selected ME (micro engine)
321 * Switches the currently active registers instances. Some
322 * registers are instanced per VMID, others are instanced per
323 * me/pipe/queue combination.
325 void vi_srbm_select(struct amdgpu_device
*adev
,
326 u32 me
, u32 pipe
, u32 queue
, u32 vmid
)
328 u32 srbm_gfx_cntl
= 0;
329 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, PIPEID
, pipe
);
330 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, MEID
, me
);
331 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, VMID
, vmid
);
332 srbm_gfx_cntl
= REG_SET_FIELD(srbm_gfx_cntl
, SRBM_GFX_CNTL
, QUEUEID
, queue
);
333 WREG32(mmSRBM_GFX_CNTL
, srbm_gfx_cntl
);
336 static void vi_vga_set_state(struct amdgpu_device
*adev
, bool state
)
341 static bool vi_read_disabled_bios(struct amdgpu_device
*adev
)
344 u32 d1vga_control
= 0;
345 u32 d2vga_control
= 0;
346 u32 vga_render_control
= 0;
350 bus_cntl
= RREG32(mmBUS_CNTL
);
351 if (adev
->mode_info
.num_crtc
) {
352 d1vga_control
= RREG32(mmD1VGA_CONTROL
);
353 d2vga_control
= RREG32(mmD2VGA_CONTROL
);
354 vga_render_control
= RREG32(mmVGA_RENDER_CONTROL
);
356 rom_cntl
= RREG32_SMC(ixROM_CNTL
);
359 WREG32(mmBUS_CNTL
, (bus_cntl
& ~BUS_CNTL__BIOS_ROM_DIS_MASK
));
360 if (adev
->mode_info
.num_crtc
) {
361 /* Disable VGA mode */
362 WREG32(mmD1VGA_CONTROL
,
363 (d1vga_control
& ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK
|
364 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK
)));
365 WREG32(mmD2VGA_CONTROL
,
366 (d2vga_control
& ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK
|
367 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK
)));
368 WREG32(mmVGA_RENDER_CONTROL
,
369 (vga_render_control
& ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK
));
371 WREG32_SMC(ixROM_CNTL
, rom_cntl
| ROM_CNTL__SCK_OVERWRITE_MASK
);
373 r
= amdgpu_read_bios(adev
);
376 WREG32(mmBUS_CNTL
, bus_cntl
);
377 if (adev
->mode_info
.num_crtc
) {
378 WREG32(mmD1VGA_CONTROL
, d1vga_control
);
379 WREG32(mmD2VGA_CONTROL
, d2vga_control
);
380 WREG32(mmVGA_RENDER_CONTROL
, vga_render_control
);
382 WREG32_SMC(ixROM_CNTL
, rom_cntl
);
386 static bool vi_read_bios_from_rom(struct amdgpu_device
*adev
,
387 u8
*bios
, u32 length_bytes
)
395 if (length_bytes
== 0)
397 /* APU vbios image is part of sbios image */
398 if (adev
->flags
& AMD_IS_APU
)
401 dw_ptr
= (u32
*)bios
;
402 length_dw
= ALIGN(length_bytes
, 4) / 4;
403 /* take the smc lock since we are using the smc index */
404 spin_lock_irqsave(&adev
->smc_idx_lock
, flags
);
405 /* set rom index to 0 */
406 WREG32(mmSMC_IND_INDEX_0
, ixROM_INDEX
);
407 WREG32(mmSMC_IND_DATA_0
, 0);
408 /* set index to data for continous read */
409 WREG32(mmSMC_IND_INDEX_0
, ixROM_DATA
);
410 for (i
= 0; i
< length_dw
; i
++)
411 dw_ptr
[i
] = RREG32(mmSMC_IND_DATA_0
);
412 spin_unlock_irqrestore(&adev
->smc_idx_lock
, flags
);
417 static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers
[] = {
418 {mmGB_MACROTILE_MODE7
, true},
421 static const struct amdgpu_allowed_register_entry cz_allowed_read_registers
[] = {
422 {mmGB_TILE_MODE7
, true},
423 {mmGB_TILE_MODE12
, true},
424 {mmGB_TILE_MODE17
, true},
425 {mmGB_TILE_MODE23
, true},
426 {mmGB_MACROTILE_MODE7
, true},
429 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers
[] = {
430 {mmGRBM_STATUS
, false},
431 {mmGRBM_STATUS2
, false},
432 {mmGRBM_STATUS_SE0
, false},
433 {mmGRBM_STATUS_SE1
, false},
434 {mmGRBM_STATUS_SE2
, false},
435 {mmGRBM_STATUS_SE3
, false},
436 {mmSRBM_STATUS
, false},
437 {mmSRBM_STATUS2
, false},
438 {mmSRBM_STATUS3
, false},
439 {mmSDMA0_STATUS_REG
+ SDMA0_REGISTER_OFFSET
, false},
440 {mmSDMA0_STATUS_REG
+ SDMA1_REGISTER_OFFSET
, false},
442 {mmCP_STALLED_STAT1
, false},
443 {mmCP_STALLED_STAT2
, false},
444 {mmCP_STALLED_STAT3
, false},
445 {mmCP_CPF_BUSY_STAT
, false},
446 {mmCP_CPF_STALLED_STAT1
, false},
447 {mmCP_CPF_STATUS
, false},
448 {mmCP_CPC_BUSY_STAT
, false},
449 {mmCP_CPC_STALLED_STAT1
, false},
450 {mmCP_CPC_STATUS
, false},
451 {mmGB_ADDR_CONFIG
, false},
452 {mmMC_ARB_RAMCFG
, false},
453 {mmGB_TILE_MODE0
, false},
454 {mmGB_TILE_MODE1
, false},
455 {mmGB_TILE_MODE2
, false},
456 {mmGB_TILE_MODE3
, false},
457 {mmGB_TILE_MODE4
, false},
458 {mmGB_TILE_MODE5
, false},
459 {mmGB_TILE_MODE6
, false},
460 {mmGB_TILE_MODE7
, false},
461 {mmGB_TILE_MODE8
, false},
462 {mmGB_TILE_MODE9
, false},
463 {mmGB_TILE_MODE10
, false},
464 {mmGB_TILE_MODE11
, false},
465 {mmGB_TILE_MODE12
, false},
466 {mmGB_TILE_MODE13
, false},
467 {mmGB_TILE_MODE14
, false},
468 {mmGB_TILE_MODE15
, false},
469 {mmGB_TILE_MODE16
, false},
470 {mmGB_TILE_MODE17
, false},
471 {mmGB_TILE_MODE18
, false},
472 {mmGB_TILE_MODE19
, false},
473 {mmGB_TILE_MODE20
, false},
474 {mmGB_TILE_MODE21
, false},
475 {mmGB_TILE_MODE22
, false},
476 {mmGB_TILE_MODE23
, false},
477 {mmGB_TILE_MODE24
, false},
478 {mmGB_TILE_MODE25
, false},
479 {mmGB_TILE_MODE26
, false},
480 {mmGB_TILE_MODE27
, false},
481 {mmGB_TILE_MODE28
, false},
482 {mmGB_TILE_MODE29
, false},
483 {mmGB_TILE_MODE30
, false},
484 {mmGB_TILE_MODE31
, false},
485 {mmGB_MACROTILE_MODE0
, false},
486 {mmGB_MACROTILE_MODE1
, false},
487 {mmGB_MACROTILE_MODE2
, false},
488 {mmGB_MACROTILE_MODE3
, false},
489 {mmGB_MACROTILE_MODE4
, false},
490 {mmGB_MACROTILE_MODE5
, false},
491 {mmGB_MACROTILE_MODE6
, false},
492 {mmGB_MACROTILE_MODE7
, false},
493 {mmGB_MACROTILE_MODE8
, false},
494 {mmGB_MACROTILE_MODE9
, false},
495 {mmGB_MACROTILE_MODE10
, false},
496 {mmGB_MACROTILE_MODE11
, false},
497 {mmGB_MACROTILE_MODE12
, false},
498 {mmGB_MACROTILE_MODE13
, false},
499 {mmGB_MACROTILE_MODE14
, false},
500 {mmGB_MACROTILE_MODE15
, false},
501 {mmCC_RB_BACKEND_DISABLE
, false, true},
502 {mmGC_USER_RB_BACKEND_DISABLE
, false, true},
503 {mmGB_BACKEND_MAP
, false, false},
504 {mmPA_SC_RASTER_CONFIG
, false, true},
505 {mmPA_SC_RASTER_CONFIG_1
, false, true},
508 static uint32_t vi_read_indexed_register(struct amdgpu_device
*adev
, u32 se_num
,
509 u32 sh_num
, u32 reg_offset
)
513 mutex_lock(&adev
->grbm_idx_mutex
);
514 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
515 gfx_v8_0_select_se_sh(adev
, se_num
, sh_num
);
517 val
= RREG32(reg_offset
);
519 if (se_num
!= 0xffffffff || sh_num
!= 0xffffffff)
520 gfx_v8_0_select_se_sh(adev
, 0xffffffff, 0xffffffff);
521 mutex_unlock(&adev
->grbm_idx_mutex
);
525 static int vi_read_register(struct amdgpu_device
*adev
, u32 se_num
,
526 u32 sh_num
, u32 reg_offset
, u32
*value
)
528 const struct amdgpu_allowed_register_entry
*asic_register_table
= NULL
;
529 const struct amdgpu_allowed_register_entry
*asic_register_entry
;
533 switch (adev
->asic_type
) {
535 asic_register_table
= tonga_allowed_read_registers
;
536 size
= ARRAY_SIZE(tonga_allowed_read_registers
);
542 asic_register_table
= cz_allowed_read_registers
;
543 size
= ARRAY_SIZE(cz_allowed_read_registers
);
549 if (asic_register_table
) {
550 for (i
= 0; i
< size
; i
++) {
551 asic_register_entry
= asic_register_table
+ i
;
552 if (reg_offset
!= asic_register_entry
->reg_offset
)
554 if (!asic_register_entry
->untouched
)
555 *value
= asic_register_entry
->grbm_indexed
?
556 vi_read_indexed_register(adev
, se_num
,
557 sh_num
, reg_offset
) :
563 for (i
= 0; i
< ARRAY_SIZE(vi_allowed_read_registers
); i
++) {
564 if (reg_offset
!= vi_allowed_read_registers
[i
].reg_offset
)
567 if (!vi_allowed_read_registers
[i
].untouched
)
568 *value
= vi_allowed_read_registers
[i
].grbm_indexed
?
569 vi_read_indexed_register(adev
, se_num
,
570 sh_num
, reg_offset
) :
577 static void vi_gpu_pci_config_reset(struct amdgpu_device
*adev
)
581 dev_info(adev
->dev
, "GPU pci config reset\n");
584 pci_clear_master(adev
->pdev
);
586 amdgpu_pci_config_reset(adev
);
590 /* wait for asic to come out of reset */
591 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
592 if (RREG32(mmCONFIG_MEMSIZE
) != 0xffffffff)
599 static void vi_set_bios_scratch_engine_hung(struct amdgpu_device
*adev
, bool hung
)
601 u32 tmp
= RREG32(mmBIOS_SCRATCH_3
);
604 tmp
|= ATOM_S3_ASIC_GUI_ENGINE_HUNG
;
606 tmp
&= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG
;
608 WREG32(mmBIOS_SCRATCH_3
, tmp
);
612 * vi_asic_reset - soft reset GPU
614 * @adev: amdgpu_device pointer
616 * Look up which blocks are hung and attempt
618 * Returns 0 for success.
620 static int vi_asic_reset(struct amdgpu_device
*adev
)
622 vi_set_bios_scratch_engine_hung(adev
, true);
624 vi_gpu_pci_config_reset(adev
);
626 vi_set_bios_scratch_engine_hung(adev
, false);
631 static int vi_set_uvd_clock(struct amdgpu_device
*adev
, u32 clock
,
632 u32 cntl_reg
, u32 status_reg
)
635 struct atom_clock_dividers dividers
;
638 r
= amdgpu_atombios_get_clock_dividers(adev
,
639 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK
,
640 clock
, false, ÷rs
);
644 tmp
= RREG32_SMC(cntl_reg
);
645 tmp
&= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK
|
646 CG_DCLK_CNTL__DCLK_DIVIDER_MASK
);
647 tmp
|= dividers
.post_divider
;
648 WREG32_SMC(cntl_reg
, tmp
);
650 for (i
= 0; i
< 100; i
++) {
651 if (RREG32_SMC(status_reg
) & CG_DCLK_STATUS__DCLK_STATUS_MASK
)
661 static int vi_set_uvd_clocks(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
)
665 r
= vi_set_uvd_clock(adev
, vclk
, ixCG_VCLK_CNTL
, ixCG_VCLK_STATUS
);
669 r
= vi_set_uvd_clock(adev
, dclk
, ixCG_DCLK_CNTL
, ixCG_DCLK_STATUS
);
674 static int vi_set_vce_clocks(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
)
681 static void vi_pcie_gen3_enable(struct amdgpu_device
*adev
)
683 if (pci_is_root_bus(adev
->pdev
->bus
))
686 if (amdgpu_pcie_gen2
== 0)
689 if (adev
->flags
& AMD_IS_APU
)
692 if (!(adev
->pm
.pcie_gen_mask
& (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2
|
693 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
)))
699 static void vi_program_aspm(struct amdgpu_device
*adev
)
702 if (amdgpu_aspm
== 0)
708 static void vi_enable_doorbell_aperture(struct amdgpu_device
*adev
,
713 /* not necessary on CZ */
714 if (adev
->flags
& AMD_IS_APU
)
717 tmp
= RREG32(mmBIF_DOORBELL_APER_EN
);
719 tmp
= REG_SET_FIELD(tmp
, BIF_DOORBELL_APER_EN
, BIF_DOORBELL_APER_EN
, 1);
721 tmp
= REG_SET_FIELD(tmp
, BIF_DOORBELL_APER_EN
, BIF_DOORBELL_APER_EN
, 0);
723 WREG32(mmBIF_DOORBELL_APER_EN
, tmp
);
726 /* topaz has no DCE, UVD, VCE */
727 static const struct amdgpu_ip_block_version topaz_ip_blocks
[] =
731 .type
= AMD_IP_BLOCK_TYPE_COMMON
,
735 .funcs
= &vi_common_ip_funcs
,
738 .type
= AMD_IP_BLOCK_TYPE_GMC
,
742 .funcs
= &gmc_v7_0_ip_funcs
,
745 .type
= AMD_IP_BLOCK_TYPE_IH
,
749 .funcs
= &iceland_ih_ip_funcs
,
752 .type
= AMD_IP_BLOCK_TYPE_SMC
,
756 .funcs
= &amdgpu_pp_ip_funcs
,
759 .type
= AMD_IP_BLOCK_TYPE_GFX
,
763 .funcs
= &gfx_v8_0_ip_funcs
,
766 .type
= AMD_IP_BLOCK_TYPE_SDMA
,
770 .funcs
= &sdma_v2_4_ip_funcs
,
774 static const struct amdgpu_ip_block_version tonga_ip_blocks
[] =
778 .type
= AMD_IP_BLOCK_TYPE_COMMON
,
782 .funcs
= &vi_common_ip_funcs
,
785 .type
= AMD_IP_BLOCK_TYPE_GMC
,
789 .funcs
= &gmc_v8_0_ip_funcs
,
792 .type
= AMD_IP_BLOCK_TYPE_IH
,
796 .funcs
= &tonga_ih_ip_funcs
,
799 .type
= AMD_IP_BLOCK_TYPE_SMC
,
803 .funcs
= &amdgpu_pp_ip_funcs
,
806 .type
= AMD_IP_BLOCK_TYPE_DCE
,
810 .funcs
= &dce_v10_0_ip_funcs
,
813 .type
= AMD_IP_BLOCK_TYPE_GFX
,
817 .funcs
= &gfx_v8_0_ip_funcs
,
820 .type
= AMD_IP_BLOCK_TYPE_SDMA
,
824 .funcs
= &sdma_v3_0_ip_funcs
,
827 .type
= AMD_IP_BLOCK_TYPE_UVD
,
831 .funcs
= &uvd_v5_0_ip_funcs
,
834 .type
= AMD_IP_BLOCK_TYPE_VCE
,
838 .funcs
= &vce_v3_0_ip_funcs
,
842 static const struct amdgpu_ip_block_version fiji_ip_blocks
[] =
846 .type
= AMD_IP_BLOCK_TYPE_COMMON
,
850 .funcs
= &vi_common_ip_funcs
,
853 .type
= AMD_IP_BLOCK_TYPE_GMC
,
857 .funcs
= &gmc_v8_0_ip_funcs
,
860 .type
= AMD_IP_BLOCK_TYPE_IH
,
864 .funcs
= &tonga_ih_ip_funcs
,
867 .type
= AMD_IP_BLOCK_TYPE_SMC
,
871 .funcs
= &amdgpu_pp_ip_funcs
,
874 .type
= AMD_IP_BLOCK_TYPE_DCE
,
878 .funcs
= &dce_v10_0_ip_funcs
,
881 .type
= AMD_IP_BLOCK_TYPE_GFX
,
885 .funcs
= &gfx_v8_0_ip_funcs
,
888 .type
= AMD_IP_BLOCK_TYPE_SDMA
,
892 .funcs
= &sdma_v3_0_ip_funcs
,
895 .type
= AMD_IP_BLOCK_TYPE_UVD
,
899 .funcs
= &uvd_v6_0_ip_funcs
,
902 .type
= AMD_IP_BLOCK_TYPE_VCE
,
906 .funcs
= &vce_v3_0_ip_funcs
,
910 static const struct amdgpu_ip_block_version cz_ip_blocks
[] =
914 .type
= AMD_IP_BLOCK_TYPE_COMMON
,
918 .funcs
= &vi_common_ip_funcs
,
921 .type
= AMD_IP_BLOCK_TYPE_GMC
,
925 .funcs
= &gmc_v8_0_ip_funcs
,
928 .type
= AMD_IP_BLOCK_TYPE_IH
,
932 .funcs
= &cz_ih_ip_funcs
,
935 .type
= AMD_IP_BLOCK_TYPE_SMC
,
939 .funcs
= &amdgpu_pp_ip_funcs
942 .type
= AMD_IP_BLOCK_TYPE_DCE
,
946 .funcs
= &dce_v11_0_ip_funcs
,
949 .type
= AMD_IP_BLOCK_TYPE_GFX
,
953 .funcs
= &gfx_v8_0_ip_funcs
,
956 .type
= AMD_IP_BLOCK_TYPE_SDMA
,
960 .funcs
= &sdma_v3_0_ip_funcs
,
963 .type
= AMD_IP_BLOCK_TYPE_UVD
,
967 .funcs
= &uvd_v6_0_ip_funcs
,
970 .type
= AMD_IP_BLOCK_TYPE_VCE
,
974 .funcs
= &vce_v3_0_ip_funcs
,
976 #if defined(CONFIG_DRM_AMD_ACP)
978 .type
= AMD_IP_BLOCK_TYPE_ACP
,
982 .funcs
= &acp_ip_funcs
,
987 int vi_set_ip_blocks(struct amdgpu_device
*adev
)
989 switch (adev
->asic_type
) {
991 adev
->ip_blocks
= topaz_ip_blocks
;
992 adev
->num_ip_blocks
= ARRAY_SIZE(topaz_ip_blocks
);
995 adev
->ip_blocks
= fiji_ip_blocks
;
996 adev
->num_ip_blocks
= ARRAY_SIZE(fiji_ip_blocks
);
999 adev
->ip_blocks
= tonga_ip_blocks
;
1000 adev
->num_ip_blocks
= ARRAY_SIZE(tonga_ip_blocks
);
1004 adev
->ip_blocks
= cz_ip_blocks
;
1005 adev
->num_ip_blocks
= ARRAY_SIZE(cz_ip_blocks
);
1008 /* FIXME: not supported yet */
1015 #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1016 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1017 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
1019 static uint32_t vi_get_rev_id(struct amdgpu_device
*adev
)
1021 if (adev
->flags
& AMD_IS_APU
)
1022 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS
) & ATI_REV_ID_FUSE_MACRO__MASK
)
1023 >> ATI_REV_ID_FUSE_MACRO__SHIFT
;
1025 return (RREG32(mmPCIE_EFUSE4
) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK
)
1026 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT
;
1029 static const struct amdgpu_asic_funcs vi_asic_funcs
=
1031 .read_disabled_bios
= &vi_read_disabled_bios
,
1032 .read_bios_from_rom
= &vi_read_bios_from_rom
,
1033 .read_register
= &vi_read_register
,
1034 .reset
= &vi_asic_reset
,
1035 .set_vga_state
= &vi_vga_set_state
,
1036 .get_xclk
= &vi_get_xclk
,
1037 .set_uvd_clocks
= &vi_set_uvd_clocks
,
1038 .set_vce_clocks
= &vi_set_vce_clocks
,
1039 .get_cu_info
= &gfx_v8_0_get_cu_info
,
1040 /* these should be moved to their own ip modules */
1041 .get_gpu_clock_counter
= &gfx_v8_0_get_gpu_clock_counter
,
1042 .wait_for_mc_idle
= &gmc_v8_0_mc_wait_for_idle
,
1045 static int vi_common_early_init(void *handle
)
1047 bool smc_enabled
= false;
1048 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1050 if (adev
->flags
& AMD_IS_APU
) {
1051 adev
->smc_rreg
= &cz_smc_rreg
;
1052 adev
->smc_wreg
= &cz_smc_wreg
;
1054 adev
->smc_rreg
= &vi_smc_rreg
;
1055 adev
->smc_wreg
= &vi_smc_wreg
;
1057 adev
->pcie_rreg
= &vi_pcie_rreg
;
1058 adev
->pcie_wreg
= &vi_pcie_wreg
;
1059 adev
->uvd_ctx_rreg
= &vi_uvd_ctx_rreg
;
1060 adev
->uvd_ctx_wreg
= &vi_uvd_ctx_wreg
;
1061 adev
->didt_rreg
= &vi_didt_rreg
;
1062 adev
->didt_wreg
= &vi_didt_wreg
;
1064 adev
->asic_funcs
= &vi_asic_funcs
;
1066 if (amdgpu_get_ip_block(adev
, AMD_IP_BLOCK_TYPE_SMC
) &&
1067 (amdgpu_ip_block_mask
& (1 << AMD_IP_BLOCK_TYPE_SMC
)))
1070 adev
->rev_id
= vi_get_rev_id(adev
);
1071 adev
->external_rev_id
= 0xFF;
1072 switch (adev
->asic_type
) {
1076 adev
->external_rev_id
= 0x1;
1079 adev
->cg_flags
= AMD_CG_SUPPORT_GFX_MGCG
|
1080 AMD_CG_SUPPORT_GFX_MGLS
|
1081 AMD_CG_SUPPORT_GFX_RLC_LS
|
1082 AMD_CG_SUPPORT_GFX_CP_LS
|
1083 AMD_CG_SUPPORT_GFX_CGTS
|
1084 AMD_CG_SUPPORT_GFX_CGTS_LS
|
1085 AMD_CG_SUPPORT_GFX_CGCG
|
1086 AMD_CG_SUPPORT_GFX_CGLS
|
1087 AMD_CG_SUPPORT_SDMA_MGCG
|
1088 AMD_CG_SUPPORT_SDMA_LS
|
1089 AMD_CG_SUPPORT_BIF_LS
|
1090 AMD_CG_SUPPORT_HDP_MGCG
|
1091 AMD_CG_SUPPORT_HDP_LS
|
1092 AMD_CG_SUPPORT_ROM_MGCG
|
1093 AMD_CG_SUPPORT_MC_MGCG
|
1094 AMD_CG_SUPPORT_MC_LS
;
1096 adev
->external_rev_id
= adev
->rev_id
+ 0x3c;
1099 adev
->cg_flags
= AMD_CG_SUPPORT_UVD_MGCG
;
1101 adev
->external_rev_id
= adev
->rev_id
+ 0x14;
1104 adev
->cg_flags
= AMD_CG_SUPPORT_GFX_MGCG
|
1105 AMD_CG_SUPPORT_GFX_MGLS
|
1106 AMD_CG_SUPPORT_GFX_RLC_LS
|
1107 AMD_CG_SUPPORT_GFX_CP_LS
|
1108 AMD_CG_SUPPORT_GFX_CGTS
|
1109 AMD_CG_SUPPORT_GFX_MGLS
|
1110 AMD_CG_SUPPORT_GFX_CGTS_LS
|
1111 AMD_CG_SUPPORT_GFX_CGCG
|
1112 AMD_CG_SUPPORT_GFX_CGLS
|
1113 AMD_CG_SUPPORT_BIF_LS
|
1114 AMD_CG_SUPPORT_HDP_MGCG
|
1115 AMD_CG_SUPPORT_HDP_LS
;
1117 adev
->external_rev_id
= adev
->rev_id
+ 0x1;
1120 adev
->cg_flags
= AMD_CG_SUPPORT_UVD_MGCG
|
1121 AMD_CG_SUPPORT_GFX_MGCG
|
1122 AMD_CG_SUPPORT_GFX_MGLS
;
1124 adev
->external_rev_id
= adev
->rev_id
+ 0x1;
1127 /* FIXME: not supported yet */
1131 if (amdgpu_smc_load_fw
&& smc_enabled
)
1132 adev
->firmware
.smu_load
= true;
1134 amdgpu_get_pcie_info(adev
);
1139 static int vi_common_sw_init(void *handle
)
1144 static int vi_common_sw_fini(void *handle
)
1149 static int vi_common_hw_init(void *handle
)
1151 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1153 /* move the golden regs per IP block */
1154 vi_init_golden_registers(adev
);
1155 /* enable pcie gen2/3 link */
1156 vi_pcie_gen3_enable(adev
);
1158 vi_program_aspm(adev
);
1159 /* enable the doorbell aperture */
1160 vi_enable_doorbell_aperture(adev
, true);
1165 static int vi_common_hw_fini(void *handle
)
1167 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1169 /* enable the doorbell aperture */
1170 vi_enable_doorbell_aperture(adev
, false);
1175 static int vi_common_suspend(void *handle
)
1177 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1179 return vi_common_hw_fini(adev
);
1182 static int vi_common_resume(void *handle
)
1184 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1186 return vi_common_hw_init(adev
);
1189 static bool vi_common_is_idle(void *handle
)
1194 static int vi_common_wait_for_idle(void *handle
)
1199 static void vi_common_print_status(void *handle
)
1204 static int vi_common_soft_reset(void *handle
)
1209 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device
*adev
,
1212 uint32_t temp
, data
;
1214 temp
= data
= RREG32_PCIE(ixPCIE_CNTL2
);
1216 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_BIF_LS
))
1217 data
|= PCIE_CNTL2__SLV_MEM_LS_EN_MASK
|
1218 PCIE_CNTL2__MST_MEM_LS_EN_MASK
|
1219 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK
;
1221 data
&= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK
|
1222 PCIE_CNTL2__MST_MEM_LS_EN_MASK
|
1223 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK
);
1226 WREG32_PCIE(ixPCIE_CNTL2
, data
);
1229 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device
*adev
,
1232 uint32_t temp
, data
;
1234 temp
= data
= RREG32(mmHDP_HOST_PATH_CNTL
);
1236 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_HDP_MGCG
))
1237 data
&= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK
;
1239 data
|= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK
;
1242 WREG32(mmHDP_HOST_PATH_CNTL
, data
);
1245 static void vi_update_hdp_light_sleep(struct amdgpu_device
*adev
,
1248 uint32_t temp
, data
;
1250 temp
= data
= RREG32(mmHDP_MEM_POWER_LS
);
1252 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_HDP_LS
))
1253 data
|= HDP_MEM_POWER_LS__LS_ENABLE_MASK
;
1255 data
&= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK
;
1258 WREG32(mmHDP_MEM_POWER_LS
, data
);
1261 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device
*adev
,
1264 uint32_t temp
, data
;
1266 temp
= data
= RREG32_SMC(ixCGTT_ROM_CLK_CTRL0
);
1268 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_ROM_MGCG
))
1269 data
&= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
|
1270 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK
);
1272 data
|= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK
|
1273 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK
;
1276 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0
, data
);
1279 static int vi_common_set_clockgating_state(void *handle
,
1280 enum amd_clockgating_state state
)
1282 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1284 switch (adev
->asic_type
) {
1286 vi_update_bif_medium_grain_light_sleep(adev
,
1287 state
== AMD_CG_STATE_GATE
? true : false);
1288 vi_update_hdp_medium_grain_clock_gating(adev
,
1289 state
== AMD_CG_STATE_GATE
? true : false);
1290 vi_update_hdp_light_sleep(adev
,
1291 state
== AMD_CG_STATE_GATE
? true : false);
1292 vi_update_rom_medium_grain_clock_gating(adev
,
1293 state
== AMD_CG_STATE_GATE
? true : false);
1297 vi_update_bif_medium_grain_light_sleep(adev
,
1298 state
== AMD_CG_STATE_GATE
? true : false);
1299 vi_update_hdp_medium_grain_clock_gating(adev
,
1300 state
== AMD_CG_STATE_GATE
? true : false);
1301 vi_update_hdp_light_sleep(adev
,
1302 state
== AMD_CG_STATE_GATE
? true : false);
1310 static int vi_common_set_powergating_state(void *handle
,
1311 enum amd_powergating_state state
)
1316 const struct amd_ip_funcs vi_common_ip_funcs
= {
1317 .early_init
= vi_common_early_init
,
1319 .sw_init
= vi_common_sw_init
,
1320 .sw_fini
= vi_common_sw_fini
,
1321 .hw_init
= vi_common_hw_init
,
1322 .hw_fini
= vi_common_hw_fini
,
1323 .suspend
= vi_common_suspend
,
1324 .resume
= vi_common_resume
,
1325 .is_idle
= vi_common_is_idle
,
1326 .wait_for_idle
= vi_common_wait_for_idle
,
1327 .soft_reset
= vi_common_soft_reset
,
1328 .print_status
= vi_common_print_status
,
1329 .set_clockgating_state
= vi_common_set_clockgating_state
,
1330 .set_powergating_state
= vi_common_set_powergating_state
,