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drm/amdgpu: allow userspace to read more debug registers
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / vi.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include "drmP.h"
27 #include "amdgpu.h"
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
33 #include "atom.h"
34
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
37
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40
41 #include "bif/bif_5_0_d.h"
42 #include "bif/bif_5_0_sh_mask.h"
43
44 #include "gca/gfx_8_0_d.h"
45 #include "gca/gfx_8_0_sh_mask.h"
46
47 #include "smu/smu_7_1_1_d.h"
48 #include "smu/smu_7_1_1_sh_mask.h"
49
50 #include "uvd/uvd_5_0_d.h"
51 #include "uvd/uvd_5_0_sh_mask.h"
52
53 #include "vce/vce_3_0_d.h"
54 #include "vce/vce_3_0_sh_mask.h"
55
56 #include "dce/dce_10_0_d.h"
57 #include "dce/dce_10_0_sh_mask.h"
58
59 #include "vid.h"
60 #include "vi.h"
61 #include "vi_dpm.h"
62 #include "gmc_v8_0.h"
63 #include "gfx_v8_0.h"
64 #include "sdma_v2_4.h"
65 #include "sdma_v3_0.h"
66 #include "dce_v10_0.h"
67 #include "dce_v11_0.h"
68 #include "iceland_ih.h"
69 #include "tonga_ih.h"
70 #include "cz_ih.h"
71 #include "uvd_v5_0.h"
72 #include "uvd_v6_0.h"
73 #include "vce_v3_0.h"
74
75 /*
76 * Indirect registers accessor
77 */
78 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
79 {
80 unsigned long flags;
81 u32 r;
82
83 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
84 WREG32(mmPCIE_INDEX, reg);
85 (void)RREG32(mmPCIE_INDEX);
86 r = RREG32(mmPCIE_DATA);
87 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
88 return r;
89 }
90
91 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
92 {
93 unsigned long flags;
94
95 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
96 WREG32(mmPCIE_INDEX, reg);
97 (void)RREG32(mmPCIE_INDEX);
98 WREG32(mmPCIE_DATA, v);
99 (void)RREG32(mmPCIE_DATA);
100 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
101 }
102
103 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
104 {
105 unsigned long flags;
106 u32 r;
107
108 spin_lock_irqsave(&adev->smc_idx_lock, flags);
109 WREG32(mmSMC_IND_INDEX_0, (reg));
110 r = RREG32(mmSMC_IND_DATA_0);
111 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
112 return r;
113 }
114
115 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
116 {
117 unsigned long flags;
118
119 spin_lock_irqsave(&adev->smc_idx_lock, flags);
120 WREG32(mmSMC_IND_INDEX_0, (reg));
121 WREG32(mmSMC_IND_DATA_0, (v));
122 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
123 }
124
125 /* smu_8_0_d.h */
126 #define mmMP0PUB_IND_INDEX 0x180
127 #define mmMP0PUB_IND_DATA 0x181
128
129 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
130 {
131 unsigned long flags;
132 u32 r;
133
134 spin_lock_irqsave(&adev->smc_idx_lock, flags);
135 WREG32(mmMP0PUB_IND_INDEX, (reg));
136 r = RREG32(mmMP0PUB_IND_DATA);
137 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
138 return r;
139 }
140
141 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
142 {
143 unsigned long flags;
144
145 spin_lock_irqsave(&adev->smc_idx_lock, flags);
146 WREG32(mmMP0PUB_IND_INDEX, (reg));
147 WREG32(mmMP0PUB_IND_DATA, (v));
148 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
149 }
150
151 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
152 {
153 unsigned long flags;
154 u32 r;
155
156 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
157 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
158 r = RREG32(mmUVD_CTX_DATA);
159 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
160 return r;
161 }
162
163 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
164 {
165 unsigned long flags;
166
167 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
168 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
169 WREG32(mmUVD_CTX_DATA, (v));
170 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
171 }
172
173 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
174 {
175 unsigned long flags;
176 u32 r;
177
178 spin_lock_irqsave(&adev->didt_idx_lock, flags);
179 WREG32(mmDIDT_IND_INDEX, (reg));
180 r = RREG32(mmDIDT_IND_DATA);
181 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
182 return r;
183 }
184
185 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
186 {
187 unsigned long flags;
188
189 spin_lock_irqsave(&adev->didt_idx_lock, flags);
190 WREG32(mmDIDT_IND_INDEX, (reg));
191 WREG32(mmDIDT_IND_DATA, (v));
192 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
193 }
194
195 static const u32 tonga_mgcg_cgcg_init[] =
196 {
197 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
198 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
199 mmPCIE_DATA, 0x000f0000, 0x00000000,
200 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
201 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
202 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
203 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
204 };
205
206 static const u32 iceland_mgcg_cgcg_init[] =
207 {
208 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
209 mmPCIE_DATA, 0x000f0000, 0x00000000,
210 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
211 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
212 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
213 };
214
215 static const u32 cz_mgcg_cgcg_init[] =
216 {
217 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
218 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
219 mmPCIE_DATA, 0x000f0000, 0x00000000,
220 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
221 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
222 };
223
224 static void vi_init_golden_registers(struct amdgpu_device *adev)
225 {
226 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
227 mutex_lock(&adev->grbm_idx_mutex);
228
229 switch (adev->asic_type) {
230 case CHIP_TOPAZ:
231 amdgpu_program_register_sequence(adev,
232 iceland_mgcg_cgcg_init,
233 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
234 break;
235 case CHIP_TONGA:
236 amdgpu_program_register_sequence(adev,
237 tonga_mgcg_cgcg_init,
238 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
239 break;
240 case CHIP_CARRIZO:
241 amdgpu_program_register_sequence(adev,
242 cz_mgcg_cgcg_init,
243 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
244 break;
245 default:
246 break;
247 }
248 mutex_unlock(&adev->grbm_idx_mutex);
249 }
250
251 /**
252 * vi_get_xclk - get the xclk
253 *
254 * @adev: amdgpu_device pointer
255 *
256 * Returns the reference clock used by the gfx engine
257 * (VI).
258 */
259 static u32 vi_get_xclk(struct amdgpu_device *adev)
260 {
261 u32 reference_clock = adev->clock.spll.reference_freq;
262 u32 tmp;
263
264 if (adev->flags & AMDGPU_IS_APU)
265 return reference_clock;
266
267 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
268 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
269 return 1000;
270
271 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
272 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
273 return reference_clock / 4;
274
275 return reference_clock;
276 }
277
278 /**
279 * vi_srbm_select - select specific register instances
280 *
281 * @adev: amdgpu_device pointer
282 * @me: selected ME (micro engine)
283 * @pipe: pipe
284 * @queue: queue
285 * @vmid: VMID
286 *
287 * Switches the currently active registers instances. Some
288 * registers are instanced per VMID, others are instanced per
289 * me/pipe/queue combination.
290 */
291 void vi_srbm_select(struct amdgpu_device *adev,
292 u32 me, u32 pipe, u32 queue, u32 vmid)
293 {
294 u32 srbm_gfx_cntl = 0;
295 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
296 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
297 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
298 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
299 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
300 }
301
302 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
303 {
304 /* todo */
305 }
306
307 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
308 {
309 u32 bus_cntl;
310 u32 d1vga_control = 0;
311 u32 d2vga_control = 0;
312 u32 vga_render_control = 0;
313 u32 rom_cntl;
314 bool r;
315
316 bus_cntl = RREG32(mmBUS_CNTL);
317 if (adev->mode_info.num_crtc) {
318 d1vga_control = RREG32(mmD1VGA_CONTROL);
319 d2vga_control = RREG32(mmD2VGA_CONTROL);
320 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
321 }
322 rom_cntl = RREG32_SMC(ixROM_CNTL);
323
324 /* enable the rom */
325 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
326 if (adev->mode_info.num_crtc) {
327 /* Disable VGA mode */
328 WREG32(mmD1VGA_CONTROL,
329 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
330 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
331 WREG32(mmD2VGA_CONTROL,
332 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
333 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
334 WREG32(mmVGA_RENDER_CONTROL,
335 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
336 }
337 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
338
339 r = amdgpu_read_bios(adev);
340
341 /* restore regs */
342 WREG32(mmBUS_CNTL, bus_cntl);
343 if (adev->mode_info.num_crtc) {
344 WREG32(mmD1VGA_CONTROL, d1vga_control);
345 WREG32(mmD2VGA_CONTROL, d2vga_control);
346 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
347 }
348 WREG32_SMC(ixROM_CNTL, rom_cntl);
349 return r;
350 }
351 static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
352 {mmGB_MACROTILE_MODE7, true},
353 };
354
355 static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
356 {mmGB_TILE_MODE7, true},
357 {mmGB_TILE_MODE12, true},
358 {mmGB_TILE_MODE17, true},
359 {mmGB_TILE_MODE23, true},
360 {mmGB_MACROTILE_MODE7, true},
361 };
362
363 static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
364 {mmGRBM_STATUS, false},
365 {mmGRBM_STATUS2, false},
366 {mmGRBM_STATUS_SE0, false},
367 {mmGRBM_STATUS_SE1, false},
368 {mmGRBM_STATUS_SE2, false},
369 {mmGRBM_STATUS_SE3, false},
370 {mmSRBM_STATUS, false},
371 {mmSRBM_STATUS2, false},
372 {mmSRBM_STATUS3, false},
373 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
374 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
375 {mmCP_STAT, false},
376 {mmCP_STALLED_STAT1, false},
377 {mmCP_STALLED_STAT2, false},
378 {mmCP_STALLED_STAT3, false},
379 {mmCP_CPF_BUSY_STAT, false},
380 {mmCP_CPF_STALLED_STAT1, false},
381 {mmCP_CPF_STATUS, false},
382 {mmCP_CPC_BUSY_STAT, false},
383 {mmCP_CPC_STALLED_STAT1, false},
384 {mmCP_CPC_STATUS, false},
385 {mmGB_ADDR_CONFIG, false},
386 {mmMC_ARB_RAMCFG, false},
387 {mmGB_TILE_MODE0, false},
388 {mmGB_TILE_MODE1, false},
389 {mmGB_TILE_MODE2, false},
390 {mmGB_TILE_MODE3, false},
391 {mmGB_TILE_MODE4, false},
392 {mmGB_TILE_MODE5, false},
393 {mmGB_TILE_MODE6, false},
394 {mmGB_TILE_MODE7, false},
395 {mmGB_TILE_MODE8, false},
396 {mmGB_TILE_MODE9, false},
397 {mmGB_TILE_MODE10, false},
398 {mmGB_TILE_MODE11, false},
399 {mmGB_TILE_MODE12, false},
400 {mmGB_TILE_MODE13, false},
401 {mmGB_TILE_MODE14, false},
402 {mmGB_TILE_MODE15, false},
403 {mmGB_TILE_MODE16, false},
404 {mmGB_TILE_MODE17, false},
405 {mmGB_TILE_MODE18, false},
406 {mmGB_TILE_MODE19, false},
407 {mmGB_TILE_MODE20, false},
408 {mmGB_TILE_MODE21, false},
409 {mmGB_TILE_MODE22, false},
410 {mmGB_TILE_MODE23, false},
411 {mmGB_TILE_MODE24, false},
412 {mmGB_TILE_MODE25, false},
413 {mmGB_TILE_MODE26, false},
414 {mmGB_TILE_MODE27, false},
415 {mmGB_TILE_MODE28, false},
416 {mmGB_TILE_MODE29, false},
417 {mmGB_TILE_MODE30, false},
418 {mmGB_TILE_MODE31, false},
419 {mmGB_MACROTILE_MODE0, false},
420 {mmGB_MACROTILE_MODE1, false},
421 {mmGB_MACROTILE_MODE2, false},
422 {mmGB_MACROTILE_MODE3, false},
423 {mmGB_MACROTILE_MODE4, false},
424 {mmGB_MACROTILE_MODE5, false},
425 {mmGB_MACROTILE_MODE6, false},
426 {mmGB_MACROTILE_MODE7, false},
427 {mmGB_MACROTILE_MODE8, false},
428 {mmGB_MACROTILE_MODE9, false},
429 {mmGB_MACROTILE_MODE10, false},
430 {mmGB_MACROTILE_MODE11, false},
431 {mmGB_MACROTILE_MODE12, false},
432 {mmGB_MACROTILE_MODE13, false},
433 {mmGB_MACROTILE_MODE14, false},
434 {mmGB_MACROTILE_MODE15, false},
435 {mmCC_RB_BACKEND_DISABLE, false, true},
436 {mmGC_USER_RB_BACKEND_DISABLE, false, true},
437 {mmGB_BACKEND_MAP, false, false},
438 {mmPA_SC_RASTER_CONFIG, false, true},
439 {mmPA_SC_RASTER_CONFIG_1, false, true},
440 };
441
442 static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
443 u32 sh_num, u32 reg_offset)
444 {
445 uint32_t val;
446
447 mutex_lock(&adev->grbm_idx_mutex);
448 if (se_num != 0xffffffff || sh_num != 0xffffffff)
449 gfx_v8_0_select_se_sh(adev, se_num, sh_num);
450
451 val = RREG32(reg_offset);
452
453 if (se_num != 0xffffffff || sh_num != 0xffffffff)
454 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
455 mutex_unlock(&adev->grbm_idx_mutex);
456 return val;
457 }
458
459 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
460 u32 sh_num, u32 reg_offset, u32 *value)
461 {
462 struct amdgpu_allowed_register_entry *asic_register_table = NULL;
463 struct amdgpu_allowed_register_entry *asic_register_entry;
464 uint32_t size, i;
465
466 *value = 0;
467 switch (adev->asic_type) {
468 case CHIP_TOPAZ:
469 asic_register_table = tonga_allowed_read_registers;
470 size = ARRAY_SIZE(tonga_allowed_read_registers);
471 break;
472 case CHIP_TONGA:
473 case CHIP_CARRIZO:
474 asic_register_table = cz_allowed_read_registers;
475 size = ARRAY_SIZE(cz_allowed_read_registers);
476 break;
477 default:
478 return -EINVAL;
479 }
480
481 if (asic_register_table) {
482 for (i = 0; i < size; i++) {
483 asic_register_entry = asic_register_table + i;
484 if (reg_offset != asic_register_entry->reg_offset)
485 continue;
486 if (!asic_register_entry->untouched)
487 *value = asic_register_entry->grbm_indexed ?
488 vi_read_indexed_register(adev, se_num,
489 sh_num, reg_offset) :
490 RREG32(reg_offset);
491 return 0;
492 }
493 }
494
495 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
496 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
497 continue;
498
499 if (!vi_allowed_read_registers[i].untouched)
500 *value = vi_allowed_read_registers[i].grbm_indexed ?
501 vi_read_indexed_register(adev, se_num,
502 sh_num, reg_offset) :
503 RREG32(reg_offset);
504 return 0;
505 }
506 return -EINVAL;
507 }
508
509 static void vi_print_gpu_status_regs(struct amdgpu_device *adev)
510 {
511 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
512 RREG32(mmGRBM_STATUS));
513 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
514 RREG32(mmGRBM_STATUS2));
515 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
516 RREG32(mmGRBM_STATUS_SE0));
517 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
518 RREG32(mmGRBM_STATUS_SE1));
519 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
520 RREG32(mmGRBM_STATUS_SE2));
521 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
522 RREG32(mmGRBM_STATUS_SE3));
523 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
524 RREG32(mmSRBM_STATUS));
525 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
526 RREG32(mmSRBM_STATUS2));
527 dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
528 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
529 dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
530 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
531 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
532 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
533 RREG32(mmCP_STALLED_STAT1));
534 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
535 RREG32(mmCP_STALLED_STAT2));
536 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
537 RREG32(mmCP_STALLED_STAT3));
538 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
539 RREG32(mmCP_CPF_BUSY_STAT));
540 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
541 RREG32(mmCP_CPF_STALLED_STAT1));
542 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
543 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
544 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
545 RREG32(mmCP_CPC_STALLED_STAT1));
546 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
547 }
548
549 /**
550 * vi_gpu_check_soft_reset - check which blocks are busy
551 *
552 * @adev: amdgpu_device pointer
553 *
554 * Check which blocks are busy and return the relevant reset
555 * mask to be used by vi_gpu_soft_reset().
556 * Returns a mask of the blocks to be reset.
557 */
558 u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev)
559 {
560 u32 reset_mask = 0;
561 u32 tmp;
562
563 /* GRBM_STATUS */
564 tmp = RREG32(mmGRBM_STATUS);
565 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
566 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
567 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
568 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
569 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
570 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
571 reset_mask |= AMDGPU_RESET_GFX;
572
573 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))
574 reset_mask |= AMDGPU_RESET_CP;
575
576 /* GRBM_STATUS2 */
577 tmp = RREG32(mmGRBM_STATUS2);
578 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
579 reset_mask |= AMDGPU_RESET_RLC;
580
581 if (tmp & (GRBM_STATUS2__CPF_BUSY_MASK |
582 GRBM_STATUS2__CPC_BUSY_MASK |
583 GRBM_STATUS2__CPG_BUSY_MASK))
584 reset_mask |= AMDGPU_RESET_CP;
585
586 /* SRBM_STATUS2 */
587 tmp = RREG32(mmSRBM_STATUS2);
588 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)
589 reset_mask |= AMDGPU_RESET_DMA;
590
591 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)
592 reset_mask |= AMDGPU_RESET_DMA1;
593
594 /* SRBM_STATUS */
595 tmp = RREG32(mmSRBM_STATUS);
596
597 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
598 reset_mask |= AMDGPU_RESET_IH;
599
600 if (tmp & SRBM_STATUS__SEM_BUSY_MASK)
601 reset_mask |= AMDGPU_RESET_SEM;
602
603 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
604 reset_mask |= AMDGPU_RESET_GRBM;
605
606 if (adev->asic_type != CHIP_TOPAZ) {
607 if (tmp & (SRBM_STATUS__UVD_RQ_PENDING_MASK |
608 SRBM_STATUS__UVD_BUSY_MASK))
609 reset_mask |= AMDGPU_RESET_UVD;
610 }
611
612 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
613 reset_mask |= AMDGPU_RESET_VMC;
614
615 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
616 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK))
617 reset_mask |= AMDGPU_RESET_MC;
618
619 /* SDMA0_STATUS_REG */
620 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
621 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
622 reset_mask |= AMDGPU_RESET_DMA;
623
624 /* SDMA1_STATUS_REG */
625 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
626 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
627 reset_mask |= AMDGPU_RESET_DMA1;
628 #if 0
629 /* VCE_STATUS */
630 if (adev->asic_type != CHIP_TOPAZ) {
631 tmp = RREG32(mmVCE_STATUS);
632 if (tmp & VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK)
633 reset_mask |= AMDGPU_RESET_VCE;
634 if (tmp & VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK)
635 reset_mask |= AMDGPU_RESET_VCE1;
636
637 }
638
639 if (adev->asic_type != CHIP_TOPAZ) {
640 if (amdgpu_display_is_display_hung(adev))
641 reset_mask |= AMDGPU_RESET_DISPLAY;
642 }
643 #endif
644
645 /* Skip MC reset as it's mostly likely not hung, just busy */
646 if (reset_mask & AMDGPU_RESET_MC) {
647 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
648 reset_mask &= ~AMDGPU_RESET_MC;
649 }
650
651 return reset_mask;
652 }
653
654 /**
655 * vi_gpu_soft_reset - soft reset GPU
656 *
657 * @adev: amdgpu_device pointer
658 * @reset_mask: mask of which blocks to reset
659 *
660 * Soft reset the blocks specified in @reset_mask.
661 */
662 static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
663 {
664 struct amdgpu_mode_mc_save save;
665 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
666 u32 tmp;
667
668 if (reset_mask == 0)
669 return;
670
671 dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask);
672
673 vi_print_gpu_status_regs(adev);
674 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
675 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
676 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
677 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
678
679 /* disable CG/PG */
680
681 /* stop the rlc */
682 //XXX
683 //gfx_v8_0_rlc_stop(adev);
684
685 /* Disable GFX parsing/prefetching */
686 tmp = RREG32(mmCP_ME_CNTL);
687 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
688 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
689 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
690 WREG32(mmCP_ME_CNTL, tmp);
691
692 /* Disable MEC parsing/prefetching */
693 tmp = RREG32(mmCP_MEC_CNTL);
694 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
695 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
696 WREG32(mmCP_MEC_CNTL, tmp);
697
698 if (reset_mask & AMDGPU_RESET_DMA) {
699 /* sdma0 */
700 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
701 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
702 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
703 }
704 if (reset_mask & AMDGPU_RESET_DMA1) {
705 /* sdma1 */
706 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
707 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
708 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
709 }
710
711 gmc_v8_0_mc_stop(adev, &save);
712 if (amdgpu_asic_wait_for_mc_idle(adev)) {
713 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
714 }
715
716 if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) {
717 grbm_soft_reset =
718 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
719 grbm_soft_reset =
720 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
721 }
722
723 if (reset_mask & AMDGPU_RESET_CP) {
724 grbm_soft_reset =
725 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
726 srbm_soft_reset =
727 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
728 }
729
730 if (reset_mask & AMDGPU_RESET_DMA)
731 srbm_soft_reset =
732 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA, 1);
733
734 if (reset_mask & AMDGPU_RESET_DMA1)
735 srbm_soft_reset =
736 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1, 1);
737
738 if (reset_mask & AMDGPU_RESET_DISPLAY)
739 srbm_soft_reset =
740 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_DC, 1);
741
742 if (reset_mask & AMDGPU_RESET_RLC)
743 grbm_soft_reset =
744 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
745
746 if (reset_mask & AMDGPU_RESET_SEM)
747 srbm_soft_reset =
748 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
749
750 if (reset_mask & AMDGPU_RESET_IH)
751 srbm_soft_reset =
752 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_IH, 1);
753
754 if (reset_mask & AMDGPU_RESET_GRBM)
755 srbm_soft_reset =
756 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
757
758 if (reset_mask & AMDGPU_RESET_VMC)
759 srbm_soft_reset =
760 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
761
762 if (reset_mask & AMDGPU_RESET_UVD)
763 srbm_soft_reset =
764 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
765
766 if (reset_mask & AMDGPU_RESET_VCE)
767 srbm_soft_reset =
768 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
769
770 if (reset_mask & AMDGPU_RESET_VCE)
771 srbm_soft_reset =
772 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
773
774 if (!(adev->flags & AMDGPU_IS_APU)) {
775 if (reset_mask & AMDGPU_RESET_MC)
776 srbm_soft_reset =
777 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
778 }
779
780 if (grbm_soft_reset) {
781 tmp = RREG32(mmGRBM_SOFT_RESET);
782 tmp |= grbm_soft_reset;
783 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
784 WREG32(mmGRBM_SOFT_RESET, tmp);
785 tmp = RREG32(mmGRBM_SOFT_RESET);
786
787 udelay(50);
788
789 tmp &= ~grbm_soft_reset;
790 WREG32(mmGRBM_SOFT_RESET, tmp);
791 tmp = RREG32(mmGRBM_SOFT_RESET);
792 }
793
794 if (srbm_soft_reset) {
795 tmp = RREG32(mmSRBM_SOFT_RESET);
796 tmp |= srbm_soft_reset;
797 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
798 WREG32(mmSRBM_SOFT_RESET, tmp);
799 tmp = RREG32(mmSRBM_SOFT_RESET);
800
801 udelay(50);
802
803 tmp &= ~srbm_soft_reset;
804 WREG32(mmSRBM_SOFT_RESET, tmp);
805 tmp = RREG32(mmSRBM_SOFT_RESET);
806 }
807
808 /* Wait a little for things to settle down */
809 udelay(50);
810
811 gmc_v8_0_mc_resume(adev, &save);
812 udelay(50);
813
814 vi_print_gpu_status_regs(adev);
815 }
816
817 static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)
818 {
819 struct amdgpu_mode_mc_save save;
820 u32 tmp, i;
821
822 dev_info(adev->dev, "GPU pci config reset\n");
823
824 /* disable dpm? */
825
826 /* disable cg/pg */
827
828 /* Disable GFX parsing/prefetching */
829 tmp = RREG32(mmCP_ME_CNTL);
830 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
831 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
832 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
833 WREG32(mmCP_ME_CNTL, tmp);
834
835 /* Disable MEC parsing/prefetching */
836 tmp = RREG32(mmCP_MEC_CNTL);
837 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
838 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
839 WREG32(mmCP_MEC_CNTL, tmp);
840
841 /* Disable GFX parsing/prefetching */
842 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |
843 CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
844
845 /* Disable MEC parsing/prefetching */
846 WREG32(mmCP_MEC_CNTL,
847 CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
848
849 /* sdma0 */
850 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
851 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
852 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
853
854 /* sdma1 */
855 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
856 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
857 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
858
859 /* XXX other engines? */
860
861 /* halt the rlc, disable cp internal ints */
862 //XXX
863 //gfx_v8_0_rlc_stop(adev);
864
865 udelay(50);
866
867 /* disable mem access */
868 gmc_v8_0_mc_stop(adev, &save);
869 if (amdgpu_asic_wait_for_mc_idle(adev)) {
870 dev_warn(adev->dev, "Wait for MC idle timed out !\n");
871 }
872
873 /* disable BM */
874 pci_clear_master(adev->pdev);
875 /* reset */
876 amdgpu_pci_config_reset(adev);
877
878 udelay(100);
879
880 /* wait for asic to come out of reset */
881 for (i = 0; i < adev->usec_timeout; i++) {
882 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
883 break;
884 udelay(1);
885 }
886
887 }
888
889 static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
890 {
891 u32 tmp = RREG32(mmBIOS_SCRATCH_3);
892
893 if (hung)
894 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
895 else
896 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
897
898 WREG32(mmBIOS_SCRATCH_3, tmp);
899 }
900
901 /**
902 * vi_asic_reset - soft reset GPU
903 *
904 * @adev: amdgpu_device pointer
905 *
906 * Look up which blocks are hung and attempt
907 * to reset them.
908 * Returns 0 for success.
909 */
910 static int vi_asic_reset(struct amdgpu_device *adev)
911 {
912 u32 reset_mask;
913
914 reset_mask = vi_gpu_check_soft_reset(adev);
915
916 if (reset_mask)
917 vi_set_bios_scratch_engine_hung(adev, true);
918
919 /* try soft reset */
920 vi_gpu_soft_reset(adev, reset_mask);
921
922 reset_mask = vi_gpu_check_soft_reset(adev);
923
924 /* try pci config reset */
925 if (reset_mask && amdgpu_hard_reset)
926 vi_gpu_pci_config_reset(adev);
927
928 reset_mask = vi_gpu_check_soft_reset(adev);
929
930 if (!reset_mask)
931 vi_set_bios_scratch_engine_hung(adev, false);
932
933 return 0;
934 }
935
936 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
937 u32 cntl_reg, u32 status_reg)
938 {
939 int r, i;
940 struct atom_clock_dividers dividers;
941 uint32_t tmp;
942
943 r = amdgpu_atombios_get_clock_dividers(adev,
944 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
945 clock, false, &dividers);
946 if (r)
947 return r;
948
949 tmp = RREG32_SMC(cntl_reg);
950 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
951 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
952 tmp |= dividers.post_divider;
953 WREG32_SMC(cntl_reg, tmp);
954
955 for (i = 0; i < 100; i++) {
956 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
957 break;
958 mdelay(10);
959 }
960 if (i == 100)
961 return -ETIMEDOUT;
962
963 return 0;
964 }
965
966 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
967 {
968 int r;
969
970 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
971 if (r)
972 return r;
973
974 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
975
976 return 0;
977 }
978
979 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
980 {
981 /* todo */
982
983 return 0;
984 }
985
986 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
987 {
988 u32 mask;
989 int ret;
990
991 if (amdgpu_pcie_gen2 == 0)
992 return;
993
994 if (adev->flags & AMDGPU_IS_APU)
995 return;
996
997 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
998 if (ret != 0)
999 return;
1000
1001 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1002 return;
1003
1004 /* todo */
1005 }
1006
1007 static void vi_program_aspm(struct amdgpu_device *adev)
1008 {
1009
1010 if (amdgpu_aspm == 0)
1011 return;
1012
1013 /* todo */
1014 }
1015
1016 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
1017 bool enable)
1018 {
1019 u32 tmp;
1020
1021 /* not necessary on CZ */
1022 if (adev->flags & AMDGPU_IS_APU)
1023 return;
1024
1025 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
1026 if (enable)
1027 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
1028 else
1029 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
1030
1031 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
1032 }
1033
1034 /* topaz has no DCE, UVD, VCE */
1035 static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
1036 {
1037 /* ORDER MATTERS! */
1038 {
1039 .type = AMD_IP_BLOCK_TYPE_COMMON,
1040 .major = 2,
1041 .minor = 0,
1042 .rev = 0,
1043 .funcs = &vi_common_ip_funcs,
1044 },
1045 {
1046 .type = AMD_IP_BLOCK_TYPE_GMC,
1047 .major = 8,
1048 .minor = 0,
1049 .rev = 0,
1050 .funcs = &gmc_v8_0_ip_funcs,
1051 },
1052 {
1053 .type = AMD_IP_BLOCK_TYPE_IH,
1054 .major = 2,
1055 .minor = 4,
1056 .rev = 0,
1057 .funcs = &iceland_ih_ip_funcs,
1058 },
1059 {
1060 .type = AMD_IP_BLOCK_TYPE_SMC,
1061 .major = 7,
1062 .minor = 1,
1063 .rev = 0,
1064 .funcs = &iceland_dpm_ip_funcs,
1065 },
1066 {
1067 .type = AMD_IP_BLOCK_TYPE_GFX,
1068 .major = 8,
1069 .minor = 0,
1070 .rev = 0,
1071 .funcs = &gfx_v8_0_ip_funcs,
1072 },
1073 {
1074 .type = AMD_IP_BLOCK_TYPE_SDMA,
1075 .major = 2,
1076 .minor = 4,
1077 .rev = 0,
1078 .funcs = &sdma_v2_4_ip_funcs,
1079 },
1080 };
1081
1082 static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
1083 {
1084 /* ORDER MATTERS! */
1085 {
1086 .type = AMD_IP_BLOCK_TYPE_COMMON,
1087 .major = 2,
1088 .minor = 0,
1089 .rev = 0,
1090 .funcs = &vi_common_ip_funcs,
1091 },
1092 {
1093 .type = AMD_IP_BLOCK_TYPE_GMC,
1094 .major = 8,
1095 .minor = 0,
1096 .rev = 0,
1097 .funcs = &gmc_v8_0_ip_funcs,
1098 },
1099 {
1100 .type = AMD_IP_BLOCK_TYPE_IH,
1101 .major = 3,
1102 .minor = 0,
1103 .rev = 0,
1104 .funcs = &tonga_ih_ip_funcs,
1105 },
1106 {
1107 .type = AMD_IP_BLOCK_TYPE_SMC,
1108 .major = 7,
1109 .minor = 1,
1110 .rev = 0,
1111 .funcs = &tonga_dpm_ip_funcs,
1112 },
1113 {
1114 .type = AMD_IP_BLOCK_TYPE_DCE,
1115 .major = 10,
1116 .minor = 0,
1117 .rev = 0,
1118 .funcs = &dce_v10_0_ip_funcs,
1119 },
1120 {
1121 .type = AMD_IP_BLOCK_TYPE_GFX,
1122 .major = 8,
1123 .minor = 0,
1124 .rev = 0,
1125 .funcs = &gfx_v8_0_ip_funcs,
1126 },
1127 {
1128 .type = AMD_IP_BLOCK_TYPE_SDMA,
1129 .major = 3,
1130 .minor = 0,
1131 .rev = 0,
1132 .funcs = &sdma_v3_0_ip_funcs,
1133 },
1134 {
1135 .type = AMD_IP_BLOCK_TYPE_UVD,
1136 .major = 5,
1137 .minor = 0,
1138 .rev = 0,
1139 .funcs = &uvd_v5_0_ip_funcs,
1140 },
1141 {
1142 .type = AMD_IP_BLOCK_TYPE_VCE,
1143 .major = 3,
1144 .minor = 0,
1145 .rev = 0,
1146 .funcs = &vce_v3_0_ip_funcs,
1147 },
1148 };
1149
1150 static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1151 {
1152 /* ORDER MATTERS! */
1153 {
1154 .type = AMD_IP_BLOCK_TYPE_COMMON,
1155 .major = 2,
1156 .minor = 0,
1157 .rev = 0,
1158 .funcs = &vi_common_ip_funcs,
1159 },
1160 {
1161 .type = AMD_IP_BLOCK_TYPE_GMC,
1162 .major = 8,
1163 .minor = 0,
1164 .rev = 0,
1165 .funcs = &gmc_v8_0_ip_funcs,
1166 },
1167 {
1168 .type = AMD_IP_BLOCK_TYPE_IH,
1169 .major = 3,
1170 .minor = 0,
1171 .rev = 0,
1172 .funcs = &cz_ih_ip_funcs,
1173 },
1174 {
1175 .type = AMD_IP_BLOCK_TYPE_SMC,
1176 .major = 8,
1177 .minor = 0,
1178 .rev = 0,
1179 .funcs = &cz_dpm_ip_funcs,
1180 },
1181 {
1182 .type = AMD_IP_BLOCK_TYPE_DCE,
1183 .major = 11,
1184 .minor = 0,
1185 .rev = 0,
1186 .funcs = &dce_v11_0_ip_funcs,
1187 },
1188 {
1189 .type = AMD_IP_BLOCK_TYPE_GFX,
1190 .major = 8,
1191 .minor = 0,
1192 .rev = 0,
1193 .funcs = &gfx_v8_0_ip_funcs,
1194 },
1195 {
1196 .type = AMD_IP_BLOCK_TYPE_SDMA,
1197 .major = 3,
1198 .minor = 0,
1199 .rev = 0,
1200 .funcs = &sdma_v3_0_ip_funcs,
1201 },
1202 {
1203 .type = AMD_IP_BLOCK_TYPE_UVD,
1204 .major = 6,
1205 .minor = 0,
1206 .rev = 0,
1207 .funcs = &uvd_v6_0_ip_funcs,
1208 },
1209 {
1210 .type = AMD_IP_BLOCK_TYPE_VCE,
1211 .major = 3,
1212 .minor = 0,
1213 .rev = 0,
1214 .funcs = &vce_v3_0_ip_funcs,
1215 },
1216 };
1217
1218 int vi_set_ip_blocks(struct amdgpu_device *adev)
1219 {
1220 switch (adev->asic_type) {
1221 case CHIP_TOPAZ:
1222 adev->ip_blocks = topaz_ip_blocks;
1223 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1224 break;
1225 case CHIP_TONGA:
1226 adev->ip_blocks = tonga_ip_blocks;
1227 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1228 break;
1229 case CHIP_CARRIZO:
1230 adev->ip_blocks = cz_ip_blocks;
1231 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1232 break;
1233 default:
1234 /* FIXME: not supported yet */
1235 return -EINVAL;
1236 }
1237
1238 return 0;
1239 }
1240
1241 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1242 {
1243 if (adev->asic_type == CHIP_TOPAZ)
1244 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1245 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
1246 else
1247 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1248 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1249 }
1250
1251 static const struct amdgpu_asic_funcs vi_asic_funcs =
1252 {
1253 .read_disabled_bios = &vi_read_disabled_bios,
1254 .read_register = &vi_read_register,
1255 .reset = &vi_asic_reset,
1256 .set_vga_state = &vi_vga_set_state,
1257 .get_xclk = &vi_get_xclk,
1258 .set_uvd_clocks = &vi_set_uvd_clocks,
1259 .set_vce_clocks = &vi_set_vce_clocks,
1260 .get_cu_info = &gfx_v8_0_get_cu_info,
1261 /* these should be moved to their own ip modules */
1262 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
1263 .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
1264 };
1265
1266 static int vi_common_early_init(void *handle)
1267 {
1268 bool smc_enabled = false;
1269 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1270
1271 if (adev->flags & AMDGPU_IS_APU) {
1272 adev->smc_rreg = &cz_smc_rreg;
1273 adev->smc_wreg = &cz_smc_wreg;
1274 } else {
1275 adev->smc_rreg = &vi_smc_rreg;
1276 adev->smc_wreg = &vi_smc_wreg;
1277 }
1278 adev->pcie_rreg = &vi_pcie_rreg;
1279 adev->pcie_wreg = &vi_pcie_wreg;
1280 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1281 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1282 adev->didt_rreg = &vi_didt_rreg;
1283 adev->didt_wreg = &vi_didt_wreg;
1284
1285 adev->asic_funcs = &vi_asic_funcs;
1286
1287 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
1288 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
1289 smc_enabled = true;
1290
1291 adev->rev_id = vi_get_rev_id(adev);
1292 adev->external_rev_id = 0xFF;
1293 switch (adev->asic_type) {
1294 case CHIP_TOPAZ:
1295 adev->has_uvd = false;
1296 adev->cg_flags = 0;
1297 adev->pg_flags = 0;
1298 adev->external_rev_id = 0x1;
1299 if (amdgpu_smc_load_fw && smc_enabled)
1300 adev->firmware.smu_load = true;
1301 break;
1302 case CHIP_TONGA:
1303 adev->has_uvd = true;
1304 adev->cg_flags = 0;
1305 adev->pg_flags = 0;
1306 adev->external_rev_id = adev->rev_id + 0x14;
1307 if (amdgpu_smc_load_fw && smc_enabled)
1308 adev->firmware.smu_load = true;
1309 break;
1310 case CHIP_CARRIZO:
1311 adev->has_uvd = true;
1312 adev->cg_flags = 0;
1313 adev->pg_flags = AMDGPU_PG_SUPPORT_UVD | AMDGPU_PG_SUPPORT_VCE;
1314 adev->external_rev_id = adev->rev_id + 0x1;
1315 if (amdgpu_smc_load_fw && smc_enabled)
1316 adev->firmware.smu_load = true;
1317 break;
1318 default:
1319 /* FIXME: not supported yet */
1320 return -EINVAL;
1321 }
1322
1323 return 0;
1324 }
1325
1326 static int vi_common_sw_init(void *handle)
1327 {
1328 return 0;
1329 }
1330
1331 static int vi_common_sw_fini(void *handle)
1332 {
1333 return 0;
1334 }
1335
1336 static int vi_common_hw_init(void *handle)
1337 {
1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339
1340 /* move the golden regs per IP block */
1341 vi_init_golden_registers(adev);
1342 /* enable pcie gen2/3 link */
1343 vi_pcie_gen3_enable(adev);
1344 /* enable aspm */
1345 vi_program_aspm(adev);
1346 /* enable the doorbell aperture */
1347 vi_enable_doorbell_aperture(adev, true);
1348
1349 return 0;
1350 }
1351
1352 static int vi_common_hw_fini(void *handle)
1353 {
1354 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1355
1356 /* enable the doorbell aperture */
1357 vi_enable_doorbell_aperture(adev, false);
1358
1359 return 0;
1360 }
1361
1362 static int vi_common_suspend(void *handle)
1363 {
1364 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1365
1366 return vi_common_hw_fini(adev);
1367 }
1368
1369 static int vi_common_resume(void *handle)
1370 {
1371 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1372
1373 return vi_common_hw_init(adev);
1374 }
1375
1376 static bool vi_common_is_idle(void *handle)
1377 {
1378 return true;
1379 }
1380
1381 static int vi_common_wait_for_idle(void *handle)
1382 {
1383 return 0;
1384 }
1385
1386 static void vi_common_print_status(void *handle)
1387 {
1388 return;
1389 }
1390
1391 static int vi_common_soft_reset(void *handle)
1392 {
1393 return 0;
1394 }
1395
1396 static int vi_common_set_clockgating_state(void *handle,
1397 enum amd_clockgating_state state)
1398 {
1399 return 0;
1400 }
1401
1402 static int vi_common_set_powergating_state(void *handle,
1403 enum amd_powergating_state state)
1404 {
1405 return 0;
1406 }
1407
1408 const struct amd_ip_funcs vi_common_ip_funcs = {
1409 .early_init = vi_common_early_init,
1410 .late_init = NULL,
1411 .sw_init = vi_common_sw_init,
1412 .sw_fini = vi_common_sw_fini,
1413 .hw_init = vi_common_hw_init,
1414 .hw_fini = vi_common_hw_fini,
1415 .suspend = vi_common_suspend,
1416 .resume = vi_common_resume,
1417 .is_idle = vi_common_is_idle,
1418 .wait_for_idle = vi_common_wait_for_idle,
1419 .soft_reset = vi_common_soft_reset,
1420 .print_status = vi_common_print_status,
1421 .set_clockgating_state = vi_common_set_clockgating_state,
1422 .set_powergating_state = vi_common_set_powergating_state,
1423 };
1424
Linux kernel - Deliverables
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