drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef KFD_DEVICE_QUEUE_MANAGER_H_
  25 #define KFD_DEVICE_QUEUE_MANAGER_H_
  26
  27 #include <linux/rwsem.h>
  28 #include <linux/list.h>
  29 #include "kfd_priv.h"
  30 #include "kfd_mqd_manager.h"
  31
  32 #define QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS        (500)
  33 #define QUEUES_PER_PIPE                         (8)
  34 #define PIPE_PER_ME_CP_SCHEDULING               (3)
  35 #define CIK_VMID_NUM                            (8)
  36 #define KFD_VMID_START_OFFSET                   (8)
  37 #define VMID_PER_DEVICE                         CIK_VMID_NUM
  38 #define KFD_DQM_FIRST_PIPE                      (0)
  39 #define CIK_SDMA_QUEUES                         (4)
  40 #define CIK_SDMA_QUEUES_PER_ENGINE              (2)
  41 #define CIK_SDMA_ENGINE_NUM                     (2)
  42
  43 struct device_process_node {
  44         struct qcm_process_device *qpd;
  45         struct list_head list;
  46 };
  47
  48 /**
  49  * struct device_queue_manager_ops
  50  *
  51  * @create_queue: Queue creation routine.
  52  *
  53  * @destroy_queue: Queue destruction routine.
  54  *
  55  * @update_queue: Queue update routine.
  56  *
  57  * @get_mqd_manager: Returns the mqd manager according to the mqd type.
  58  *
  59  * @exeute_queues: Dispatches the queues list to the H/W.
  60  *
  61  * @register_process: This routine associates a specific process with device.
  62  *
  63  * @unregister_process: destroys the associations between process to device.
  64  *
  65  * @initialize: Initializes the pipelines and memory module for that device.
  66  *
  67  * @start: Initializes the resources/modules the the device needs for queues
  68  * execution. This function is called on device initialization and after the
  69  * system woke up after suspension.
  70  *
  71  * @stop: This routine stops execution of all the active queue running on the
  72  * H/W and basically this function called on system suspend.
  73  *
  74  * @uninitialize: Destroys all the device queue manager resources allocated in
  75  * initialize routine.
  76  *
  77  * @create_kernel_queue: Creates kernel queue. Used for debug queue.
  78  *
  79  * @destroy_kernel_queue: Destroys kernel queue. Used for debug queue.
  80  *
  81  * @set_cache_memory_policy: Sets memory policy (cached/ non cached) for the
  82  * memory apertures.
  83  *
  84  */
  85
  86 struct device_queue_manager_ops {
  87         int     (*create_queue)(struct device_queue_manager *dqm,
  88                                 struct queue *q,
  89                                 struct qcm_process_device *qpd,
  90                                 int *allocate_vmid);
  91         int     (*destroy_queue)(struct device_queue_manager *dqm,
  92                                 struct qcm_process_device *qpd,
  93                                 struct queue *q);
  94         int     (*update_queue)(struct device_queue_manager *dqm,
  95                                 struct queue *q);
  96
  97         struct mqd_manager * (*get_mqd_manager)
  98                                         (struct device_queue_manager *dqm,
  99                                         enum KFD_MQD_TYPE type);
 100
 101         int     (*register_process)(struct device_queue_manager *dqm,
 102                                         struct qcm_process_device *qpd);
 103         int     (*unregister_process)(struct device_queue_manager *dqm,
 104                                         struct qcm_process_device *qpd);
 105         int     (*initialize)(struct device_queue_manager *dqm);
 106         int     (*start)(struct device_queue_manager *dqm);
 107         int     (*stop)(struct device_queue_manager *dqm);
 108         void    (*uninitialize)(struct device_queue_manager *dqm);
 109         int     (*create_kernel_queue)(struct device_queue_manager *dqm,
 110                                         struct kernel_queue *kq,
 111                                         struct qcm_process_device *qpd);
 112         void    (*destroy_kernel_queue)(struct device_queue_manager *dqm,
 113                                         struct kernel_queue *kq,
 114                                         struct qcm_process_device *qpd);
 115         bool    (*set_cache_memory_policy)(struct device_queue_manager *dqm,
 116                                            struct qcm_process_device *qpd,
 117                                            enum cache_policy default_policy,
 118                                            enum cache_policy alternate_policy,
 119                                            void __user *alternate_aperture_base,
 120                                            uint64_t alternate_aperture_size);
 121 };
 122
 123 /**
 124  * struct device_queue_manager
 125  *
 126  * This struct is a base class for the kfd queues scheduler in the
 127  * device level. The device base class should expose the basic operations
 128  * for queue creation and queue destruction. This base class hides the
 129  * scheduling mode of the driver and the specific implementation of the
 130  * concrete device. This class is the only class in the queues scheduler
 131  * that configures the H/W.
 132  *
 133  */
 134
 135 struct device_queue_manager {
 136         struct device_queue_manager_ops ops;
 137         struct device_queue_manager_ops ops_asic_specific;
 138
 139         struct mqd_manager      *mqds[KFD_MQD_TYPE_MAX];
 140         struct packet_manager   packets;
 141         struct kfd_dev          *dev;
 142         struct mutex            lock;
 143         struct list_head        queues;
 144         unsigned int            processes_count;
 145         unsigned int            queue_count;
 146         unsigned int            sdma_queue_count;
 147         unsigned int            total_queue_count;
 148         unsigned int            next_pipe_to_allocate;
 149         unsigned int            *allocated_queues;
 150         unsigned int            sdma_bitmap;
 151         unsigned int            vmid_bitmap;
 152         uint64_t                pipelines_addr;
 153         struct kfd_mem_obj      *pipeline_mem;
 154         uint64_t                fence_gpu_addr;
 155         unsigned int            *fence_addr;
 156         struct kfd_mem_obj      *fence_mem;
 157         bool                    active_runlist;
 158 };
 159
 160 void device_queue_manager_init_cik(struct device_queue_manager_ops *ops);
 161 void device_queue_manager_init_vi(struct device_queue_manager_ops *ops);
 162 void program_sh_mem_settings(struct device_queue_manager *dqm,
 163                                         struct qcm_process_device *qpd);
 164 int init_pipelines(struct device_queue_manager *dqm,
 165                 unsigned int pipes_num, unsigned int first_pipe);
 166
 167 extern inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
 168 {
 169         return (pdd->lds_base >> 16) & 0xFF;
 170 }
 171
 172 extern inline unsigned int
 173 get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd)
 174 {
 175         return (pdd->lds_base >> 60) & 0x0E;
 176 }
 177
 178 extern inline unsigned int get_pipes_num(struct device_queue_manager *dqm)
 179 {
 180         BUG_ON(!dqm || !dqm->dev);
 181         return dqm->dev->shared_resources.compute_pipe_count;
 182 }
 183
 184 #endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */