2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include "kfd_device_queue_manager.h"
27 static bool set_cache_memory_policy_cik(struct device_queue_manager
*dqm
,
28 struct qcm_process_device
*qpd
,
29 enum cache_policy default_policy
,
30 enum cache_policy alternate_policy
,
31 void __user
*alternate_aperture_base
,
32 uint64_t alternate_aperture_size
);
33 static int register_process_cik(struct device_queue_manager
*dqm
,
34 struct qcm_process_device
*qpd
);
35 static int initialize_cpsch_cik(struct device_queue_manager
*dqm
);
37 void device_queue_manager_init_cik(struct device_queue_manager_ops
*ops
)
39 ops
->set_cache_memory_policy
= set_cache_memory_policy_cik
;
40 ops
->register_process
= register_process_cik
;
41 ops
->initialize
= initialize_cpsch_cik
;
44 static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble
)
46 /* In 64-bit mode, we can only control the top 3 bits of the LDS,
47 * scratch and GPUVM apertures.
48 * The hardware fills in the remaining 59 bits according to the
50 * LDS: X0000000'00000000 - X0000001'00000000 (4GB)
51 * Scratch: X0000001'00000000 - X0000002'00000000 (4GB)
52 * GPUVM: Y0010000'00000000 - Y0020000'00000000 (1TB)
54 * (where X/Y is the configurable nybble with the low-bit 0)
56 * LDS and scratch will have the same top nybble programmed in the
57 * top 3 bits of SH_MEM_BASES.PRIVATE_BASE.
58 * GPUVM can have a different top nybble programmed in the
59 * top 3 bits of SH_MEM_BASES.SHARED_BASE.
60 * We don't bother to support different top nybbles
61 * for LDS/Scratch and GPUVM.
64 BUG_ON((top_address_nybble
& 1) || top_address_nybble
> 0xE ||
65 top_address_nybble
== 0);
67 return PRIVATE_BASE(top_address_nybble
<< 12) |
68 SHARED_BASE(top_address_nybble
<< 12);
71 static bool set_cache_memory_policy_cik(struct device_queue_manager
*dqm
,
72 struct qcm_process_device
*qpd
,
73 enum cache_policy default_policy
,
74 enum cache_policy alternate_policy
,
75 void __user
*alternate_aperture_base
,
76 uint64_t alternate_aperture_size
)
78 uint32_t default_mtype
;
81 default_mtype
= (default_policy
== cache_policy_coherent
) ?
85 ape1_mtype
= (alternate_policy
== cache_policy_coherent
) ?
89 qpd
->sh_mem_config
= (qpd
->sh_mem_config
& PTR32
)
90 | ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED
)
91 | DEFAULT_MTYPE(default_mtype
)
92 | APE1_MTYPE(ape1_mtype
);
97 static int register_process_cik(struct device_queue_manager
*dqm
,
98 struct qcm_process_device
*qpd
)
100 struct kfd_process_device
*pdd
;
103 BUG_ON(!dqm
|| !qpd
);
105 pdd
= qpd_to_pdd(qpd
);
107 /* check if sh_mem_config register already configured */
108 if (qpd
->sh_mem_config
== 0) {
110 ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED
) |
111 DEFAULT_MTYPE(MTYPE_NONCACHED
) |
112 APE1_MTYPE(MTYPE_NONCACHED
);
113 qpd
->sh_mem_ape1_limit
= 0;
114 qpd
->sh_mem_ape1_base
= 0;
117 if (qpd
->pqm
->process
->is_32bit_user_mode
) {
118 temp
= get_sh_mem_bases_32(pdd
);
119 qpd
->sh_mem_bases
= SHARED_BASE(temp
);
120 qpd
->sh_mem_config
|= PTR32
;
122 temp
= get_sh_mem_bases_nybble_64(pdd
);
123 qpd
->sh_mem_bases
= compute_sh_mem_bases_64bit(temp
);
126 pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",
127 qpd
->pqm
->process
->is_32bit_user_mode
, temp
, qpd
->sh_mem_bases
);
132 static int initialize_cpsch_cik(struct device_queue_manager
*dqm
)
134 return init_pipelines(dqm
, get_pipes_num(dqm
), get_first_pipe(dqm
));