drivers/gpu/drm/amd/include/cgs_common.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _CGS_COMMON_H
  25 #define _CGS_COMMON_H
  26
  27 #include "amd_shared.h"
  28
  29 /**
  30  * enum cgs_gpu_mem_type - GPU memory types
  31  */
  32 enum cgs_gpu_mem_type {
  33         CGS_GPU_MEM_TYPE__VISIBLE_FB,
  34         CGS_GPU_MEM_TYPE__INVISIBLE_FB,
  35         CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
  36         CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
  37         CGS_GPU_MEM_TYPE__GART_CACHEABLE,
  38         CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
  39 };
  40
  41 /**
  42  * enum cgs_ind_reg - Indirect register spaces
  43  */
  44 enum cgs_ind_reg {
  45         CGS_IND_REG__MMIO,
  46         CGS_IND_REG__PCIE,
  47         CGS_IND_REG__SMC,
  48         CGS_IND_REG__UVD_CTX,
  49         CGS_IND_REG__DIDT,
  50         CGS_IND_REG__AUDIO_ENDPT
  51 };
  52
  53 /**
  54  * enum cgs_clock - Clocks controlled by the SMU
  55  */
  56 enum cgs_clock {
  57         CGS_CLOCK__SCLK,
  58         CGS_CLOCK__MCLK,
  59         CGS_CLOCK__VCLK,
  60         CGS_CLOCK__DCLK,
  61         CGS_CLOCK__ECLK,
  62         CGS_CLOCK__ACLK,
  63         CGS_CLOCK__ICLK,
  64         /* ... */
  65 };
  66
  67 /**
  68  * enum cgs_engine - Engines that can be statically power-gated
  69  */
  70 enum cgs_engine {
  71         CGS_ENGINE__UVD,
  72         CGS_ENGINE__VCE,
  73         CGS_ENGINE__VP8,
  74         CGS_ENGINE__ACP_DMA,
  75         CGS_ENGINE__ACP_DSP0,
  76         CGS_ENGINE__ACP_DSP1,
  77         CGS_ENGINE__ISP,
  78         /* ... */
  79 };
  80
  81 /**
  82  * enum cgs_voltage_planes - Voltage planes for external camera HW
  83  */
  84 enum cgs_voltage_planes {
  85         CGS_VOLTAGE_PLANE__SENSOR0,
  86         CGS_VOLTAGE_PLANE__SENSOR1,
  87         /* ... */
  88 };
  89
  90 /*
  91  * enum cgs_ucode_id - Firmware types for different IPs
  92  */
  93 enum cgs_ucode_id {
  94         CGS_UCODE_ID_SMU = 0,
  95         CGS_UCODE_ID_SDMA0,
  96         CGS_UCODE_ID_SDMA1,
  97         CGS_UCODE_ID_CP_CE,
  98         CGS_UCODE_ID_CP_PFP,
  99         CGS_UCODE_ID_CP_ME,
 100         CGS_UCODE_ID_CP_MEC,
 101         CGS_UCODE_ID_CP_MEC_JT1,
 102         CGS_UCODE_ID_CP_MEC_JT2,
 103         CGS_UCODE_ID_GMCON_RENG,
 104         CGS_UCODE_ID_RLC_G,
 105         CGS_UCODE_ID_MAXIMUM,
 106 };
 107
 108 enum cgs_system_info_id {
 109         CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
 110         CGS_SYSTEM_INFO_ID_MAXIMUM,
 111 };
 112
 113 struct cgs_system_info {
 114         uint64_t       size;
 115         uint64_t       info_id;
 116         union {
 117                 void           *ptr;
 118                 uint64_t        value;
 119         };
 120         uint64_t               padding[13];
 121 };
 122
 123 /**
 124  * struct cgs_clock_limits - Clock limits
 125  *
 126  * Clocks are specified in 10KHz units.
 127  */
 128 struct cgs_clock_limits {
 129         unsigned min;           /**< Minimum supported frequency */
 130         unsigned max;           /**< Maxumim supported frequency */
 131         unsigned sustainable;   /**< Thermally sustainable frequency */
 132 };
 133
 134 /**
 135  * struct cgs_firmware_info - Firmware information
 136  */
 137 struct cgs_firmware_info {
 138         uint16_t                version;
 139         uint16_t                feature_version;
 140         uint32_t                image_size;
 141         uint64_t                mc_addr;
 142         void                    *kptr;
 143 };
 144
 145 typedef unsigned long cgs_handle_t;
 146
 147 #define CGS_ACPI_METHOD_ATCS          0x53435441
 148 #define CGS_ACPI_METHOD_ATIF          0x46495441
 149 #define CGS_ACPI_METHOD_ATPX          0x58505441
 150 #define CGS_ACPI_FIELD_METHOD_NAME                      0x00000001
 151 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT             0x00000002
 152 #define CGS_ACPI_MAX_BUFFER_SIZE     256
 153 #define CGS_ACPI_TYPE_ANY                      0x00
 154 #define CGS_ACPI_TYPE_INTEGER               0x01
 155 #define CGS_ACPI_TYPE_STRING                0x02
 156 #define CGS_ACPI_TYPE_BUFFER                0x03
 157 #define CGS_ACPI_TYPE_PACKAGE               0x04
 158
 159 struct cgs_acpi_method_argument {
 160         uint32_t type;
 161         uint32_t method_length;
 162         uint32_t data_length;
 163         union{
 164                 uint32_t value;
 165                 void *pointer;
 166         };
 167 };
 168
 169 struct cgs_acpi_method_info {
 170         uint32_t size;
 171         uint32_t field;
 172         uint32_t input_count;
 173         uint32_t name;
 174         struct cgs_acpi_method_argument *pinput_argument;
 175         uint32_t output_count;
 176         struct cgs_acpi_method_argument *poutput_argument;
 177         uint32_t padding[9];
 178 };
 179
 180 /**
 181  * cgs_gpu_mem_info() - Return information about memory heaps
 182  * @cgs_device: opaque device handle
 183  * @type:       memory type
 184  * @mc_start:   Start MC address of the heap (output)
 185  * @mc_size:    MC address space size (output)
 186  * @mem_size:   maximum amount of memory available for allocation (output)
 187  *
 188  * This function returns information about memory heaps. The type
 189  * parameter is used to select the memory heap. The mc_start and
 190  * mc_size for GART heaps may be bigger than the memory available for
 191  * allocation.
 192  *
 193  * mc_start and mc_size are undefined for non-contiguous FB memory
 194  * types, since buffers allocated with these types may or may not be
 195  * GART mapped.
 196  *
 197  * Return:  0 on success, -errno otherwise
 198  */
 199 typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type,
 200                                   uint64_t *mc_start, uint64_t *mc_size,
 201                                   uint64_t *mem_size);
 202
 203 /**
 204  * cgs_gmap_kmem() - map kernel memory to GART aperture
 205  * @cgs_device: opaque device handle
 206  * @kmem:       pointer to kernel memory
 207  * @size:       size to map
 208  * @min_offset: minimum offset from start of GART aperture
 209  * @max_offset: maximum offset from start of GART aperture
 210  * @kmem_handle: kernel memory handle (output)
 211  * @mcaddr:     MC address (output)
 212  *
 213  * Return:  0 on success, -errno otherwise
 214  */
 215 typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size,
 216                                uint64_t min_offset, uint64_t max_offset,
 217                                cgs_handle_t *kmem_handle, uint64_t *mcaddr);
 218
 219 /**
 220  * cgs_gunmap_kmem() - unmap kernel memory
 221  * @cgs_device: opaque device handle
 222  * @kmem_handle: kernel memory handle returned by gmap_kmem
 223  *
 224  * Return:  0 on success, -errno otherwise
 225  */
 226 typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle);
 227
 228 /**
 229  * cgs_alloc_gpu_mem() - Allocate GPU memory
 230  * @cgs_device: opaque device handle
 231  * @type:       memory type
 232  * @size:       size in bytes
 233  * @align:      alignment in bytes
 234  * @min_offset: minimum offset from start of heap
 235  * @max_offset: maximum offset from start of heap
 236  * @handle:     memory handle (output)
 237  *
 238  * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
 239  * memory allocation. This guarantees that the MC address returned by
 240  * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
 241  * FB memory types may be GART mapped depending on memory
 242  * fragmentation and memory allocator policies.
 243  *
 244  * If min/max_offset are non-0, the allocation will be forced to
 245  * reside between these offsets in its respective memory heap. The
 246  * base address that the offset relates to, depends on the memory
 247  * type.
 248  *
 249  * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
 250  * - CGS_GPU_MEM_TYPE__GART_*:      GART aperture base address
 251  * - others:                        undefined, don't use with max_offset
 252  *
 253  * Return:  0 on success, -errno otherwise
 254  */
 255 typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type,
 256                                    uint64_t size, uint64_t align,
 257                                    uint64_t min_offset, uint64_t max_offset,
 258                                    cgs_handle_t *handle);
 259
 260 /**
 261  * cgs_free_gpu_mem() - Free GPU memory
 262  * @cgs_device: opaque device handle
 263  * @handle:     memory handle returned by alloc or import
 264  *
 265  * Return:  0 on success, -errno otherwise
 266  */
 267 typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
 268
 269 /**
 270  * cgs_gmap_gpu_mem() - GPU-map GPU memory
 271  * @cgs_device: opaque device handle
 272  * @handle:     memory handle returned by alloc or import
 273  * @mcaddr:     MC address (output)
 274  *
 275  * Ensures that a buffer is GPU accessible and returns its MC address.
 276  *
 277  * Return:  0 on success, -errno otherwise
 278  */
 279 typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
 280                                   uint64_t *mcaddr);
 281
 282 /**
 283  * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
 284  * @cgs_device: opaque device handle
 285  * @handle:     memory handle returned by alloc or import
 286  *
 287  * Allows the buffer to be migrated while it's not used by the GPU.
 288  *
 289  * Return:  0 on success, -errno otherwise
 290  */
 291 typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
 292
 293 /**
 294  * cgs_kmap_gpu_mem() - Kernel-map GPU memory
 295  *
 296  * @cgs_device: opaque device handle
 297  * @handle:     memory handle returned by alloc or import
 298  * @map:        Kernel virtual address the memory was mapped to (output)
 299  *
 300  * Return:  0 on success, -errno otherwise
 301  */
 302 typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
 303                                   void **map);
 304
 305 /**
 306  * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
 307  * @cgs_device: opaque device handle
 308  * @handle:     memory handle returned by alloc or import
 309  *
 310  * Return:  0 on success, -errno otherwise
 311  */
 312 typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
 313
 314 /**
 315  * cgs_read_register() - Read an MMIO register
 316  * @cgs_device: opaque device handle
 317  * @offset:     register offset
 318  *
 319  * Return:  register value
 320  */
 321 typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset);
 322
 323 /**
 324  * cgs_write_register() - Write an MMIO register
 325  * @cgs_device: opaque device handle
 326  * @offset:     register offset
 327  * @value:      register value
 328  */
 329 typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset,
 330                                      uint32_t value);
 331
 332 /**
 333  * cgs_read_ind_register() - Read an indirect register
 334  * @cgs_device: opaque device handle
 335  * @offset:     register offset
 336  *
 337  * Return:  register value
 338  */
 339 typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
 340                                             unsigned index);
 341
 342 /**
 343  * cgs_write_ind_register() - Write an indirect register
 344  * @cgs_device: opaque device handle
 345  * @offset:     register offset
 346  * @value:      register value
 347  */
 348 typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
 349                                          unsigned index, uint32_t value);
 350
 351 /**
 352  * cgs_read_pci_config_byte() - Read byte from PCI configuration space
 353  * @cgs_device: opaque device handle
 354  * @addr:       address
 355  *
 356  * Return:  Value read
 357  */
 358 typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr);
 359
 360 /**
 361  * cgs_read_pci_config_word() - Read word from PCI configuration space
 362  * @cgs_device: opaque device handle
 363  * @addr:       address, must be word-aligned
 364  *
 365  * Return:  Value read
 366  */
 367 typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr);
 368
 369 /**
 370  * cgs_read_pci_config_dword() - Read dword from PCI configuration space
 371  * @cgs_device: opaque device handle
 372  * @addr:       address, must be dword-aligned
 373  *
 374  * Return:  Value read
 375  */
 376 typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device,
 377                                                 unsigned addr);
 378
 379 /**
 380  * cgs_write_pci_config_byte() - Write byte to PCI configuration space
 381  * @cgs_device: opaque device handle
 382  * @addr:       address
 383  * @value:      value to write
 384  */
 385 typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr,
 386                                             uint8_t value);
 387
 388 /**
 389  * cgs_write_pci_config_word() - Write byte to PCI configuration space
 390  * @cgs_device: opaque device handle
 391  * @addr:       address, must be word-aligned
 392  * @value:      value to write
 393  */
 394 typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr,
 395                                             uint16_t value);
 396
 397 /**
 398  * cgs_write_pci_config_dword() - Write byte to PCI configuration space
 399  * @cgs_device: opaque device handle
 400  * @addr:       address, must be dword-aligned
 401  * @value:      value to write
 402  */
 403 typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr,
 404                                              uint32_t value);
 405
 406 /**
 407  * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
 408  * @cgs_device: opaque device handle
 409  * @table:      data table index
 410  * @size:       size of the table (output, may be NULL)
 411  * @frev:       table format revision (output, may be NULL)
 412  * @crev:       table content revision (output, may be NULL)
 413  *
 414  * Return: Pointer to start of the table, or NULL on failure
 415  */
 416 typedef const void *(*cgs_atom_get_data_table_t)(
 417         void *cgs_device, unsigned table,
 418         uint16_t *size, uint8_t *frev, uint8_t *crev);
 419
 420 /**
 421  * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
 422  * @cgs_device: opaque device handle
 423  * @table:      data table index
 424  * @frev:       table format revision (output, may be NULL)
 425  * @crev:       table content revision (output, may be NULL)
 426  *
 427  * Return: 0 on success, -errno otherwise
 428  */
 429 typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table,
 430                                              uint8_t *frev, uint8_t *crev);
 431
 432 /**
 433  * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
 434  * @cgs_device: opaque device handle
 435  * @table:      command table index
 436  * @args:       arguments
 437  *
 438  * Return: 0 on success, -errno otherwise
 439  */
 440 typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device,
 441                                          unsigned table, void *args);
 442
 443 /**
 444  * cgs_create_pm_request() - Create a power management request
 445  * @cgs_device: opaque device handle
 446  * @request:    handle of created PM request (output)
 447  *
 448  * Return:  0 on success, -errno otherwise
 449  */
 450 typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request);
 451
 452 /**
 453  * cgs_destroy_pm_request() - Destroy a power management request
 454  * @cgs_device: opaque device handle
 455  * @request:    handle of created PM request
 456  *
 457  * Return:  0 on success, -errno otherwise
 458  */
 459 typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request);
 460
 461 /**
 462  * cgs_set_pm_request() - Activate or deactiveate a PM request
 463  * @cgs_device: opaque device handle
 464  * @request:    PM request handle
 465  * @active:     0 = deactivate, non-0 = activate
 466  *
 467  * While a PM request is active, its minimum clock requests are taken
 468  * into account as the requested engines are powered up. When the
 469  * request is inactive, the engines may be powered down and clocks may
 470  * be lower, depending on other PM requests by other driver
 471  * components.
 472  *
 473  * Return:  0 on success, -errno otherwise
 474  */
 475 typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request,
 476                                     int active);
 477
 478 /**
 479  * cgs_pm_request_clock() - Request a minimum frequency for a specific clock
 480  * @cgs_device: opaque device handle
 481  * @request:    PM request handle
 482  * @clock:      which clock?
 483  * @freq:       requested min. frequency in 10KHz units (0 to clear request)
 484  *
 485  * Return:  0 on success, -errno otherwise
 486  */
 487 typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request,
 488                                       enum cgs_clock clock, unsigned freq);
 489
 490 /**
 491  * cgs_pm_request_engine() - Request an engine to be powered up
 492  * @cgs_device: opaque device handle
 493  * @request:    PM request handle
 494  * @engine:     which engine?
 495  * @powered:    0 = powered down, non-0 = powered up
 496  *
 497  * Return:  0 on success, -errno otherwise
 498  */
 499 typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request,
 500                                        enum cgs_engine engine, int powered);
 501
 502 /**
 503  * cgs_pm_query_clock_limits() - Query clock frequency limits
 504  * @cgs_device: opaque device handle
 505  * @clock:      which clock?
 506  * @limits:     clock limits
 507  *
 508  * Return:  0 on success, -errno otherwise
 509  */
 510 typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device,
 511                                            enum cgs_clock clock,
 512                                            struct cgs_clock_limits *limits);
 513
 514 /**
 515  * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
 516  * @cgs_device: opaque device handle
 517  * @mask:       bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
 518  * @voltages:   pointer to array of voltage values in 1mV units
 519  *
 520  * Return: 0 on success, -errno otherwise
 521  */
 522 typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask,
 523                                          const uint32_t *voltages);
 524 /**
 525  * cgs_get_firmware_info - Get the firmware information from core driver
 526  * @cgs_device: opaque device handle
 527  * @type: the firmware type
 528  * @info: returend firmware information
 529  *
 530  * Return: 0 on success, -errno otherwise
 531  */
 532 typedef int (*cgs_get_firmware_info)(void *cgs_device,
 533                                      enum cgs_ucode_id type,
 534                                      struct cgs_firmware_info *info);
 535
 536 typedef int(*cgs_set_powergating_state)(void *cgs_device,
 537                                   enum amd_ip_block_type block_type,
 538                                   enum amd_powergating_state state);
 539
 540 typedef int(*cgs_set_clockgating_state)(void *cgs_device,
 541                                   enum amd_ip_block_type block_type,
 542                                   enum amd_clockgating_state state);
 543
 544 typedef int (*cgs_call_acpi_method)(void *cgs_device,
 545                                         uint32_t acpi_method,
 546                                         uint32_t acpi_function,
 547                                         void *pinput, void *poutput,
 548                                         uint32_t output_count,
 549                                         uint32_t input_size,
 550                                         uint32_t output_size);
 551
 552 typedef int (*cgs_query_system_info)(void *cgs_device,
 553                                 struct cgs_system_info *sys_info);
 554
 555 struct cgs_ops {
 556         /* memory management calls (similar to KFD interface) */
 557         cgs_gpu_mem_info_t gpu_mem_info;
 558         cgs_gmap_kmem_t gmap_kmem;
 559         cgs_gunmap_kmem_t gunmap_kmem;
 560         cgs_alloc_gpu_mem_t alloc_gpu_mem;
 561         cgs_free_gpu_mem_t free_gpu_mem;
 562         cgs_gmap_gpu_mem_t gmap_gpu_mem;
 563         cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
 564         cgs_kmap_gpu_mem_t kmap_gpu_mem;
 565         cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
 566         /* MMIO access */
 567         cgs_read_register_t read_register;
 568         cgs_write_register_t write_register;
 569         cgs_read_ind_register_t read_ind_register;
 570         cgs_write_ind_register_t write_ind_register;
 571         /* PCI configuration space access */
 572         cgs_read_pci_config_byte_t read_pci_config_byte;
 573         cgs_read_pci_config_word_t read_pci_config_word;
 574         cgs_read_pci_config_dword_t read_pci_config_dword;
 575         cgs_write_pci_config_byte_t write_pci_config_byte;
 576         cgs_write_pci_config_word_t write_pci_config_word;
 577         cgs_write_pci_config_dword_t write_pci_config_dword;
 578         /* ATOM BIOS */
 579         cgs_atom_get_data_table_t atom_get_data_table;
 580         cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
 581         cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
 582         /* Power management */
 583         cgs_create_pm_request_t create_pm_request;
 584         cgs_destroy_pm_request_t destroy_pm_request;
 585         cgs_set_pm_request_t set_pm_request;
 586         cgs_pm_request_clock_t pm_request_clock;
 587         cgs_pm_request_engine_t pm_request_engine;
 588         cgs_pm_query_clock_limits_t pm_query_clock_limits;
 589         cgs_set_camera_voltages_t set_camera_voltages;
 590         /* Firmware Info */
 591         cgs_get_firmware_info get_firmware_info;
 592         /* cg pg interface*/
 593         cgs_set_powergating_state set_powergating_state;
 594         cgs_set_clockgating_state set_clockgating_state;
 595         /* ACPI */
 596         cgs_call_acpi_method call_acpi_method;
 597         /* get system info */
 598         cgs_query_system_info query_system_info;
 599 };
 600
 601 struct cgs_os_ops; /* To be define in OS-specific CGS header */
 602
 603 struct cgs_device
 604 {
 605         const struct cgs_ops *ops;
 606         const struct cgs_os_ops *os_ops;
 607         /* to be embedded at the start of driver private structure */
 608 };
 609
 610 /* Convenience macros that make CGS indirect function calls look like
 611  * normal function calls */
 612 #define CGS_CALL(func,dev,...) \
 613         (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
 614 #define CGS_OS_CALL(func,dev,...) \
 615         (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
 616
 617 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size)            \
 618         CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
 619 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
 620         CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
 621 #define cgs_gunmap_kmem(dev,kmem_handle)        \
 622         CGS_CALL(gunmap_kmem,dev,keme_handle)
 623 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle)   \
 624         CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
 625 #define cgs_free_gpu_mem(dev,handle)            \
 626         CGS_CALL(free_gpu_mem,dev,handle)
 627 #define cgs_gmap_gpu_mem(dev,handle,mcaddr)     \
 628         CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
 629 #define cgs_gunmap_gpu_mem(dev,handle)          \
 630         CGS_CALL(gunmap_gpu_mem,dev,handle)
 631 #define cgs_kmap_gpu_mem(dev,handle,map)        \
 632         CGS_CALL(kmap_gpu_mem,dev,handle,map)
 633 #define cgs_kunmap_gpu_mem(dev,handle)          \
 634         CGS_CALL(kunmap_gpu_mem,dev,handle)
 635
 636 #define cgs_read_register(dev,offset)           \
 637         CGS_CALL(read_register,dev,offset)
 638 #define cgs_write_register(dev,offset,value)            \
 639         CGS_CALL(write_register,dev,offset,value)
 640 #define cgs_read_ind_register(dev,space,index)          \
 641         CGS_CALL(read_ind_register,dev,space,index)
 642 #define cgs_write_ind_register(dev,space,index,value)           \
 643         CGS_CALL(write_ind_register,dev,space,index,value)
 644
 645 #define cgs_read_pci_config_byte(dev,addr)      \
 646         CGS_CALL(read_pci_config_byte,dev,addr)
 647 #define cgs_read_pci_config_word(dev,addr)      \
 648         CGS_CALL(read_pci_config_word,dev,addr)
 649 #define cgs_read_pci_config_dword(dev,addr)             \
 650         CGS_CALL(read_pci_config_dword,dev,addr)
 651 #define cgs_write_pci_config_byte(dev,addr,value)       \
 652         CGS_CALL(write_pci_config_byte,dev,addr,value)
 653 #define cgs_write_pci_config_word(dev,addr,value)       \
 654         CGS_CALL(write_pci_config_word,dev,addr,value)
 655 #define cgs_write_pci_config_dword(dev,addr,value)      \
 656         CGS_CALL(write_pci_config_dword,dev,addr,value)
 657
 658 #define cgs_atom_get_data_table(dev,table,size,frev,crev)       \
 659         CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
 660 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev)        \
 661         CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
 662 #define cgs_atom_exec_cmd_table(dev,table,args)         \
 663         CGS_CALL(atom_exec_cmd_table,dev,table,args)
 664
 665 #define cgs_create_pm_request(dev,request)      \
 666         CGS_CALL(create_pm_request,dev,request)
 667 #define cgs_destroy_pm_request(dev,request)             \
 668         CGS_CALL(destroy_pm_request,dev,request)
 669 #define cgs_set_pm_request(dev,request,active)          \
 670         CGS_CALL(set_pm_request,dev,request,active)
 671 #define cgs_pm_request_clock(dev,request,clock,freq)            \
 672         CGS_CALL(pm_request_clock,dev,request,clock,freq)
 673 #define cgs_pm_request_engine(dev,request,engine,powered)       \
 674         CGS_CALL(pm_request_engine,dev,request,engine,powered)
 675 #define cgs_pm_query_clock_limits(dev,clock,limits)             \
 676         CGS_CALL(pm_query_clock_limits,dev,clock,limits)
 677 #define cgs_set_camera_voltages(dev,mask,voltages)      \
 678         CGS_CALL(set_camera_voltages,dev,mask,voltages)
 679 #define cgs_get_firmware_info(dev, type, info)  \
 680         CGS_CALL(get_firmware_info, dev, type, info)
 681 #define cgs_set_powergating_state(dev, block_type, state)       \
 682         CGS_CALL(set_powergating_state, dev, block_type, state)
 683 #define cgs_set_clockgating_state(dev, block_type, state)       \
 684         CGS_CALL(set_clockgating_state, dev, block_type, state)
 685 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)  \
 686         CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
 687 #define cgs_query_system_info(dev, sys_info)    \
 688         CGS_CALL(query_system_info, dev, sys_info)
 689
 690 #endif /* _CGS_COMMON_H */