drivers/gpu/drm/amd/include/cgs_common.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _CGS_COMMON_H
  25 #define _CGS_COMMON_H
  26
  27 #include "amd_shared.h"
  28
  29 struct cgs_device;
  30
  31 /**
  32  * enum cgs_gpu_mem_type - GPU memory types
  33  */
  34 enum cgs_gpu_mem_type {
  35         CGS_GPU_MEM_TYPE__VISIBLE_FB,
  36         CGS_GPU_MEM_TYPE__INVISIBLE_FB,
  37         CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
  38         CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
  39         CGS_GPU_MEM_TYPE__GART_CACHEABLE,
  40         CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
  41 };
  42
  43 /**
  44  * enum cgs_ind_reg - Indirect register spaces
  45  */
  46 enum cgs_ind_reg {
  47         CGS_IND_REG__MMIO,
  48         CGS_IND_REG__PCIE,
  49         CGS_IND_REG__SMC,
  50         CGS_IND_REG__UVD_CTX,
  51         CGS_IND_REG__DIDT,
  52         CGS_IND_REG__AUDIO_ENDPT
  53 };
  54
  55 /**
  56  * enum cgs_clock - Clocks controlled by the SMU
  57  */
  58 enum cgs_clock {
  59         CGS_CLOCK__SCLK,
  60         CGS_CLOCK__MCLK,
  61         CGS_CLOCK__VCLK,
  62         CGS_CLOCK__DCLK,
  63         CGS_CLOCK__ECLK,
  64         CGS_CLOCK__ACLK,
  65         CGS_CLOCK__ICLK,
  66         /* ... */
  67 };
  68
  69 /**
  70  * enum cgs_engine - Engines that can be statically power-gated
  71  */
  72 enum cgs_engine {
  73         CGS_ENGINE__UVD,
  74         CGS_ENGINE__VCE,
  75         CGS_ENGINE__VP8,
  76         CGS_ENGINE__ACP_DMA,
  77         CGS_ENGINE__ACP_DSP0,
  78         CGS_ENGINE__ACP_DSP1,
  79         CGS_ENGINE__ISP,
  80         /* ... */
  81 };
  82
  83 /**
  84  * enum cgs_voltage_planes - Voltage planes for external camera HW
  85  */
  86 enum cgs_voltage_planes {
  87         CGS_VOLTAGE_PLANE__SENSOR0,
  88         CGS_VOLTAGE_PLANE__SENSOR1,
  89         /* ... */
  90 };
  91
  92 /*
  93  * enum cgs_ucode_id - Firmware types for different IPs
  94  */
  95 enum cgs_ucode_id {
  96         CGS_UCODE_ID_SMU = 0,
  97         CGS_UCODE_ID_SMU_SK,
  98         CGS_UCODE_ID_SDMA0,
  99         CGS_UCODE_ID_SDMA1,
 100         CGS_UCODE_ID_CP_CE,
 101         CGS_UCODE_ID_CP_PFP,
 102         CGS_UCODE_ID_CP_ME,
 103         CGS_UCODE_ID_CP_MEC,
 104         CGS_UCODE_ID_CP_MEC_JT1,
 105         CGS_UCODE_ID_CP_MEC_JT2,
 106         CGS_UCODE_ID_GMCON_RENG,
 107         CGS_UCODE_ID_RLC_G,
 108         CGS_UCODE_ID_MAXIMUM,
 109 };
 110
 111 enum cgs_system_info_id {
 112         CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
 113         CGS_SYSTEM_INFO_PCIE_GEN_INFO,
 114         CGS_SYSTEM_INFO_PCIE_MLW,
 115         CGS_SYSTEM_INFO_CG_FLAGS,
 116         CGS_SYSTEM_INFO_PG_FLAGS,
 117         CGS_SYSTEM_INFO_GFX_CU_INFO,
 118         CGS_SYSTEM_INFO_ID_MAXIMUM,
 119 };
 120
 121 struct cgs_system_info {
 122         uint64_t       size;
 123         uint64_t       info_id;
 124         union {
 125                 void           *ptr;
 126                 uint64_t        value;
 127         };
 128         uint64_t               padding[13];
 129 };
 130
 131 /*
 132  * enum cgs_resource_type - GPU resource type
 133  */
 134 enum cgs_resource_type {
 135         CGS_RESOURCE_TYPE_MMIO = 0,
 136         CGS_RESOURCE_TYPE_FB,
 137         CGS_RESOURCE_TYPE_IO,
 138         CGS_RESOURCE_TYPE_DOORBELL,
 139         CGS_RESOURCE_TYPE_ROM,
 140 };
 141
 142 /**
 143  * struct cgs_clock_limits - Clock limits
 144  *
 145  * Clocks are specified in 10KHz units.
 146  */
 147 struct cgs_clock_limits {
 148         unsigned min;           /**< Minimum supported frequency */
 149         unsigned max;           /**< Maxumim supported frequency */
 150         unsigned sustainable;   /**< Thermally sustainable frequency */
 151 };
 152
 153 /**
 154  * struct cgs_firmware_info - Firmware information
 155  */
 156 struct cgs_firmware_info {
 157         uint16_t                version;
 158         uint16_t                feature_version;
 159         uint32_t                image_size;
 160         uint64_t                mc_addr;
 161         void                    *kptr;
 162 };
 163
 164 struct cgs_mode_info {
 165         uint32_t                refresh_rate;
 166         uint32_t                ref_clock;
 167         uint32_t                vblank_time_us;
 168 };
 169
 170 struct cgs_display_info {
 171         uint32_t                display_count;
 172         uint32_t                active_display_mask;
 173         struct cgs_mode_info *mode_info;
 174 };
 175
 176 typedef unsigned long cgs_handle_t;
 177
 178 #define CGS_ACPI_METHOD_ATCS          0x53435441
 179 #define CGS_ACPI_METHOD_ATIF          0x46495441
 180 #define CGS_ACPI_METHOD_ATPX          0x58505441
 181 #define CGS_ACPI_FIELD_METHOD_NAME                      0x00000001
 182 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT             0x00000002
 183 #define CGS_ACPI_MAX_BUFFER_SIZE     256
 184 #define CGS_ACPI_TYPE_ANY                      0x00
 185 #define CGS_ACPI_TYPE_INTEGER               0x01
 186 #define CGS_ACPI_TYPE_STRING                0x02
 187 #define CGS_ACPI_TYPE_BUFFER                0x03
 188 #define CGS_ACPI_TYPE_PACKAGE               0x04
 189
 190 struct cgs_acpi_method_argument {
 191         uint32_t type;
 192         uint32_t method_length;
 193         uint32_t data_length;
 194         union{
 195                 uint32_t value;
 196                 void *pointer;
 197         };
 198 };
 199
 200 struct cgs_acpi_method_info {
 201         uint32_t size;
 202         uint32_t field;
 203         uint32_t input_count;
 204         uint32_t name;
 205         struct cgs_acpi_method_argument *pinput_argument;
 206         uint32_t output_count;
 207         struct cgs_acpi_method_argument *poutput_argument;
 208         uint32_t padding[9];
 209 };
 210
 211 /**
 212  * cgs_gpu_mem_info() - Return information about memory heaps
 213  * @cgs_device: opaque device handle
 214  * @type:       memory type
 215  * @mc_start:   Start MC address of the heap (output)
 216  * @mc_size:    MC address space size (output)
 217  * @mem_size:   maximum amount of memory available for allocation (output)
 218  *
 219  * This function returns information about memory heaps. The type
 220  * parameter is used to select the memory heap. The mc_start and
 221  * mc_size for GART heaps may be bigger than the memory available for
 222  * allocation.
 223  *
 224  * mc_start and mc_size are undefined for non-contiguous FB memory
 225  * types, since buffers allocated with these types may or may not be
 226  * GART mapped.
 227  *
 228  * Return:  0 on success, -errno otherwise
 229  */
 230 typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
 231                                   uint64_t *mc_start, uint64_t *mc_size,
 232                                   uint64_t *mem_size);
 233
 234 /**
 235  * cgs_gmap_kmem() - map kernel memory to GART aperture
 236  * @cgs_device: opaque device handle
 237  * @kmem:       pointer to kernel memory
 238  * @size:       size to map
 239  * @min_offset: minimum offset from start of GART aperture
 240  * @max_offset: maximum offset from start of GART aperture
 241  * @kmem_handle: kernel memory handle (output)
 242  * @mcaddr:     MC address (output)
 243  *
 244  * Return:  0 on success, -errno otherwise
 245  */
 246 typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size,
 247                                uint64_t min_offset, uint64_t max_offset,
 248                                cgs_handle_t *kmem_handle, uint64_t *mcaddr);
 249
 250 /**
 251  * cgs_gunmap_kmem() - unmap kernel memory
 252  * @cgs_device: opaque device handle
 253  * @kmem_handle: kernel memory handle returned by gmap_kmem
 254  *
 255  * Return:  0 on success, -errno otherwise
 256  */
 257 typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle);
 258
 259 /**
 260  * cgs_alloc_gpu_mem() - Allocate GPU memory
 261  * @cgs_device: opaque device handle
 262  * @type:       memory type
 263  * @size:       size in bytes
 264  * @align:      alignment in bytes
 265  * @min_offset: minimum offset from start of heap
 266  * @max_offset: maximum offset from start of heap
 267  * @handle:     memory handle (output)
 268  *
 269  * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
 270  * memory allocation. This guarantees that the MC address returned by
 271  * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
 272  * FB memory types may be GART mapped depending on memory
 273  * fragmentation and memory allocator policies.
 274  *
 275  * If min/max_offset are non-0, the allocation will be forced to
 276  * reside between these offsets in its respective memory heap. The
 277  * base address that the offset relates to, depends on the memory
 278  * type.
 279  *
 280  * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
 281  * - CGS_GPU_MEM_TYPE__GART_*:      GART aperture base address
 282  * - others:                        undefined, don't use with max_offset
 283  *
 284  * Return:  0 on success, -errno otherwise
 285  */
 286 typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
 287                                    uint64_t size, uint64_t align,
 288                                    uint64_t min_offset, uint64_t max_offset,
 289                                    cgs_handle_t *handle);
 290
 291 /**
 292  * cgs_free_gpu_mem() - Free GPU memory
 293  * @cgs_device: opaque device handle
 294  * @handle:     memory handle returned by alloc or import
 295  *
 296  * Return:  0 on success, -errno otherwise
 297  */
 298 typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
 299
 300 /**
 301  * cgs_gmap_gpu_mem() - GPU-map GPU memory
 302  * @cgs_device: opaque device handle
 303  * @handle:     memory handle returned by alloc or import
 304  * @mcaddr:     MC address (output)
 305  *
 306  * Ensures that a buffer is GPU accessible and returns its MC address.
 307  *
 308  * Return:  0 on success, -errno otherwise
 309  */
 310 typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
 311                                   uint64_t *mcaddr);
 312
 313 /**
 314  * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
 315  * @cgs_device: opaque device handle
 316  * @handle:     memory handle returned by alloc or import
 317  *
 318  * Allows the buffer to be migrated while it's not used by the GPU.
 319  *
 320  * Return:  0 on success, -errno otherwise
 321  */
 322 typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
 323
 324 /**
 325  * cgs_kmap_gpu_mem() - Kernel-map GPU memory
 326  *
 327  * @cgs_device: opaque device handle
 328  * @handle:     memory handle returned by alloc or import
 329  * @map:        Kernel virtual address the memory was mapped to (output)
 330  *
 331  * Return:  0 on success, -errno otherwise
 332  */
 333 typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
 334                                   void **map);
 335
 336 /**
 337  * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
 338  * @cgs_device: opaque device handle
 339  * @handle:     memory handle returned by alloc or import
 340  *
 341  * Return:  0 on success, -errno otherwise
 342  */
 343 typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
 344
 345 /**
 346  * cgs_read_register() - Read an MMIO register
 347  * @cgs_device: opaque device handle
 348  * @offset:     register offset
 349  *
 350  * Return:  register value
 351  */
 352 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
 353
 354 /**
 355  * cgs_write_register() - Write an MMIO register
 356  * @cgs_device: opaque device handle
 357  * @offset:     register offset
 358  * @value:      register value
 359  */
 360 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
 361                                      uint32_t value);
 362
 363 /**
 364  * cgs_read_ind_register() - Read an indirect register
 365  * @cgs_device: opaque device handle
 366  * @offset:     register offset
 367  *
 368  * Return:  register value
 369  */
 370 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
 371                                             unsigned index);
 372
 373 /**
 374  * cgs_write_ind_register() - Write an indirect register
 375  * @cgs_device: opaque device handle
 376  * @offset:     register offset
 377  * @value:      register value
 378  */
 379 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
 380                                          unsigned index, uint32_t value);
 381
 382 /**
 383  * cgs_read_pci_config_byte() - Read byte from PCI configuration space
 384  * @cgs_device: opaque device handle
 385  * @addr:       address
 386  *
 387  * Return:  Value read
 388  */
 389 typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr);
 390
 391 /**
 392  * cgs_read_pci_config_word() - Read word from PCI configuration space
 393  * @cgs_device: opaque device handle
 394  * @addr:       address, must be word-aligned
 395  *
 396  * Return:  Value read
 397  */
 398 typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr);
 399
 400 /**
 401  * cgs_read_pci_config_dword() - Read dword from PCI configuration space
 402  * @cgs_device: opaque device handle
 403  * @addr:       address, must be dword-aligned
 404  *
 405  * Return:  Value read
 406  */
 407 typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device,
 408                                                 unsigned addr);
 409
 410 /**
 411  * cgs_write_pci_config_byte() - Write byte to PCI configuration space
 412  * @cgs_device: opaque device handle
 413  * @addr:       address
 414  * @value:      value to write
 415  */
 416 typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr,
 417                                             uint8_t value);
 418
 419 /**
 420  * cgs_write_pci_config_word() - Write byte to PCI configuration space
 421  * @cgs_device: opaque device handle
 422  * @addr:       address, must be word-aligned
 423  * @value:      value to write
 424  */
 425 typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr,
 426                                             uint16_t value);
 427
 428 /**
 429  * cgs_write_pci_config_dword() - Write byte to PCI configuration space
 430  * @cgs_device: opaque device handle
 431  * @addr:       address, must be dword-aligned
 432  * @value:      value to write
 433  */
 434 typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr,
 435                                              uint32_t value);
 436
 437
 438 /**
 439  * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
 440  * @cgs_device: opaque device handle
 441  * @resource_type:      Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
 442  * @size:       size of the region
 443  * @offset:     offset from the start of the region
 444  * @resource_base:      base address (not including offset) returned
 445  *
 446  * Return: 0 on success, -errno otherwise
 447  */
 448 typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
 449                                       enum cgs_resource_type resource_type,
 450                                       uint64_t size,
 451                                       uint64_t offset,
 452                                       uint64_t *resource_base);
 453
 454 /**
 455  * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
 456  * @cgs_device: opaque device handle
 457  * @table:      data table index
 458  * @size:       size of the table (output, may be NULL)
 459  * @frev:       table format revision (output, may be NULL)
 460  * @crev:       table content revision (output, may be NULL)
 461  *
 462  * Return: Pointer to start of the table, or NULL on failure
 463  */
 464 typedef const void *(*cgs_atom_get_data_table_t)(
 465         struct cgs_device *cgs_device, unsigned table,
 466         uint16_t *size, uint8_t *frev, uint8_t *crev);
 467
 468 /**
 469  * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
 470  * @cgs_device: opaque device handle
 471  * @table:      data table index
 472  * @frev:       table format revision (output, may be NULL)
 473  * @crev:       table content revision (output, may be NULL)
 474  *
 475  * Return: 0 on success, -errno otherwise
 476  */
 477 typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
 478                                              uint8_t *frev, uint8_t *crev);
 479
 480 /**
 481  * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
 482  * @cgs_device: opaque device handle
 483  * @table:      command table index
 484  * @args:       arguments
 485  *
 486  * Return: 0 on success, -errno otherwise
 487  */
 488 typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
 489                                          unsigned table, void *args);
 490
 491 /**
 492  * cgs_create_pm_request() - Create a power management request
 493  * @cgs_device: opaque device handle
 494  * @request:    handle of created PM request (output)
 495  *
 496  * Return:  0 on success, -errno otherwise
 497  */
 498 typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request);
 499
 500 /**
 501  * cgs_destroy_pm_request() - Destroy a power management request
 502  * @cgs_device: opaque device handle
 503  * @request:    handle of created PM request
 504  *
 505  * Return:  0 on success, -errno otherwise
 506  */
 507 typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request);
 508
 509 /**
 510  * cgs_set_pm_request() - Activate or deactiveate a PM request
 511  * @cgs_device: opaque device handle
 512  * @request:    PM request handle
 513  * @active:     0 = deactivate, non-0 = activate
 514  *
 515  * While a PM request is active, its minimum clock requests are taken
 516  * into account as the requested engines are powered up. When the
 517  * request is inactive, the engines may be powered down and clocks may
 518  * be lower, depending on other PM requests by other driver
 519  * components.
 520  *
 521  * Return:  0 on success, -errno otherwise
 522  */
 523 typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request,
 524                                     int active);
 525
 526 /**
 527  * cgs_pm_request_clock() - Request a minimum frequency for a specific clock
 528  * @cgs_device: opaque device handle
 529  * @request:    PM request handle
 530  * @clock:      which clock?
 531  * @freq:       requested min. frequency in 10KHz units (0 to clear request)
 532  *
 533  * Return:  0 on success, -errno otherwise
 534  */
 535 typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request,
 536                                       enum cgs_clock clock, unsigned freq);
 537
 538 /**
 539  * cgs_pm_request_engine() - Request an engine to be powered up
 540  * @cgs_device: opaque device handle
 541  * @request:    PM request handle
 542  * @engine:     which engine?
 543  * @powered:    0 = powered down, non-0 = powered up
 544  *
 545  * Return:  0 on success, -errno otherwise
 546  */
 547 typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request,
 548                                        enum cgs_engine engine, int powered);
 549
 550 /**
 551  * cgs_pm_query_clock_limits() - Query clock frequency limits
 552  * @cgs_device: opaque device handle
 553  * @clock:      which clock?
 554  * @limits:     clock limits
 555  *
 556  * Return:  0 on success, -errno otherwise
 557  */
 558 typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device,
 559                                            enum cgs_clock clock,
 560                                            struct cgs_clock_limits *limits);
 561
 562 /**
 563  * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
 564  * @cgs_device: opaque device handle
 565  * @mask:       bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
 566  * @voltages:   pointer to array of voltage values in 1mV units
 567  *
 568  * Return: 0 on success, -errno otherwise
 569  */
 570 typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask,
 571                                          const uint32_t *voltages);
 572 /**
 573  * cgs_get_firmware_info - Get the firmware information from core driver
 574  * @cgs_device: opaque device handle
 575  * @type: the firmware type
 576  * @info: returend firmware information
 577  *
 578  * Return: 0 on success, -errno otherwise
 579  */
 580 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
 581                                      enum cgs_ucode_id type,
 582                                      struct cgs_firmware_info *info);
 583
 584 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
 585                                   enum amd_ip_block_type block_type,
 586                                   enum amd_powergating_state state);
 587
 588 typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
 589                                   enum amd_ip_block_type block_type,
 590                                   enum amd_clockgating_state state);
 591
 592 typedef int(*cgs_get_active_displays_info)(
 593                                         struct cgs_device *cgs_device,
 594                                         struct cgs_display_info *info);
 595
 596 typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
 597
 598 typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device,
 599                                         uint32_t acpi_method,
 600                                         uint32_t acpi_function,
 601                                         void *pinput, void *poutput,
 602                                         uint32_t output_count,
 603                                         uint32_t input_size,
 604                                         uint32_t output_size);
 605
 606 typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,
 607                                 struct cgs_system_info *sys_info);
 608
 609 struct cgs_ops {
 610         /* memory management calls (similar to KFD interface) */
 611         cgs_gpu_mem_info_t gpu_mem_info;
 612         cgs_gmap_kmem_t gmap_kmem;
 613         cgs_gunmap_kmem_t gunmap_kmem;
 614         cgs_alloc_gpu_mem_t alloc_gpu_mem;
 615         cgs_free_gpu_mem_t free_gpu_mem;
 616         cgs_gmap_gpu_mem_t gmap_gpu_mem;
 617         cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
 618         cgs_kmap_gpu_mem_t kmap_gpu_mem;
 619         cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
 620         /* MMIO access */
 621         cgs_read_register_t read_register;
 622         cgs_write_register_t write_register;
 623         cgs_read_ind_register_t read_ind_register;
 624         cgs_write_ind_register_t write_ind_register;
 625         /* PCI configuration space access */
 626         cgs_read_pci_config_byte_t read_pci_config_byte;
 627         cgs_read_pci_config_word_t read_pci_config_word;
 628         cgs_read_pci_config_dword_t read_pci_config_dword;
 629         cgs_write_pci_config_byte_t write_pci_config_byte;
 630         cgs_write_pci_config_word_t write_pci_config_word;
 631         cgs_write_pci_config_dword_t write_pci_config_dword;
 632         /* PCI resources */
 633         cgs_get_pci_resource_t get_pci_resource;
 634         /* ATOM BIOS */
 635         cgs_atom_get_data_table_t atom_get_data_table;
 636         cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
 637         cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
 638         /* Power management */
 639         cgs_create_pm_request_t create_pm_request;
 640         cgs_destroy_pm_request_t destroy_pm_request;
 641         cgs_set_pm_request_t set_pm_request;
 642         cgs_pm_request_clock_t pm_request_clock;
 643         cgs_pm_request_engine_t pm_request_engine;
 644         cgs_pm_query_clock_limits_t pm_query_clock_limits;
 645         cgs_set_camera_voltages_t set_camera_voltages;
 646         /* Firmware Info */
 647         cgs_get_firmware_info get_firmware_info;
 648         /* cg pg interface*/
 649         cgs_set_powergating_state set_powergating_state;
 650         cgs_set_clockgating_state set_clockgating_state;
 651         /* display manager */
 652         cgs_get_active_displays_info get_active_displays_info;
 653         /* notify dpm enabled */
 654         cgs_notify_dpm_enabled notify_dpm_enabled;
 655         /* ACPI */
 656         cgs_call_acpi_method call_acpi_method;
 657         /* get system info */
 658         cgs_query_system_info query_system_info;
 659 };
 660
 661 struct cgs_os_ops; /* To be define in OS-specific CGS header */
 662
 663 struct cgs_device
 664 {
 665         const struct cgs_ops *ops;
 666         const struct cgs_os_ops *os_ops;
 667         /* to be embedded at the start of driver private structure */
 668 };
 669
 670 /* Convenience macros that make CGS indirect function calls look like
 671  * normal function calls */
 672 #define CGS_CALL(func,dev,...) \
 673         (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
 674 #define CGS_OS_CALL(func,dev,...) \
 675         (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
 676
 677 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size)            \
 678         CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
 679 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
 680         CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
 681 #define cgs_gunmap_kmem(dev,kmem_handle)        \
 682         CGS_CALL(gunmap_kmem,dev,keme_handle)
 683 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle)   \
 684         CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
 685 #define cgs_free_gpu_mem(dev,handle)            \
 686         CGS_CALL(free_gpu_mem,dev,handle)
 687 #define cgs_gmap_gpu_mem(dev,handle,mcaddr)     \
 688         CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
 689 #define cgs_gunmap_gpu_mem(dev,handle)          \
 690         CGS_CALL(gunmap_gpu_mem,dev,handle)
 691 #define cgs_kmap_gpu_mem(dev,handle,map)        \
 692         CGS_CALL(kmap_gpu_mem,dev,handle,map)
 693 #define cgs_kunmap_gpu_mem(dev,handle)          \
 694         CGS_CALL(kunmap_gpu_mem,dev,handle)
 695
 696 #define cgs_read_register(dev,offset)           \
 697         CGS_CALL(read_register,dev,offset)
 698 #define cgs_write_register(dev,offset,value)            \
 699         CGS_CALL(write_register,dev,offset,value)
 700 #define cgs_read_ind_register(dev,space,index)          \
 701         CGS_CALL(read_ind_register,dev,space,index)
 702 #define cgs_write_ind_register(dev,space,index,value)           \
 703         CGS_CALL(write_ind_register,dev,space,index,value)
 704
 705 #define cgs_read_pci_config_byte(dev,addr)      \
 706         CGS_CALL(read_pci_config_byte,dev,addr)
 707 #define cgs_read_pci_config_word(dev,addr)      \
 708         CGS_CALL(read_pci_config_word,dev,addr)
 709 #define cgs_read_pci_config_dword(dev,addr)             \
 710         CGS_CALL(read_pci_config_dword,dev,addr)
 711 #define cgs_write_pci_config_byte(dev,addr,value)       \
 712         CGS_CALL(write_pci_config_byte,dev,addr,value)
 713 #define cgs_write_pci_config_word(dev,addr,value)       \
 714         CGS_CALL(write_pci_config_word,dev,addr,value)
 715 #define cgs_write_pci_config_dword(dev,addr,value)      \
 716         CGS_CALL(write_pci_config_dword,dev,addr,value)
 717
 718 #define cgs_atom_get_data_table(dev,table,size,frev,crev)       \
 719         CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
 720 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev)        \
 721         CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
 722 #define cgs_atom_exec_cmd_table(dev,table,args)         \
 723         CGS_CALL(atom_exec_cmd_table,dev,table,args)
 724
 725 #define cgs_create_pm_request(dev,request)      \
 726         CGS_CALL(create_pm_request,dev,request)
 727 #define cgs_destroy_pm_request(dev,request)             \
 728         CGS_CALL(destroy_pm_request,dev,request)
 729 #define cgs_set_pm_request(dev,request,active)          \
 730         CGS_CALL(set_pm_request,dev,request,active)
 731 #define cgs_pm_request_clock(dev,request,clock,freq)            \
 732         CGS_CALL(pm_request_clock,dev,request,clock,freq)
 733 #define cgs_pm_request_engine(dev,request,engine,powered)       \
 734         CGS_CALL(pm_request_engine,dev,request,engine,powered)
 735 #define cgs_pm_query_clock_limits(dev,clock,limits)             \
 736         CGS_CALL(pm_query_clock_limits,dev,clock,limits)
 737 #define cgs_set_camera_voltages(dev,mask,voltages)      \
 738         CGS_CALL(set_camera_voltages,dev,mask,voltages)
 739 #define cgs_get_firmware_info(dev, type, info)  \
 740         CGS_CALL(get_firmware_info, dev, type, info)
 741 #define cgs_set_powergating_state(dev, block_type, state)       \
 742         CGS_CALL(set_powergating_state, dev, block_type, state)
 743 #define cgs_set_clockgating_state(dev, block_type, state)       \
 744         CGS_CALL(set_clockgating_state, dev, block_type, state)
 745 #define cgs_notify_dpm_enabled(dev, enabled)    \
 746         CGS_CALL(notify_dpm_enabled, dev, enabled)
 747
 748 #define cgs_get_active_displays_info(dev, info) \
 749         CGS_CALL(get_active_displays_info, dev, info)
 750
 751 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)  \
 752         CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
 753 #define cgs_query_system_info(dev, sys_info)    \
 754         CGS_CALL(query_system_info, dev, sys_info)
 755 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
 756         resource_base) \
 757         CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
 758         resource_base)
 759
 760 #endif /* _CGS_COMMON_H */