drivers/gpu/drm/amd/include/cgs_common.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _CGS_COMMON_H
  25 #define _CGS_COMMON_H
  26
  27 #include "amd_shared.h"
  28
  29 /**
  30  * enum cgs_gpu_mem_type - GPU memory types
  31  */
  32 enum cgs_gpu_mem_type {
  33         CGS_GPU_MEM_TYPE__VISIBLE_FB,
  34         CGS_GPU_MEM_TYPE__INVISIBLE_FB,
  35         CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
  36         CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
  37         CGS_GPU_MEM_TYPE__GART_CACHEABLE,
  38         CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
  39 };
  40
  41 /**
  42  * enum cgs_ind_reg - Indirect register spaces
  43  */
  44 enum cgs_ind_reg {
  45         CGS_IND_REG__MMIO,
  46         CGS_IND_REG__PCIE,
  47         CGS_IND_REG__SMC,
  48         CGS_IND_REG__UVD_CTX,
  49         CGS_IND_REG__DIDT,
  50         CGS_IND_REG__AUDIO_ENDPT
  51 };
  52
  53 /**
  54  * enum cgs_clock - Clocks controlled by the SMU
  55  */
  56 enum cgs_clock {
  57         CGS_CLOCK__SCLK,
  58         CGS_CLOCK__MCLK,
  59         CGS_CLOCK__VCLK,
  60         CGS_CLOCK__DCLK,
  61         CGS_CLOCK__ECLK,
  62         CGS_CLOCK__ACLK,
  63         CGS_CLOCK__ICLK,
  64         /* ... */
  65 };
  66
  67 /**
  68  * enum cgs_engine - Engines that can be statically power-gated
  69  */
  70 enum cgs_engine {
  71         CGS_ENGINE__UVD,
  72         CGS_ENGINE__VCE,
  73         CGS_ENGINE__VP8,
  74         CGS_ENGINE__ACP_DMA,
  75         CGS_ENGINE__ACP_DSP0,
  76         CGS_ENGINE__ACP_DSP1,
  77         CGS_ENGINE__ISP,
  78         /* ... */
  79 };
  80
  81 /**
  82  * enum cgs_voltage_planes - Voltage planes for external camera HW
  83  */
  84 enum cgs_voltage_planes {
  85         CGS_VOLTAGE_PLANE__SENSOR0,
  86         CGS_VOLTAGE_PLANE__SENSOR1,
  87         /* ... */
  88 };
  89
  90 /*
  91  * enum cgs_ucode_id - Firmware types for different IPs
  92  */
  93 enum cgs_ucode_id {
  94         CGS_UCODE_ID_SMU = 0,
  95         CGS_UCODE_ID_SDMA0,
  96         CGS_UCODE_ID_SDMA1,
  97         CGS_UCODE_ID_CP_CE,
  98         CGS_UCODE_ID_CP_PFP,
  99         CGS_UCODE_ID_CP_ME,
 100         CGS_UCODE_ID_CP_MEC,
 101         CGS_UCODE_ID_CP_MEC_JT1,
 102         CGS_UCODE_ID_CP_MEC_JT2,
 103         CGS_UCODE_ID_GMCON_RENG,
 104         CGS_UCODE_ID_RLC_G,
 105         CGS_UCODE_ID_MAXIMUM,
 106 };
 107
 108 /**
 109  * struct cgs_clock_limits - Clock limits
 110  *
 111  * Clocks are specified in 10KHz units.
 112  */
 113 struct cgs_clock_limits {
 114         unsigned min;           /**< Minimum supported frequency */
 115         unsigned max;           /**< Maxumim supported frequency */
 116         unsigned sustainable;   /**< Thermally sustainable frequency */
 117 };
 118
 119 /**
 120  * struct cgs_firmware_info - Firmware information
 121  */
 122 struct cgs_firmware_info {
 123         uint16_t                version;
 124         uint16_t                feature_version;
 125         uint32_t                image_size;
 126         uint64_t                mc_addr;
 127         void                    *kptr;
 128 };
 129
 130 typedef unsigned long cgs_handle_t;
 131
 132 /**
 133  * cgs_gpu_mem_info() - Return information about memory heaps
 134  * @cgs_device: opaque device handle
 135  * @type:       memory type
 136  * @mc_start:   Start MC address of the heap (output)
 137  * @mc_size:    MC address space size (output)
 138  * @mem_size:   maximum amount of memory available for allocation (output)
 139  *
 140  * This function returns information about memory heaps. The type
 141  * parameter is used to select the memory heap. The mc_start and
 142  * mc_size for GART heaps may be bigger than the memory available for
 143  * allocation.
 144  *
 145  * mc_start and mc_size are undefined for non-contiguous FB memory
 146  * types, since buffers allocated with these types may or may not be
 147  * GART mapped.
 148  *
 149  * Return:  0 on success, -errno otherwise
 150  */
 151 typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type,
 152                                   uint64_t *mc_start, uint64_t *mc_size,
 153                                   uint64_t *mem_size);
 154
 155 /**
 156  * cgs_gmap_kmem() - map kernel memory to GART aperture
 157  * @cgs_device: opaque device handle
 158  * @kmem:       pointer to kernel memory
 159  * @size:       size to map
 160  * @min_offset: minimum offset from start of GART aperture
 161  * @max_offset: maximum offset from start of GART aperture
 162  * @kmem_handle: kernel memory handle (output)
 163  * @mcaddr:     MC address (output)
 164  *
 165  * Return:  0 on success, -errno otherwise
 166  */
 167 typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size,
 168                                uint64_t min_offset, uint64_t max_offset,
 169                                cgs_handle_t *kmem_handle, uint64_t *mcaddr);
 170
 171 /**
 172  * cgs_gunmap_kmem() - unmap kernel memory
 173  * @cgs_device: opaque device handle
 174  * @kmem_handle: kernel memory handle returned by gmap_kmem
 175  *
 176  * Return:  0 on success, -errno otherwise
 177  */
 178 typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle);
 179
 180 /**
 181  * cgs_alloc_gpu_mem() - Allocate GPU memory
 182  * @cgs_device: opaque device handle
 183  * @type:       memory type
 184  * @size:       size in bytes
 185  * @align:      alignment in bytes
 186  * @min_offset: minimum offset from start of heap
 187  * @max_offset: maximum offset from start of heap
 188  * @handle:     memory handle (output)
 189  *
 190  * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
 191  * memory allocation. This guarantees that the MC address returned by
 192  * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
 193  * FB memory types may be GART mapped depending on memory
 194  * fragmentation and memory allocator policies.
 195  *
 196  * If min/max_offset are non-0, the allocation will be forced to
 197  * reside between these offsets in its respective memory heap. The
 198  * base address that the offset relates to, depends on the memory
 199  * type.
 200  *
 201  * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
 202  * - CGS_GPU_MEM_TYPE__GART_*:      GART aperture base address
 203  * - others:                        undefined, don't use with max_offset
 204  *
 205  * Return:  0 on success, -errno otherwise
 206  */
 207 typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type,
 208                                    uint64_t size, uint64_t align,
 209                                    uint64_t min_offset, uint64_t max_offset,
 210                                    cgs_handle_t *handle);
 211
 212 /**
 213  * cgs_free_gpu_mem() - Free GPU memory
 214  * @cgs_device: opaque device handle
 215  * @handle:     memory handle returned by alloc or import
 216  *
 217  * Return:  0 on success, -errno otherwise
 218  */
 219 typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
 220
 221 /**
 222  * cgs_gmap_gpu_mem() - GPU-map GPU memory
 223  * @cgs_device: opaque device handle
 224  * @handle:     memory handle returned by alloc or import
 225  * @mcaddr:     MC address (output)
 226  *
 227  * Ensures that a buffer is GPU accessible and returns its MC address.
 228  *
 229  * Return:  0 on success, -errno otherwise
 230  */
 231 typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
 232                                   uint64_t *mcaddr);
 233
 234 /**
 235  * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
 236  * @cgs_device: opaque device handle
 237  * @handle:     memory handle returned by alloc or import
 238  *
 239  * Allows the buffer to be migrated while it's not used by the GPU.
 240  *
 241  * Return:  0 on success, -errno otherwise
 242  */
 243 typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
 244
 245 /**
 246  * cgs_kmap_gpu_mem() - Kernel-map GPU memory
 247  *
 248  * @cgs_device: opaque device handle
 249  * @handle:     memory handle returned by alloc or import
 250  * @map:        Kernel virtual address the memory was mapped to (output)
 251  *
 252  * Return:  0 on success, -errno otherwise
 253  */
 254 typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
 255                                   void **map);
 256
 257 /**
 258  * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
 259  * @cgs_device: opaque device handle
 260  * @handle:     memory handle returned by alloc or import
 261  *
 262  * Return:  0 on success, -errno otherwise
 263  */
 264 typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
 265
 266 /**
 267  * cgs_read_register() - Read an MMIO register
 268  * @cgs_device: opaque device handle
 269  * @offset:     register offset
 270  *
 271  * Return:  register value
 272  */
 273 typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset);
 274
 275 /**
 276  * cgs_write_register() - Write an MMIO register
 277  * @cgs_device: opaque device handle
 278  * @offset:     register offset
 279  * @value:      register value
 280  */
 281 typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset,
 282                                      uint32_t value);
 283
 284 /**
 285  * cgs_read_ind_register() - Read an indirect register
 286  * @cgs_device: opaque device handle
 287  * @offset:     register offset
 288  *
 289  * Return:  register value
 290  */
 291 typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
 292                                             unsigned index);
 293
 294 /**
 295  * cgs_write_ind_register() - Write an indirect register
 296  * @cgs_device: opaque device handle
 297  * @offset:     register offset
 298  * @value:      register value
 299  */
 300 typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
 301                                          unsigned index, uint32_t value);
 302
 303 /**
 304  * cgs_read_pci_config_byte() - Read byte from PCI configuration space
 305  * @cgs_device: opaque device handle
 306  * @addr:       address
 307  *
 308  * Return:  Value read
 309  */
 310 typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr);
 311
 312 /**
 313  * cgs_read_pci_config_word() - Read word from PCI configuration space
 314  * @cgs_device: opaque device handle
 315  * @addr:       address, must be word-aligned
 316  *
 317  * Return:  Value read
 318  */
 319 typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr);
 320
 321 /**
 322  * cgs_read_pci_config_dword() - Read dword from PCI configuration space
 323  * @cgs_device: opaque device handle
 324  * @addr:       address, must be dword-aligned
 325  *
 326  * Return:  Value read
 327  */
 328 typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device,
 329                                                 unsigned addr);
 330
 331 /**
 332  * cgs_write_pci_config_byte() - Write byte to PCI configuration space
 333  * @cgs_device: opaque device handle
 334  * @addr:       address
 335  * @value:      value to write
 336  */
 337 typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr,
 338                                             uint8_t value);
 339
 340 /**
 341  * cgs_write_pci_config_word() - Write byte to PCI configuration space
 342  * @cgs_device: opaque device handle
 343  * @addr:       address, must be word-aligned
 344  * @value:      value to write
 345  */
 346 typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr,
 347                                             uint16_t value);
 348
 349 /**
 350  * cgs_write_pci_config_dword() - Write byte to PCI configuration space
 351  * @cgs_device: opaque device handle
 352  * @addr:       address, must be dword-aligned
 353  * @value:      value to write
 354  */
 355 typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr,
 356                                              uint32_t value);
 357
 358 /**
 359  * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
 360  * @cgs_device: opaque device handle
 361  * @table:      data table index
 362  * @size:       size of the table (output, may be NULL)
 363  * @frev:       table format revision (output, may be NULL)
 364  * @crev:       table content revision (output, may be NULL)
 365  *
 366  * Return: Pointer to start of the table, or NULL on failure
 367  */
 368 typedef const void *(*cgs_atom_get_data_table_t)(
 369         void *cgs_device, unsigned table,
 370         uint16_t *size, uint8_t *frev, uint8_t *crev);
 371
 372 /**
 373  * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
 374  * @cgs_device: opaque device handle
 375  * @table:      data table index
 376  * @frev:       table format revision (output, may be NULL)
 377  * @crev:       table content revision (output, may be NULL)
 378  *
 379  * Return: 0 on success, -errno otherwise
 380  */
 381 typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table,
 382                                              uint8_t *frev, uint8_t *crev);
 383
 384 /**
 385  * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
 386  * @cgs_device: opaque device handle
 387  * @table:      command table index
 388  * @args:       arguments
 389  *
 390  * Return: 0 on success, -errno otherwise
 391  */
 392 typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device,
 393                                          unsigned table, void *args);
 394
 395 /**
 396  * cgs_create_pm_request() - Create a power management request
 397  * @cgs_device: opaque device handle
 398  * @request:    handle of created PM request (output)
 399  *
 400  * Return:  0 on success, -errno otherwise
 401  */
 402 typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request);
 403
 404 /**
 405  * cgs_destroy_pm_request() - Destroy a power management request
 406  * @cgs_device: opaque device handle
 407  * @request:    handle of created PM request
 408  *
 409  * Return:  0 on success, -errno otherwise
 410  */
 411 typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request);
 412
 413 /**
 414  * cgs_set_pm_request() - Activate or deactiveate a PM request
 415  * @cgs_device: opaque device handle
 416  * @request:    PM request handle
 417  * @active:     0 = deactivate, non-0 = activate
 418  *
 419  * While a PM request is active, its minimum clock requests are taken
 420  * into account as the requested engines are powered up. When the
 421  * request is inactive, the engines may be powered down and clocks may
 422  * be lower, depending on other PM requests by other driver
 423  * components.
 424  *
 425  * Return:  0 on success, -errno otherwise
 426  */
 427 typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request,
 428                                     int active);
 429
 430 /**
 431  * cgs_pm_request_clock() - Request a minimum frequency for a specific clock
 432  * @cgs_device: opaque device handle
 433  * @request:    PM request handle
 434  * @clock:      which clock?
 435  * @freq:       requested min. frequency in 10KHz units (0 to clear request)
 436  *
 437  * Return:  0 on success, -errno otherwise
 438  */
 439 typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request,
 440                                       enum cgs_clock clock, unsigned freq);
 441
 442 /**
 443  * cgs_pm_request_engine() - Request an engine to be powered up
 444  * @cgs_device: opaque device handle
 445  * @request:    PM request handle
 446  * @engine:     which engine?
 447  * @powered:    0 = powered down, non-0 = powered up
 448  *
 449  * Return:  0 on success, -errno otherwise
 450  */
 451 typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request,
 452                                        enum cgs_engine engine, int powered);
 453
 454 /**
 455  * cgs_pm_query_clock_limits() - Query clock frequency limits
 456  * @cgs_device: opaque device handle
 457  * @clock:      which clock?
 458  * @limits:     clock limits
 459  *
 460  * Return:  0 on success, -errno otherwise
 461  */
 462 typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device,
 463                                            enum cgs_clock clock,
 464                                            struct cgs_clock_limits *limits);
 465
 466 /**
 467  * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
 468  * @cgs_device: opaque device handle
 469  * @mask:       bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
 470  * @voltages:   pointer to array of voltage values in 1mV units
 471  *
 472  * Return: 0 on success, -errno otherwise
 473  */
 474 typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask,
 475                                          const uint32_t *voltages);
 476 /**
 477  * cgs_get_firmware_info - Get the firmware information from core driver
 478  * @cgs_device: opaque device handle
 479  * @type: the firmware type
 480  * @info: returend firmware information
 481  *
 482  * Return: 0 on success, -errno otherwise
 483  */
 484 typedef int (*cgs_get_firmware_info)(void *cgs_device,
 485                                      enum cgs_ucode_id type,
 486                                      struct cgs_firmware_info *info);
 487
 488 typedef int(*cgs_set_powergating_state)(void *cgs_device,
 489                                   enum amd_ip_block_type block_type,
 490                                   enum amd_powergating_state state);
 491
 492 typedef int(*cgs_set_clockgating_state)(void *cgs_device,
 493                                   enum amd_ip_block_type block_type,
 494                                   enum amd_clockgating_state state);
 495
 496 struct cgs_ops {
 497         /* memory management calls (similar to KFD interface) */
 498         cgs_gpu_mem_info_t gpu_mem_info;
 499         cgs_gmap_kmem_t gmap_kmem;
 500         cgs_gunmap_kmem_t gunmap_kmem;
 501         cgs_alloc_gpu_mem_t alloc_gpu_mem;
 502         cgs_free_gpu_mem_t free_gpu_mem;
 503         cgs_gmap_gpu_mem_t gmap_gpu_mem;
 504         cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
 505         cgs_kmap_gpu_mem_t kmap_gpu_mem;
 506         cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
 507         /* MMIO access */
 508         cgs_read_register_t read_register;
 509         cgs_write_register_t write_register;
 510         cgs_read_ind_register_t read_ind_register;
 511         cgs_write_ind_register_t write_ind_register;
 512         /* PCI configuration space access */
 513         cgs_read_pci_config_byte_t read_pci_config_byte;
 514         cgs_read_pci_config_word_t read_pci_config_word;
 515         cgs_read_pci_config_dword_t read_pci_config_dword;
 516         cgs_write_pci_config_byte_t write_pci_config_byte;
 517         cgs_write_pci_config_word_t write_pci_config_word;
 518         cgs_write_pci_config_dword_t write_pci_config_dword;
 519         /* ATOM BIOS */
 520         cgs_atom_get_data_table_t atom_get_data_table;
 521         cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
 522         cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
 523         /* Power management */
 524         cgs_create_pm_request_t create_pm_request;
 525         cgs_destroy_pm_request_t destroy_pm_request;
 526         cgs_set_pm_request_t set_pm_request;
 527         cgs_pm_request_clock_t pm_request_clock;
 528         cgs_pm_request_engine_t pm_request_engine;
 529         cgs_pm_query_clock_limits_t pm_query_clock_limits;
 530         cgs_set_camera_voltages_t set_camera_voltages;
 531         /* Firmware Info */
 532         cgs_get_firmware_info get_firmware_info;
 533         /* cg pg interface*/
 534         cgs_set_powergating_state set_powergating_state;
 535         cgs_set_clockgating_state set_clockgating_state;
 536         /* ACPI (TODO) */
 537 };
 538
 539 struct cgs_os_ops; /* To be define in OS-specific CGS header */
 540
 541 struct cgs_device
 542 {
 543         const struct cgs_ops *ops;
 544         const struct cgs_os_ops *os_ops;
 545         /* to be embedded at the start of driver private structure */
 546 };
 547
 548 /* Convenience macros that make CGS indirect function calls look like
 549  * normal function calls */
 550 #define CGS_CALL(func,dev,...) \
 551         (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
 552 #define CGS_OS_CALL(func,dev,...) \
 553         (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
 554
 555 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size)            \
 556         CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
 557 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
 558         CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
 559 #define cgs_gunmap_kmem(dev,kmem_handle)        \
 560         CGS_CALL(gunmap_kmem,dev,keme_handle)
 561 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle)   \
 562         CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
 563 #define cgs_free_gpu_mem(dev,handle)            \
 564         CGS_CALL(free_gpu_mem,dev,handle)
 565 #define cgs_gmap_gpu_mem(dev,handle,mcaddr)     \
 566         CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
 567 #define cgs_gunmap_gpu_mem(dev,handle)          \
 568         CGS_CALL(gunmap_gpu_mem,dev,handle)
 569 #define cgs_kmap_gpu_mem(dev,handle,map)        \
 570         CGS_CALL(kmap_gpu_mem,dev,handle,map)
 571 #define cgs_kunmap_gpu_mem(dev,handle)          \
 572         CGS_CALL(kunmap_gpu_mem,dev,handle)
 573
 574 #define cgs_read_register(dev,offset)           \
 575         CGS_CALL(read_register,dev,offset)
 576 #define cgs_write_register(dev,offset,value)            \
 577         CGS_CALL(write_register,dev,offset,value)
 578 #define cgs_read_ind_register(dev,space,index)          \
 579         CGS_CALL(read_ind_register,dev,space,index)
 580 #define cgs_write_ind_register(dev,space,index,value)           \
 581         CGS_CALL(write_ind_register,dev,space,index,value)
 582
 583 #define cgs_read_pci_config_byte(dev,addr)      \
 584         CGS_CALL(read_pci_config_byte,dev,addr)
 585 #define cgs_read_pci_config_word(dev,addr)      \
 586         CGS_CALL(read_pci_config_word,dev,addr)
 587 #define cgs_read_pci_config_dword(dev,addr)             \
 588         CGS_CALL(read_pci_config_dword,dev,addr)
 589 #define cgs_write_pci_config_byte(dev,addr,value)       \
 590         CGS_CALL(write_pci_config_byte,dev,addr,value)
 591 #define cgs_write_pci_config_word(dev,addr,value)       \
 592         CGS_CALL(write_pci_config_word,dev,addr,value)
 593 #define cgs_write_pci_config_dword(dev,addr,value)      \
 594         CGS_CALL(write_pci_config_dword,dev,addr,value)
 595
 596 #define cgs_atom_get_data_table(dev,table,size,frev,crev)       \
 597         CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
 598 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev)        \
 599         CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
 600 #define cgs_atom_exec_cmd_table(dev,table,args)         \
 601         CGS_CALL(atom_exec_cmd_table,dev,table,args)
 602
 603 #define cgs_create_pm_request(dev,request)      \
 604         CGS_CALL(create_pm_request,dev,request)
 605 #define cgs_destroy_pm_request(dev,request)             \
 606         CGS_CALL(destroy_pm_request,dev,request)
 607 #define cgs_set_pm_request(dev,request,active)          \
 608         CGS_CALL(set_pm_request,dev,request,active)
 609 #define cgs_pm_request_clock(dev,request,clock,freq)            \
 610         CGS_CALL(pm_request_clock,dev,request,clock,freq)
 611 #define cgs_pm_request_engine(dev,request,engine,powered)       \
 612         CGS_CALL(pm_request_engine,dev,request,engine,powered)
 613 #define cgs_pm_query_clock_limits(dev,clock,limits)             \
 614         CGS_CALL(pm_query_clock_limits,dev,clock,limits)
 615 #define cgs_set_camera_voltages(dev,mask,voltages)      \
 616         CGS_CALL(set_camera_voltages,dev,mask,voltages)
 617 #define cgs_get_firmware_info(dev, type, info)  \
 618         CGS_CALL(get_firmware_info, dev, type, info)
 619 #define cgs_set_powergating_state(dev, block_type, state)       \
 620         CGS_CALL(set_powergating_state, dev, block_type, state)
 621 #define cgs_set_clockgating_state(dev, block_type, state)       \
 622         CGS_CALL(set_clockgating_state, dev, block_type, state)
 623
 624 #endif /* _CGS_COMMON_H */