drivers/gpu/drm/amd/include/cgs_common.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _CGS_COMMON_H
  25 #define _CGS_COMMON_H
  26
  27 #include "amd_shared.h"
  28
  29 /**
  30  * enum cgs_gpu_mem_type - GPU memory types
  31  */
  32 enum cgs_gpu_mem_type {
  33         CGS_GPU_MEM_TYPE__VISIBLE_FB,
  34         CGS_GPU_MEM_TYPE__INVISIBLE_FB,
  35         CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
  36         CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
  37         CGS_GPU_MEM_TYPE__GART_CACHEABLE,
  38         CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
  39 };
  40
  41 /**
  42  * enum cgs_ind_reg - Indirect register spaces
  43  */
  44 enum cgs_ind_reg {
  45         CGS_IND_REG__MMIO,
  46         CGS_IND_REG__PCIE,
  47         CGS_IND_REG__SMC,
  48         CGS_IND_REG__UVD_CTX,
  49         CGS_IND_REG__DIDT,
  50         CGS_IND_REG__AUDIO_ENDPT
  51 };
  52
  53 /**
  54  * enum cgs_clock - Clocks controlled by the SMU
  55  */
  56 enum cgs_clock {
  57         CGS_CLOCK__SCLK,
  58         CGS_CLOCK__MCLK,
  59         CGS_CLOCK__VCLK,
  60         CGS_CLOCK__DCLK,
  61         CGS_CLOCK__ECLK,
  62         CGS_CLOCK__ACLK,
  63         CGS_CLOCK__ICLK,
  64         /* ... */
  65 };
  66
  67 /**
  68  * enum cgs_engine - Engines that can be statically power-gated
  69  */
  70 enum cgs_engine {
  71         CGS_ENGINE__UVD,
  72         CGS_ENGINE__VCE,
  73         CGS_ENGINE__VP8,
  74         CGS_ENGINE__ACP_DMA,
  75         CGS_ENGINE__ACP_DSP0,
  76         CGS_ENGINE__ACP_DSP1,
  77         CGS_ENGINE__ISP,
  78         /* ... */
  79 };
  80
  81 /**
  82  * enum cgs_voltage_planes - Voltage planes for external camera HW
  83  */
  84 enum cgs_voltage_planes {
  85         CGS_VOLTAGE_PLANE__SENSOR0,
  86         CGS_VOLTAGE_PLANE__SENSOR1,
  87         /* ... */
  88 };
  89
  90 /*
  91  * enum cgs_ucode_id - Firmware types for different IPs
  92  */
  93 enum cgs_ucode_id {
  94         CGS_UCODE_ID_SMU = 0,
  95         CGS_UCODE_ID_SDMA0,
  96         CGS_UCODE_ID_SDMA1,
  97         CGS_UCODE_ID_CP_CE,
  98         CGS_UCODE_ID_CP_PFP,
  99         CGS_UCODE_ID_CP_ME,
 100         CGS_UCODE_ID_CP_MEC,
 101         CGS_UCODE_ID_CP_MEC_JT1,
 102         CGS_UCODE_ID_CP_MEC_JT2,
 103         CGS_UCODE_ID_GMCON_RENG,
 104         CGS_UCODE_ID_RLC_G,
 105         CGS_UCODE_ID_MAXIMUM,
 106 };
 107
 108 /**
 109  * struct cgs_clock_limits - Clock limits
 110  *
 111  * Clocks are specified in 10KHz units.
 112  */
 113 struct cgs_clock_limits {
 114         unsigned min;           /**< Minimum supported frequency */
 115         unsigned max;           /**< Maxumim supported frequency */
 116         unsigned sustainable;   /**< Thermally sustainable frequency */
 117 };
 118
 119 /**
 120  * struct cgs_firmware_info - Firmware information
 121  */
 122 struct cgs_firmware_info {
 123         uint16_t                version;
 124         uint16_t                feature_version;
 125         uint32_t                image_size;
 126         uint64_t                mc_addr;
 127         void                    *kptr;
 128 };
 129
 130 typedef unsigned long cgs_handle_t;
 131
 132 #define CGS_ACPI_METHOD_ATCS          0x53435441
 133 #define CGS_ACPI_METHOD_ATIF          0x46495441
 134 #define CGS_ACPI_METHOD_ATPX          0x58505441
 135 #define CGS_ACPI_FIELD_METHOD_NAME                      0x00000001
 136 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT             0x00000002
 137 #define CGS_ACPI_MAX_BUFFER_SIZE     256
 138 #define CGS_ACPI_TYPE_ANY                      0x00
 139 #define CGS_ACPI_TYPE_INTEGER               0x01
 140 #define CGS_ACPI_TYPE_STRING                0x02
 141 #define CGS_ACPI_TYPE_BUFFER                0x03
 142 #define CGS_ACPI_TYPE_PACKAGE               0x04
 143
 144 struct cgs_acpi_method_argument {
 145         uint32_t type;
 146         uint32_t method_length;
 147         uint32_t data_length;
 148         union{
 149                 uint32_t value;
 150                 void *pointer;
 151         };
 152 };
 153
 154 struct cgs_acpi_method_info {
 155         uint32_t size;
 156         uint32_t field;
 157         uint32_t input_count;
 158         uint32_t name;
 159         struct cgs_acpi_method_argument *pinput_argument;
 160         uint32_t output_count;
 161         struct cgs_acpi_method_argument *poutput_argument;
 162         uint32_t padding[9];
 163 };
 164
 165 /**
 166  * cgs_gpu_mem_info() - Return information about memory heaps
 167  * @cgs_device: opaque device handle
 168  * @type:       memory type
 169  * @mc_start:   Start MC address of the heap (output)
 170  * @mc_size:    MC address space size (output)
 171  * @mem_size:   maximum amount of memory available for allocation (output)
 172  *
 173  * This function returns information about memory heaps. The type
 174  * parameter is used to select the memory heap. The mc_start and
 175  * mc_size for GART heaps may be bigger than the memory available for
 176  * allocation.
 177  *
 178  * mc_start and mc_size are undefined for non-contiguous FB memory
 179  * types, since buffers allocated with these types may or may not be
 180  * GART mapped.
 181  *
 182  * Return:  0 on success, -errno otherwise
 183  */
 184 typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type,
 185                                   uint64_t *mc_start, uint64_t *mc_size,
 186                                   uint64_t *mem_size);
 187
 188 /**
 189  * cgs_gmap_kmem() - map kernel memory to GART aperture
 190  * @cgs_device: opaque device handle
 191  * @kmem:       pointer to kernel memory
 192  * @size:       size to map
 193  * @min_offset: minimum offset from start of GART aperture
 194  * @max_offset: maximum offset from start of GART aperture
 195  * @kmem_handle: kernel memory handle (output)
 196  * @mcaddr:     MC address (output)
 197  *
 198  * Return:  0 on success, -errno otherwise
 199  */
 200 typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size,
 201                                uint64_t min_offset, uint64_t max_offset,
 202                                cgs_handle_t *kmem_handle, uint64_t *mcaddr);
 203
 204 /**
 205  * cgs_gunmap_kmem() - unmap kernel memory
 206  * @cgs_device: opaque device handle
 207  * @kmem_handle: kernel memory handle returned by gmap_kmem
 208  *
 209  * Return:  0 on success, -errno otherwise
 210  */
 211 typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle);
 212
 213 /**
 214  * cgs_alloc_gpu_mem() - Allocate GPU memory
 215  * @cgs_device: opaque device handle
 216  * @type:       memory type
 217  * @size:       size in bytes
 218  * @align:      alignment in bytes
 219  * @min_offset: minimum offset from start of heap
 220  * @max_offset: maximum offset from start of heap
 221  * @handle:     memory handle (output)
 222  *
 223  * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
 224  * memory allocation. This guarantees that the MC address returned by
 225  * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
 226  * FB memory types may be GART mapped depending on memory
 227  * fragmentation and memory allocator policies.
 228  *
 229  * If min/max_offset are non-0, the allocation will be forced to
 230  * reside between these offsets in its respective memory heap. The
 231  * base address that the offset relates to, depends on the memory
 232  * type.
 233  *
 234  * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
 235  * - CGS_GPU_MEM_TYPE__GART_*:      GART aperture base address
 236  * - others:                        undefined, don't use with max_offset
 237  *
 238  * Return:  0 on success, -errno otherwise
 239  */
 240 typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type,
 241                                    uint64_t size, uint64_t align,
 242                                    uint64_t min_offset, uint64_t max_offset,
 243                                    cgs_handle_t *handle);
 244
 245 /**
 246  * cgs_free_gpu_mem() - Free GPU memory
 247  * @cgs_device: opaque device handle
 248  * @handle:     memory handle returned by alloc or import
 249  *
 250  * Return:  0 on success, -errno otherwise
 251  */
 252 typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
 253
 254 /**
 255  * cgs_gmap_gpu_mem() - GPU-map GPU memory
 256  * @cgs_device: opaque device handle
 257  * @handle:     memory handle returned by alloc or import
 258  * @mcaddr:     MC address (output)
 259  *
 260  * Ensures that a buffer is GPU accessible and returns its MC address.
 261  *
 262  * Return:  0 on success, -errno otherwise
 263  */
 264 typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
 265                                   uint64_t *mcaddr);
 266
 267 /**
 268  * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
 269  * @cgs_device: opaque device handle
 270  * @handle:     memory handle returned by alloc or import
 271  *
 272  * Allows the buffer to be migrated while it's not used by the GPU.
 273  *
 274  * Return:  0 on success, -errno otherwise
 275  */
 276 typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
 277
 278 /**
 279  * cgs_kmap_gpu_mem() - Kernel-map GPU memory
 280  *
 281  * @cgs_device: opaque device handle
 282  * @handle:     memory handle returned by alloc or import
 283  * @map:        Kernel virtual address the memory was mapped to (output)
 284  *
 285  * Return:  0 on success, -errno otherwise
 286  */
 287 typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
 288                                   void **map);
 289
 290 /**
 291  * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
 292  * @cgs_device: opaque device handle
 293  * @handle:     memory handle returned by alloc or import
 294  *
 295  * Return:  0 on success, -errno otherwise
 296  */
 297 typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
 298
 299 /**
 300  * cgs_read_register() - Read an MMIO register
 301  * @cgs_device: opaque device handle
 302  * @offset:     register offset
 303  *
 304  * Return:  register value
 305  */
 306 typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset);
 307
 308 /**
 309  * cgs_write_register() - Write an MMIO register
 310  * @cgs_device: opaque device handle
 311  * @offset:     register offset
 312  * @value:      register value
 313  */
 314 typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset,
 315                                      uint32_t value);
 316
 317 /**
 318  * cgs_read_ind_register() - Read an indirect register
 319  * @cgs_device: opaque device handle
 320  * @offset:     register offset
 321  *
 322  * Return:  register value
 323  */
 324 typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
 325                                             unsigned index);
 326
 327 /**
 328  * cgs_write_ind_register() - Write an indirect register
 329  * @cgs_device: opaque device handle
 330  * @offset:     register offset
 331  * @value:      register value
 332  */
 333 typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
 334                                          unsigned index, uint32_t value);
 335
 336 /**
 337  * cgs_read_pci_config_byte() - Read byte from PCI configuration space
 338  * @cgs_device: opaque device handle
 339  * @addr:       address
 340  *
 341  * Return:  Value read
 342  */
 343 typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr);
 344
 345 /**
 346  * cgs_read_pci_config_word() - Read word from PCI configuration space
 347  * @cgs_device: opaque device handle
 348  * @addr:       address, must be word-aligned
 349  *
 350  * Return:  Value read
 351  */
 352 typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr);
 353
 354 /**
 355  * cgs_read_pci_config_dword() - Read dword from PCI configuration space
 356  * @cgs_device: opaque device handle
 357  * @addr:       address, must be dword-aligned
 358  *
 359  * Return:  Value read
 360  */
 361 typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device,
 362                                                 unsigned addr);
 363
 364 /**
 365  * cgs_write_pci_config_byte() - Write byte to PCI configuration space
 366  * @cgs_device: opaque device handle
 367  * @addr:       address
 368  * @value:      value to write
 369  */
 370 typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr,
 371                                             uint8_t value);
 372
 373 /**
 374  * cgs_write_pci_config_word() - Write byte to PCI configuration space
 375  * @cgs_device: opaque device handle
 376  * @addr:       address, must be word-aligned
 377  * @value:      value to write
 378  */
 379 typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr,
 380                                             uint16_t value);
 381
 382 /**
 383  * cgs_write_pci_config_dword() - Write byte to PCI configuration space
 384  * @cgs_device: opaque device handle
 385  * @addr:       address, must be dword-aligned
 386  * @value:      value to write
 387  */
 388 typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr,
 389                                              uint32_t value);
 390
 391 /**
 392  * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
 393  * @cgs_device: opaque device handle
 394  * @table:      data table index
 395  * @size:       size of the table (output, may be NULL)
 396  * @frev:       table format revision (output, may be NULL)
 397  * @crev:       table content revision (output, may be NULL)
 398  *
 399  * Return: Pointer to start of the table, or NULL on failure
 400  */
 401 typedef const void *(*cgs_atom_get_data_table_t)(
 402         void *cgs_device, unsigned table,
 403         uint16_t *size, uint8_t *frev, uint8_t *crev);
 404
 405 /**
 406  * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
 407  * @cgs_device: opaque device handle
 408  * @table:      data table index
 409  * @frev:       table format revision (output, may be NULL)
 410  * @crev:       table content revision (output, may be NULL)
 411  *
 412  * Return: 0 on success, -errno otherwise
 413  */
 414 typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table,
 415                                              uint8_t *frev, uint8_t *crev);
 416
 417 /**
 418  * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
 419  * @cgs_device: opaque device handle
 420  * @table:      command table index
 421  * @args:       arguments
 422  *
 423  * Return: 0 on success, -errno otherwise
 424  */
 425 typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device,
 426                                          unsigned table, void *args);
 427
 428 /**
 429  * cgs_create_pm_request() - Create a power management request
 430  * @cgs_device: opaque device handle
 431  * @request:    handle of created PM request (output)
 432  *
 433  * Return:  0 on success, -errno otherwise
 434  */
 435 typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request);
 436
 437 /**
 438  * cgs_destroy_pm_request() - Destroy a power management request
 439  * @cgs_device: opaque device handle
 440  * @request:    handle of created PM request
 441  *
 442  * Return:  0 on success, -errno otherwise
 443  */
 444 typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request);
 445
 446 /**
 447  * cgs_set_pm_request() - Activate or deactiveate a PM request
 448  * @cgs_device: opaque device handle
 449  * @request:    PM request handle
 450  * @active:     0 = deactivate, non-0 = activate
 451  *
 452  * While a PM request is active, its minimum clock requests are taken
 453  * into account as the requested engines are powered up. When the
 454  * request is inactive, the engines may be powered down and clocks may
 455  * be lower, depending on other PM requests by other driver
 456  * components.
 457  *
 458  * Return:  0 on success, -errno otherwise
 459  */
 460 typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request,
 461                                     int active);
 462
 463 /**
 464  * cgs_pm_request_clock() - Request a minimum frequency for a specific clock
 465  * @cgs_device: opaque device handle
 466  * @request:    PM request handle
 467  * @clock:      which clock?
 468  * @freq:       requested min. frequency in 10KHz units (0 to clear request)
 469  *
 470  * Return:  0 on success, -errno otherwise
 471  */
 472 typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request,
 473                                       enum cgs_clock clock, unsigned freq);
 474
 475 /**
 476  * cgs_pm_request_engine() - Request an engine to be powered up
 477  * @cgs_device: opaque device handle
 478  * @request:    PM request handle
 479  * @engine:     which engine?
 480  * @powered:    0 = powered down, non-0 = powered up
 481  *
 482  * Return:  0 on success, -errno otherwise
 483  */
 484 typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request,
 485                                        enum cgs_engine engine, int powered);
 486
 487 /**
 488  * cgs_pm_query_clock_limits() - Query clock frequency limits
 489  * @cgs_device: opaque device handle
 490  * @clock:      which clock?
 491  * @limits:     clock limits
 492  *
 493  * Return:  0 on success, -errno otherwise
 494  */
 495 typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device,
 496                                            enum cgs_clock clock,
 497                                            struct cgs_clock_limits *limits);
 498
 499 /**
 500  * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
 501  * @cgs_device: opaque device handle
 502  * @mask:       bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
 503  * @voltages:   pointer to array of voltage values in 1mV units
 504  *
 505  * Return: 0 on success, -errno otherwise
 506  */
 507 typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask,
 508                                          const uint32_t *voltages);
 509 /**
 510  * cgs_get_firmware_info - Get the firmware information from core driver
 511  * @cgs_device: opaque device handle
 512  * @type: the firmware type
 513  * @info: returend firmware information
 514  *
 515  * Return: 0 on success, -errno otherwise
 516  */
 517 typedef int (*cgs_get_firmware_info)(void *cgs_device,
 518                                      enum cgs_ucode_id type,
 519                                      struct cgs_firmware_info *info);
 520
 521 typedef int(*cgs_set_powergating_state)(void *cgs_device,
 522                                   enum amd_ip_block_type block_type,
 523                                   enum amd_powergating_state state);
 524
 525 typedef int(*cgs_set_clockgating_state)(void *cgs_device,
 526                                   enum amd_ip_block_type block_type,
 527                                   enum amd_clockgating_state state);
 528
 529 typedef int (*cgs_call_acpi_method)(void *cgs_device,
 530                                         uint32_t acpi_method,
 531                                         uint32_t acpi_function,
 532                                         void *pinput, void *poutput,
 533                                         uint32_t output_count,
 534                                         uint32_t input_size,
 535                                         uint32_t output_size);
 536 struct cgs_ops {
 537         /* memory management calls (similar to KFD interface) */
 538         cgs_gpu_mem_info_t gpu_mem_info;
 539         cgs_gmap_kmem_t gmap_kmem;
 540         cgs_gunmap_kmem_t gunmap_kmem;
 541         cgs_alloc_gpu_mem_t alloc_gpu_mem;
 542         cgs_free_gpu_mem_t free_gpu_mem;
 543         cgs_gmap_gpu_mem_t gmap_gpu_mem;
 544         cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
 545         cgs_kmap_gpu_mem_t kmap_gpu_mem;
 546         cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
 547         /* MMIO access */
 548         cgs_read_register_t read_register;
 549         cgs_write_register_t write_register;
 550         cgs_read_ind_register_t read_ind_register;
 551         cgs_write_ind_register_t write_ind_register;
 552         /* PCI configuration space access */
 553         cgs_read_pci_config_byte_t read_pci_config_byte;
 554         cgs_read_pci_config_word_t read_pci_config_word;
 555         cgs_read_pci_config_dword_t read_pci_config_dword;
 556         cgs_write_pci_config_byte_t write_pci_config_byte;
 557         cgs_write_pci_config_word_t write_pci_config_word;
 558         cgs_write_pci_config_dword_t write_pci_config_dword;
 559         /* ATOM BIOS */
 560         cgs_atom_get_data_table_t atom_get_data_table;
 561         cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
 562         cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
 563         /* Power management */
 564         cgs_create_pm_request_t create_pm_request;
 565         cgs_destroy_pm_request_t destroy_pm_request;
 566         cgs_set_pm_request_t set_pm_request;
 567         cgs_pm_request_clock_t pm_request_clock;
 568         cgs_pm_request_engine_t pm_request_engine;
 569         cgs_pm_query_clock_limits_t pm_query_clock_limits;
 570         cgs_set_camera_voltages_t set_camera_voltages;
 571         /* Firmware Info */
 572         cgs_get_firmware_info get_firmware_info;
 573         /* cg pg interface*/
 574         cgs_set_powergating_state set_powergating_state;
 575         cgs_set_clockgating_state set_clockgating_state;
 576         /* ACPI */
 577         cgs_call_acpi_method call_acpi_method;
 578 };
 579
 580 struct cgs_os_ops; /* To be define in OS-specific CGS header */
 581
 582 struct cgs_device
 583 {
 584         const struct cgs_ops *ops;
 585         const struct cgs_os_ops *os_ops;
 586         /* to be embedded at the start of driver private structure */
 587 };
 588
 589 /* Convenience macros that make CGS indirect function calls look like
 590  * normal function calls */
 591 #define CGS_CALL(func,dev,...) \
 592         (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
 593 #define CGS_OS_CALL(func,dev,...) \
 594         (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
 595
 596 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size)            \
 597         CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
 598 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
 599         CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
 600 #define cgs_gunmap_kmem(dev,kmem_handle)        \
 601         CGS_CALL(gunmap_kmem,dev,keme_handle)
 602 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle)   \
 603         CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
 604 #define cgs_free_gpu_mem(dev,handle)            \
 605         CGS_CALL(free_gpu_mem,dev,handle)
 606 #define cgs_gmap_gpu_mem(dev,handle,mcaddr)     \
 607         CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
 608 #define cgs_gunmap_gpu_mem(dev,handle)          \
 609         CGS_CALL(gunmap_gpu_mem,dev,handle)
 610 #define cgs_kmap_gpu_mem(dev,handle,map)        \
 611         CGS_CALL(kmap_gpu_mem,dev,handle,map)
 612 #define cgs_kunmap_gpu_mem(dev,handle)          \
 613         CGS_CALL(kunmap_gpu_mem,dev,handle)
 614
 615 #define cgs_read_register(dev,offset)           \
 616         CGS_CALL(read_register,dev,offset)
 617 #define cgs_write_register(dev,offset,value)            \
 618         CGS_CALL(write_register,dev,offset,value)
 619 #define cgs_read_ind_register(dev,space,index)          \
 620         CGS_CALL(read_ind_register,dev,space,index)
 621 #define cgs_write_ind_register(dev,space,index,value)           \
 622         CGS_CALL(write_ind_register,dev,space,index,value)
 623
 624 #define cgs_read_pci_config_byte(dev,addr)      \
 625         CGS_CALL(read_pci_config_byte,dev,addr)
 626 #define cgs_read_pci_config_word(dev,addr)      \
 627         CGS_CALL(read_pci_config_word,dev,addr)
 628 #define cgs_read_pci_config_dword(dev,addr)             \
 629         CGS_CALL(read_pci_config_dword,dev,addr)
 630 #define cgs_write_pci_config_byte(dev,addr,value)       \
 631         CGS_CALL(write_pci_config_byte,dev,addr,value)
 632 #define cgs_write_pci_config_word(dev,addr,value)       \
 633         CGS_CALL(write_pci_config_word,dev,addr,value)
 634 #define cgs_write_pci_config_dword(dev,addr,value)      \
 635         CGS_CALL(write_pci_config_dword,dev,addr,value)
 636
 637 #define cgs_atom_get_data_table(dev,table,size,frev,crev)       \
 638         CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
 639 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev)        \
 640         CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
 641 #define cgs_atom_exec_cmd_table(dev,table,args)         \
 642         CGS_CALL(atom_exec_cmd_table,dev,table,args)
 643
 644 #define cgs_create_pm_request(dev,request)      \
 645         CGS_CALL(create_pm_request,dev,request)
 646 #define cgs_destroy_pm_request(dev,request)             \
 647         CGS_CALL(destroy_pm_request,dev,request)
 648 #define cgs_set_pm_request(dev,request,active)          \
 649         CGS_CALL(set_pm_request,dev,request,active)
 650 #define cgs_pm_request_clock(dev,request,clock,freq)            \
 651         CGS_CALL(pm_request_clock,dev,request,clock,freq)
 652 #define cgs_pm_request_engine(dev,request,engine,powered)       \
 653         CGS_CALL(pm_request_engine,dev,request,engine,powered)
 654 #define cgs_pm_query_clock_limits(dev,clock,limits)             \
 655         CGS_CALL(pm_query_clock_limits,dev,clock,limits)
 656 #define cgs_set_camera_voltages(dev,mask,voltages)      \
 657         CGS_CALL(set_camera_voltages,dev,mask,voltages)
 658 #define cgs_get_firmware_info(dev, type, info)  \
 659         CGS_CALL(get_firmware_info, dev, type, info)
 660 #define cgs_set_powergating_state(dev, block_type, state)       \
 661         CGS_CALL(set_powergating_state, dev, block_type, state)
 662 #define cgs_set_clockgating_state(dev, block_type, state)       \
 663         CGS_CALL(set_clockgating_state, dev, block_type, state)
 664 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)  \
 665         CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
 666
 667 #endif /* _CGS_COMMON_H */