drivers/gpu/drm/amd/powerplay/amd_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/gfp.h>
  26 #include <linux/slab.h>
  27 #include "amd_shared.h"
  28 #include "amd_powerplay.h"
  29 #include "pp_instance.h"
  30 #include "power_state.h"
  31 #include "eventmanager.h"
  32 #include "pp_debug.h"
  33
  34
  35 #define PP_CHECK(handle)                                                \
  36         do {                                                            \
  37                 if ((handle) == NULL || (handle)->pp_valid != PP_VALID) \
  38                         return -EINVAL;                                 \
  39         } while (0)
  40
  41 #define PP_CHECK_HW(hwmgr)                                              \
  42         do {                                                            \
  43                 if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL)     \
  44                         return -EINVAL;                                 \
  45         } while (0)
  46
  47 static int pp_early_init(void *handle)
  48 {
  49         return 0;
  50 }
  51
  52 static int pp_sw_init(void *handle)
  53 {
  54         struct pp_instance *pp_handle;
  55         struct pp_hwmgr  *hwmgr;
  56         int ret = 0;
  57
  58         if (handle == NULL)
  59                 return -EINVAL;
  60
  61         pp_handle = (struct pp_instance *)handle;
  62         hwmgr = pp_handle->hwmgr;
  63
  64         PP_CHECK_HW(hwmgr);
  65
  66         if (hwmgr->pptable_func == NULL ||
  67             hwmgr->pptable_func->pptable_init == NULL ||
  68             hwmgr->hwmgr_func->backend_init == NULL)
  69                 return -EINVAL;
  70
  71         ret = hwmgr->pptable_func->pptable_init(hwmgr);
  72         if (ret)
  73                 goto err;
  74
  75         ret = hwmgr->hwmgr_func->backend_init(hwmgr);
  76         if (ret)
  77                 goto err1;
  78
  79         pr_info("amdgpu: powerplay initialized\n");
  80
  81         return 0;
  82 err1:
  83         if (hwmgr->pptable_func->pptable_fini)
  84                 hwmgr->pptable_func->pptable_fini(hwmgr);
  85 err:
  86         pr_err("amdgpu: powerplay initialization failed\n");
  87         return ret;
  88 }
  89
  90 static int pp_sw_fini(void *handle)
  91 {
  92         struct pp_instance *pp_handle;
  93         struct pp_hwmgr  *hwmgr;
  94         int ret = 0;
  95
  96         if (handle == NULL)
  97                 return -EINVAL;
  98
  99         pp_handle = (struct pp_instance *)handle;
 100         hwmgr = pp_handle->hwmgr;
 101
 102         PP_CHECK_HW(hwmgr);
 103
 104         if (hwmgr->hwmgr_func->backend_fini != NULL)
 105                 ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
 106
 107         if (hwmgr->pptable_func->pptable_fini)
 108                 hwmgr->pptable_func->pptable_fini(hwmgr);
 109
 110         return ret;
 111 }
 112
 113 static int pp_hw_init(void *handle)
 114 {
 115         struct pp_instance *pp_handle;
 116         struct pp_smumgr *smumgr;
 117         struct pp_eventmgr *eventmgr;
 118         int ret = 0;
 119
 120         if (handle == NULL)
 121                 return -EINVAL;
 122
 123         pp_handle = (struct pp_instance *)handle;
 124         smumgr = pp_handle->smu_mgr;
 125
 126         if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
 127                 smumgr->smumgr_funcs->smu_init == NULL ||
 128                 smumgr->smumgr_funcs->start_smu == NULL)
 129                 return -EINVAL;
 130
 131         ret = smumgr->smumgr_funcs->smu_init(smumgr);
 132         if (ret) {
 133                 printk(KERN_ERR "[ powerplay ] smc initialization failed\n");
 134                 return ret;
 135         }
 136
 137         ret = smumgr->smumgr_funcs->start_smu(smumgr);
 138         if (ret) {
 139                 printk(KERN_ERR "[ powerplay ] smc start failed\n");
 140                 smumgr->smumgr_funcs->smu_fini(smumgr);
 141                 return ret;
 142         }
 143
 144         hw_init_power_state_table(pp_handle->hwmgr);
 145         eventmgr = pp_handle->eventmgr;
 146
 147         if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
 148                 return -EINVAL;
 149
 150         ret = eventmgr->pp_eventmgr_init(eventmgr);
 151         return 0;
 152 }
 153
 154 static int pp_hw_fini(void *handle)
 155 {
 156         struct pp_instance *pp_handle;
 157         struct pp_smumgr *smumgr;
 158         struct pp_eventmgr *eventmgr;
 159
 160         if (handle == NULL)
 161                 return -EINVAL;
 162
 163         pp_handle = (struct pp_instance *)handle;
 164         eventmgr = pp_handle->eventmgr;
 165
 166         if (eventmgr != NULL && eventmgr->pp_eventmgr_fini != NULL)
 167                 eventmgr->pp_eventmgr_fini(eventmgr);
 168
 169         smumgr = pp_handle->smu_mgr;
 170
 171         if (smumgr != NULL && smumgr->smumgr_funcs != NULL &&
 172                 smumgr->smumgr_funcs->smu_fini != NULL)
 173                 smumgr->smumgr_funcs->smu_fini(smumgr);
 174
 175         return 0;
 176 }
 177
 178 static bool pp_is_idle(void *handle)
 179 {
 180         return false;
 181 }
 182
 183 static int pp_wait_for_idle(void *handle)
 184 {
 185         return 0;
 186 }
 187
 188 static int pp_sw_reset(void *handle)
 189 {
 190         return 0;
 191 }
 192
 193
 194 static int pp_set_clockgating_state(void *handle,
 195                                     enum amd_clockgating_state state)
 196 {
 197         struct pp_hwmgr  *hwmgr;
 198         uint32_t msg_id, pp_state;
 199
 200         if (handle == NULL)
 201                 return -EINVAL;
 202
 203         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 204
 205         PP_CHECK_HW(hwmgr);
 206
 207         if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
 208                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 209                 return 0;
 210         }
 211
 212         if (state == AMD_CG_STATE_UNGATE)
 213                 pp_state = 0;
 214         else
 215                 pp_state = PP_STATE_CG | PP_STATE_LS;
 216
 217         /* Enable/disable GFX blocks clock gating through SMU */
 218         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 219                         PP_BLOCK_GFX_CG,
 220                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 221                         pp_state);
 222         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 223         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 224                         PP_BLOCK_GFX_3D,
 225                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 226                         pp_state);
 227         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 228         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 229                         PP_BLOCK_GFX_RLC,
 230                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 231                         pp_state);
 232         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 233         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 234                         PP_BLOCK_GFX_CP,
 235                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 236                         pp_state);
 237         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 238         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 239                         PP_BLOCK_GFX_MG,
 240                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 241                         pp_state);
 242         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 243
 244         /* Enable/disable System blocks clock gating through SMU */
 245         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 246                         PP_BLOCK_SYS_BIF,
 247                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 248                         pp_state);
 249         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 250         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 251                         PP_BLOCK_SYS_BIF,
 252                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 253                         pp_state);
 254         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 255         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 256                         PP_BLOCK_SYS_MC,
 257                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 258                         pp_state);
 259         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 260         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 261                         PP_BLOCK_SYS_ROM,
 262                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 263                         pp_state);
 264         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 265         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 266                         PP_BLOCK_SYS_DRM,
 267                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 268                         pp_state);
 269         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 270         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 271                         PP_BLOCK_SYS_HDP,
 272                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 273                         pp_state);
 274         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 275         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 276                         PP_BLOCK_SYS_SDMA,
 277                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 278                         pp_state);
 279         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 280
 281         return 0;
 282 }
 283
 284 static int pp_set_powergating_state(void *handle,
 285                                     enum amd_powergating_state state)
 286 {
 287         struct pp_hwmgr  *hwmgr;
 288
 289         if (handle == NULL)
 290                 return -EINVAL;
 291
 292         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 293
 294         PP_CHECK_HW(hwmgr);
 295
 296         if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
 297                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 298                 return 0;
 299         }
 300
 301         /* Enable/disable GFX per cu powergating through SMU */
 302         return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
 303                         state == AMD_PG_STATE_GATE ? true : false);
 304 }
 305
 306 static int pp_suspend(void *handle)
 307 {
 308         struct pp_instance *pp_handle;
 309         struct pp_eventmgr *eventmgr;
 310         struct pem_event_data event_data = { {0} };
 311
 312         if (handle == NULL)
 313                 return -EINVAL;
 314
 315         pp_handle = (struct pp_instance *)handle;
 316         eventmgr = pp_handle->eventmgr;
 317         pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
 318         return 0;
 319 }
 320
 321 static int pp_resume(void *handle)
 322 {
 323         struct pp_instance *pp_handle;
 324         struct pp_eventmgr *eventmgr;
 325         struct pem_event_data event_data = { {0} };
 326         struct pp_smumgr *smumgr;
 327         int ret;
 328
 329         if (handle == NULL)
 330                 return -EINVAL;
 331
 332         pp_handle = (struct pp_instance *)handle;
 333         smumgr = pp_handle->smu_mgr;
 334
 335         if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
 336                 smumgr->smumgr_funcs->start_smu == NULL)
 337                 return -EINVAL;
 338
 339         ret = smumgr->smumgr_funcs->start_smu(smumgr);
 340         if (ret) {
 341                 printk(KERN_ERR "[ powerplay ] smc start failed\n");
 342                 smumgr->smumgr_funcs->smu_fini(smumgr);
 343                 return ret;
 344         }
 345
 346         eventmgr = pp_handle->eventmgr;
 347         pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
 348
 349         return 0;
 350 }
 351
 352 const struct amd_ip_funcs pp_ip_funcs = {
 353         .name = "powerplay",
 354         .early_init = pp_early_init,
 355         .late_init = NULL,
 356         .sw_init = pp_sw_init,
 357         .sw_fini = pp_sw_fini,
 358         .hw_init = pp_hw_init,
 359         .hw_fini = pp_hw_fini,
 360         .suspend = pp_suspend,
 361         .resume = pp_resume,
 362         .is_idle = pp_is_idle,
 363         .wait_for_idle = pp_wait_for_idle,
 364         .soft_reset = pp_sw_reset,
 365         .set_clockgating_state = pp_set_clockgating_state,
 366         .set_powergating_state = pp_set_powergating_state,
 367 };
 368
 369 static int pp_dpm_load_fw(void *handle)
 370 {
 371         return 0;
 372 }
 373
 374 static int pp_dpm_fw_loading_complete(void *handle)
 375 {
 376         return 0;
 377 }
 378
 379 static int pp_dpm_force_performance_level(void *handle,
 380                                         enum amd_dpm_forced_level level)
 381 {
 382         struct pp_instance *pp_handle;
 383         struct pp_hwmgr  *hwmgr;
 384
 385         if (handle == NULL)
 386                 return -EINVAL;
 387
 388         pp_handle = (struct pp_instance *)handle;
 389
 390         hwmgr = pp_handle->hwmgr;
 391
 392         PP_CHECK_HW(hwmgr);
 393
 394         if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
 395                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 396                 return 0;
 397         }
 398
 399         hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
 400
 401         return 0;
 402 }
 403
 404 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
 405                                                                 void *handle)
 406 {
 407         struct pp_hwmgr  *hwmgr;
 408
 409         if (handle == NULL)
 410                 return -EINVAL;
 411
 412         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 413
 414         if (hwmgr == NULL)
 415                 return -EINVAL;
 416
 417         return (((struct pp_instance *)handle)->hwmgr->dpm_level);
 418 }
 419
 420 static int pp_dpm_get_sclk(void *handle, bool low)
 421 {
 422         struct pp_hwmgr  *hwmgr;
 423
 424         if (handle == NULL)
 425                 return -EINVAL;
 426
 427         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 428
 429         PP_CHECK_HW(hwmgr);
 430
 431         if (hwmgr->hwmgr_func->get_sclk == NULL) {
 432                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 433                 return 0;
 434         }
 435
 436         return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
 437 }
 438
 439 static int pp_dpm_get_mclk(void *handle, bool low)
 440 {
 441         struct pp_hwmgr  *hwmgr;
 442
 443         if (handle == NULL)
 444                 return -EINVAL;
 445
 446         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 447
 448         PP_CHECK_HW(hwmgr);
 449
 450         if (hwmgr->hwmgr_func->get_mclk == NULL) {
 451                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 452                 return 0;
 453         }
 454
 455         return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
 456 }
 457
 458 static int pp_dpm_powergate_vce(void *handle, bool gate)
 459 {
 460         struct pp_hwmgr  *hwmgr;
 461
 462         if (handle == NULL)
 463                 return -EINVAL;
 464
 465         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 466
 467         PP_CHECK_HW(hwmgr);
 468
 469         if (hwmgr->hwmgr_func->powergate_vce == NULL) {
 470                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 471                 return 0;
 472         }
 473
 474         return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
 475 }
 476
 477 static int pp_dpm_powergate_uvd(void *handle, bool gate)
 478 {
 479         struct pp_hwmgr  *hwmgr;
 480
 481         if (handle == NULL)
 482                 return -EINVAL;
 483
 484         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 485
 486         PP_CHECK_HW(hwmgr);
 487
 488         if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
 489                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 490                 return 0;
 491         }
 492
 493         return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
 494 }
 495
 496 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
 497 {
 498         switch (state) {
 499         case POWER_STATE_TYPE_BATTERY:
 500                 return PP_StateUILabel_Battery;
 501         case POWER_STATE_TYPE_BALANCED:
 502                 return PP_StateUILabel_Balanced;
 503         case POWER_STATE_TYPE_PERFORMANCE:
 504                 return PP_StateUILabel_Performance;
 505         default:
 506                 return PP_StateUILabel_None;
 507         }
 508 }
 509
 510 int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
 511 {
 512         int ret = 0;
 513         struct pp_instance *pp_handle;
 514         struct pem_event_data data = { {0} };
 515
 516         pp_handle = (struct pp_instance *)handle;
 517
 518         if (pp_handle == NULL)
 519                 return -EINVAL;
 520
 521         switch (event_id) {
 522         case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
 523                 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 524                 break;
 525         case AMD_PP_EVENT_ENABLE_USER_STATE:
 526         {
 527                 enum amd_pm_state_type  ps;
 528
 529                 if (input == NULL)
 530                         return -EINVAL;
 531                 ps = *(unsigned long *)input;
 532
 533                 data.requested_ui_label = power_state_convert(ps);
 534                 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 535                 break;
 536         }
 537         case AMD_PP_EVENT_COMPLETE_INIT:
 538                 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 539                 break;
 540         case AMD_PP_EVENT_READJUST_POWER_STATE:
 541                 pp_handle->hwmgr->current_ps = pp_handle->hwmgr->boot_ps;
 542                 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 543                 break;
 544         default:
 545                 break;
 546         }
 547         return ret;
 548 }
 549
 550 enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
 551 {
 552         struct pp_hwmgr *hwmgr;
 553         struct pp_power_state *state;
 554
 555         if (handle == NULL)
 556                 return -EINVAL;
 557
 558         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 559
 560         if (hwmgr == NULL || hwmgr->current_ps == NULL)
 561                 return -EINVAL;
 562
 563         state = hwmgr->current_ps;
 564
 565         switch (state->classification.ui_label) {
 566         case PP_StateUILabel_Battery:
 567                 return POWER_STATE_TYPE_BATTERY;
 568         case PP_StateUILabel_Balanced:
 569                 return POWER_STATE_TYPE_BALANCED;
 570         case PP_StateUILabel_Performance:
 571                 return POWER_STATE_TYPE_PERFORMANCE;
 572         default:
 573                 if (state->classification.flags & PP_StateClassificationFlag_Boot)
 574                         return  POWER_STATE_TYPE_INTERNAL_BOOT;
 575                 else
 576                         return POWER_STATE_TYPE_DEFAULT;
 577         }
 578 }
 579
 580 static void
 581 pp_debugfs_print_current_performance_level(void *handle,
 582                                                struct seq_file *m)
 583 {
 584         struct pp_hwmgr  *hwmgr;
 585
 586         if (handle == NULL)
 587                 return;
 588
 589         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 590
 591         if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
 592                 return;
 593
 594         if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) {
 595                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 596                 return;
 597         }
 598
 599         hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
 600 }
 601
 602 static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
 603 {
 604         struct pp_hwmgr  *hwmgr;
 605
 606         if (handle == NULL)
 607                 return -EINVAL;
 608
 609         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 610
 611         PP_CHECK_HW(hwmgr);
 612
 613         if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
 614                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 615                 return 0;
 616         }
 617
 618         return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
 619 }
 620
 621 static int pp_dpm_get_fan_control_mode(void *handle)
 622 {
 623         struct pp_hwmgr  *hwmgr;
 624
 625         if (handle == NULL)
 626                 return -EINVAL;
 627
 628         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 629
 630         PP_CHECK_HW(hwmgr);
 631
 632         if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
 633                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 634                 return 0;
 635         }
 636
 637         return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
 638 }
 639
 640 static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
 641 {
 642         struct pp_hwmgr  *hwmgr;
 643
 644         if (handle == NULL)
 645                 return -EINVAL;
 646
 647         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 648
 649         PP_CHECK_HW(hwmgr);
 650
 651         if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
 652                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 653                 return 0;
 654         }
 655
 656         return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
 657 }
 658
 659 static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
 660 {
 661         struct pp_hwmgr  *hwmgr;
 662
 663         if (handle == NULL)
 664                 return -EINVAL;
 665
 666         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 667
 668         PP_CHECK_HW(hwmgr);
 669
 670         if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
 671                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 672                 return 0;
 673         }
 674
 675         return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
 676 }
 677
 678 static int pp_dpm_get_temperature(void *handle)
 679 {
 680         struct pp_hwmgr  *hwmgr;
 681
 682         if (handle == NULL)
 683                 return -EINVAL;
 684
 685         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 686
 687         PP_CHECK_HW(hwmgr);
 688
 689         if (hwmgr->hwmgr_func->get_temperature == NULL) {
 690                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 691                 return 0;
 692         }
 693
 694         return hwmgr->hwmgr_func->get_temperature(hwmgr);
 695 }
 696
 697 static int pp_dpm_get_pp_num_states(void *handle,
 698                 struct pp_states_info *data)
 699 {
 700         struct pp_hwmgr *hwmgr;
 701         int i;
 702
 703         if (!handle)
 704                 return -EINVAL;
 705
 706         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 707
 708         if (hwmgr == NULL || hwmgr->ps == NULL)
 709                 return -EINVAL;
 710
 711         data->nums = hwmgr->num_ps;
 712
 713         for (i = 0; i < hwmgr->num_ps; i++) {
 714                 struct pp_power_state *state = (struct pp_power_state *)
 715                                 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
 716                 switch (state->classification.ui_label) {
 717                 case PP_StateUILabel_Battery:
 718                         data->states[i] = POWER_STATE_TYPE_BATTERY;
 719                         break;
 720                 case PP_StateUILabel_Balanced:
 721                         data->states[i] = POWER_STATE_TYPE_BALANCED;
 722                         break;
 723                 case PP_StateUILabel_Performance:
 724                         data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
 725                         break;
 726                 default:
 727                         if (state->classification.flags & PP_StateClassificationFlag_Boot)
 728                                 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
 729                         else
 730                                 data->states[i] = POWER_STATE_TYPE_DEFAULT;
 731                 }
 732         }
 733
 734         return 0;
 735 }
 736
 737 static int pp_dpm_get_pp_table(void *handle, char **table)
 738 {
 739         struct pp_hwmgr *hwmgr;
 740
 741         if (!handle)
 742                 return -EINVAL;
 743
 744         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 745
 746         PP_CHECK_HW(hwmgr);
 747
 748         if (!hwmgr->soft_pp_table)
 749                 return -EINVAL;
 750
 751         *table = (char *)hwmgr->soft_pp_table;
 752
 753         return hwmgr->soft_pp_table_size;
 754 }
 755
 756 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
 757 {
 758         struct pp_hwmgr *hwmgr;
 759
 760         if (!handle)
 761                 return -EINVAL;
 762
 763         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 764
 765         PP_CHECK_HW(hwmgr);
 766
 767         if (!hwmgr->hardcode_pp_table) {
 768                 hwmgr->hardcode_pp_table =
 769                                 kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
 770
 771                 if (!hwmgr->hardcode_pp_table)
 772                         return -ENOMEM;
 773
 774                 /* to avoid powerplay crash when hardcode pptable is empty */
 775                 memcpy(hwmgr->hardcode_pp_table, hwmgr->soft_pp_table,
 776                                 hwmgr->soft_pp_table_size);
 777         }
 778
 779         memcpy(hwmgr->hardcode_pp_table, buf, size);
 780
 781         hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
 782
 783         return amd_powerplay_reset(handle);
 784 }
 785
 786 static int pp_dpm_force_clock_level(void *handle,
 787                 enum pp_clock_type type, uint32_t mask)
 788 {
 789         struct pp_hwmgr *hwmgr;
 790
 791         if (!handle)
 792                 return -EINVAL;
 793
 794         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 795
 796         PP_CHECK_HW(hwmgr);
 797
 798         if (hwmgr->hwmgr_func->force_clock_level == NULL) {
 799                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 800                 return 0;
 801         }
 802
 803         return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
 804 }
 805
 806 static int pp_dpm_print_clock_levels(void *handle,
 807                 enum pp_clock_type type, char *buf)
 808 {
 809         struct pp_hwmgr *hwmgr;
 810
 811         if (!handle)
 812                 return -EINVAL;
 813
 814         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 815
 816         PP_CHECK_HW(hwmgr);
 817
 818         if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
 819                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 820                 return 0;
 821         }
 822         return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
 823 }
 824
 825 static int pp_dpm_get_sclk_od(void *handle)
 826 {
 827         struct pp_hwmgr *hwmgr;
 828
 829         if (!handle)
 830                 return -EINVAL;
 831
 832         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 833
 834         PP_CHECK_HW(hwmgr);
 835
 836         if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
 837                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 838                 return 0;
 839         }
 840
 841         return hwmgr->hwmgr_func->get_sclk_od(hwmgr);
 842 }
 843
 844 static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
 845 {
 846         struct pp_hwmgr *hwmgr;
 847
 848         if (!handle)
 849                 return -EINVAL;
 850
 851         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 852
 853         PP_CHECK_HW(hwmgr);
 854
 855         if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
 856                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 857                 return 0;
 858         }
 859
 860         return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
 861 }
 862
 863 static int pp_dpm_get_mclk_od(void *handle)
 864 {
 865         struct pp_hwmgr *hwmgr;
 866
 867         if (!handle)
 868                 return -EINVAL;
 869
 870         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 871
 872         PP_CHECK_HW(hwmgr);
 873
 874         if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
 875                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 876                 return 0;
 877         }
 878
 879         return hwmgr->hwmgr_func->get_mclk_od(hwmgr);
 880 }
 881
 882 static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
 883 {
 884         struct pp_hwmgr *hwmgr;
 885
 886         if (!handle)
 887                 return -EINVAL;
 888
 889         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 890
 891         PP_CHECK_HW(hwmgr);
 892
 893         if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
 894                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 895                 return 0;
 896         }
 897
 898         return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
 899 }
 900
 901 const struct amd_powerplay_funcs pp_dpm_funcs = {
 902         .get_temperature = pp_dpm_get_temperature,
 903         .load_firmware = pp_dpm_load_fw,
 904         .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
 905         .force_performance_level = pp_dpm_force_performance_level,
 906         .get_performance_level = pp_dpm_get_performance_level,
 907         .get_current_power_state = pp_dpm_get_current_power_state,
 908         .get_sclk = pp_dpm_get_sclk,
 909         .get_mclk = pp_dpm_get_mclk,
 910         .powergate_vce = pp_dpm_powergate_vce,
 911         .powergate_uvd = pp_dpm_powergate_uvd,
 912         .dispatch_tasks = pp_dpm_dispatch_tasks,
 913         .print_current_performance_level = pp_debugfs_print_current_performance_level,
 914         .set_fan_control_mode = pp_dpm_set_fan_control_mode,
 915         .get_fan_control_mode = pp_dpm_get_fan_control_mode,
 916         .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
 917         .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
 918         .get_pp_num_states = pp_dpm_get_pp_num_states,
 919         .get_pp_table = pp_dpm_get_pp_table,
 920         .set_pp_table = pp_dpm_set_pp_table,
 921         .force_clock_level = pp_dpm_force_clock_level,
 922         .print_clock_levels = pp_dpm_print_clock_levels,
 923         .get_sclk_od = pp_dpm_get_sclk_od,
 924         .set_sclk_od = pp_dpm_set_sclk_od,
 925         .get_mclk_od = pp_dpm_get_mclk_od,
 926         .set_mclk_od = pp_dpm_set_mclk_od,
 927 };
 928
 929 static int amd_pp_instance_init(struct amd_pp_init *pp_init,
 930                                 struct amd_powerplay *amd_pp)
 931 {
 932         int ret;
 933         struct pp_instance *handle;
 934
 935         handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
 936         if (handle == NULL)
 937                 return -ENOMEM;
 938
 939         handle->pp_valid = PP_VALID;
 940
 941         ret = smum_init(pp_init, handle);
 942         if (ret)
 943                 goto fail_smum;
 944
 945         ret = hwmgr_init(pp_init, handle);
 946         if (ret)
 947                 goto fail_hwmgr;
 948
 949         ret = eventmgr_init(handle);
 950         if (ret)
 951                 goto fail_eventmgr;
 952
 953         amd_pp->pp_handle = handle;
 954         return 0;
 955
 956 fail_eventmgr:
 957         hwmgr_fini(handle->hwmgr);
 958 fail_hwmgr:
 959         smum_fini(handle->smu_mgr);
 960 fail_smum:
 961         kfree(handle);
 962         return ret;
 963 }
 964
 965 static int amd_pp_instance_fini(void *handle)
 966 {
 967         struct pp_instance *instance = (struct pp_instance *)handle;
 968
 969         if (instance == NULL)
 970                 return -EINVAL;
 971
 972         eventmgr_fini(instance->eventmgr);
 973
 974         hwmgr_fini(instance->hwmgr);
 975
 976         smum_fini(instance->smu_mgr);
 977
 978         kfree(handle);
 979         return 0;
 980 }
 981
 982 int amd_powerplay_init(struct amd_pp_init *pp_init,
 983                        struct amd_powerplay *amd_pp)
 984 {
 985         int ret;
 986
 987         if (pp_init == NULL || amd_pp == NULL)
 988                 return -EINVAL;
 989
 990         ret = amd_pp_instance_init(pp_init, amd_pp);
 991
 992         if (ret)
 993                 return ret;
 994
 995         amd_pp->ip_funcs = &pp_ip_funcs;
 996         amd_pp->pp_funcs = &pp_dpm_funcs;
 997
 998         return 0;
 999 }
1000
1001 int amd_powerplay_fini(void *handle)
1002 {
1003         amd_pp_instance_fini(handle);
1004
1005         return 0;
1006 }
1007
1008 int amd_powerplay_reset(void *handle)
1009 {
1010         struct pp_instance *instance = (struct pp_instance *)handle;
1011         struct pp_eventmgr *eventmgr;
1012         struct pem_event_data event_data = { {0} };
1013         int ret;
1014
1015         if (instance == NULL)
1016                 return -EINVAL;
1017
1018         eventmgr = instance->eventmgr;
1019         if (!eventmgr || !eventmgr->pp_eventmgr_fini)
1020                 return -EINVAL;
1021
1022         eventmgr->pp_eventmgr_fini(eventmgr);
1023
1024         ret = pp_sw_fini(handle);
1025         if (ret)
1026                 return ret;
1027
1028         kfree(instance->hwmgr->ps);
1029
1030         ret = pp_sw_init(handle);
1031         if (ret)
1032                 return ret;
1033
1034         hw_init_power_state_table(instance->hwmgr);
1035
1036         if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
1037                 return -EINVAL;
1038
1039         ret = eventmgr->pp_eventmgr_init(eventmgr);
1040         if (ret)
1041                 return ret;
1042
1043         return pem_handle_event(eventmgr, AMD_PP_EVENT_COMPLETE_INIT, &event_data);
1044 }
1045
1046 /* export this function to DAL */
1047
1048 int amd_powerplay_display_configuration_change(void *handle,
1049         const struct amd_pp_display_configuration *display_config)
1050 {
1051         struct pp_hwmgr  *hwmgr;
1052
1053         PP_CHECK((struct pp_instance *)handle);
1054
1055         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1056
1057         phm_store_dal_configuration_data(hwmgr, display_config);
1058
1059         return 0;
1060 }
1061
1062 int amd_powerplay_get_display_power_level(void *handle,
1063                 struct amd_pp_simple_clock_info *output)
1064 {
1065         struct pp_hwmgr  *hwmgr;
1066
1067         PP_CHECK((struct pp_instance *)handle);
1068
1069         if (output == NULL)
1070                 return -EINVAL;
1071
1072         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1073
1074         return phm_get_dal_power_level(hwmgr, output);
1075 }
1076
1077 int amd_powerplay_get_current_clocks(void *handle,
1078                 struct amd_pp_clock_info *clocks)
1079 {
1080         struct pp_hwmgr  *hwmgr;
1081         struct amd_pp_simple_clock_info simple_clocks;
1082         struct pp_clock_info hw_clocks;
1083
1084         PP_CHECK((struct pp_instance *)handle);
1085
1086         if (clocks == NULL)
1087                 return -EINVAL;
1088
1089         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1090
1091         phm_get_dal_power_level(hwmgr, &simple_clocks);
1092
1093         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
1094                 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment))
1095                         PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1);
1096         } else {
1097                 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity))
1098                         PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1);
1099         }
1100
1101         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1102         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1103         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1104         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1105         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1106         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1107
1108         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1109         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1110
1111         clocks->max_clocks_state = simple_clocks.level;
1112
1113         if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1114                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1115                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1116         }
1117
1118         return 0;
1119
1120 }
1121
1122 int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1123 {
1124         int result = -1;
1125
1126         struct pp_hwmgr *hwmgr;
1127
1128         PP_CHECK((struct pp_instance *)handle);
1129
1130         if (clocks == NULL)
1131                 return -EINVAL;
1132
1133         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1134
1135         result = phm_get_clock_by_type(hwmgr, type, clocks);
1136
1137         return result;
1138 }
1139
1140 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
1141                 struct amd_pp_simple_clock_info *clocks)
1142 {
1143         int result = -1;
1144         struct pp_hwmgr  *hwmgr;
1145
1146         PP_CHECK((struct pp_instance *)handle);
1147
1148         if (clocks == NULL)
1149                 return -EINVAL;
1150
1151         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1152
1153         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1154                 result = phm_get_max_high_clocks(hwmgr, clocks);
1155
1156         return result;
1157 }
1158