2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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25 #include "cz_clockpowergating.h"
28 /* PhyID -> Status Mapping in DDI_PHY_GEN_STATUS
29 0 GFX0L (3:0), (27:24),
30 1 GFX0H (7:4), (31:28),
31 2 GFX1L (3:0), (19:16),
32 3 GFX1H (7:4), (23:20),
33 4 DDIL (3:0), (11: 8),
34 5 DDIH (7:4), (15:12),
35 6 DDI2L (3:0), ( 3: 0),
36 7 DDI2H (7:4), ( 7: 4),
38 #define DDI_PHY_GEN_STATUS_VAL(phyID) (1 << ((3 - ((phyID & 0x07)/2))*8 + (phyID & 0x01)*4))
39 #define IS_PHY_ID_USED_BY_PLL(PhyID) (((0xF3 & (1 << PhyID)) & 0xFF) ? true : false)
42 int cz_phm_set_asic_block_gating(struct pp_hwmgr
*hwmgr
, enum PHM_AsicBlock block
, enum PHM_ClockGateSetting gating
)
47 case PHM_AsicBlock_UVD_MVC
:
48 case PHM_AsicBlock_UVD
:
49 case PHM_AsicBlock_UVD_HD
:
50 case PHM_AsicBlock_UVD_SD
:
51 if (gating
== PHM_ClockGateSetting_StaticOff
)
52 ret
= cz_dpm_powerdown_uvd(hwmgr
);
54 ret
= cz_dpm_powerup_uvd(hwmgr
);
56 case PHM_AsicBlock_GFX
:
65 bool cz_phm_is_safe_for_asic_block(struct pp_hwmgr
*hwmgr
, const struct pp_hw_power_state
*state
, enum PHM_AsicBlock block
)
71 int cz_phm_enable_disable_gfx_power_gating(struct pp_hwmgr
*hwmgr
, bool enable
)
76 int cz_phm_smu_power_up_down_pcie(struct pp_hwmgr
*hwmgr
, uint32_t target
, bool up
, uint32_t args
)
82 int cz_phm_initialize_display_phy_access(struct pp_hwmgr
*hwmgr
, bool initialize
, bool accesshw
)
88 int cz_phm_get_display_phy_access_info(struct pp_hwmgr
*hwmgr
)
94 int cz_phm_gate_unused_display_phys(struct pp_hwmgr
*hwmgr
)
100 int cz_phm_ungate_all_display_phys(struct pp_hwmgr
*hwmgr
)
106 static int cz_tf_uvd_power_gating_initialize(struct pp_hwmgr
*hwmgr
, void *pInput
, void *pOutput
, void *pStorage
, int Result
)
111 static int cz_tf_vce_power_gating_initialize(struct pp_hwmgr
*hwmgr
, void *pInput
, void *pOutput
, void *pStorage
, int Result
)
116 int cz_enable_disable_uvd_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
118 struct cz_hwmgr
*cz_hwmgr
= (struct cz_hwmgr
*)(hwmgr
->backend
);
119 uint32_t dpm_features
= 0;
122 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
123 PHM_PlatformCaps_UVDDPM
)) {
124 cz_hwmgr
->dpm_flags
|= DPMFlags_UVD_Enabled
;
125 dpm_features
|= UVD_DPM_MASK
;
126 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
127 PPSMC_MSG_EnableAllSmuFeatures
, dpm_features
);
129 dpm_features
|= UVD_DPM_MASK
;
130 cz_hwmgr
->dpm_flags
&= ~DPMFlags_UVD_Enabled
;
131 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
132 PPSMC_MSG_DisableAllSmuFeatures
, dpm_features
);
137 int cz_enable_disable_vce_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
139 struct cz_hwmgr
*cz_hwmgr
= (struct cz_hwmgr
*)(hwmgr
->backend
);
140 uint32_t dpm_features
= 0;
142 if (enable
&& phm_cap_enabled(
143 hwmgr
->platform_descriptor
.platformCaps
,
144 PHM_PlatformCaps_VCEDPM
)) {
145 cz_hwmgr
->dpm_flags
|= DPMFlags_VCE_Enabled
;
146 dpm_features
|= VCE_DPM_MASK
;
147 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
148 PPSMC_MSG_EnableAllSmuFeatures
, dpm_features
);
150 dpm_features
|= VCE_DPM_MASK
;
151 cz_hwmgr
->dpm_flags
&= ~DPMFlags_VCE_Enabled
;
152 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
153 PPSMC_MSG_DisableAllSmuFeatures
, dpm_features
);
160 int cz_dpm_powergate_uvd(struct pp_hwmgr
*hwmgr
, bool bgate
)
162 struct cz_hwmgr
*cz_hwmgr
= (struct cz_hwmgr
*)(hwmgr
->backend
);
164 if (cz_hwmgr
->uvd_power_gated
== bgate
)
167 cz_hwmgr
->uvd_power_gated
= bgate
;
170 cgs_set_clockgating_state(hwmgr
->device
,
171 AMD_IP_BLOCK_TYPE_UVD
,
172 AMD_CG_STATE_UNGATE
);
173 cgs_set_powergating_state(hwmgr
->device
,
174 AMD_IP_BLOCK_TYPE_UVD
,
176 cz_dpm_update_uvd_dpm(hwmgr
, true);
177 cz_dpm_powerdown_uvd(hwmgr
);
179 cz_dpm_powerup_uvd(hwmgr
);
180 cgs_set_clockgating_state(hwmgr
->device
,
181 AMD_IP_BLOCK_TYPE_UVD
,
183 cgs_set_powergating_state(hwmgr
->device
,
184 AMD_IP_BLOCK_TYPE_UVD
,
185 AMD_CG_STATE_UNGATE
);
186 cz_dpm_update_uvd_dpm(hwmgr
, false);
192 int cz_dpm_powergate_vce(struct pp_hwmgr
*hwmgr
, bool bgate
)
194 struct cz_hwmgr
*cz_hwmgr
= (struct cz_hwmgr
*)(hwmgr
->backend
);
196 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
197 PHM_PlatformCaps_VCEPowerGating
)) {
198 if (cz_hwmgr
->vce_power_gated
!= bgate
) {
200 cgs_set_clockgating_state(
202 AMD_IP_BLOCK_TYPE_VCE
,
203 AMD_CG_STATE_UNGATE
);
204 cgs_set_powergating_state(
206 AMD_IP_BLOCK_TYPE_VCE
,
208 cz_enable_disable_vce_dpm(hwmgr
, false);
209 /* TODO: to figure out why vce can't be poweroff*/
210 cz_hwmgr
->vce_power_gated
= true;
212 cz_dpm_powerup_vce(hwmgr
);
213 cz_hwmgr
->vce_power_gated
= false;
214 cgs_set_clockgating_state(
216 AMD_IP_BLOCK_TYPE_VCE
,
218 cgs_set_powergating_state(
220 AMD_IP_BLOCK_TYPE_VCE
,
221 AMD_CG_STATE_UNGATE
);
222 cz_dpm_update_vce_dpm(hwmgr
);
223 cz_enable_disable_vce_dpm(hwmgr
, true);
228 cz_dpm_update_vce_dpm(hwmgr
);
229 cz_enable_disable_vce_dpm(hwmgr
, true);
233 if (!cz_hwmgr
->vce_power_gated
)
234 cz_dpm_update_vce_dpm(hwmgr
);
240 static struct phm_master_table_item cz_enable_clock_power_gatings_list
[] = {
241 /*we don't need an exit table here, because there is only D3 cold on Kv*/
242 { phm_cf_want_uvd_power_gating
, cz_tf_uvd_power_gating_initialize
},
243 { phm_cf_want_vce_power_gating
, cz_tf_vce_power_gating_initialize
},
244 /* to do { NULL, cz_tf_xdma_power_gating_enable }, */
248 struct phm_master_table_header cz_phm_enable_clock_power_gatings_master
= {
250 PHM_MasterTableFlag_None
,
251 cz_enable_clock_power_gatings_list