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[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / cz_hwmgr.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include "atom-types.h"
27 #include "atombios.h"
28 #include "processpptables.h"
29 #include "pp_debug.h"
30 #include "cgs_common.h"
31 #include "smu/smu_8_0_d.h"
32 #include "smu8_fusion.h"
33 #include "smu/smu_8_0_sh_mask.h"
34 #include "smumgr.h"
35 #include "hwmgr.h"
36 #include "hardwaremanager.h"
37 #include "cz_ppsmc.h"
38 #include "cz_hwmgr.h"
39 #include "power_state.h"
40 #include "cz_clockpowergating.h"
41 #include "pp_debug.h"
42
43 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
44 #define CURRENT_NB_VID_MASK 0xff000000
45 #define CURRENT_NB_VID__SHIFT 24
46 #define ixSMUSVI_GFX_CURRENTVID 0xD8230048
47 #define CURRENT_GFX_VID_MASK 0xff000000
48 #define CURRENT_GFX_VID__SHIFT 24
49
50 static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
51
52 static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
53 {
54 if (PhwCz_Magic != hw_ps->magic)
55 return NULL;
56
57 return (struct cz_power_state *)hw_ps;
58 }
59
60 static const struct cz_power_state *cast_const_PhwCzPowerState(
61 const struct pp_hw_power_state *hw_ps)
62 {
63 if (PhwCz_Magic != hw_ps->magic)
64 return NULL;
65
66 return (struct cz_power_state *)hw_ps;
67 }
68
69 uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
70 uint32_t clock, uint32_t msg)
71 {
72 int i = 0;
73 struct phm_vce_clock_voltage_dependency_table *ptable =
74 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
75
76 switch (msg) {
77 case PPSMC_MSG_SetEclkSoftMin:
78 case PPSMC_MSG_SetEclkHardMin:
79 for (i = 0; i < (int)ptable->count; i++) {
80 if (clock <= ptable->entries[i].ecclk)
81 break;
82 }
83 break;
84
85 case PPSMC_MSG_SetEclkSoftMax:
86 case PPSMC_MSG_SetEclkHardMax:
87 for (i = ptable->count - 1; i >= 0; i--) {
88 if (clock >= ptable->entries[i].ecclk)
89 break;
90 }
91 break;
92
93 default:
94 break;
95 }
96
97 return i;
98 }
99
100 static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
101 uint32_t clock, uint32_t msg)
102 {
103 int i = 0;
104 struct phm_clock_voltage_dependency_table *table =
105 hwmgr->dyn_state.vddc_dependency_on_sclk;
106
107 switch (msg) {
108 case PPSMC_MSG_SetSclkSoftMin:
109 case PPSMC_MSG_SetSclkHardMin:
110 for (i = 0; i < (int)table->count; i++) {
111 if (clock <= table->entries[i].clk)
112 break;
113 }
114 break;
115
116 case PPSMC_MSG_SetSclkSoftMax:
117 case PPSMC_MSG_SetSclkHardMax:
118 for (i = table->count - 1; i >= 0; i--) {
119 if (clock >= table->entries[i].clk)
120 break;
121 }
122 break;
123
124 default:
125 break;
126 }
127 return i;
128 }
129
130 static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
131 uint32_t clock, uint32_t msg)
132 {
133 int i = 0;
134 struct phm_uvd_clock_voltage_dependency_table *ptable =
135 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
136
137 switch (msg) {
138 case PPSMC_MSG_SetUvdSoftMin:
139 case PPSMC_MSG_SetUvdHardMin:
140 for (i = 0; i < (int)ptable->count; i++) {
141 if (clock <= ptable->entries[i].vclk)
142 break;
143 }
144 break;
145
146 case PPSMC_MSG_SetUvdSoftMax:
147 case PPSMC_MSG_SetUvdHardMax:
148 for (i = ptable->count - 1; i >= 0; i--) {
149 if (clock >= ptable->entries[i].vclk)
150 break;
151 }
152 break;
153
154 default:
155 break;
156 }
157
158 return i;
159 }
160
161 static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
162 {
163 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
164
165 if (cz_hwmgr->max_sclk_level == 0) {
166 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
167 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
168 }
169
170 return cz_hwmgr->max_sclk_level;
171 }
172
173 static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
174 {
175 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
176 uint32_t i;
177
178 cz_hwmgr->gfx_ramp_step = 256*25/100;
179
180 cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
181
182 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
183 cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
184
185 cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
186 cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
187
188 cz_hwmgr->clock_slow_down_freq = 25000;
189
190 cz_hwmgr->skip_clock_slow_down = 1;
191
192 cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
193
194 cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
195
196 cz_hwmgr->voting_rights_clients = 0x00C00033;
197
198 cz_hwmgr->static_screen_threshold = 8;
199
200 cz_hwmgr->ddi_power_gating_disabled = 0;
201
202 cz_hwmgr->bapm_enabled = 1;
203
204 cz_hwmgr->voltage_drop_threshold = 0;
205
206 cz_hwmgr->gfx_power_gating_threshold = 500;
207
208 cz_hwmgr->vce_slow_sclk_threshold = 20000;
209
210 cz_hwmgr->dce_slow_sclk_threshold = 30000;
211
212 cz_hwmgr->disable_driver_thermal_policy = 1;
213
214 cz_hwmgr->disable_nb_ps3_in_battery = 0;
215
216 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_ABM);
218
219 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
220 PHM_PlatformCaps_NonABMSupportInPPLib);
221
222 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
223 PHM_PlatformCaps_SclkDeepSleep);
224
225 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
226 PHM_PlatformCaps_DynamicM3Arbiter);
227
228 cz_hwmgr->override_dynamic_mgpg = 1;
229
230 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
231 PHM_PlatformCaps_DynamicPatchPowerState);
232
233 cz_hwmgr->thermal_auto_throttling_treshold = 0;
234
235 cz_hwmgr->tdr_clock = 0;
236
237 cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
238
239 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
240 PHM_PlatformCaps_DynamicUVDState);
241
242 cz_hwmgr->display_cfg.cpu_cc6_disable = false;
243 cz_hwmgr->display_cfg.cpu_pstate_disable = false;
244 cz_hwmgr->display_cfg.nb_pstate_switch_disable = false;
245 cz_hwmgr->display_cfg.cpu_pstate_separation_time = 0;
246
247 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
248 PHM_PlatformCaps_DisableVoltageIsland);
249
250 return 0;
251 }
252
253 static uint32_t cz_convert_8Bit_index_to_voltage(
254 struct pp_hwmgr *hwmgr, uint16_t voltage)
255 {
256 return 6200 - (voltage * 25);
257 }
258
259 static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
260 struct phm_clock_and_voltage_limits *table)
261 {
262 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
263 struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
264 struct phm_clock_voltage_dependency_table *dep_table =
265 hwmgr->dyn_state.vddc_dependency_on_sclk;
266
267 if (dep_table->count > 0) {
268 table->sclk = dep_table->entries[dep_table->count-1].clk;
269 table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
270 (uint16_t)dep_table->entries[dep_table->count-1].v);
271 }
272 table->mclk = sys_info->nbp_memory_clock[0];
273 return 0;
274 }
275
276 static int cz_init_dynamic_state_adjustment_rule_settings(
277 struct pp_hwmgr *hwmgr,
278 ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
279 {
280 uint32_t table_size =
281 sizeof(struct phm_clock_voltage_dependency_table) +
282 (7 * sizeof(struct phm_clock_voltage_dependency_record));
283
284 struct phm_clock_voltage_dependency_table *table_clk_vlt =
285 kzalloc(table_size, GFP_KERNEL);
286
287 if (NULL == table_clk_vlt) {
288 printk(KERN_ERR "[ powerplay ] Can not allocate memory!\n");
289 return -ENOMEM;
290 }
291
292 table_clk_vlt->count = 8;
293 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
294 table_clk_vlt->entries[0].v = 0;
295 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
296 table_clk_vlt->entries[1].v = 1;
297 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
298 table_clk_vlt->entries[2].v = 2;
299 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
300 table_clk_vlt->entries[3].v = 3;
301 table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
302 table_clk_vlt->entries[4].v = 4;
303 table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
304 table_clk_vlt->entries[5].v = 5;
305 table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
306 table_clk_vlt->entries[6].v = 6;
307 table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
308 table_clk_vlt->entries[7].v = 7;
309 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
310
311 return 0;
312 }
313
314 static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
315 {
316 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
317 ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
318 uint32_t i;
319 int result = 0;
320 uint8_t frev, crev;
321 uint16_t size;
322
323 info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
324 hwmgr->device,
325 GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
326 &size, &frev, &crev);
327
328 if (crev != 9) {
329 printk(KERN_ERR "[ powerplay ] Unsupported IGP table: %d %d\n", frev, crev);
330 return -EINVAL;
331 }
332
333 if (info == NULL) {
334 printk(KERN_ERR "[ powerplay ] Could not retrieve the Integrated System Info Table!\n");
335 return -EINVAL;
336 }
337
338 cz_hwmgr->sys_info.bootup_uma_clock =
339 le32_to_cpu(info->ulBootUpUMAClock);
340
341 cz_hwmgr->sys_info.bootup_engine_clock =
342 le32_to_cpu(info->ulBootUpEngineClock);
343
344 cz_hwmgr->sys_info.dentist_vco_freq =
345 le32_to_cpu(info->ulDentistVCOFreq);
346
347 cz_hwmgr->sys_info.system_config =
348 le32_to_cpu(info->ulSystemConfig);
349
350 cz_hwmgr->sys_info.bootup_nb_voltage_index =
351 le16_to_cpu(info->usBootUpNBVoltage);
352
353 cz_hwmgr->sys_info.htc_hyst_lmt =
354 (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
355
356 cz_hwmgr->sys_info.htc_tmp_lmt =
357 (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
358
359 if (cz_hwmgr->sys_info.htc_tmp_lmt <=
360 cz_hwmgr->sys_info.htc_hyst_lmt) {
361 printk(KERN_ERR "[ powerplay ] The htcTmpLmt should be larger than htcHystLmt.\n");
362 return -EINVAL;
363 }
364
365 cz_hwmgr->sys_info.nb_dpm_enable =
366 cz_hwmgr->enable_nb_ps_policy &&
367 (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
368
369 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
370 if (i < CZ_NUM_NBPMEMORYCLOCK) {
371 cz_hwmgr->sys_info.nbp_memory_clock[i] =
372 le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
373 }
374 cz_hwmgr->sys_info.nbp_n_clock[i] =
375 le32_to_cpu(info->ulNbpStateNClkFreq[i]);
376 }
377
378 for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
379 cz_hwmgr->sys_info.display_clock[i] =
380 le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
381 }
382
383 /* Here use 4 levels, make sure not exceed */
384 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
385 cz_hwmgr->sys_info.nbp_voltage_index[i] =
386 le16_to_cpu(info->usNBPStateVoltage[i]);
387 }
388
389 if (!cz_hwmgr->sys_info.nb_dpm_enable) {
390 for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
391 if (i < CZ_NUM_NBPMEMORYCLOCK) {
392 cz_hwmgr->sys_info.nbp_memory_clock[i] =
393 cz_hwmgr->sys_info.nbp_memory_clock[0];
394 }
395 cz_hwmgr->sys_info.nbp_n_clock[i] =
396 cz_hwmgr->sys_info.nbp_n_clock[0];
397 cz_hwmgr->sys_info.nbp_voltage_index[i] =
398 cz_hwmgr->sys_info.nbp_voltage_index[0];
399 }
400 }
401
402 if (le32_to_cpu(info->ulGPUCapInfo) &
403 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
404 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
405 PHM_PlatformCaps_EnableDFSBypass);
406 }
407
408 cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
409
410 cz_construct_max_power_limits_table (hwmgr,
411 &hwmgr->dyn_state.max_clock_voltage_on_ac);
412
413 cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
414 &info->sDISPCLK_Voltage[0]);
415
416 return result;
417 }
418
419 static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
420 {
421 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
422
423 cz_hwmgr->boot_power_level.engineClock =
424 cz_hwmgr->sys_info.bootup_engine_clock;
425
426 cz_hwmgr->boot_power_level.vddcIndex =
427 (uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
428
429 cz_hwmgr->boot_power_level.dsDividerIndex = 0;
430
431 cz_hwmgr->boot_power_level.ssDividerIndex = 0;
432
433 cz_hwmgr->boot_power_level.allowGnbSlow = 1;
434
435 cz_hwmgr->boot_power_level.forceNBPstate = 0;
436
437 cz_hwmgr->boot_power_level.hysteresis_up = 0;
438
439 cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
440
441 cz_hwmgr->boot_power_level.display_wm = 0;
442
443 cz_hwmgr->boot_power_level.vce_wm = 0;
444
445 return 0;
446 }
447
448 static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
449 void *output, void *storage, int result)
450 {
451 return 0;
452 }
453
454 static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
455 void *output, void *storage, int result)
456 {
457 struct SMU8_Fusion_ClkTable *clock_table;
458 int ret;
459 uint32_t i;
460 void *table = NULL;
461 pp_atomctrl_clock_dividers_kong dividers;
462
463 struct phm_clock_voltage_dependency_table *vddc_table =
464 hwmgr->dyn_state.vddc_dependency_on_sclk;
465 struct phm_clock_voltage_dependency_table *vdd_gfx_table =
466 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
467 struct phm_acp_clock_voltage_dependency_table *acp_table =
468 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
469 struct phm_uvd_clock_voltage_dependency_table *uvd_table =
470 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
471 struct phm_vce_clock_voltage_dependency_table *vce_table =
472 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
473
474 if (!hwmgr->need_pp_table_upload)
475 return 0;
476
477 ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
478
479 PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
480 "Fail to get clock table from SMU!", return -EINVAL;);
481
482 clock_table = (struct SMU8_Fusion_ClkTable *)table;
483
484 /* patch clock table */
485 PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
486 "Dependency table entry exceeds max limit!", return -EINVAL;);
487 PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
488 "Dependency table entry exceeds max limit!", return -EINVAL;);
489 PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
490 "Dependency table entry exceeds max limit!", return -EINVAL;);
491 PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
492 "Dependency table entry exceeds max limit!", return -EINVAL;);
493 PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
494 "Dependency table entry exceeds max limit!", return -EINVAL;);
495
496 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
497
498 /* vddc_sclk */
499 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
500 (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
501 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
502 (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
503
504 atomctrl_get_engine_pll_dividers_kong(hwmgr,
505 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
506 &dividers);
507
508 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
509 (uint8_t)dividers.pll_post_divider;
510
511 /* vddgfx_sclk */
512 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
513 (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
514
515 /* acp breakdown */
516 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
517 (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
518 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
519 (i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
520
521 atomctrl_get_engine_pll_dividers_kong(hwmgr,
522 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
523 &dividers);
524
525 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
526 (uint8_t)dividers.pll_post_divider;
527
528
529 /* uvd breakdown */
530 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
531 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
532 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
533 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
534
535 atomctrl_get_engine_pll_dividers_kong(hwmgr,
536 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
537 &dividers);
538
539 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
540 (uint8_t)dividers.pll_post_divider;
541
542 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
543 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
544 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
545 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
546
547 atomctrl_get_engine_pll_dividers_kong(hwmgr,
548 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
549 &dividers);
550
551 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
552 (uint8_t)dividers.pll_post_divider;
553
554 /* vce breakdown */
555 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
556 (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
557 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
558 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
559
560
561 atomctrl_get_engine_pll_dividers_kong(hwmgr,
562 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
563 &dividers);
564
565 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
566 (uint8_t)dividers.pll_post_divider;
567
568 }
569 ret = smum_upload_powerplay_table(hwmgr->smumgr);
570
571 return ret;
572 }
573
574 static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
575 void *output, void *storage, int result)
576 {
577 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
578 struct phm_clock_voltage_dependency_table *table =
579 hwmgr->dyn_state.vddc_dependency_on_sclk;
580 unsigned long clock = 0, level;
581
582 if (NULL == table && table->count <= 0)
583 return -EINVAL;
584
585 cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
586 cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
587
588 level = cz_get_max_sclk_level(hwmgr) - 1;
589
590 if (level < table->count)
591 clock = table->entries[level].clk;
592 else
593 clock = table->entries[table->count - 1].clk;
594
595 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
596 cz_hwmgr->sclk_dpm.hard_max_clk = clock;
597
598 return 0;
599 }
600
601 static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
602 void *output, void *storage, int result)
603 {
604 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
605 struct phm_uvd_clock_voltage_dependency_table *table =
606 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
607 unsigned long clock = 0, level;
608
609 if (NULL == table && table->count <= 0)
610 return -EINVAL;
611
612 cz_hwmgr->uvd_dpm.soft_min_clk = 0;
613 cz_hwmgr->uvd_dpm.hard_min_clk = 0;
614
615 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
616 level = smum_get_argument(hwmgr->smumgr);
617
618 if (level < table->count)
619 clock = table->entries[level].vclk;
620 else
621 clock = table->entries[table->count - 1].vclk;
622
623 cz_hwmgr->uvd_dpm.soft_max_clk = clock;
624 cz_hwmgr->uvd_dpm.hard_max_clk = clock;
625
626 return 0;
627 }
628
629 static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
630 void *output, void *storage, int result)
631 {
632 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
633 struct phm_vce_clock_voltage_dependency_table *table =
634 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
635 unsigned long clock = 0, level;
636
637 if (NULL == table && table->count <= 0)
638 return -EINVAL;
639
640 cz_hwmgr->vce_dpm.soft_min_clk = 0;
641 cz_hwmgr->vce_dpm.hard_min_clk = 0;
642
643 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
644 level = smum_get_argument(hwmgr->smumgr);
645
646 if (level < table->count)
647 clock = table->entries[level].ecclk;
648 else
649 clock = table->entries[table->count - 1].ecclk;
650
651 cz_hwmgr->vce_dpm.soft_max_clk = clock;
652 cz_hwmgr->vce_dpm.hard_max_clk = clock;
653
654 return 0;
655 }
656
657 static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
658 void *output, void *storage, int result)
659 {
660 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
661 struct phm_acp_clock_voltage_dependency_table *table =
662 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
663 unsigned long clock = 0, level;
664
665 if (NULL == table && table->count <= 0)
666 return -EINVAL;
667
668 cz_hwmgr->acp_dpm.soft_min_clk = 0;
669 cz_hwmgr->acp_dpm.hard_min_clk = 0;
670
671 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
672 level = smum_get_argument(hwmgr->smumgr);
673
674 if (level < table->count)
675 clock = table->entries[level].acpclk;
676 else
677 clock = table->entries[table->count - 1].acpclk;
678
679 cz_hwmgr->acp_dpm.soft_max_clk = clock;
680 cz_hwmgr->acp_dpm.hard_max_clk = clock;
681 return 0;
682 }
683
684 static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
685 void *output, void *storage, int result)
686 {
687 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
688
689 cz_hwmgr->uvd_power_gated = false;
690 cz_hwmgr->vce_power_gated = false;
691 cz_hwmgr->samu_power_gated = false;
692 cz_hwmgr->acp_power_gated = false;
693 cz_hwmgr->pgacpinit = true;
694
695 return 0;
696 }
697
698 static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
699 void *output, void *storage, int result)
700 {
701 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
702
703 cz_hwmgr->low_sclk_interrupt_threshold = 0;
704
705 return 0;
706 }
707 static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
708 void *input, void *output,
709 void *storage, int result)
710 {
711 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
712 struct phm_clock_voltage_dependency_table *table =
713 hwmgr->dyn_state.vddc_dependency_on_sclk;
714
715 unsigned long clock = 0;
716 unsigned long level;
717 unsigned long stable_pstate_sclk;
718 struct PP_Clocks clocks;
719 unsigned long percentage;
720
721 cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
722 level = cz_get_max_sclk_level(hwmgr) - 1;
723
724 if (level < table->count)
725 cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[level].clk;
726 else
727 cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;
728
729 /*PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks);*/
730 clock = clocks.engineClock;
731
732 if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
733 cz_hwmgr->sclk_dpm.hard_min_clk = clock;
734
735 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
736 PPSMC_MSG_SetSclkHardMin,
737 cz_get_sclk_level(hwmgr,
738 cz_hwmgr->sclk_dpm.hard_min_clk,
739 PPSMC_MSG_SetSclkHardMin));
740 }
741
742 clock = cz_hwmgr->sclk_dpm.soft_min_clk;
743
744 /* update minimum clocks for Stable P-State feature */
745 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
746 PHM_PlatformCaps_StablePState)) {
747 percentage = 75;
748 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table */
749 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
750 percentage) / 100;
751
752 if (clock < stable_pstate_sclk)
753 clock = stable_pstate_sclk;
754 } else {
755 if (clock < hwmgr->gfx_arbiter.sclk)
756 clock = hwmgr->gfx_arbiter.sclk;
757 }
758
759 if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
760 cz_hwmgr->sclk_dpm.soft_min_clk = clock;
761 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
762 PPSMC_MSG_SetSclkSoftMin,
763 cz_get_sclk_level(hwmgr,
764 cz_hwmgr->sclk_dpm.soft_min_clk,
765 PPSMC_MSG_SetSclkSoftMin));
766 }
767
768 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
769 PHM_PlatformCaps_StablePState) &&
770 cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
771 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
772 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
773 PPSMC_MSG_SetSclkSoftMax,
774 cz_get_sclk_level(hwmgr,
775 cz_hwmgr->sclk_dpm.soft_max_clk,
776 PPSMC_MSG_SetSclkSoftMax));
777 }
778
779 return 0;
780 }
781
782 static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
783 void *input, void *output,
784 void *storage, int result)
785 {
786 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
787 PHM_PlatformCaps_SclkDeepSleep)) {
788 /* TO DO get from dal PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks); */
789 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
790 PPSMC_MSG_SetMinDeepSleepSclk,
791 CZ_MIN_DEEP_SLEEP_SCLK);
792 }
793
794 return 0;
795 }
796
797 static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
798 void *input, void *output,
799 void *storage, int result)
800 {
801 struct cz_hwmgr *cz_hwmgr =
802 (struct cz_hwmgr *)(hwmgr->backend);
803
804 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
805 PPSMC_MSG_SetWatermarkFrequency,
806 cz_hwmgr->sclk_dpm.soft_max_clk);
807
808 return 0;
809 }
810
811 static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
812 void *input, void *output,
813 void *storage, int result)
814 {
815 return 0;
816 }
817
818
819 static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
820 void *input, void *output,
821 void *storage, int result)
822 {
823 int ret = 0;
824
825 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
826 unsigned long dpm_features = 0;
827
828 if (!cz_hwmgr->is_nb_dpm_enabled) {
829 PP_DBG_LOG("enabling ALL SMU features.\n");
830 dpm_features |= NB_DPM_MASK;
831 ret = smum_send_msg_to_smc_with_parameter(
832 hwmgr->smumgr,
833 PPSMC_MSG_EnableAllSmuFeatures,
834 dpm_features);
835 if (ret == 0)
836 cz_hwmgr->is_nb_dpm_enabled = true;
837 }
838
839 return ret;
840 }
841
842 static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
843 {
844 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
845
846 if (hw_data->is_nb_dpm_enabled) {
847 if (enable) {
848 PP_DBG_LOG("enable Low Memory PState.\n");
849
850 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
851 PPSMC_MSG_EnableLowMemoryPstate,
852 (lock ? 1 : 0));
853 } else {
854 PP_DBG_LOG("disable Low Memory PState.\n");
855
856 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
857 PPSMC_MSG_DisableLowMemoryPstate,
858 (lock ? 1 : 0));
859 }
860 }
861
862 return 0;
863 }
864
865 static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
866 void *input, void *output,
867 void *storage, int result)
868 {
869 bool disable_switch;
870 bool enable_low_mem_state;
871 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
872 const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
873 const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
874
875 if (hw_data->sys_info.nb_dpm_enable) {
876 disable_switch = hw_data->display_cfg.nb_pstate_switch_disable ? true : false;
877 enable_low_mem_state = hw_data->display_cfg.nb_pstate_switch_disable ? false : true;
878
879 if (pnew_state->action == FORCE_HIGH)
880 cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
881 else if(pnew_state->action == CANCEL_FORCE_HIGH)
882 cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
883 else
884 cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
885 }
886 return 0;
887 }
888
889 static struct phm_master_table_item cz_set_power_state_list[] = {
890 {NULL, cz_tf_update_sclk_limit},
891 {NULL, cz_tf_set_deep_sleep_sclk_threshold},
892 {NULL, cz_tf_set_watermark_threshold},
893 {NULL, cz_tf_set_enabled_levels},
894 {NULL, cz_tf_enable_nb_dpm},
895 {NULL, cz_tf_update_low_mem_pstate},
896 {NULL, NULL}
897 };
898
899 static struct phm_master_table_header cz_set_power_state_master = {
900 0,
901 PHM_MasterTableFlag_None,
902 cz_set_power_state_list
903 };
904
905 static struct phm_master_table_item cz_setup_asic_list[] = {
906 {NULL, cz_tf_reset_active_process_mask},
907 {NULL, cz_tf_upload_pptable_to_smu},
908 {NULL, cz_tf_init_sclk_limit},
909 {NULL, cz_tf_init_uvd_limit},
910 {NULL, cz_tf_init_vce_limit},
911 {NULL, cz_tf_init_acp_limit},
912 {NULL, cz_tf_init_power_gate_state},
913 {NULL, cz_tf_init_sclk_threshold},
914 {NULL, NULL}
915 };
916
917 static struct phm_master_table_header cz_setup_asic_master = {
918 0,
919 PHM_MasterTableFlag_None,
920 cz_setup_asic_list
921 };
922
923 static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
924 void *output, void *storage, int result)
925 {
926 PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
927 PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
928 return 0;
929 }
930
931 static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
932 void *storage, int result)
933 {
934 int res = 0xff;
935 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
936 unsigned long dpm_features = 0;
937
938 cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
939 dpm_features |= SCLK_DPM_MASK;
940
941 res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
942 PPSMC_MSG_EnableAllSmuFeatures,
943 dpm_features);
944
945 return res;
946 }
947
948 static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
949 void *output, void *storage, int result)
950 {
951 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
952
953 cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
954 cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
955
956 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
957 PPSMC_MSG_SetSclkSoftMin,
958 cz_get_sclk_level(hwmgr,
959 cz_hwmgr->sclk_dpm.soft_min_clk,
960 PPSMC_MSG_SetSclkSoftMin));
961
962 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
963 PPSMC_MSG_SetSclkSoftMax,
964 cz_get_sclk_level(hwmgr,
965 cz_hwmgr->sclk_dpm.soft_max_clk,
966 PPSMC_MSG_SetSclkSoftMax));
967
968 return 0;
969 }
970
971 int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
972 void *output, void *storage, int result)
973 {
974 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
975
976 cz_hwmgr->acp_boot_level = 0xff;
977 return 0;
978 }
979
980 static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
981 unsigned long check_feature)
982 {
983 int result;
984 unsigned long features;
985
986 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
987 if (result == 0) {
988 features = smum_get_argument(hwmgr->smumgr);
989 if (features & check_feature)
990 return true;
991 }
992
993 return result;
994 }
995
996 static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
997 void *output, void *storage, int result)
998 {
999 if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
1000 return PP_Result_TableImmediateExit;
1001 return 0;
1002 }
1003
1004 static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
1005 void *output, void *storage, int result)
1006 {
1007 /* TO DO */
1008 return 0;
1009 }
1010
1011 static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
1012 void *input, void *output,
1013 void *storage, int result)
1014 {
1015 if (!cz_dpm_check_smu_features(hwmgr,
1016 SMU_EnabledFeatureScoreboard_SclkDpmOn))
1017 return PP_Result_TableImmediateExit;
1018 return 0;
1019 }
1020
1021 static struct phm_master_table_item cz_disable_dpm_list[] = {
1022 { NULL, cz_tf_check_for_dpm_enabled},
1023 {NULL, NULL},
1024 };
1025
1026
1027 static struct phm_master_table_header cz_disable_dpm_master = {
1028 0,
1029 PHM_MasterTableFlag_None,
1030 cz_disable_dpm_list
1031 };
1032
1033 static struct phm_master_table_item cz_enable_dpm_list[] = {
1034 { NULL, cz_tf_check_for_dpm_disabled },
1035 { NULL, cz_tf_program_voting_clients },
1036 { NULL, cz_tf_start_dpm},
1037 { NULL, cz_tf_program_bootup_state},
1038 { NULL, cz_tf_enable_didt },
1039 { NULL, cz_tf_reset_acp_boot_level },
1040 {NULL, NULL},
1041 };
1042
1043 static struct phm_master_table_header cz_enable_dpm_master = {
1044 0,
1045 PHM_MasterTableFlag_None,
1046 cz_enable_dpm_list
1047 };
1048
1049 static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
1050 struct pp_power_state *prequest_ps,
1051 const struct pp_power_state *pcurrent_ps)
1052 {
1053 struct cz_power_state *cz_ps =
1054 cast_PhwCzPowerState(&prequest_ps->hardware);
1055
1056 const struct cz_power_state *cz_current_ps =
1057 cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
1058
1059 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1060 struct PP_Clocks clocks;
1061 bool force_high;
1062 unsigned long num_of_active_displays = 4;
1063
1064 cz_ps->evclk = hwmgr->vce_arbiter.evclk;
1065 cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
1066
1067 cz_ps->need_dfs_bypass = true;
1068
1069 cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
1070 hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
1071
1072 cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
1073
1074 /* to do PECI_GetMinClockSettings(pHwMgr->pPECI, &clocks); */
1075 /* PECI_GetNumberOfActiveDisplays(pHwMgr->pPECI, &numOfActiveDisplays); */
1076 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
1077 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1078 else
1079 clocks.memoryClock = 0;
1080
1081 if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
1082 clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
1083
1084 force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
1085 || (num_of_active_displays >= 3);
1086
1087 cz_ps->action = cz_current_ps->action;
1088
1089 if ((force_high == false) && (cz_ps->action == FORCE_HIGH))
1090 cz_ps->action = CANCEL_FORCE_HIGH;
1091 else if ((force_high == true) && (cz_ps->action != FORCE_HIGH))
1092 cz_ps->action = FORCE_HIGH;
1093 else
1094 cz_ps->action = DO_NOTHING;
1095
1096 return 0;
1097 }
1098
1099 static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
1100 {
1101 int result = 0;
1102
1103 result = cz_initialize_dpm_defaults(hwmgr);
1104 if (result != 0) {
1105 printk(KERN_ERR "[ powerplay ] cz_initialize_dpm_defaults failed\n");
1106 return result;
1107 }
1108
1109 result = cz_get_system_info_data(hwmgr);
1110 if (result != 0) {
1111 printk(KERN_ERR "[ powerplay ] cz_get_system_info_data failed\n");
1112 return result;
1113 }
1114
1115 cz_construct_boot_state(hwmgr);
1116
1117 result = phm_construct_table(hwmgr, &cz_setup_asic_master,
1118 &(hwmgr->setup_asic));
1119 if (result != 0) {
1120 printk(KERN_ERR "[ powerplay ] Fail to construct setup ASIC\n");
1121 return result;
1122 }
1123
1124 result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
1125 &(hwmgr->disable_dynamic_state_management));
1126 if (result != 0) {
1127 printk(KERN_ERR "[ powerplay ] Fail to disable_dynamic_state\n");
1128 return result;
1129 }
1130 result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
1131 &(hwmgr->enable_dynamic_state_management));
1132 if (result != 0) {
1133 printk(KERN_ERR "[ powerplay ] Fail to enable_dynamic_state\n");
1134 return result;
1135 }
1136 result = phm_construct_table(hwmgr, &cz_set_power_state_master,
1137 &(hwmgr->set_power_state));
1138 if (result != 0) {
1139 printk(KERN_ERR "[ powerplay ] Fail to construct set_power_state\n");
1140 return result;
1141 }
1142
1143 result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
1144 if (result != 0) {
1145 printk(KERN_ERR "[ powerplay ] Fail to construct enable_clock_power_gatings\n");
1146 return result;
1147 }
1148 return result;
1149 }
1150
1151 static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
1152 {
1153 if (hwmgr != NULL || hwmgr->backend != NULL) {
1154 kfree(hwmgr->backend);
1155 kfree(hwmgr);
1156 }
1157 return 0;
1158 }
1159
1160 int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
1161 {
1162 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1163
1164 if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1165 cz_hwmgr->sclk_dpm.soft_max_clk)
1166 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1167 PPSMC_MSG_SetSclkSoftMin,
1168 cz_get_sclk_level(hwmgr,
1169 cz_hwmgr->sclk_dpm.soft_max_clk,
1170 PPSMC_MSG_SetSclkSoftMin));
1171 return 0;
1172 }
1173
1174 int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1175 {
1176 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1177 struct phm_clock_voltage_dependency_table *table =
1178 hwmgr->dyn_state.vddc_dependency_on_sclk;
1179 unsigned long clock = 0, level;
1180
1181 if (NULL == table && table->count <= 0)
1182 return -EINVAL;
1183
1184 cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
1185 cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
1186
1187 level = cz_get_max_sclk_level(hwmgr) - 1;
1188
1189 if (level < table->count)
1190 clock = table->entries[level].clk;
1191 else
1192 clock = table->entries[table->count - 1].clk;
1193
1194 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
1195 cz_hwmgr->sclk_dpm.hard_max_clk = clock;
1196
1197 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1198 PPSMC_MSG_SetSclkSoftMin,
1199 cz_get_sclk_level(hwmgr,
1200 cz_hwmgr->sclk_dpm.soft_min_clk,
1201 PPSMC_MSG_SetSclkSoftMin));
1202
1203 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1204 PPSMC_MSG_SetSclkSoftMax,
1205 cz_get_sclk_level(hwmgr,
1206 cz_hwmgr->sclk_dpm.soft_max_clk,
1207 PPSMC_MSG_SetSclkSoftMax));
1208
1209 return 0;
1210 }
1211
1212 int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1213 {
1214 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1215
1216 if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1217 cz_hwmgr->sclk_dpm.soft_max_clk) {
1218 cz_hwmgr->sclk_dpm.soft_max_clk =
1219 cz_hwmgr->sclk_dpm.soft_min_clk;
1220
1221 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1222 PPSMC_MSG_SetSclkSoftMax,
1223 cz_get_sclk_level(hwmgr,
1224 cz_hwmgr->sclk_dpm.soft_max_clk,
1225 PPSMC_MSG_SetSclkSoftMax));
1226 }
1227
1228 return 0;
1229 }
1230
1231 static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1232 enum amd_dpm_forced_level level)
1233 {
1234 int ret = 0;
1235
1236 switch (level) {
1237 case AMD_DPM_FORCED_LEVEL_HIGH:
1238 ret = cz_phm_force_dpm_highest(hwmgr);
1239 if (ret)
1240 return ret;
1241 break;
1242 case AMD_DPM_FORCED_LEVEL_LOW:
1243 ret = cz_phm_force_dpm_lowest(hwmgr);
1244 if (ret)
1245 return ret;
1246 break;
1247 case AMD_DPM_FORCED_LEVEL_AUTO:
1248 ret = cz_phm_unforce_dpm_levels(hwmgr);
1249 if (ret)
1250 return ret;
1251 break;
1252 default:
1253 break;
1254 }
1255
1256 hwmgr->dpm_level = level;
1257
1258 return ret;
1259 }
1260
1261 int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
1262 {
1263 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1264 PHM_PlatformCaps_UVDPowerGating))
1265 return smum_send_msg_to_smc(hwmgr->smumgr,
1266 PPSMC_MSG_UVDPowerOFF);
1267 return 0;
1268 }
1269
1270 int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
1271 {
1272 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1273 PHM_PlatformCaps_UVDPowerGating)) {
1274 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1275 PHM_PlatformCaps_UVDDynamicPowerGating)) {
1276 return smum_send_msg_to_smc_with_parameter(
1277 hwmgr->smumgr,
1278 PPSMC_MSG_UVDPowerON, 1);
1279 } else {
1280 return smum_send_msg_to_smc_with_parameter(
1281 hwmgr->smumgr,
1282 PPSMC_MSG_UVDPowerON, 0);
1283 }
1284 }
1285
1286 return 0;
1287 }
1288
1289 int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
1290 {
1291 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1292 struct phm_uvd_clock_voltage_dependency_table *ptable =
1293 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1294
1295 if (!bgate) {
1296 /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
1297 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1298 PHM_PlatformCaps_StablePState)) {
1299 cz_hwmgr->uvd_dpm.hard_min_clk =
1300 ptable->entries[ptable->count - 1].vclk;
1301
1302 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1303 PPSMC_MSG_SetUvdHardMin,
1304 cz_get_uvd_level(hwmgr,
1305 cz_hwmgr->uvd_dpm.hard_min_clk,
1306 PPSMC_MSG_SetUvdHardMin));
1307
1308 cz_enable_disable_uvd_dpm(hwmgr, true);
1309 } else
1310 cz_enable_disable_uvd_dpm(hwmgr, true);
1311 } else
1312 cz_enable_disable_uvd_dpm(hwmgr, false);
1313
1314 return 0;
1315 }
1316
1317 int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1318 {
1319 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1320 struct phm_vce_clock_voltage_dependency_table *ptable =
1321 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1322
1323 /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1324 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1325 PHM_PlatformCaps_StablePState)) {
1326 cz_hwmgr->vce_dpm.hard_min_clk =
1327 ptable->entries[ptable->count - 1].ecclk;
1328
1329 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1330 PPSMC_MSG_SetEclkHardMin,
1331 cz_get_eclk_level(hwmgr,
1332 cz_hwmgr->vce_dpm.hard_min_clk,
1333 PPSMC_MSG_SetEclkHardMin));
1334 } else {
1335 /*EPR# 419220 -HW limitation to to */
1336 cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
1337 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1338 PPSMC_MSG_SetEclkHardMin,
1339 cz_get_eclk_level(hwmgr,
1340 cz_hwmgr->vce_dpm.hard_min_clk,
1341 PPSMC_MSG_SetEclkHardMin));
1342
1343 }
1344 return 0;
1345 }
1346
1347 int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
1348 {
1349 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1350 PHM_PlatformCaps_VCEPowerGating))
1351 return smum_send_msg_to_smc(hwmgr->smumgr,
1352 PPSMC_MSG_VCEPowerOFF);
1353 return 0;
1354 }
1355
1356 int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
1357 {
1358 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1359 PHM_PlatformCaps_VCEPowerGating))
1360 return smum_send_msg_to_smc(hwmgr->smumgr,
1361 PPSMC_MSG_VCEPowerON);
1362 return 0;
1363 }
1364
1365 static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1366 {
1367 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1368
1369 return cz_hwmgr->sys_info.bootup_uma_clock;
1370 }
1371
1372 static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1373 {
1374 struct pp_power_state *ps;
1375 struct cz_power_state *cz_ps;
1376
1377 if (hwmgr == NULL)
1378 return -EINVAL;
1379
1380 ps = hwmgr->request_ps;
1381
1382 if (ps == NULL)
1383 return -EINVAL;
1384
1385 cz_ps = cast_PhwCzPowerState(&ps->hardware);
1386
1387 if (low)
1388 return cz_ps->levels[0].engineClock;
1389 else
1390 return cz_ps->levels[cz_ps->level-1].engineClock;
1391 }
1392
1393 static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
1394 struct pp_hw_power_state *hw_ps)
1395 {
1396 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1397 struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1398
1399 cz_ps->level = 1;
1400 cz_ps->nbps_flags = 0;
1401 cz_ps->bapm_flags = 0;
1402 cz_ps->levels[0] = cz_hwmgr->boot_power_level;
1403
1404 return 0;
1405 }
1406
1407 static int cz_dpm_get_pp_table_entry_callback(
1408 struct pp_hwmgr *hwmgr,
1409 struct pp_hw_power_state *hw_ps,
1410 unsigned int index,
1411 const void *clock_info)
1412 {
1413 struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1414
1415 const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
1416
1417 struct phm_clock_voltage_dependency_table *table =
1418 hwmgr->dyn_state.vddc_dependency_on_sclk;
1419 uint8_t clock_info_index = cz_clock_info->index;
1420
1421 if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
1422 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
1423
1424 cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1425 cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1426
1427 cz_ps->level = index + 1;
1428
1429 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
1430 cz_ps->levels[index].dsDividerIndex = 5;
1431 cz_ps->levels[index].ssDividerIndex = 5;
1432 }
1433
1434 return 0;
1435 }
1436
1437 static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
1438 {
1439 int result;
1440 unsigned long ret = 0;
1441
1442 result = pp_tables_get_num_of_entries(hwmgr, &ret);
1443
1444 return result ? 0 : ret;
1445 }
1446
1447 static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
1448 unsigned long entry, struct pp_power_state *ps)
1449 {
1450 int result;
1451 struct cz_power_state *cz_ps;
1452
1453 ps->hardware.magic = PhwCz_Magic;
1454
1455 cz_ps = cast_PhwCzPowerState(&(ps->hardware));
1456
1457 result = pp_tables_get_entry(hwmgr, entry, ps,
1458 cz_dpm_get_pp_table_entry_callback);
1459
1460 cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1461 cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1462
1463 return result;
1464 }
1465
1466 int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
1467 {
1468 return sizeof(struct cz_power_state);
1469 }
1470
1471 static void
1472 cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
1473 {
1474 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1475
1476 struct phm_clock_voltage_dependency_table *table =
1477 hwmgr->dyn_state.vddc_dependency_on_sclk;
1478
1479 struct phm_vce_clock_voltage_dependency_table *vce_table =
1480 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1481
1482 struct phm_uvd_clock_voltage_dependency_table *uvd_table =
1483 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1484
1485 uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
1486 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
1487 uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1488 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
1489 uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1490 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
1491
1492 uint32_t sclk, vclk, dclk, ecclk, tmp;
1493 uint16_t vddnb, vddgfx;
1494
1495 if (sclk_index >= NUM_SCLK_LEVELS) {
1496 seq_printf(m, "\n invalid sclk dpm profile %d\n", sclk_index);
1497 } else {
1498 sclk = table->entries[sclk_index].clk;
1499 seq_printf(m, "\n index: %u sclk: %u MHz\n", sclk_index, sclk/100);
1500 }
1501
1502 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
1503 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
1504 vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
1505 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
1506 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
1507 vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
1508 seq_printf(m, "\n vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
1509
1510 seq_printf(m, "\n uvd %sabled\n", cz_hwmgr->uvd_power_gated ? "dis" : "en");
1511 if (!cz_hwmgr->uvd_power_gated) {
1512 if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1513 seq_printf(m, "\n invalid uvd dpm level %d\n", uvd_index);
1514 } else {
1515 vclk = uvd_table->entries[uvd_index].vclk;
1516 dclk = uvd_table->entries[uvd_index].dclk;
1517 seq_printf(m, "\n index: %u uvd vclk: %u MHz dclk: %u MHz\n", uvd_index, vclk/100, dclk/100);
1518 }
1519 }
1520
1521 seq_printf(m, "\n vce %sabled\n", cz_hwmgr->vce_power_gated ? "dis" : "en");
1522 if (!cz_hwmgr->vce_power_gated) {
1523 if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1524 seq_printf(m, "\n invalid vce dpm level %d\n", vce_index);
1525 } else {
1526 ecclk = vce_table->entries[vce_index].ecclk;
1527 seq_printf(m, "\n index: %u vce ecclk: %u MHz\n", vce_index, ecclk/100);
1528 }
1529 }
1530 }
1531
1532 static void cz_hw_print_display_cfg(
1533 const struct amd_pp_display_configuration *display_cfg)
1534 {
1535 PP_DBG_LOG("New Display Configuration:\n");
1536
1537 PP_DBG_LOG(" cpu_cc6_disable: %d\n",
1538 display_cfg->cpu_cc6_disable);
1539 PP_DBG_LOG(" cpu_pstate_disable: %d\n",
1540 display_cfg->cpu_pstate_disable);
1541 PP_DBG_LOG(" nb_pstate_switch_disable: %d\n",
1542 display_cfg->nb_pstate_switch_disable);
1543 PP_DBG_LOG(" cpu_pstate_separation_time: %d\n\n",
1544 display_cfg->cpu_pstate_separation_time);
1545 }
1546
1547 static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
1548 {
1549 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1550 uint32_t data = 0;
1551
1552 if (hw_data->cc6_setting_changed == true) {
1553
1554 cz_hw_print_display_cfg(&hw_data->display_cfg);
1555
1556 data |= (hw_data->display_cfg.cpu_pstate_separation_time
1557 & PWRMGT_SEPARATION_TIME_MASK)
1558 << PWRMGT_SEPARATION_TIME_SHIFT;
1559
1560 data|= (hw_data->display_cfg.cpu_cc6_disable ? 0x1 : 0x0)
1561 << PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
1562
1563 data|= (hw_data->display_cfg.cpu_pstate_disable ? 0x1 : 0x0)
1564 << PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
1565
1566 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
1567 data);
1568
1569 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1570 PPSMC_MSG_SetDisplaySizePowerParams,
1571 data);
1572
1573 hw_data->cc6_setting_changed = false;
1574 }
1575
1576 return 0;
1577 }
1578
1579 static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
1580 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
1581 {
1582 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1583
1584 if (separation_time != hw_data->display_cfg.cpu_pstate_separation_time
1585 || cc6_disable != hw_data->display_cfg.cpu_cc6_disable
1586 || pstate_disable != hw_data->display_cfg.cpu_pstate_disable
1587 || pstate_switch_disable != hw_data->display_cfg.nb_pstate_switch_disable) {
1588
1589 hw_data->display_cfg.cpu_pstate_separation_time = separation_time;
1590 hw_data->display_cfg.cpu_cc6_disable = cc6_disable;
1591 hw_data->display_cfg.cpu_pstate_disable = pstate_disable;
1592 hw_data->display_cfg.nb_pstate_switch_disable = pstate_switch_disable;
1593 hw_data->cc6_setting_changed = true;
1594
1595 }
1596 return 0;
1597 }
1598
1599 static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
1600 struct pp_dal_clock_info*info)
1601 {
1602 uint32_t i;
1603 const struct phm_clock_voltage_dependency_table * table =
1604 hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
1605 const struct phm_clock_and_voltage_limits* limits =
1606 &hwmgr->dyn_state.max_clock_voltage_on_ac;
1607
1608 info->engine_max_clock = limits->sclk;
1609 info->memory_max_clock = limits->mclk;
1610
1611 for (i = table->count - 1; i > 0; i--) {
1612
1613 if (limits->vddc >= table->entries[i].v) {
1614 info->level = table->entries[i].clk;
1615 return 0;
1616 }
1617 }
1618 return -EINVAL;
1619 }
1620
1621 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
1622 .backend_init = cz_hwmgr_backend_init,
1623 .backend_fini = cz_hwmgr_backend_fini,
1624 .asic_setup = NULL,
1625 .apply_state_adjust_rules = cz_apply_state_adjust_rules,
1626 .force_dpm_level = cz_dpm_force_dpm_level,
1627 .get_power_state_size = cz_get_power_state_size,
1628 .powerdown_uvd = cz_dpm_powerdown_uvd,
1629 .powergate_uvd = cz_dpm_powergate_uvd,
1630 .powergate_vce = cz_dpm_powergate_vce,
1631 .get_mclk = cz_dpm_get_mclk,
1632 .get_sclk = cz_dpm_get_sclk,
1633 .patch_boot_state = cz_dpm_patch_boot_state,
1634 .get_pp_table_entry = cz_dpm_get_pp_table_entry,
1635 .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
1636 .print_current_perforce_level = cz_print_current_perforce_level,
1637 .set_cpu_power_state = cz_set_cpu_power_state,
1638 .store_cc6_data = cz_store_cc6_data,
1639 .get_dal_power_level= cz_get_dal_power_level,
1640 };
1641
1642 int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
1643 {
1644 struct cz_hwmgr *cz_hwmgr;
1645 int ret = 0;
1646
1647 cz_hwmgr = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
1648 if (cz_hwmgr == NULL)
1649 return -ENOMEM;
1650
1651 hwmgr->backend = cz_hwmgr;
1652 hwmgr->hwmgr_func = &cz_hwmgr_funcs;
1653 hwmgr->pptable_func = &pptable_funcs;
1654 return ret;
1655 }
Linux kernel - Deliverables
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