2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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24 #ifndef FIJI_DYN_DEFAULTS_H
25 #define FIJI_DYN_DEFAULTS_H
28 * Volcanic Islands Dynamic default parameters.
31 enum FIJIdpm_TrendDetection
33 FIJIAdpm_TrendDetection_AUTO
,
34 FIJIAdpm_TrendDetection_UP
,
35 FIJIAdpm_TrendDetection_DOWN
37 typedef enum FIJIdpm_TrendDetection FIJIdpm_TrendDetection
;
39 /* We need to fill in the default values!!!!!!!!!!!!!!!!!!!!!!! */
41 /* Bit vector representing same fields as hardware register. */
42 #define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 /* CP_Gfx_busy ????
50 #define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1 0x000400 /* FE_Gfx_busy - Intended for primary usage. Rest are for flexibility. ????
55 #define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2 0xC00080 /* SH_Gfx_busy - Intended for primary usage. Rest are for flexibility.
60 #define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3 0xC00200 /* RB_Gfx_busy - Intended for primary usage. Rest are for flexibility.
65 #define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4 0xC01680 /* UVD_busy
70 #define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5 0xC00033 /* GFX, HDP */
71 #define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6 0xC00033 /* GFX, HDP */
72 #define PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7 0x3FFFC000 /* GFX, HDP */
75 /* thermal protection counter (units). */
76 #define PPFIJI_THERMALPROTECTCOUNTER_DFLT 0x200 /* ~19us */
78 /* static screen threshold unit */
79 #define PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT 0
81 /* static screen threshold */
82 #define PPFIJI_STATICSCREENTHRESHOLD_DFLT 0x00C8
84 /* gfx idle clock stop threshold */
85 #define PPFIJI_GFXIDLECLOCKSTOPTHRESHOLD_DFLT 0x200 /* ~19us with static screen threshold unit of 0 */
87 /* Fixed reference divider to use when building baby stepping tables. */
88 #define PPFIJI_REFERENCEDIVIDER_DFLT 4
90 /* ULV voltage change delay time
91 * Used to be delay_vreg in N.I. split for S.I.
92 * Using N.I. delay_vreg value as default
93 * ReferenceClock = 2700
94 * VoltageResponseTime = 1000
95 * VDDCDelayTime = (VoltageResponseTime * ReferenceClock) / 1600 = 1687
97 #define PPFIJI_ULVVOLTAGECHANGEDELAY_DFLT 1687
99 #define PPFIJI_CGULVPARAMETER_DFLT 0x00040035
100 #define PPFIJI_CGULVCONTROL_DFLT 0x00007450
101 #define PPFIJI_TARGETACTIVITY_DFLT 30 /* 30%*/
102 #define PPFIJI_MCLK_TARGETACTIVITY_DFLT 10 /* 10% */