2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/slab.h>
26 #include "linux/delay.h"
29 #include "fiji_smumgr.h"
31 #include "hardwaremanager.h"
32 #include "ppatomctrl.h"
34 #include "cgs_common.h"
35 #include "fiji_dyn_defaults.h"
36 #include "fiji_powertune.h"
38 #include "smu/smu_7_1_3_d.h"
39 #include "smu/smu_7_1_3_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
44 #include "dce/dce_10_0_d.h"
45 #include "dce/dce_10_0_sh_mask.h"
46 #include "pppcielanes.h"
47 #include "fiji_hwmgr.h"
48 #include "tonga_processpptables.h"
49 #include "tonga_pptable.h"
52 #include "amd_pcie_helpers.h"
54 #include "fiji_clockpowergating.h"
56 #define VOLTAGE_SCALE 4
57 #define SMC_RAM_END 0x40000
58 #define VDDC_VDDCI_DELTA 300
60 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
61 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
62 #define MC_SEQ_MISC0_GDDR5_VALUE 5
64 #define MC_CG_ARB_FREQ_F0 0x0a /* boot-up default */
65 #define MC_CG_ARB_FREQ_F1 0x0b
66 #define MC_CG_ARB_FREQ_F2 0x0c
67 #define MC_CG_ARB_FREQ_F3 0x0d
70 #define SMC_CG_IND_START 0xc0030000
71 #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND */
73 #define VOLTAGE_SCALE 4
74 #define VOLTAGE_VID_OFFSET_SCALE1 625
75 #define VOLTAGE_VID_OFFSET_SCALE2 100
77 #define VDDC_VDDCI_DELTA 300
79 #define ixSWRST_COMMAND_1 0x1400103
80 #define MC_SEQ_CNTL__CAC_EN_MASK 0x40000000
82 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
84 DPM_EVENT_SRC_ANALOG
= 0, /* Internal analog trip point */
85 DPM_EVENT_SRC_EXTERNAL
= 1, /* External (GPIO 17) signal */
86 DPM_EVENT_SRC_DIGITAL
= 2, /* Internal digital trip point (DIG_THERM_DPM) */
87 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3, /* Internal analog or external */
88 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL
= 4 /* Internal digital or external */
92 DISPLAY_GAP_VBLANK_OR_WM
= 0, /* Wait for vblank or MCHG watermark. */
93 DISPLAY_GAP_VBLANK
= 1, /* Wait for vblank. */
94 DISPLAY_GAP_WATERMARK
= 2, /* Wait for MCHG watermark. */
95 DISPLAY_GAP_IGNORE
= 3 /* Do not wait. */
98 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
99 * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
101 uint16_t fiji_clock_stretcher_lookup_table
[2][4] = { {600, 1050, 3, 0},
104 /* [FF, SS] type, [] 4 voltage ranges, and
105 * [Floor Freq, Boundary Freq, VID min , VID max]
107 uint32_t fiji_clock_stretcher_ddt_table
[2][4][4] =
108 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
109 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
111 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
112 * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
114 uint8_t fiji_clock_stretch_amount_conversion
[2][6] = { {0, 1, 3, 2, 4, 5},
115 {0, 2, 4, 5, 6, 5} };
117 const unsigned long PhwFiji_Magic
= (unsigned long)(PHM_VIslands_Magic
);
119 struct fiji_power_state
*cast_phw_fiji_power_state(
120 struct pp_hw_power_state
*hw_ps
)
122 PP_ASSERT_WITH_CODE((PhwFiji_Magic
== hw_ps
->magic
),
123 "Invalid Powerstate Type!",
126 return (struct fiji_power_state
*)hw_ps
;
129 const struct fiji_power_state
*cast_const_phw_fiji_power_state(
130 const struct pp_hw_power_state
*hw_ps
)
132 PP_ASSERT_WITH_CODE((PhwFiji_Magic
== hw_ps
->magic
),
133 "Invalid Powerstate Type!",
136 return (const struct fiji_power_state
*)hw_ps
;
139 static bool fiji_is_dpm_running(struct pp_hwmgr
*hwmgr
)
141 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr
->device
,
142 CGS_IND_REG__SMC
, FEATURE_STATUS
, VOLTAGE_CONTROLLER_ON
))
146 static void fiji_init_dpm_defaults(struct pp_hwmgr
*hwmgr
)
148 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
149 struct fiji_ulv_parm
*ulv
= &data
->ulv
;
151 ulv
->cg_ulv_parameter
= PPFIJI_CGULVPARAMETER_DFLT
;
152 data
->voting_rights_clients0
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0
;
153 data
->voting_rights_clients1
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1
;
154 data
->voting_rights_clients2
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2
;
155 data
->voting_rights_clients3
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3
;
156 data
->voting_rights_clients4
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4
;
157 data
->voting_rights_clients5
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5
;
158 data
->voting_rights_clients6
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6
;
159 data
->voting_rights_clients7
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7
;
161 data
->static_screen_threshold_unit
=
162 PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT
;
163 data
->static_screen_threshold
=
164 PPFIJI_STATICSCREENTHRESHOLD_DFLT
;
166 /* Unset ABM cap as it moved to DAL.
167 * Add PHM_PlatformCaps_NonABMSupportInPPLib
168 * for re-direct ABM related request to DAL
170 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
171 PHM_PlatformCaps_ABM
);
172 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
173 PHM_PlatformCaps_NonABMSupportInPPLib
);
175 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
176 PHM_PlatformCaps_DynamicACTiming
);
178 fiji_initialize_power_tune_defaults(hwmgr
);
180 data
->mclk_stutter_mode_threshold
= 60000;
181 data
->pcie_gen_performance
.max
= PP_PCIEGen1
;
182 data
->pcie_gen_performance
.min
= PP_PCIEGen3
;
183 data
->pcie_gen_power_saving
.max
= PP_PCIEGen1
;
184 data
->pcie_gen_power_saving
.min
= PP_PCIEGen3
;
185 data
->pcie_lane_performance
.max
= 0;
186 data
->pcie_lane_performance
.min
= 16;
187 data
->pcie_lane_power_saving
.max
= 0;
188 data
->pcie_lane_power_saving
.min
= 16;
190 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
191 PHM_PlatformCaps_DynamicUVDState
);
194 static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr
*hwmgr
,
195 phm_ppt_v1_voltage_lookup_table
*lookup_table
,
196 uint16_t virtual_voltage_id
, int32_t *sclk
)
200 struct phm_ppt_v1_information
*table_info
=
201 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
203 PP_ASSERT_WITH_CODE(lookup_table
->count
!= 0, "Lookup table is empty", return -EINVAL
);
205 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
206 for (entryId
= 0; entryId
< table_info
->vdd_dep_on_sclk
->count
; entryId
++) {
207 voltageId
= table_info
->vdd_dep_on_sclk
->entries
[entryId
].vddInd
;
208 if (lookup_table
->entries
[voltageId
].us_vdd
== virtual_voltage_id
)
212 PP_ASSERT_WITH_CODE(entryId
< table_info
->vdd_dep_on_sclk
->count
,
213 "Can't find requested voltage id in vdd_dep_on_sclk table!",
217 *sclk
= table_info
->vdd_dep_on_sclk
->entries
[entryId
].clk
;
223 * Get Leakage VDDC based on leakage ID.
225 * @param hwmgr the address of the powerplay hardware manager.
228 static int fiji_get_evv_voltages(struct pp_hwmgr
*hwmgr
)
230 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
233 uint16_t evv_default
= 1150;
236 struct phm_ppt_v1_information
*table_info
=
237 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
238 struct phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
=
239 table_info
->vdd_dep_on_sclk
;
242 for (i
= 0; i
< FIJI_MAX_LEAKAGE_COUNT
; i
++) {
243 vv_id
= ATOM_VIRTUAL_VOLTAGE_ID0
+ i
;
244 if (!fiji_get_sclk_for_voltage_evv(hwmgr
,
245 table_info
->vddc_lookup_table
, vv_id
, &sclk
)) {
246 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
247 PHM_PlatformCaps_ClockStretcher
)) {
248 for (j
= 1; j
< sclk_table
->count
; j
++) {
249 if (sclk_table
->entries
[j
].clk
== sclk
&&
250 sclk_table
->entries
[j
].cks_enable
== 0) {
257 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
258 PHM_PlatformCaps_EnableDriverEVV
))
259 result
= atomctrl_calculate_voltage_evv_on_sclk(hwmgr
,
260 VOLTAGE_TYPE_VDDC
, sclk
, vv_id
, &vddc
, i
, true);
265 result
= atomctrl_get_voltage_evv_on_sclk(hwmgr
,
266 VOLTAGE_TYPE_VDDC
, sclk
,vv_id
, &vddc
);
268 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
269 PP_ASSERT_WITH_CODE((vddc
< 2000),
270 "Invalid VDDC value, greater than 2v!", result
= -EINVAL
;);
273 /* 1.15V is the default safe value for Fiji */
276 /* the voltage should not be zero nor equal to leakage ID */
277 if (vddc
!= 0 && vddc
!= vv_id
) {
278 data
->vddc_leakage
.actual_voltage
279 [data
->vddc_leakage
.count
] = vddc
;
280 data
->vddc_leakage
.leakage_id
281 [data
->vddc_leakage
.count
] = vv_id
;
282 data
->vddc_leakage
.count
++;
290 * Change virtual leakage voltage to actual value.
292 * @param hwmgr the address of the powerplay hardware manager.
293 * @param pointer to changing voltage
294 * @param pointer to leakage table
296 static void fiji_patch_with_vdd_leakage(struct pp_hwmgr
*hwmgr
,
297 uint16_t *voltage
, struct fiji_leakage_voltage
*leakage_table
)
301 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
302 for (index
= 0; index
< leakage_table
->count
; index
++) {
303 /* if this voltage matches a leakage voltage ID */
304 /* patch with actual leakage voltage */
305 if (leakage_table
->leakage_id
[index
] == *voltage
) {
306 *voltage
= leakage_table
->actual_voltage
[index
];
311 if (*voltage
> ATOM_VIRTUAL_VOLTAGE_ID0
)
312 printk(KERN_ERR
"Voltage value looks like a Leakage ID but it's not patched \n");
316 * Patch voltage lookup table by EVV leakages.
318 * @param hwmgr the address of the powerplay hardware manager.
319 * @param pointer to voltage lookup table
320 * @param pointer to leakage table
323 static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr
*hwmgr
,
324 phm_ppt_v1_voltage_lookup_table
*lookup_table
,
325 struct fiji_leakage_voltage
*leakage_table
)
329 for (i
= 0; i
< lookup_table
->count
; i
++)
330 fiji_patch_with_vdd_leakage(hwmgr
,
331 &lookup_table
->entries
[i
].us_vdd
, leakage_table
);
336 static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
337 struct pp_hwmgr
*hwmgr
, struct fiji_leakage_voltage
*leakage_table
,
340 struct phm_ppt_v1_information
*table_info
=
341 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
342 fiji_patch_with_vdd_leakage(hwmgr
, (uint16_t *)vddc
, leakage_table
);
343 hwmgr
->dyn_state
.max_clock_voltage_on_dc
.vddc
=
344 table_info
->max_clock_voltage_on_dc
.vddc
;
348 static int fiji_patch_voltage_dependency_tables_with_lookup_table(
349 struct pp_hwmgr
*hwmgr
)
353 struct phm_ppt_v1_information
*table_info
=
354 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
356 struct phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
=
357 table_info
->vdd_dep_on_sclk
;
358 struct phm_ppt_v1_clock_voltage_dependency_table
*mclk_table
=
359 table_info
->vdd_dep_on_mclk
;
360 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
361 table_info
->mm_dep_table
;
363 for (entryId
= 0; entryId
< sclk_table
->count
; ++entryId
) {
364 voltageId
= sclk_table
->entries
[entryId
].vddInd
;
365 sclk_table
->entries
[entryId
].vddc
=
366 table_info
->vddc_lookup_table
->entries
[voltageId
].us_vdd
;
369 for (entryId
= 0; entryId
< mclk_table
->count
; ++entryId
) {
370 voltageId
= mclk_table
->entries
[entryId
].vddInd
;
371 mclk_table
->entries
[entryId
].vddc
=
372 table_info
->vddc_lookup_table
->entries
[voltageId
].us_vdd
;
375 for (entryId
= 0; entryId
< mm_table
->count
; ++entryId
) {
376 voltageId
= mm_table
->entries
[entryId
].vddcInd
;
377 mm_table
->entries
[entryId
].vddc
=
378 table_info
->vddc_lookup_table
->entries
[voltageId
].us_vdd
;
385 static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr
*hwmgr
)
387 /* Need to determine if we need calculated voltage. */
391 static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr
*hwmgr
)
393 /* Need to determine if we need calculated voltage from mm table. */
397 static int fiji_sort_lookup_table(struct pp_hwmgr
*hwmgr
,
398 struct phm_ppt_v1_voltage_lookup_table
*lookup_table
)
400 uint32_t table_size
, i
, j
;
401 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record
;
402 table_size
= lookup_table
->count
;
404 PP_ASSERT_WITH_CODE(0 != lookup_table
->count
,
405 "Lookup table is empty", return -EINVAL
);
407 /* Sorting voltages */
408 for (i
= 0; i
< table_size
- 1; i
++) {
409 for (j
= i
+ 1; j
> 0; j
--) {
410 if (lookup_table
->entries
[j
].us_vdd
<
411 lookup_table
->entries
[j
- 1].us_vdd
) {
412 tmp_voltage_lookup_record
= lookup_table
->entries
[j
- 1];
413 lookup_table
->entries
[j
- 1] = lookup_table
->entries
[j
];
414 lookup_table
->entries
[j
] = tmp_voltage_lookup_record
;
422 static int fiji_complete_dependency_tables(struct pp_hwmgr
*hwmgr
)
426 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
427 struct phm_ppt_v1_information
*table_info
=
428 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
430 tmp_result
= fiji_patch_lookup_table_with_leakage(hwmgr
,
431 table_info
->vddc_lookup_table
, &(data
->vddc_leakage
));
435 tmp_result
= fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr
,
436 &(data
->vddc_leakage
), &table_info
->max_clock_voltage_on_dc
.vddc
);
440 tmp_result
= fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr
);
444 tmp_result
= fiji_calc_voltage_dependency_tables(hwmgr
);
448 tmp_result
= fiji_calc_mm_voltage_dependency_table(hwmgr
);
452 tmp_result
= fiji_sort_lookup_table(hwmgr
, table_info
->vddc_lookup_table
);
459 static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr
*hwmgr
)
461 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
462 struct phm_ppt_v1_information
*table_info
=
463 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
465 struct phm_ppt_v1_clock_voltage_dependency_table
*allowed_sclk_vdd_table
=
466 table_info
->vdd_dep_on_sclk
;
467 struct phm_ppt_v1_clock_voltage_dependency_table
*allowed_mclk_vdd_table
=
468 table_info
->vdd_dep_on_mclk
;
470 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table
!= NULL
,
471 "VDD dependency on SCLK table is missing. \
472 This table is mandatory", return -EINVAL
);
473 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table
->count
>= 1,
474 "VDD dependency on SCLK table has to have is missing. \
475 This table is mandatory", return -EINVAL
);
477 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table
!= NULL
,
478 "VDD dependency on MCLK table is missing. \
479 This table is mandatory", return -EINVAL
);
480 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table
->count
>= 1,
481 "VDD dependency on MCLK table has to have is missing. \
482 This table is mandatory", return -EINVAL
);
484 data
->min_vddc_in_pptable
= (uint16_t)allowed_sclk_vdd_table
->entries
[0].vddc
;
485 data
->max_vddc_in_pptable
= (uint16_t)allowed_sclk_vdd_table
->
486 entries
[allowed_sclk_vdd_table
->count
- 1].vddc
;
488 table_info
->max_clock_voltage_on_ac
.sclk
=
489 allowed_sclk_vdd_table
->entries
[allowed_sclk_vdd_table
->count
- 1].clk
;
490 table_info
->max_clock_voltage_on_ac
.mclk
=
491 allowed_mclk_vdd_table
->entries
[allowed_mclk_vdd_table
->count
- 1].clk
;
492 table_info
->max_clock_voltage_on_ac
.vddc
=
493 allowed_sclk_vdd_table
->entries
[allowed_sclk_vdd_table
->count
- 1].vddc
;
494 table_info
->max_clock_voltage_on_ac
.vddci
=
495 allowed_mclk_vdd_table
->entries
[allowed_mclk_vdd_table
->count
- 1].vddci
;
497 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.sclk
=
498 table_info
->max_clock_voltage_on_ac
.sclk
;
499 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.mclk
=
500 table_info
->max_clock_voltage_on_ac
.mclk
;
501 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddc
=
502 table_info
->max_clock_voltage_on_ac
.vddc
;
503 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddci
=
504 table_info
->max_clock_voltage_on_ac
.vddci
;
509 static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr
*hwmgr
)
511 uint32_t speedCntl
= 0;
513 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
514 speedCntl
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__PCIE
,
515 ixPCIE_LC_SPEED_CNTL
);
516 return((uint16_t)PHM_GET_FIELD(speedCntl
,
517 PCIE_LC_SPEED_CNTL
, LC_CURRENT_DATA_RATE
));
520 static int fiji_get_current_pcie_lane_number(struct pp_hwmgr
*hwmgr
)
524 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
525 link_width
= PHM_READ_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__PCIE
,
526 PCIE_LC_LINK_WIDTH_CNTL
, LC_LINK_WIDTH_RD
);
528 PP_ASSERT_WITH_CODE((7 >= link_width
),
529 "Invalid PCIe lane width!", return 0);
531 return decode_pcie_lane_width(link_width
);
534 /** Patch the Boot State to match VBIOS boot clocks and voltage.
536 * @param hwmgr Pointer to the hardware manager.
537 * @param pPowerState The address of the PowerState instance being created.
540 static int fiji_patch_boot_state(struct pp_hwmgr
*hwmgr
,
541 struct pp_hw_power_state
*hw_ps
)
543 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
544 struct fiji_power_state
*ps
= (struct fiji_power_state
*)hw_ps
;
545 ATOM_FIRMWARE_INFO_V2_2
*fw_info
;
548 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
550 /* First retrieve the Boot clocks and VDDC from the firmware info table.
551 * We assume here that fw_info is unchanged if this call fails.
553 fw_info
= (ATOM_FIRMWARE_INFO_V2_2
*)cgs_atom_get_data_table(
554 hwmgr
->device
, index
,
555 &size
, &frev
, &crev
);
557 /* During a test, there is no firmware info table. */
560 /* Patch the state. */
561 data
->vbios_boot_state
.sclk_bootup_value
=
562 le32_to_cpu(fw_info
->ulDefaultEngineClock
);
563 data
->vbios_boot_state
.mclk_bootup_value
=
564 le32_to_cpu(fw_info
->ulDefaultMemoryClock
);
565 data
->vbios_boot_state
.mvdd_bootup_value
=
566 le16_to_cpu(fw_info
->usBootUpMVDDCVoltage
);
567 data
->vbios_boot_state
.vddc_bootup_value
=
568 le16_to_cpu(fw_info
->usBootUpVDDCVoltage
);
569 data
->vbios_boot_state
.vddci_bootup_value
=
570 le16_to_cpu(fw_info
->usBootUpVDDCIVoltage
);
571 data
->vbios_boot_state
.pcie_gen_bootup_value
=
572 fiji_get_current_pcie_speed(hwmgr
);
573 data
->vbios_boot_state
.pcie_lane_bootup_value
=
574 (uint16_t)fiji_get_current_pcie_lane_number(hwmgr
);
576 /* set boot power state */
577 ps
->performance_levels
[0].memory_clock
= data
->vbios_boot_state
.mclk_bootup_value
;
578 ps
->performance_levels
[0].engine_clock
= data
->vbios_boot_state
.sclk_bootup_value
;
579 ps
->performance_levels
[0].pcie_gen
= data
->vbios_boot_state
.pcie_gen_bootup_value
;
580 ps
->performance_levels
[0].pcie_lane
= data
->vbios_boot_state
.pcie_lane_bootup_value
;
585 static int fiji_hwmgr_backend_init(struct pp_hwmgr
*hwmgr
)
587 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
589 struct phm_ppt_v1_information
*table_info
=
590 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
594 data
->dll_default_on
= false;
595 data
->sram_end
= SMC_RAM_END
;
597 for (i
= 0; i
< SMU73_MAX_LEVELS_GRAPHICS
; i
++)
598 data
->activity_target
[i
] = FIJI_AT_DFLT
;
600 data
->vddc_vddci_delta
= VDDC_VDDCI_DELTA
;
602 data
->mclk_activity_target
= PPFIJI_MCLK_TARGETACTIVITY_DFLT
;
603 data
->mclk_dpm0_activity_target
= 0xa;
605 data
->sclk_dpm_key_disabled
= 0;
606 data
->mclk_dpm_key_disabled
= 0;
607 data
->pcie_dpm_key_disabled
= 0;
609 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
610 PHM_PlatformCaps_UnTabledHardwareInterface
);
611 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
612 PHM_PlatformCaps_TablelessHardwareInterface
);
614 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
615 PHM_PlatformCaps_SclkDeepSleep
);
617 data
->gpio_debug
= 0;
619 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
620 PHM_PlatformCaps_DynamicPatchPowerState
);
622 /* need to set voltage control types before EVV patching */
623 data
->voltage_control
= FIJI_VOLTAGE_CONTROL_NONE
;
624 data
->vddci_control
= FIJI_VOLTAGE_CONTROL_NONE
;
625 data
->mvdd_control
= FIJI_VOLTAGE_CONTROL_NONE
;
627 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
628 VOLTAGE_TYPE_VDDC
, VOLTAGE_OBJ_SVID2
))
629 data
->voltage_control
= FIJI_VOLTAGE_CONTROL_BY_SVID2
;
631 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
632 PHM_PlatformCaps_EnableMVDDControl
))
633 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
634 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_GPIO_LUT
))
635 data
->mvdd_control
= FIJI_VOLTAGE_CONTROL_BY_GPIO
;
637 if (data
->mvdd_control
== FIJI_VOLTAGE_CONTROL_NONE
)
638 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
639 PHM_PlatformCaps_EnableMVDDControl
);
641 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
642 PHM_PlatformCaps_ControlVDDCI
)) {
643 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
644 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
))
645 data
->vddci_control
= FIJI_VOLTAGE_CONTROL_BY_GPIO
;
646 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
647 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_SVID2
))
648 data
->vddci_control
= FIJI_VOLTAGE_CONTROL_BY_SVID2
;
651 if (data
->vddci_control
== FIJI_VOLTAGE_CONTROL_NONE
)
652 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
653 PHM_PlatformCaps_ControlVDDCI
);
655 if (table_info
&& table_info
->cac_dtp_table
->usClockStretchAmount
)
656 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
657 PHM_PlatformCaps_ClockStretcher
);
659 fiji_init_dpm_defaults(hwmgr
);
661 /* Get leakage voltage based on leakage ID. */
662 fiji_get_evv_voltages(hwmgr
);
664 /* Patch our voltage dependency table with actual leakage voltage
665 * We need to perform leakage translation before it's used by other functions
667 fiji_complete_dependency_tables(hwmgr
);
669 /* Parse pptable data read from VBIOS */
670 fiji_set_private_data_based_on_pptable(hwmgr
);
673 data
->ulv
.ulv_supported
= true; /* ULV feature is enabled by default */
675 /* Initalize Dynamic State Adjustment Rule Settings */
676 result
= tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr
);
679 data
->uvd_enabled
= false;
680 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
681 PHM_PlatformCaps_EnableSMU7ThermalManagement
);
682 data
->vddc_phase_shed_control
= false;
685 stay_in_boot
= phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
686 PHM_PlatformCaps_StayInBootState
);
689 struct cgs_system_info sys_info
= {0};
691 data
->is_tlu_enabled
= 0;
692 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
=
693 FIJI_MAX_HARDWARE_POWERLEVELS
;
694 hwmgr
->platform_descriptor
.hardwarePerformanceLevels
= 2;
695 hwmgr
->platform_descriptor
.minimumClocksReductionPercentage
= 50;
697 sys_info
.size
= sizeof(struct cgs_system_info
);
698 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_GEN_INFO
;
699 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
701 data
->pcie_gen_cap
= 0x30007;
703 data
->pcie_gen_cap
= (uint32_t)sys_info
.value
;
704 if (data
->pcie_gen_cap
& CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
)
705 data
->pcie_spc_cap
= 20;
706 sys_info
.size
= sizeof(struct cgs_system_info
);
707 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_MLW
;
708 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
710 data
->pcie_lane_cap
= 0x2f0000;
712 data
->pcie_lane_cap
= (uint32_t)sys_info
.value
;
714 /* Ignore return value in here, we are cleaning up a mess. */
715 tonga_hwmgr_backend_fini(hwmgr
);
722 * Read clock related registers.
724 * @param hwmgr the address of the powerplay hardware manager.
727 static int fiji_read_clock_registers(struct pp_hwmgr
*hwmgr
)
729 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
731 data
->clock_registers
.vCG_SPLL_FUNC_CNTL
=
732 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
733 ixCG_SPLL_FUNC_CNTL
);
734 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_2
=
735 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
736 ixCG_SPLL_FUNC_CNTL_2
);
737 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
=
738 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
739 ixCG_SPLL_FUNC_CNTL_3
);
740 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
=
741 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
742 ixCG_SPLL_FUNC_CNTL_4
);
743 data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
=
744 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
745 ixCG_SPLL_SPREAD_SPECTRUM
);
746 data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
=
747 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
748 ixCG_SPLL_SPREAD_SPECTRUM_2
);
754 * Find out if memory is GDDR5.
756 * @param hwmgr the address of the powerplay hardware manager.
759 static int fiji_get_memory_type(struct pp_hwmgr
*hwmgr
)
761 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
764 temp
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC0
);
766 data
->is_memory_gddr5
= (MC_SEQ_MISC0_GDDR5_VALUE
==
767 ((temp
& MC_SEQ_MISC0_GDDR5_MASK
) >>
768 MC_SEQ_MISC0_GDDR5_SHIFT
));
774 * Enables Dynamic Power Management by SMC
776 * @param hwmgr the address of the powerplay hardware manager.
779 static int fiji_enable_acpi_power_management(struct pp_hwmgr
*hwmgr
)
781 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
782 GENERAL_PWRMGT
, STATIC_PM_EN
, 1);
788 * Initialize PowerGating States for different engines
790 * @param hwmgr the address of the powerplay hardware manager.
793 static int fiji_init_power_gate_state(struct pp_hwmgr
*hwmgr
)
795 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
797 data
->uvd_power_gated
= false;
798 data
->vce_power_gated
= false;
799 data
->samu_power_gated
= false;
800 data
->acp_power_gated
= false;
801 data
->pg_acp_init
= true;
806 static int fiji_init_sclk_threshold(struct pp_hwmgr
*hwmgr
)
808 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
809 data
->low_sclk_interrupt_threshold
= 0;
814 static int fiji_setup_asic_task(struct pp_hwmgr
*hwmgr
)
816 int tmp_result
, result
= 0;
818 tmp_result
= fiji_read_clock_registers(hwmgr
);
819 PP_ASSERT_WITH_CODE((0 == tmp_result
),
820 "Failed to read clock registers!", result
= tmp_result
);
822 tmp_result
= fiji_get_memory_type(hwmgr
);
823 PP_ASSERT_WITH_CODE((0 == tmp_result
),
824 "Failed to get memory type!", result
= tmp_result
);
826 tmp_result
= fiji_enable_acpi_power_management(hwmgr
);
827 PP_ASSERT_WITH_CODE((0 == tmp_result
),
828 "Failed to enable ACPI power management!", result
= tmp_result
);
830 tmp_result
= fiji_init_power_gate_state(hwmgr
);
831 PP_ASSERT_WITH_CODE((0 == tmp_result
),
832 "Failed to init power gate state!", result
= tmp_result
);
834 tmp_result
= tonga_get_mc_microcode_version(hwmgr
);
835 PP_ASSERT_WITH_CODE((0 == tmp_result
),
836 "Failed to get MC microcode version!", result
= tmp_result
);
838 tmp_result
= fiji_init_sclk_threshold(hwmgr
);
839 PP_ASSERT_WITH_CODE((0 == tmp_result
),
840 "Failed to init sclk threshold!", result
= tmp_result
);
846 * Checks if we want to support voltage control
848 * @param hwmgr the address of the powerplay hardware manager.
850 static bool fiji_voltage_control(const struct pp_hwmgr
*hwmgr
)
852 const struct fiji_hwmgr
*data
=
853 (const struct fiji_hwmgr
*)(hwmgr
->backend
);
855 return (FIJI_VOLTAGE_CONTROL_NONE
!= data
->voltage_control
);
859 * Enable voltage control
861 * @param hwmgr the address of the powerplay hardware manager.
864 static int fiji_enable_voltage_control(struct pp_hwmgr
*hwmgr
)
866 /* enable voltage control */
867 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
868 GENERAL_PWRMGT
, VOLT_PWRMGT_EN
, 1);
874 * Remove repeated voltage values and create table with unique values.
876 * @param hwmgr the address of the powerplay hardware manager.
877 * @param vol_table the pointer to changing voltage table
878 * @return 0 in success
881 static int fiji_trim_voltage_table(struct pp_hwmgr
*hwmgr
,
882 struct pp_atomctrl_voltage_table
*vol_table
)
887 struct pp_atomctrl_voltage_table
*table
;
889 PP_ASSERT_WITH_CODE((NULL
!= vol_table
),
890 "Voltage Table empty.", return -EINVAL
);
891 table
= kzalloc(sizeof(struct pp_atomctrl_voltage_table
),
897 table
->mask_low
= vol_table
->mask_low
;
898 table
->phase_delay
= vol_table
->phase_delay
;
900 for (i
= 0; i
< vol_table
->count
; i
++) {
901 vvalue
= vol_table
->entries
[i
].value
;
904 for (j
= 0; j
< table
->count
; j
++) {
905 if (vvalue
== table
->entries
[j
].value
) {
912 table
->entries
[table
->count
].value
= vvalue
;
913 table
->entries
[table
->count
].smio_low
=
914 vol_table
->entries
[i
].smio_low
;
919 memcpy(vol_table
, table
, sizeof(struct pp_atomctrl_voltage_table
));
924 static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr
*hwmgr
,
925 phm_ppt_v1_clock_voltage_dependency_table
*dep_table
)
929 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
930 struct pp_atomctrl_voltage_table
*vol_table
= &(data
->mvdd_voltage_table
);
932 PP_ASSERT_WITH_CODE((0 != dep_table
->count
),
933 "Voltage Dependency Table empty.", return -EINVAL
);
935 vol_table
->mask_low
= 0;
936 vol_table
->phase_delay
= 0;
937 vol_table
->count
= dep_table
->count
;
939 for (i
= 0; i
< dep_table
->count
; i
++) {
940 vol_table
->entries
[i
].value
= dep_table
->entries
[i
].mvdd
;
941 vol_table
->entries
[i
].smio_low
= 0;
944 result
= fiji_trim_voltage_table(hwmgr
, vol_table
);
945 PP_ASSERT_WITH_CODE((0 == result
),
946 "Failed to trim MVDD table.", return result
);
951 static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr
*hwmgr
,
952 phm_ppt_v1_clock_voltage_dependency_table
*dep_table
)
956 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
957 struct pp_atomctrl_voltage_table
*vol_table
= &(data
->vddci_voltage_table
);
959 PP_ASSERT_WITH_CODE((0 != dep_table
->count
),
960 "Voltage Dependency Table empty.", return -EINVAL
);
962 vol_table
->mask_low
= 0;
963 vol_table
->phase_delay
= 0;
964 vol_table
->count
= dep_table
->count
;
966 for (i
= 0; i
< dep_table
->count
; i
++) {
967 vol_table
->entries
[i
].value
= dep_table
->entries
[i
].vddci
;
968 vol_table
->entries
[i
].smio_low
= 0;
971 result
= fiji_trim_voltage_table(hwmgr
, vol_table
);
972 PP_ASSERT_WITH_CODE((0 == result
),
973 "Failed to trim VDDCI table.", return result
);
978 static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr
*hwmgr
,
979 phm_ppt_v1_voltage_lookup_table
*lookup_table
)
982 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
983 struct pp_atomctrl_voltage_table
*vol_table
= &(data
->vddc_voltage_table
);
985 PP_ASSERT_WITH_CODE((0 != lookup_table
->count
),
986 "Voltage Lookup Table empty.", return -EINVAL
);
988 vol_table
->mask_low
= 0;
989 vol_table
->phase_delay
= 0;
991 vol_table
->count
= lookup_table
->count
;
993 for (i
= 0; i
< vol_table
->count
; i
++) {
994 vol_table
->entries
[i
].value
= lookup_table
->entries
[i
].us_vdd
;
995 vol_table
->entries
[i
].smio_low
= 0;
1001 /* ---- Voltage Tables ----
1002 * If the voltage table would be bigger than
1003 * what will fit into the state table on
1004 * the SMC keep only the higher entries.
1006 static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr
*hwmgr
,
1007 uint32_t max_vol_steps
, struct pp_atomctrl_voltage_table
*vol_table
)
1009 unsigned int i
, diff
;
1011 if (vol_table
->count
<= max_vol_steps
)
1014 diff
= vol_table
->count
- max_vol_steps
;
1016 for (i
= 0; i
< max_vol_steps
; i
++)
1017 vol_table
->entries
[i
] = vol_table
->entries
[i
+ diff
];
1019 vol_table
->count
= max_vol_steps
;
1025 * Create Voltage Tables.
1027 * @param hwmgr the address of the powerplay hardware manager.
1030 static int fiji_construct_voltage_tables(struct pp_hwmgr
*hwmgr
)
1032 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1033 struct phm_ppt_v1_information
*table_info
=
1034 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
1037 if (FIJI_VOLTAGE_CONTROL_BY_GPIO
== data
->mvdd_control
) {
1038 result
= atomctrl_get_voltage_table_v3(hwmgr
,
1039 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_GPIO_LUT
,
1040 &(data
->mvdd_voltage_table
));
1041 PP_ASSERT_WITH_CODE((0 == result
),
1042 "Failed to retrieve MVDD table.",
1044 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->mvdd_control
) {
1045 result
= fiji_get_svi2_mvdd_voltage_table(hwmgr
,
1046 table_info
->vdd_dep_on_mclk
);
1047 PP_ASSERT_WITH_CODE((0 == result
),
1048 "Failed to retrieve SVI2 MVDD table from dependancy table.",
1052 if (FIJI_VOLTAGE_CONTROL_BY_GPIO
== data
->vddci_control
) {
1053 result
= atomctrl_get_voltage_table_v3(hwmgr
,
1054 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
,
1055 &(data
->vddci_voltage_table
));
1056 PP_ASSERT_WITH_CODE((0 == result
),
1057 "Failed to retrieve VDDCI table.",
1059 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->vddci_control
) {
1060 result
= fiji_get_svi2_vddci_voltage_table(hwmgr
,
1061 table_info
->vdd_dep_on_mclk
);
1062 PP_ASSERT_WITH_CODE((0 == result
),
1063 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
1067 if(FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
) {
1068 result
= fiji_get_svi2_vdd_voltage_table(hwmgr
,
1069 table_info
->vddc_lookup_table
);
1070 PP_ASSERT_WITH_CODE((0 == result
),
1071 "Failed to retrieve SVI2 VDDC table from lookup table.",
1075 PP_ASSERT_WITH_CODE(
1076 (data
->vddc_voltage_table
.count
<= (SMU73_MAX_LEVELS_VDDC
)),
1077 "Too many voltage values for VDDC. Trimming to fit state table.",
1078 fiji_trim_voltage_table_to_fit_state_table(hwmgr
,
1079 SMU73_MAX_LEVELS_VDDC
, &(data
->vddc_voltage_table
)));
1081 PP_ASSERT_WITH_CODE(
1082 (data
->vddci_voltage_table
.count
<= (SMU73_MAX_LEVELS_VDDCI
)),
1083 "Too many voltage values for VDDCI. Trimming to fit state table.",
1084 fiji_trim_voltage_table_to_fit_state_table(hwmgr
,
1085 SMU73_MAX_LEVELS_VDDCI
, &(data
->vddci_voltage_table
)));
1087 PP_ASSERT_WITH_CODE(
1088 (data
->mvdd_voltage_table
.count
<= (SMU73_MAX_LEVELS_MVDD
)),
1089 "Too many voltage values for MVDD. Trimming to fit state table.",
1090 fiji_trim_voltage_table_to_fit_state_table(hwmgr
,
1091 SMU73_MAX_LEVELS_MVDD
, &(data
->mvdd_voltage_table
)));
1096 static int fiji_initialize_mc_reg_table(struct pp_hwmgr
*hwmgr
)
1098 /* Program additional LP registers
1099 * that are no longer programmed by VBIOS
1101 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RAS_TIMING_LP
,
1102 cgs_read_register(hwmgr
->device
, mmMC_SEQ_RAS_TIMING
));
1103 cgs_write_register(hwmgr
->device
, mmMC_SEQ_CAS_TIMING_LP
,
1104 cgs_read_register(hwmgr
->device
, mmMC_SEQ_CAS_TIMING
));
1105 cgs_write_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING2_LP
,
1106 cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING2
));
1107 cgs_write_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D1_LP
,
1108 cgs_read_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D1
));
1109 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D0_LP
,
1110 cgs_read_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D0
));
1111 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D1_LP
,
1112 cgs_read_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D1
));
1113 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_TIMING_LP
,
1114 cgs_read_register(hwmgr
->device
, mmMC_SEQ_PMG_TIMING
));
1120 * Programs static screed detection parameters
1122 * @param hwmgr the address of the powerplay hardware manager.
1125 static int fiji_program_static_screen_threshold_parameters(
1126 struct pp_hwmgr
*hwmgr
)
1128 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1130 /* Set static screen threshold unit */
1131 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1132 CG_STATIC_SCREEN_PARAMETER
, STATIC_SCREEN_THRESHOLD_UNIT
,
1133 data
->static_screen_threshold_unit
);
1134 /* Set static screen threshold */
1135 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1136 CG_STATIC_SCREEN_PARAMETER
, STATIC_SCREEN_THRESHOLD
,
1137 data
->static_screen_threshold
);
1143 * Setup display gap for glitch free memory clock switching.
1145 * @param hwmgr the address of the powerplay hardware manager.
1148 static int fiji_enable_display_gap(struct pp_hwmgr
*hwmgr
)
1150 uint32_t displayGap
=
1151 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1152 ixCG_DISPLAY_GAP_CNTL
);
1154 displayGap
= PHM_SET_FIELD(displayGap
, CG_DISPLAY_GAP_CNTL
,
1155 DISP_GAP
, DISPLAY_GAP_IGNORE
);
1157 displayGap
= PHM_SET_FIELD(displayGap
, CG_DISPLAY_GAP_CNTL
,
1158 DISP_GAP_MCHG
, DISPLAY_GAP_VBLANK
);
1160 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1161 ixCG_DISPLAY_GAP_CNTL
, displayGap
);
1167 * Programs activity state transition voting clients
1169 * @param hwmgr the address of the powerplay hardware manager.
1172 static int fiji_program_voting_clients(struct pp_hwmgr
*hwmgr
)
1174 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1176 /* Clear reset for voting clients before enabling DPM */
1177 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1178 SCLK_PWRMGT_CNTL
, RESET_SCLK_CNT
, 0);
1179 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1180 SCLK_PWRMGT_CNTL
, RESET_BUSY_CNT
, 0);
1182 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1183 ixCG_FREQ_TRAN_VOTING_0
, data
->voting_rights_clients0
);
1184 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1185 ixCG_FREQ_TRAN_VOTING_1
, data
->voting_rights_clients1
);
1186 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1187 ixCG_FREQ_TRAN_VOTING_2
, data
->voting_rights_clients2
);
1188 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1189 ixCG_FREQ_TRAN_VOTING_3
, data
->voting_rights_clients3
);
1190 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1191 ixCG_FREQ_TRAN_VOTING_4
, data
->voting_rights_clients4
);
1192 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1193 ixCG_FREQ_TRAN_VOTING_5
, data
->voting_rights_clients5
);
1194 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1195 ixCG_FREQ_TRAN_VOTING_6
, data
->voting_rights_clients6
);
1196 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1197 ixCG_FREQ_TRAN_VOTING_7
, data
->voting_rights_clients7
);
1203 * Get the location of various tables inside the FW image.
1205 * @param hwmgr the address of the powerplay hardware manager.
1208 static int fiji_process_firmware_header(struct pp_hwmgr
*hwmgr
)
1210 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1211 struct fiji_smumgr
*smu_data
= (struct fiji_smumgr
*)(hwmgr
->smumgr
->backend
);
1216 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1217 SMU7_FIRMWARE_HEADER_LOCATION
+
1218 offsetof(SMU73_Firmware_Header
, DpmTable
),
1219 &tmp
, data
->sram_end
);
1222 data
->dpm_table_start
= tmp
;
1224 error
|= (0 != result
);
1226 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1227 SMU7_FIRMWARE_HEADER_LOCATION
+
1228 offsetof(SMU73_Firmware_Header
, SoftRegisters
),
1229 &tmp
, data
->sram_end
);
1232 data
->soft_regs_start
= tmp
;
1233 smu_data
->soft_regs_start
= tmp
;
1236 error
|= (0 != result
);
1238 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1239 SMU7_FIRMWARE_HEADER_LOCATION
+
1240 offsetof(SMU73_Firmware_Header
, mcRegisterTable
),
1241 &tmp
, data
->sram_end
);
1244 data
->mc_reg_table_start
= tmp
;
1246 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1247 SMU7_FIRMWARE_HEADER_LOCATION
+
1248 offsetof(SMU73_Firmware_Header
, FanTable
),
1249 &tmp
, data
->sram_end
);
1252 data
->fan_table_start
= tmp
;
1254 error
|= (0 != result
);
1256 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1257 SMU7_FIRMWARE_HEADER_LOCATION
+
1258 offsetof(SMU73_Firmware_Header
, mcArbDramTimingTable
),
1259 &tmp
, data
->sram_end
);
1262 data
->arb_table_start
= tmp
;
1264 error
|= (0 != result
);
1266 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1267 SMU7_FIRMWARE_HEADER_LOCATION
+
1268 offsetof(SMU73_Firmware_Header
, Version
),
1269 &tmp
, data
->sram_end
);
1272 hwmgr
->microcode_version_info
.SMC
= tmp
;
1274 error
|= (0 != result
);
1276 return error
? -1 : 0;
1279 /* Copy one arb setting to another and then switch the active set.
1280 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
1282 static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr
*hwmgr
,
1283 uint32_t arb_src
, uint32_t arb_dest
)
1285 uint32_t mc_arb_dram_timing
;
1286 uint32_t mc_arb_dram_timing2
;
1287 uint32_t burst_time
;
1288 uint32_t mc_cg_config
;
1291 case MC_CG_ARB_FREQ_F0
:
1292 mc_arb_dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
);
1293 mc_arb_dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
);
1294 burst_time
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
);
1296 case MC_CG_ARB_FREQ_F1
:
1297 mc_arb_dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING_1
);
1298 mc_arb_dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2_1
);
1299 burst_time
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE1
);
1306 case MC_CG_ARB_FREQ_F0
:
1307 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
, mc_arb_dram_timing
);
1308 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
, mc_arb_dram_timing2
);
1309 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
, burst_time
);
1311 case MC_CG_ARB_FREQ_F1
:
1312 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING_1
, mc_arb_dram_timing
);
1313 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2_1
, mc_arb_dram_timing2
);
1314 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE1
, burst_time
);
1320 mc_cg_config
= cgs_read_register(hwmgr
->device
, mmMC_CG_CONFIG
);
1321 mc_cg_config
|= 0x0000000F;
1322 cgs_write_register(hwmgr
->device
, mmMC_CG_CONFIG
, mc_cg_config
);
1323 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_CG
, CG_ARB_REQ
, arb_dest
);
1329 * Initial switch from ARB F0->F1
1331 * @param hwmgr the address of the powerplay hardware manager.
1333 * This function is to be called from the SetPowerState table.
1335 static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr
*hwmgr
)
1337 return fiji_copy_and_switch_arb_sets(hwmgr
,
1338 MC_CG_ARB_FREQ_F0
, MC_CG_ARB_FREQ_F1
);
1341 static int fiji_reset_single_dpm_table(struct pp_hwmgr
*hwmgr
,
1342 struct fiji_single_dpm_table
*dpm_table
, uint32_t count
)
1345 PP_ASSERT_WITH_CODE(count
<= MAX_REGULAR_DPM_NUMBER
,
1346 "Fatal error, can not set up single DPM table entries "
1347 "to exceed max number!",);
1349 dpm_table
->count
= count
;
1350 for (i
= 0; i
< MAX_REGULAR_DPM_NUMBER
; i
++)
1351 dpm_table
->dpm_levels
[i
].enabled
= false;
1356 static void fiji_setup_pcie_table_entry(
1357 struct fiji_single_dpm_table
*dpm_table
,
1358 uint32_t index
, uint32_t pcie_gen
,
1359 uint32_t pcie_lanes
)
1361 dpm_table
->dpm_levels
[index
].value
= pcie_gen
;
1362 dpm_table
->dpm_levels
[index
].param1
= pcie_lanes
;
1363 dpm_table
->dpm_levels
[index
].enabled
= 1;
1366 static int fiji_setup_default_pcie_table(struct pp_hwmgr
*hwmgr
)
1368 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1369 struct phm_ppt_v1_information
*table_info
=
1370 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1371 struct phm_ppt_v1_pcie_table
*pcie_table
= table_info
->pcie_table
;
1372 uint32_t i
, max_entry
;
1374 PP_ASSERT_WITH_CODE((data
->use_pcie_performance_levels
||
1375 data
->use_pcie_power_saving_levels
), "No pcie performance levels!",
1378 if (data
->use_pcie_performance_levels
&&
1379 !data
->use_pcie_power_saving_levels
) {
1380 data
->pcie_gen_power_saving
= data
->pcie_gen_performance
;
1381 data
->pcie_lane_power_saving
= data
->pcie_lane_performance
;
1382 } else if (!data
->use_pcie_performance_levels
&&
1383 data
->use_pcie_power_saving_levels
) {
1384 data
->pcie_gen_performance
= data
->pcie_gen_power_saving
;
1385 data
->pcie_lane_performance
= data
->pcie_lane_power_saving
;
1388 fiji_reset_single_dpm_table(hwmgr
,
1389 &data
->dpm_table
.pcie_speed_table
, SMU73_MAX_LEVELS_LINK
);
1391 if (pcie_table
!= NULL
) {
1392 /* max_entry is used to make sure we reserve one PCIE level
1393 * for boot level (fix for A+A PSPP issue).
1394 * If PCIE table from PPTable have ULV entry + 8 entries,
1395 * then ignore the last entry.*/
1396 max_entry
= (SMU73_MAX_LEVELS_LINK
< pcie_table
->count
) ?
1397 SMU73_MAX_LEVELS_LINK
: pcie_table
->count
;
1398 for (i
= 1; i
< max_entry
; i
++) {
1399 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, i
- 1,
1400 get_pcie_gen_support(data
->pcie_gen_cap
,
1401 pcie_table
->entries
[i
].gen_speed
),
1402 get_pcie_lane_support(data
->pcie_lane_cap
,
1403 pcie_table
->entries
[i
].lane_width
));
1405 data
->dpm_table
.pcie_speed_table
.count
= max_entry
- 1;
1407 /* Hardcode Pcie Table */
1408 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 0,
1409 get_pcie_gen_support(data
->pcie_gen_cap
,
1411 get_pcie_lane_support(data
->pcie_lane_cap
,
1413 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 1,
1414 get_pcie_gen_support(data
->pcie_gen_cap
,
1416 get_pcie_lane_support(data
->pcie_lane_cap
,
1418 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 2,
1419 get_pcie_gen_support(data
->pcie_gen_cap
,
1421 get_pcie_lane_support(data
->pcie_lane_cap
,
1423 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 3,
1424 get_pcie_gen_support(data
->pcie_gen_cap
,
1426 get_pcie_lane_support(data
->pcie_lane_cap
,
1428 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 4,
1429 get_pcie_gen_support(data
->pcie_gen_cap
,
1431 get_pcie_lane_support(data
->pcie_lane_cap
,
1433 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 5,
1434 get_pcie_gen_support(data
->pcie_gen_cap
,
1436 get_pcie_lane_support(data
->pcie_lane_cap
,
1439 data
->dpm_table
.pcie_speed_table
.count
= 6;
1441 /* Populate last level for boot PCIE level, but do not increment count. */
1442 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
,
1443 data
->dpm_table
.pcie_speed_table
.count
,
1444 get_pcie_gen_support(data
->pcie_gen_cap
,
1446 get_pcie_lane_support(data
->pcie_lane_cap
,
1453 * This function is to initalize all DPM state tables
1454 * for SMU7 based on the dependency table.
1455 * Dynamic state patching function will then trim these
1456 * state tables to the allowed range based
1457 * on the power policy or external client requests,
1458 * such as UVD request, etc.
1460 static int fiji_setup_default_dpm_tables(struct pp_hwmgr
*hwmgr
)
1462 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1463 struct phm_ppt_v1_information
*table_info
=
1464 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1467 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_sclk_table
=
1468 table_info
->vdd_dep_on_sclk
;
1469 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_mclk_table
=
1470 table_info
->vdd_dep_on_mclk
;
1472 PP_ASSERT_WITH_CODE(dep_sclk_table
!= NULL
,
1473 "SCLK dependency table is missing. This table is mandatory",
1475 PP_ASSERT_WITH_CODE(dep_sclk_table
->count
>= 1,
1476 "SCLK dependency table has to have is missing. "
1477 "This table is mandatory",
1480 PP_ASSERT_WITH_CODE(dep_mclk_table
!= NULL
,
1481 "MCLK dependency table is missing. This table is mandatory",
1483 PP_ASSERT_WITH_CODE(dep_mclk_table
->count
>= 1,
1484 "MCLK dependency table has to have is missing. "
1485 "This table is mandatory",
1488 /* clear the state table to reset everything to default */
1489 fiji_reset_single_dpm_table(hwmgr
,
1490 &data
->dpm_table
.sclk_table
, SMU73_MAX_LEVELS_GRAPHICS
);
1491 fiji_reset_single_dpm_table(hwmgr
,
1492 &data
->dpm_table
.mclk_table
, SMU73_MAX_LEVELS_MEMORY
);
1494 /* Initialize Sclk DPM table based on allow Sclk values */
1495 data
->dpm_table
.sclk_table
.count
= 0;
1496 for (i
= 0; i
< dep_sclk_table
->count
; i
++) {
1497 if (i
== 0 || data
->dpm_table
.sclk_table
.dpm_levels
1498 [data
->dpm_table
.sclk_table
.count
- 1].value
!=
1499 dep_sclk_table
->entries
[i
].clk
) {
1500 data
->dpm_table
.sclk_table
.dpm_levels
1501 [data
->dpm_table
.sclk_table
.count
].value
=
1502 dep_sclk_table
->entries
[i
].clk
;
1503 data
->dpm_table
.sclk_table
.dpm_levels
1504 [data
->dpm_table
.sclk_table
.count
].enabled
=
1505 (i
== 0) ? true : false;
1506 data
->dpm_table
.sclk_table
.count
++;
1510 /* Initialize Mclk DPM table based on allow Mclk values */
1511 data
->dpm_table
.mclk_table
.count
= 0;
1512 for (i
=0; i
<dep_mclk_table
->count
; i
++) {
1513 if ( i
==0 || data
->dpm_table
.mclk_table
.dpm_levels
1514 [data
->dpm_table
.mclk_table
.count
- 1].value
!=
1515 dep_mclk_table
->entries
[i
].clk
) {
1516 data
->dpm_table
.mclk_table
.dpm_levels
1517 [data
->dpm_table
.mclk_table
.count
].value
=
1518 dep_mclk_table
->entries
[i
].clk
;
1519 data
->dpm_table
.mclk_table
.dpm_levels
1520 [data
->dpm_table
.mclk_table
.count
].enabled
=
1521 (i
== 0) ? true : false;
1522 data
->dpm_table
.mclk_table
.count
++;
1526 /* setup PCIE gen speed levels */
1527 fiji_setup_default_pcie_table(hwmgr
);
1529 /* save a copy of the default DPM table */
1530 memcpy(&(data
->golden_dpm_table
), &(data
->dpm_table
),
1531 sizeof(struct fiji_dpm_table
));
1537 * @brief PhwFiji_GetVoltageOrder
1538 * Returns index of requested voltage record in lookup(table)
1539 * @param lookup_table - lookup list to search in
1540 * @param voltage - voltage to look for
1541 * @return 0 on success
1543 uint8_t fiji_get_voltage_index(
1544 struct phm_ppt_v1_voltage_lookup_table
*lookup_table
, uint16_t voltage
)
1546 uint8_t count
= (uint8_t) (lookup_table
->count
);
1549 PP_ASSERT_WITH_CODE((NULL
!= lookup_table
),
1550 "Lookup Table empty.", return 0);
1551 PP_ASSERT_WITH_CODE((0 != count
),
1552 "Lookup Table empty.", return 0);
1554 for (i
= 0; i
< lookup_table
->count
; i
++) {
1555 /* find first voltage equal or bigger than requested */
1556 if (lookup_table
->entries
[i
].us_vdd
>= voltage
)
1559 /* voltage is bigger than max voltage in the table */
1564 * Preparation of vddc and vddgfx CAC tables for SMC.
1566 * @param hwmgr the address of the hardware manager
1567 * @param table the SMC DPM table structure to be populated
1570 static int fiji_populate_cac_table(struct pp_hwmgr
*hwmgr
,
1571 struct SMU73_Discrete_DpmTable
*table
)
1576 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1577 struct phm_ppt_v1_information
*table_info
=
1578 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1579 struct phm_ppt_v1_voltage_lookup_table
*lookup_table
=
1580 table_info
->vddc_lookup_table
;
1581 /* tables is already swapped, so in order to use the value from it,
1582 * we need to swap it back.
1583 * We are populating vddc CAC data to BapmVddc table
1584 * in split and merged mode
1586 for( count
= 0; count
<lookup_table
->count
; count
++) {
1587 index
= fiji_get_voltage_index(lookup_table
,
1588 data
->vddc_voltage_table
.entries
[count
].value
);
1589 table
->BapmVddcVidLoSidd
[count
] = (uint8_t) ((6200 -
1590 (lookup_table
->entries
[index
].us_cac_low
*
1591 VOLTAGE_SCALE
)) / 25);
1592 table
->BapmVddcVidHiSidd
[count
] = (uint8_t) ((6200 -
1593 (lookup_table
->entries
[index
].us_cac_high
*
1594 VOLTAGE_SCALE
)) / 25);
1601 * Preparation of voltage tables for SMC.
1603 * @param hwmgr the address of the hardware manager
1604 * @param table the SMC DPM table structure to be populated
1608 int fiji_populate_smc_voltage_tables(struct pp_hwmgr
*hwmgr
,
1609 struct SMU73_Discrete_DpmTable
*table
)
1613 result
= fiji_populate_cac_table(hwmgr
, table
);
1614 PP_ASSERT_WITH_CODE(0 == result
,
1615 "can not populate CAC voltage tables to SMC",
1621 static int fiji_populate_ulv_level(struct pp_hwmgr
*hwmgr
,
1622 struct SMU73_Discrete_Ulv
*state
)
1625 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1626 struct phm_ppt_v1_information
*table_info
=
1627 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1629 state
->CcPwrDynRm
= 0;
1630 state
->CcPwrDynRm1
= 0;
1632 state
->VddcOffset
= (uint16_t) table_info
->us_ulv_voltage_offset
;
1633 state
->VddcOffsetVid
= (uint8_t)( table_info
->us_ulv_voltage_offset
*
1634 VOLTAGE_VID_OFFSET_SCALE2
/ VOLTAGE_VID_OFFSET_SCALE1
);
1636 state
->VddcPhase
= (data
->vddc_phase_shed_control
) ? 0 : 1;
1639 CONVERT_FROM_HOST_TO_SMC_UL(state
->CcPwrDynRm
);
1640 CONVERT_FROM_HOST_TO_SMC_UL(state
->CcPwrDynRm1
);
1641 CONVERT_FROM_HOST_TO_SMC_US(state
->VddcOffset
);
1646 static int fiji_populate_ulv_state(struct pp_hwmgr
*hwmgr
,
1647 struct SMU73_Discrete_DpmTable
*table
)
1649 return fiji_populate_ulv_level(hwmgr
, &table
->Ulv
);
1652 static int32_t fiji_get_dpm_level_enable_mask_value(
1653 struct fiji_single_dpm_table
* dpm_table
)
1658 for (i
= dpm_table
->count
; i
> 0; i
--) {
1660 if (dpm_table
->dpm_levels
[i
- 1].enabled
)
1668 static int fiji_populate_smc_link_level(struct pp_hwmgr
*hwmgr
,
1669 struct SMU73_Discrete_DpmTable
*table
)
1671 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1672 struct fiji_dpm_table
*dpm_table
= &data
->dpm_table
;
1675 /* Index (dpm_table->pcie_speed_table.count)
1676 * is reserved for PCIE boot level. */
1677 for (i
= 0; i
<= dpm_table
->pcie_speed_table
.count
; i
++) {
1678 table
->LinkLevel
[i
].PcieGenSpeed
=
1679 (uint8_t)dpm_table
->pcie_speed_table
.dpm_levels
[i
].value
;
1680 table
->LinkLevel
[i
].PcieLaneCount
= (uint8_t)encode_pcie_lane_width(
1681 dpm_table
->pcie_speed_table
.dpm_levels
[i
].param1
);
1682 table
->LinkLevel
[i
].EnabledForActivity
= 1;
1683 table
->LinkLevel
[i
].SPC
= (uint8_t)(data
->pcie_spc_cap
& 0xff);
1684 table
->LinkLevel
[i
].DownThreshold
= PP_HOST_TO_SMC_UL(5);
1685 table
->LinkLevel
[i
].UpThreshold
= PP_HOST_TO_SMC_UL(30);
1688 data
->smc_state_table
.LinkLevelCount
=
1689 (uint8_t)dpm_table
->pcie_speed_table
.count
;
1690 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
=
1691 fiji_get_dpm_level_enable_mask_value(&dpm_table
->pcie_speed_table
);
1697 * Calculates the SCLK dividers using the provided engine clock
1699 * @param hwmgr the address of the hardware manager
1700 * @param clock the engine clock to use to populate the structure
1701 * @param sclk the SMC SCLK structure to be populated
1703 static int fiji_calculate_sclk_params(struct pp_hwmgr
*hwmgr
,
1704 uint32_t clock
, struct SMU73_Discrete_GraphicsLevel
*sclk
)
1706 const struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1707 struct pp_atomctrl_clock_dividers_vi dividers
;
1708 uint32_t spll_func_cntl
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL
;
1709 uint32_t spll_func_cntl_3
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
;
1710 uint32_t spll_func_cntl_4
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
;
1711 uint32_t cg_spll_spread_spectrum
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
;
1712 uint32_t cg_spll_spread_spectrum_2
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
;
1714 uint32_t ref_divider
;
1718 /* get the engine clock dividers for this clock value */
1719 result
= atomctrl_get_engine_pll_dividers_vi(hwmgr
, clock
, ÷rs
);
1721 PP_ASSERT_WITH_CODE(result
== 0,
1722 "Error retrieving Engine Clock dividers from VBIOS.",
1725 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
1726 ref_clock
= atomctrl_get_reference_clock(hwmgr
);
1727 ref_divider
= 1 + dividers
.uc_pll_ref_div
;
1729 /* low 14 bits is fraction and high 12 bits is divider */
1730 fbdiv
= dividers
.ul_fb_div
.ul_fb_divider
& 0x3FFFFFF;
1732 /* SPLL_FUNC_CNTL setup */
1733 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
, CG_SPLL_FUNC_CNTL
,
1734 SPLL_REF_DIV
, dividers
.uc_pll_ref_div
);
1735 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
, CG_SPLL_FUNC_CNTL
,
1736 SPLL_PDIV_A
, dividers
.uc_pll_post_div
);
1738 /* SPLL_FUNC_CNTL_3 setup*/
1739 spll_func_cntl_3
= PHM_SET_FIELD(spll_func_cntl_3
, CG_SPLL_FUNC_CNTL_3
,
1740 SPLL_FB_DIV
, fbdiv
);
1742 /* set to use fractional accumulation*/
1743 spll_func_cntl_3
= PHM_SET_FIELD(spll_func_cntl_3
, CG_SPLL_FUNC_CNTL_3
,
1746 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1747 PHM_PlatformCaps_EngineSpreadSpectrumSupport
)) {
1748 struct pp_atomctrl_internal_ss_info ssInfo
;
1750 uint32_t vco_freq
= clock
* dividers
.uc_pll_post_div
;
1751 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr
,
1752 vco_freq
, &ssInfo
)) {
1754 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
1755 * ss_info.speed_spectrum_rate -- in unit of khz
1757 * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
1759 uint32_t clk_s
= ref_clock
* 5 /
1760 (ref_divider
* ssInfo
.speed_spectrum_rate
);
1761 /* clkv = 2 * D * fbdiv / NS */
1762 uint32_t clk_v
= 4 * ssInfo
.speed_spectrum_percentage
*
1763 fbdiv
/ (clk_s
* 10000);
1765 cg_spll_spread_spectrum
= PHM_SET_FIELD(cg_spll_spread_spectrum
,
1766 CG_SPLL_SPREAD_SPECTRUM
, CLKS
, clk_s
);
1767 cg_spll_spread_spectrum
= PHM_SET_FIELD(cg_spll_spread_spectrum
,
1768 CG_SPLL_SPREAD_SPECTRUM
, SSEN
, 1);
1769 cg_spll_spread_spectrum_2
= PHM_SET_FIELD(cg_spll_spread_spectrum_2
,
1770 CG_SPLL_SPREAD_SPECTRUM_2
, CLKV
, clk_v
);
1774 sclk
->SclkFrequency
= clock
;
1775 sclk
->CgSpllFuncCntl3
= spll_func_cntl_3
;
1776 sclk
->CgSpllFuncCntl4
= spll_func_cntl_4
;
1777 sclk
->SpllSpreadSpectrum
= cg_spll_spread_spectrum
;
1778 sclk
->SpllSpreadSpectrum2
= cg_spll_spread_spectrum_2
;
1779 sclk
->SclkDid
= (uint8_t)dividers
.pll_post_divider
;
1784 static uint16_t fiji_find_closest_vddci(struct pp_hwmgr
*hwmgr
, uint16_t vddci
)
1787 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1788 struct pp_atomctrl_voltage_table
*vddci_table
=
1789 &(data
->vddci_voltage_table
);
1791 for (i
= 0; i
< vddci_table
->count
; i
++) {
1792 if (vddci_table
->entries
[i
].value
>= vddci
)
1793 return vddci_table
->entries
[i
].value
;
1796 PP_ASSERT_WITH_CODE(false,
1797 "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
1798 return vddci_table
->entries
[i
].value
);
1801 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr
*hwmgr
,
1802 struct phm_ppt_v1_clock_voltage_dependency_table
* dep_table
,
1803 uint32_t clock
, SMU_VoltageLevel
*voltage
, uint32_t *mvdd
)
1807 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1809 *voltage
= *mvdd
= 0;
1811 /* clock - voltage dependency table is empty table */
1812 if (dep_table
->count
== 0)
1815 for (i
= 0; i
< dep_table
->count
; i
++) {
1816 /* find first sclk bigger than request */
1817 if (dep_table
->entries
[i
].clk
>= clock
) {
1818 *voltage
|= (dep_table
->entries
[i
].vddc
*
1819 VOLTAGE_SCALE
) << VDDC_SHIFT
;
1820 if (FIJI_VOLTAGE_CONTROL_NONE
== data
->vddci_control
)
1821 *voltage
|= (data
->vbios_boot_state
.vddci_bootup_value
*
1822 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1823 else if (dep_table
->entries
[i
].vddci
)
1824 *voltage
|= (dep_table
->entries
[i
].vddci
*
1825 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1827 vddci
= fiji_find_closest_vddci(hwmgr
,
1828 (dep_table
->entries
[i
].vddc
-
1829 (uint16_t)data
->vddc_vddci_delta
));
1830 *voltage
|= (vddci
* VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1833 if (FIJI_VOLTAGE_CONTROL_NONE
== data
->mvdd_control
)
1834 *mvdd
= data
->vbios_boot_state
.mvdd_bootup_value
*
1836 else if (dep_table
->entries
[i
].mvdd
)
1837 *mvdd
= (uint32_t) dep_table
->entries
[i
].mvdd
*
1840 *voltage
|= 1 << PHASES_SHIFT
;
1845 /* sclk is bigger than max sclk in the dependence table */
1846 *voltage
|= (dep_table
->entries
[i
- 1].vddc
* VOLTAGE_SCALE
) << VDDC_SHIFT
;
1848 if (FIJI_VOLTAGE_CONTROL_NONE
== data
->vddci_control
)
1849 *voltage
|= (data
->vbios_boot_state
.vddci_bootup_value
*
1850 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1851 else if (dep_table
->entries
[i
-1].vddci
) {
1852 vddci
= fiji_find_closest_vddci(hwmgr
,
1853 (dep_table
->entries
[i
].vddc
-
1854 (uint16_t)data
->vddc_vddci_delta
));
1855 *voltage
|= (vddci
* VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1858 if (FIJI_VOLTAGE_CONTROL_NONE
== data
->mvdd_control
)
1859 *mvdd
= data
->vbios_boot_state
.mvdd_bootup_value
* VOLTAGE_SCALE
;
1860 else if (dep_table
->entries
[i
].mvdd
)
1861 *mvdd
= (uint32_t) dep_table
->entries
[i
- 1].mvdd
* VOLTAGE_SCALE
;
1866 * Populates single SMC SCLK structure using the provided engine clock
1868 * @param hwmgr the address of the hardware manager
1869 * @param clock the engine clock to use to populate the structure
1870 * @param sclk the SMC SCLK structure to be populated
1873 static int fiji_populate_single_graphic_level(struct pp_hwmgr
*hwmgr
,
1874 uint32_t clock
, uint16_t sclk_al_threshold
,
1875 struct SMU73_Discrete_GraphicsLevel
*level
)
1878 /* PP_Clocks minClocks; */
1879 uint32_t threshold
, mvdd
;
1880 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1881 struct phm_ppt_v1_information
*table_info
=
1882 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1884 result
= fiji_calculate_sclk_params(hwmgr
, clock
, level
);
1886 /* populate graphics levels */
1887 result
= fiji_get_dependency_volt_by_clk(hwmgr
,
1888 table_info
->vdd_dep_on_sclk
, clock
,
1889 &level
->MinVoltage
, &mvdd
);
1890 PP_ASSERT_WITH_CODE((0 == result
),
1891 "can not find VDDC voltage value for "
1892 "VDDC engine clock dependency table",
1895 level
->SclkFrequency
= clock
;
1896 level
->ActivityLevel
= sclk_al_threshold
;
1897 level
->CcPwrDynRm
= 0;
1898 level
->CcPwrDynRm1
= 0;
1899 level
->EnabledForActivity
= 0;
1900 level
->EnabledForThrottle
= 1;
1902 level
->DownHyst
= 0;
1903 level
->VoltageDownHyst
= 0;
1904 level
->PowerThrottle
= 0;
1906 threshold
= clock
* data
->fast_watermark_threshold
/ 100;
1909 * TODO: get minimum clocks from dal configaration
1910 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1912 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1914 /* get level->DeepSleepDivId
1915 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1917 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1920 /* Default to slow, highest DPM level will be
1921 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1923 level
->DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
1925 CONVERT_FROM_HOST_TO_SMC_UL(level
->MinVoltage
);
1926 CONVERT_FROM_HOST_TO_SMC_UL(level
->SclkFrequency
);
1927 CONVERT_FROM_HOST_TO_SMC_US(level
->ActivityLevel
);
1928 CONVERT_FROM_HOST_TO_SMC_UL(level
->CgSpllFuncCntl3
);
1929 CONVERT_FROM_HOST_TO_SMC_UL(level
->CgSpllFuncCntl4
);
1930 CONVERT_FROM_HOST_TO_SMC_UL(level
->SpllSpreadSpectrum
);
1931 CONVERT_FROM_HOST_TO_SMC_UL(level
->SpllSpreadSpectrum2
);
1932 CONVERT_FROM_HOST_TO_SMC_UL(level
->CcPwrDynRm
);
1933 CONVERT_FROM_HOST_TO_SMC_UL(level
->CcPwrDynRm1
);
1938 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1940 * @param hwmgr the address of the hardware manager
1942 static int fiji_populate_all_graphic_levels(struct pp_hwmgr
*hwmgr
)
1944 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1945 struct fiji_dpm_table
*dpm_table
= &data
->dpm_table
;
1946 struct phm_ppt_v1_information
*table_info
=
1947 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1948 struct phm_ppt_v1_pcie_table
*pcie_table
= table_info
->pcie_table
;
1949 uint8_t pcie_entry_cnt
= (uint8_t) data
->dpm_table
.pcie_speed_table
.count
;
1951 uint32_t array
= data
->dpm_table_start
+
1952 offsetof(SMU73_Discrete_DpmTable
, GraphicsLevel
);
1953 uint32_t array_size
= sizeof(struct SMU73_Discrete_GraphicsLevel
) *
1954 SMU73_MAX_LEVELS_GRAPHICS
;
1955 struct SMU73_Discrete_GraphicsLevel
*levels
=
1956 data
->smc_state_table
.GraphicsLevel
;
1957 uint32_t i
, max_entry
;
1958 uint8_t hightest_pcie_level_enabled
= 0,
1959 lowest_pcie_level_enabled
= 0,
1960 mid_pcie_level_enabled
= 0,
1963 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
1964 result
= fiji_populate_single_graphic_level(hwmgr
,
1965 dpm_table
->sclk_table
.dpm_levels
[i
].value
,
1966 (uint16_t)data
->activity_target
[i
],
1971 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1973 levels
[i
].DeepSleepDivId
= 0;
1976 /* Only enable level 0 for now.*/
1977 levels
[0].EnabledForActivity
= 1;
1979 /* set highest level watermark to high */
1980 levels
[dpm_table
->sclk_table
.count
- 1].DisplayWatermark
=
1981 PPSMC_DISPLAY_WATERMARK_HIGH
;
1983 data
->smc_state_table
.GraphicsDpmLevelCount
=
1984 (uint8_t)dpm_table
->sclk_table
.count
;
1985 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
=
1986 fiji_get_dpm_level_enable_mask_value(&dpm_table
->sclk_table
);
1988 if (pcie_table
!= NULL
) {
1989 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt
),
1990 "There must be 1 or more PCIE levels defined in PPTable.",
1992 max_entry
= pcie_entry_cnt
- 1;
1993 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++)
1994 levels
[i
].pcieDpmLevel
=
1995 (uint8_t) ((i
< max_entry
)? i
: max_entry
);
1997 while (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&&
1998 ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
1999 (1 << (hightest_pcie_level_enabled
+ 1))) != 0 ))
2000 hightest_pcie_level_enabled
++;
2002 while (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&&
2003 ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
2004 (1 << lowest_pcie_level_enabled
)) == 0 ))
2005 lowest_pcie_level_enabled
++;
2007 while ((count
< hightest_pcie_level_enabled
) &&
2008 ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
2009 (1 << (lowest_pcie_level_enabled
+ 1 + count
))) == 0 ))
2012 mid_pcie_level_enabled
= (lowest_pcie_level_enabled
+ 1+ count
) <
2013 hightest_pcie_level_enabled
?
2014 (lowest_pcie_level_enabled
+ 1 + count
) :
2015 hightest_pcie_level_enabled
;
2017 /* set pcieDpmLevel to hightest_pcie_level_enabled */
2018 for(i
= 2; i
< dpm_table
->sclk_table
.count
; i
++)
2019 levels
[i
].pcieDpmLevel
= hightest_pcie_level_enabled
;
2021 /* set pcieDpmLevel to lowest_pcie_level_enabled */
2022 levels
[0].pcieDpmLevel
= lowest_pcie_level_enabled
;
2024 /* set pcieDpmLevel to mid_pcie_level_enabled */
2025 levels
[1].pcieDpmLevel
= mid_pcie_level_enabled
;
2027 /* level count will send to smc once at init smc table and never change */
2028 result
= fiji_copy_bytes_to_smc(hwmgr
->smumgr
, array
, (uint8_t *)levels
,
2029 (uint32_t)array_size
, data
->sram_end
);
2035 * MCLK Frequency Ratio
2036 * SEQ_CG_RESP Bit[31:24] - 0x0
2037 * Bit[27:24] \96 DDR3 Frequency ratio
2038 * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz
2039 * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz
2040 * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz
2041 * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz
2042 * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz
2043 * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz
2044 * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz
2045 * 400 < 0x7 <= 450MHz, 800 < 0xF
2047 static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock
)
2049 if (mem_clock
<= 10000) return 0x0;
2050 if (mem_clock
<= 15000) return 0x1;
2051 if (mem_clock
<= 20000) return 0x2;
2052 if (mem_clock
<= 25000) return 0x3;
2053 if (mem_clock
<= 30000) return 0x4;
2054 if (mem_clock
<= 35000) return 0x5;
2055 if (mem_clock
<= 40000) return 0x6;
2056 if (mem_clock
<= 45000) return 0x7;
2057 if (mem_clock
<= 50000) return 0x8;
2058 if (mem_clock
<= 55000) return 0x9;
2059 if (mem_clock
<= 60000) return 0xa;
2060 if (mem_clock
<= 65000) return 0xb;
2061 if (mem_clock
<= 70000) return 0xc;
2062 if (mem_clock
<= 75000) return 0xd;
2063 if (mem_clock
<= 80000) return 0xe;
2064 /* mem_clock > 800MHz */
2069 * Populates the SMC MCLK structure using the provided memory clock
2071 * @param hwmgr the address of the hardware manager
2072 * @param clock the memory clock to use to populate the structure
2073 * @param sclk the SMC SCLK structure to be populated
2075 static int fiji_calculate_mclk_params(struct pp_hwmgr
*hwmgr
,
2076 uint32_t clock
, struct SMU73_Discrete_MemoryLevel
*mclk
)
2078 struct pp_atomctrl_memory_clock_param mem_param
;
2081 result
= atomctrl_get_memory_pll_dividers_vi(hwmgr
, clock
, &mem_param
);
2082 PP_ASSERT_WITH_CODE((0 == result
),
2083 "Failed to get Memory PLL Dividers.",);
2085 /* Save the result data to outpupt memory level structure */
2086 mclk
->MclkFrequency
= clock
;
2087 mclk
->MclkDivider
= (uint8_t)mem_param
.mpll_post_divider
;
2088 mclk
->FreqRange
= fiji_get_mclk_frequency_ratio(clock
);
2093 static int fiji_populate_single_memory_level(struct pp_hwmgr
*hwmgr
,
2094 uint32_t clock
, struct SMU73_Discrete_MemoryLevel
*mem_level
)
2096 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2097 struct phm_ppt_v1_information
*table_info
=
2098 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2101 if (table_info
->vdd_dep_on_mclk
) {
2102 result
= fiji_get_dependency_volt_by_clk(hwmgr
,
2103 table_info
->vdd_dep_on_mclk
, clock
,
2104 &mem_level
->MinVoltage
, &mem_level
->MinMvdd
);
2105 PP_ASSERT_WITH_CODE((0 == result
),
2106 "can not find MinVddc voltage value from memory "
2107 "VDDC voltage dependency table", return result
);
2110 mem_level
->EnabledForThrottle
= 1;
2111 mem_level
->EnabledForActivity
= 0;
2112 mem_level
->UpHyst
= 0;
2113 mem_level
->DownHyst
= 100;
2114 mem_level
->VoltageDownHyst
= 0;
2115 mem_level
->ActivityLevel
= (uint16_t)data
->mclk_activity_target
;
2116 mem_level
->StutterEnable
= false;
2118 mem_level
->DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
2120 /* enable stutter mode if all the follow condition applied
2121 * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
2122 * &(data->DisplayTiming.numExistingDisplays));
2124 data
->display_timing
.num_existing_displays
= 1;
2126 if ((data
->mclk_stutter_mode_threshold
) &&
2127 (clock
<= data
->mclk_stutter_mode_threshold
) &&
2128 (!data
->is_uvd_enabled
) &&
2129 (PHM_READ_FIELD(hwmgr
->device
, DPG_PIPE_STUTTER_CONTROL
,
2130 STUTTER_ENABLE
) & 0x1))
2131 mem_level
->StutterEnable
= true;
2133 result
= fiji_calculate_mclk_params(hwmgr
, clock
, mem_level
);
2135 CONVERT_FROM_HOST_TO_SMC_UL(mem_level
->MinMvdd
);
2136 CONVERT_FROM_HOST_TO_SMC_UL(mem_level
->MclkFrequency
);
2137 CONVERT_FROM_HOST_TO_SMC_US(mem_level
->ActivityLevel
);
2138 CONVERT_FROM_HOST_TO_SMC_UL(mem_level
->MinVoltage
);
2144 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2146 * @param hwmgr the address of the hardware manager
2148 static int fiji_populate_all_memory_levels(struct pp_hwmgr
*hwmgr
)
2150 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2151 struct fiji_dpm_table
*dpm_table
= &data
->dpm_table
;
2153 /* populate MCLK dpm table to SMU7 */
2154 uint32_t array
= data
->dpm_table_start
+
2155 offsetof(SMU73_Discrete_DpmTable
, MemoryLevel
);
2156 uint32_t array_size
= sizeof(SMU73_Discrete_MemoryLevel
) *
2157 SMU73_MAX_LEVELS_MEMORY
;
2158 struct SMU73_Discrete_MemoryLevel
*levels
=
2159 data
->smc_state_table
.MemoryLevel
;
2162 for (i
= 0; i
< dpm_table
->mclk_table
.count
; i
++) {
2163 PP_ASSERT_WITH_CODE((0 != dpm_table
->mclk_table
.dpm_levels
[i
].value
),
2164 "can not populate memory level as memory clock is zero",
2166 result
= fiji_populate_single_memory_level(hwmgr
,
2167 dpm_table
->mclk_table
.dpm_levels
[i
].value
,
2173 /* Only enable level 0 for now. */
2174 levels
[0].EnabledForActivity
= 1;
2176 /* in order to prevent MC activity from stutter mode to push DPM up.
2177 * the UVD change complements this by putting the MCLK in
2178 * a higher state by default such that we are not effected by
2179 * up threshold or and MCLK DPM latency.
2181 levels
[0].ActivityLevel
= (uint16_t)data
->mclk_dpm0_activity_target
;
2182 CONVERT_FROM_HOST_TO_SMC_US(levels
[0].ActivityLevel
);
2184 data
->smc_state_table
.MemoryDpmLevelCount
=
2185 (uint8_t)dpm_table
->mclk_table
.count
;
2186 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
=
2187 fiji_get_dpm_level_enable_mask_value(&dpm_table
->mclk_table
);
2188 /* set highest level watermark to high */
2189 levels
[dpm_table
->mclk_table
.count
- 1].DisplayWatermark
=
2190 PPSMC_DISPLAY_WATERMARK_HIGH
;
2192 /* level count will send to smc once at init smc table and never change */
2193 result
= fiji_copy_bytes_to_smc(hwmgr
->smumgr
, array
, (uint8_t *)levels
,
2194 (uint32_t)array_size
, data
->sram_end
);
2200 * Populates the SMC MVDD structure using the provided memory clock.
2202 * @param hwmgr the address of the hardware manager
2203 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2204 * @param voltage the SMC VOLTAGE structure to be populated
2206 int fiji_populate_mvdd_value(struct pp_hwmgr
*hwmgr
,
2207 uint32_t mclk
, SMIO_Pattern
*smio_pat
)
2209 const struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2210 struct phm_ppt_v1_information
*table_info
=
2211 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2214 if (FIJI_VOLTAGE_CONTROL_NONE
!= data
->mvdd_control
) {
2215 /* find mvdd value which clock is more than request */
2216 for (i
= 0; i
< table_info
->vdd_dep_on_mclk
->count
; i
++) {
2217 if (mclk
<= table_info
->vdd_dep_on_mclk
->entries
[i
].clk
) {
2218 smio_pat
->Voltage
= data
->mvdd_voltage_table
.entries
[i
].value
;
2222 PP_ASSERT_WITH_CODE(i
< table_info
->vdd_dep_on_mclk
->count
,
2223 "MVDD Voltage is outside the supported range.",
2231 static int fiji_populate_smc_acpi_level(struct pp_hwmgr
*hwmgr
,
2232 SMU73_Discrete_DpmTable
*table
)
2235 const struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2236 struct phm_ppt_v1_information
*table_info
=
2237 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2238 struct pp_atomctrl_clock_dividers_vi dividers
;
2239 SMIO_Pattern vol_level
;
2242 uint32_t spll_func_cntl
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL
;
2243 uint32_t spll_func_cntl_2
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_2
;
2245 table
->ACPILevel
.Flags
&= ~PPSMC_SWSTATE_FLAG_DC
;
2247 if (!data
->sclk_dpm_key_disabled
) {
2248 /* Get MinVoltage and Frequency from DPM0,
2249 * already converted to SMC_UL */
2250 table
->ACPILevel
.SclkFrequency
=
2251 data
->dpm_table
.sclk_table
.dpm_levels
[0].value
;
2252 result
= fiji_get_dependency_volt_by_clk(hwmgr
,
2253 table_info
->vdd_dep_on_sclk
,
2254 table
->ACPILevel
.SclkFrequency
,
2255 &table
->ACPILevel
.MinVoltage
, &mvdd
);
2256 PP_ASSERT_WITH_CODE((0 == result
),
2257 "Cannot find ACPI VDDC voltage value "
2258 "in Clock Dependency Table",);
2260 table
->ACPILevel
.SclkFrequency
=
2261 data
->vbios_boot_state
.sclk_bootup_value
;
2262 table
->ACPILevel
.MinVoltage
=
2263 data
->vbios_boot_state
.vddc_bootup_value
* VOLTAGE_SCALE
;
2266 /* get the engine clock dividers for this clock value */
2267 result
= atomctrl_get_engine_pll_dividers_vi(hwmgr
,
2268 table
->ACPILevel
.SclkFrequency
, ÷rs
);
2269 PP_ASSERT_WITH_CODE(result
== 0,
2270 "Error retrieving Engine Clock dividers from VBIOS.",
2273 table
->ACPILevel
.SclkDid
= (uint8_t)dividers
.pll_post_divider
;
2274 table
->ACPILevel
.DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
2275 table
->ACPILevel
.DeepSleepDivId
= 0;
2277 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
, CG_SPLL_FUNC_CNTL
,
2279 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
, CG_SPLL_FUNC_CNTL
,
2281 spll_func_cntl_2
= PHM_SET_FIELD(spll_func_cntl_2
, CG_SPLL_FUNC_CNTL_2
,
2284 table
->ACPILevel
.CgSpllFuncCntl
= spll_func_cntl
;
2285 table
->ACPILevel
.CgSpllFuncCntl2
= spll_func_cntl_2
;
2286 table
->ACPILevel
.CgSpllFuncCntl3
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
;
2287 table
->ACPILevel
.CgSpllFuncCntl4
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
;
2288 table
->ACPILevel
.SpllSpreadSpectrum
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
;
2289 table
->ACPILevel
.SpllSpreadSpectrum2
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
;
2290 table
->ACPILevel
.CcPwrDynRm
= 0;
2291 table
->ACPILevel
.CcPwrDynRm1
= 0;
2293 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.Flags
);
2294 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SclkFrequency
);
2295 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.MinVoltage
);
2296 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl
);
2297 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl2
);
2298 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl3
);
2299 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl4
);
2300 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SpllSpreadSpectrum
);
2301 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SpllSpreadSpectrum2
);
2302 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CcPwrDynRm
);
2303 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CcPwrDynRm1
);
2305 if (!data
->mclk_dpm_key_disabled
) {
2306 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
2307 table
->MemoryACPILevel
.MclkFrequency
=
2308 data
->dpm_table
.mclk_table
.dpm_levels
[0].value
;
2309 result
= fiji_get_dependency_volt_by_clk(hwmgr
,
2310 table_info
->vdd_dep_on_mclk
,
2311 table
->MemoryACPILevel
.MclkFrequency
,
2312 &table
->MemoryACPILevel
.MinVoltage
, &mvdd
);
2313 PP_ASSERT_WITH_CODE((0 == result
),
2314 "Cannot find ACPI VDDCI voltage value "
2315 "in Clock Dependency Table",);
2317 table
->MemoryACPILevel
.MclkFrequency
=
2318 data
->vbios_boot_state
.mclk_bootup_value
;
2319 table
->MemoryACPILevel
.MinVoltage
=
2320 data
->vbios_boot_state
.vddci_bootup_value
* VOLTAGE_SCALE
;
2324 if ((FIJI_VOLTAGE_CONTROL_NONE
== data
->mvdd_control
) ||
2325 (data
->mclk_dpm_key_disabled
))
2326 us_mvdd
= data
->vbios_boot_state
.mvdd_bootup_value
;
2328 if (!fiji_populate_mvdd_value(hwmgr
,
2329 data
->dpm_table
.mclk_table
.dpm_levels
[0].value
,
2331 us_mvdd
= vol_level
.Voltage
;
2334 table
->MemoryACPILevel
.MinMvdd
=
2335 PP_HOST_TO_SMC_UL(us_mvdd
* VOLTAGE_SCALE
);
2337 table
->MemoryACPILevel
.EnabledForThrottle
= 0;
2338 table
->MemoryACPILevel
.EnabledForActivity
= 0;
2339 table
->MemoryACPILevel
.UpHyst
= 0;
2340 table
->MemoryACPILevel
.DownHyst
= 100;
2341 table
->MemoryACPILevel
.VoltageDownHyst
= 0;
2342 table
->MemoryACPILevel
.ActivityLevel
=
2343 PP_HOST_TO_SMC_US((uint16_t)data
->mclk_activity_target
);
2345 table
->MemoryACPILevel
.StutterEnable
= false;
2346 CONVERT_FROM_HOST_TO_SMC_UL(table
->MemoryACPILevel
.MclkFrequency
);
2347 CONVERT_FROM_HOST_TO_SMC_UL(table
->MemoryACPILevel
.MinVoltage
);
2352 static int fiji_populate_smc_vce_level(struct pp_hwmgr
*hwmgr
,
2353 SMU73_Discrete_DpmTable
*table
)
2355 int result
= -EINVAL
;
2357 struct pp_atomctrl_clock_dividers_vi dividers
;
2358 struct phm_ppt_v1_information
*table_info
=
2359 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2360 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
2361 table_info
->mm_dep_table
;
2362 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2364 table
->VceLevelCount
= (uint8_t)(mm_table
->count
);
2365 table
->VceBootLevel
= 0;
2367 for(count
= 0; count
< table
->VceLevelCount
; count
++) {
2368 table
->VceLevel
[count
].Frequency
= mm_table
->entries
[count
].eclk
;
2369 table
->VceLevel
[count
].MinVoltage
|=
2370 (mm_table
->entries
[count
].vddc
* VOLTAGE_SCALE
) << VDDC_SHIFT
;
2371 table
->VceLevel
[count
].MinVoltage
|=
2372 ((mm_table
->entries
[count
].vddc
- data
->vddc_vddci_delta
) *
2373 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
2374 table
->VceLevel
[count
].MinVoltage
|= 1 << PHASES_SHIFT
;
2376 /*retrieve divider value for VBIOS */
2377 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
2378 table
->VceLevel
[count
].Frequency
, ÷rs
);
2379 PP_ASSERT_WITH_CODE((0 == result
),
2380 "can not find divide id for VCE engine clock",
2383 table
->VceLevel
[count
].Divider
= (uint8_t)dividers
.pll_post_divider
;
2385 CONVERT_FROM_HOST_TO_SMC_UL(table
->VceLevel
[count
].Frequency
);
2386 CONVERT_FROM_HOST_TO_SMC_UL(table
->VceLevel
[count
].MinVoltage
);
2391 static int fiji_populate_smc_acp_level(struct pp_hwmgr
*hwmgr
,
2392 SMU73_Discrete_DpmTable
*table
)
2394 int result
= -EINVAL
;
2396 struct pp_atomctrl_clock_dividers_vi dividers
;
2397 struct phm_ppt_v1_information
*table_info
=
2398 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2399 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
2400 table_info
->mm_dep_table
;
2401 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2403 table
->AcpLevelCount
= (uint8_t)(mm_table
->count
);
2404 table
->AcpBootLevel
= 0;
2406 for (count
= 0; count
< table
->AcpLevelCount
; count
++) {
2407 table
->AcpLevel
[count
].Frequency
= mm_table
->entries
[count
].aclk
;
2408 table
->AcpLevel
[count
].MinVoltage
|= (mm_table
->entries
[count
].vddc
*
2409 VOLTAGE_SCALE
) << VDDC_SHIFT
;
2410 table
->AcpLevel
[count
].MinVoltage
|= ((mm_table
->entries
[count
].vddc
-
2411 data
->vddc_vddci_delta
) * VOLTAGE_SCALE
) << VDDCI_SHIFT
;
2412 table
->AcpLevel
[count
].MinVoltage
|= 1 << PHASES_SHIFT
;
2414 /* retrieve divider value for VBIOS */
2415 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
2416 table
->AcpLevel
[count
].Frequency
, ÷rs
);
2417 PP_ASSERT_WITH_CODE((0 == result
),
2418 "can not find divide id for engine clock", return result
);
2420 table
->AcpLevel
[count
].Divider
= (uint8_t)dividers
.pll_post_divider
;
2422 CONVERT_FROM_HOST_TO_SMC_UL(table
->AcpLevel
[count
].Frequency
);
2423 CONVERT_FROM_HOST_TO_SMC_UL(table
->AcpLevel
[count
].MinVoltage
);
2428 static int fiji_populate_smc_samu_level(struct pp_hwmgr
*hwmgr
,
2429 SMU73_Discrete_DpmTable
*table
)
2431 int result
= -EINVAL
;
2433 struct pp_atomctrl_clock_dividers_vi dividers
;
2434 struct phm_ppt_v1_information
*table_info
=
2435 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2436 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
2437 table_info
->mm_dep_table
;
2438 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2440 table
->SamuBootLevel
= 0;
2441 table
->SamuLevelCount
= (uint8_t)(mm_table
->count
);
2443 for (count
= 0; count
< table
->SamuLevelCount
; count
++) {
2444 /* not sure whether we need evclk or not */
2445 table
->SamuLevel
[count
].Frequency
= mm_table
->entries
[count
].samclock
;
2446 table
->SamuLevel
[count
].MinVoltage
|= (mm_table
->entries
[count
].vddc
*
2447 VOLTAGE_SCALE
) << VDDC_SHIFT
;
2448 table
->SamuLevel
[count
].MinVoltage
|= ((mm_table
->entries
[count
].vddc
-
2449 data
->vddc_vddci_delta
) * VOLTAGE_SCALE
) << VDDCI_SHIFT
;
2450 table
->SamuLevel
[count
].MinVoltage
|= 1 << PHASES_SHIFT
;
2452 /* retrieve divider value for VBIOS */
2453 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
2454 table
->SamuLevel
[count
].Frequency
, ÷rs
);
2455 PP_ASSERT_WITH_CODE((0 == result
),
2456 "can not find divide id for samu clock", return result
);
2458 table
->SamuLevel
[count
].Divider
= (uint8_t)dividers
.pll_post_divider
;
2460 CONVERT_FROM_HOST_TO_SMC_UL(table
->SamuLevel
[count
].Frequency
);
2461 CONVERT_FROM_HOST_TO_SMC_UL(table
->SamuLevel
[count
].MinVoltage
);
2466 static int fiji_populate_memory_timing_parameters(struct pp_hwmgr
*hwmgr
,
2467 int32_t eng_clock
, int32_t mem_clock
,
2468 struct SMU73_Discrete_MCArbDramTimingTableEntry
*arb_regs
)
2470 uint32_t dram_timing
;
2471 uint32_t dram_timing2
;
2473 ULONG state
, trrds
, trrdl
;
2476 result
= atomctrl_set_engine_dram_timings_rv770(hwmgr
,
2477 eng_clock
, mem_clock
);
2478 PP_ASSERT_WITH_CODE(result
== 0,
2479 "Error calling VBIOS to set DRAM_TIMING.", return result
);
2481 dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
);
2482 dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
);
2483 burstTime
= cgs_read_register(hwmgr
->device
, mmMC_ARB_BURST_TIME
);
2485 state
= PHM_GET_FIELD(burstTime
, MC_ARB_BURST_TIME
, STATE0
);
2486 trrds
= PHM_GET_FIELD(burstTime
, MC_ARB_BURST_TIME
, TRRDS0
);
2487 trrdl
= PHM_GET_FIELD(burstTime
, MC_ARB_BURST_TIME
, TRRDL0
);
2489 arb_regs
->McArbDramTiming
= PP_HOST_TO_SMC_UL(dram_timing
);
2490 arb_regs
->McArbDramTiming2
= PP_HOST_TO_SMC_UL(dram_timing2
);
2491 arb_regs
->McArbBurstTime
= (uint8_t)burstTime
;
2492 arb_regs
->TRRDS
= (uint8_t)trrds
;
2493 arb_regs
->TRRDL
= (uint8_t)trrdl
;
2498 static int fiji_program_memory_timing_parameters(struct pp_hwmgr
*hwmgr
)
2500 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2501 struct SMU73_Discrete_MCArbDramTimingTable arb_regs
;
2505 for (i
= 0; i
< data
->dpm_table
.sclk_table
.count
; i
++) {
2506 for (j
= 0; j
< data
->dpm_table
.mclk_table
.count
; j
++) {
2507 result
= fiji_populate_memory_timing_parameters(hwmgr
,
2508 data
->dpm_table
.sclk_table
.dpm_levels
[i
].value
,
2509 data
->dpm_table
.mclk_table
.dpm_levels
[j
].value
,
2510 &arb_regs
.entries
[i
][j
]);
2517 result
= fiji_copy_bytes_to_smc(
2519 data
->arb_table_start
,
2520 (uint8_t *)&arb_regs
,
2521 sizeof(SMU73_Discrete_MCArbDramTimingTable
),
2526 static int fiji_populate_smc_uvd_level(struct pp_hwmgr
*hwmgr
,
2527 struct SMU73_Discrete_DpmTable
*table
)
2529 int result
= -EINVAL
;
2531 struct pp_atomctrl_clock_dividers_vi dividers
;
2532 struct phm_ppt_v1_information
*table_info
=
2533 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2534 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
2535 table_info
->mm_dep_table
;
2536 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2538 table
->UvdLevelCount
= (uint8_t)(mm_table
->count
);
2539 table
->UvdBootLevel
= 0;
2541 for (count
= 0; count
< table
->UvdLevelCount
; count
++) {
2542 table
->UvdLevel
[count
].VclkFrequency
= mm_table
->entries
[count
].vclk
;
2543 table
->UvdLevel
[count
].DclkFrequency
= mm_table
->entries
[count
].dclk
;
2544 table
->UvdLevel
[count
].MinVoltage
|= (mm_table
->entries
[count
].vddc
*
2545 VOLTAGE_SCALE
) << VDDC_SHIFT
;
2546 table
->UvdLevel
[count
].MinVoltage
|= ((mm_table
->entries
[count
].vddc
-
2547 data
->vddc_vddci_delta
) * VOLTAGE_SCALE
) << VDDCI_SHIFT
;
2548 table
->UvdLevel
[count
].MinVoltage
|= 1 << PHASES_SHIFT
;
2550 /* retrieve divider value for VBIOS */
2551 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
2552 table
->UvdLevel
[count
].VclkFrequency
, ÷rs
);
2553 PP_ASSERT_WITH_CODE((0 == result
),
2554 "can not find divide id for Vclk clock", return result
);
2556 table
->UvdLevel
[count
].VclkDivider
= (uint8_t)dividers
.pll_post_divider
;
2558 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
2559 table
->UvdLevel
[count
].DclkFrequency
, ÷rs
);
2560 PP_ASSERT_WITH_CODE((0 == result
),
2561 "can not find divide id for Dclk clock", return result
);
2563 table
->UvdLevel
[count
].DclkDivider
= (uint8_t)dividers
.pll_post_divider
;
2565 CONVERT_FROM_HOST_TO_SMC_UL(table
->UvdLevel
[count
].VclkFrequency
);
2566 CONVERT_FROM_HOST_TO_SMC_UL(table
->UvdLevel
[count
].DclkFrequency
);
2567 CONVERT_FROM_HOST_TO_SMC_UL(table
->UvdLevel
[count
].MinVoltage
);
2573 static int fiji_find_boot_level(struct fiji_single_dpm_table
*table
,
2574 uint32_t value
, uint32_t *boot_level
)
2576 int result
= -EINVAL
;
2579 for (i
= 0; i
< table
->count
; i
++) {
2580 if (value
== table
->dpm_levels
[i
].value
) {
2588 static int fiji_populate_smc_boot_level(struct pp_hwmgr
*hwmgr
,
2589 struct SMU73_Discrete_DpmTable
*table
)
2592 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2594 table
->GraphicsBootLevel
= 0;
2595 table
->MemoryBootLevel
= 0;
2597 /* find boot level from dpm table */
2598 result
= fiji_find_boot_level(&(data
->dpm_table
.sclk_table
),
2599 data
->vbios_boot_state
.sclk_bootup_value
,
2600 (uint32_t *)&(table
->GraphicsBootLevel
));
2602 result
= fiji_find_boot_level(&(data
->dpm_table
.mclk_table
),
2603 data
->vbios_boot_state
.mclk_bootup_value
,
2604 (uint32_t *)&(table
->MemoryBootLevel
));
2606 table
->BootVddc
= data
->vbios_boot_state
.vddc_bootup_value
*
2608 table
->BootVddci
= data
->vbios_boot_state
.vddci_bootup_value
*
2610 table
->BootMVdd
= data
->vbios_boot_state
.mvdd_bootup_value
*
2613 CONVERT_FROM_HOST_TO_SMC_US(table
->BootVddc
);
2614 CONVERT_FROM_HOST_TO_SMC_US(table
->BootVddci
);
2615 CONVERT_FROM_HOST_TO_SMC_US(table
->BootMVdd
);
2620 static int fiji_populate_smc_initailial_state(struct pp_hwmgr
*hwmgr
)
2622 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2623 struct phm_ppt_v1_information
*table_info
=
2624 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2625 uint8_t count
, level
;
2627 count
= (uint8_t)(table_info
->vdd_dep_on_sclk
->count
);
2628 for (level
= 0; level
< count
; level
++) {
2629 if(table_info
->vdd_dep_on_sclk
->entries
[level
].clk
>=
2630 data
->vbios_boot_state
.sclk_bootup_value
) {
2631 data
->smc_state_table
.GraphicsBootLevel
= level
;
2636 count
= (uint8_t)(table_info
->vdd_dep_on_mclk
->count
);
2637 for (level
= 0; level
< count
; level
++) {
2638 if(table_info
->vdd_dep_on_mclk
->entries
[level
].clk
>=
2639 data
->vbios_boot_state
.mclk_bootup_value
) {
2640 data
->smc_state_table
.MemoryBootLevel
= level
;
2648 static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr
*hwmgr
)
2650 uint32_t ro
, efuse
, efuse2
, clock_freq
, volt_without_cks
,
2651 volt_with_cks
, value
;
2652 uint16_t clock_freq_u16
;
2653 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2654 uint8_t type
, i
, j
, cks_setting
, stretch_amount
, stretch_amount2
,
2656 struct phm_ppt_v1_information
*table_info
=
2657 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2658 struct phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
=
2659 table_info
->vdd_dep_on_sclk
;
2661 stretch_amount
= (uint8_t)table_info
->cac_dtp_table
->usClockStretchAmount
;
2663 /* Read SMU_Eefuse to read and calculate RO and determine
2664 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
2666 efuse
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2667 ixSMU_EFUSE_0
+ (146 * 4));
2668 efuse2
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2669 ixSMU_EFUSE_0
+ (148 * 4));
2670 efuse
&= 0xFF000000;
2671 efuse
= efuse
>> 24;
2675 ro
= (2300 - 1350) * efuse
/ 255 + 1350;
2677 ro
= (2500 - 1000) * efuse
/ 255 + 1000;
2684 /* Populate Stretch amount */
2685 data
->smc_state_table
.ClockStretcherAmount
= stretch_amount
;
2687 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
2688 for (i
= 0; i
< sclk_table
->count
; i
++) {
2689 data
->smc_state_table
.Sclk_CKS_masterEn0_7
|=
2690 sclk_table
->entries
[i
].cks_enable
<< i
;
2691 volt_without_cks
= (uint32_t)((14041 *
2692 (sclk_table
->entries
[i
].clk
/100) / 10000 + 3571 + 75 - ro
) * 1000 /
2693 (4026 - (13924 * (sclk_table
->entries
[i
].clk
/100) / 10000)));
2694 volt_with_cks
= (uint32_t)((13946 *
2695 (sclk_table
->entries
[i
].clk
/100) / 10000 + 3320 + 45 - ro
) * 1000 /
2696 (3664 - (11454 * (sclk_table
->entries
[i
].clk
/100) / 10000)));
2697 if (volt_without_cks
>= volt_with_cks
)
2698 volt_offset
= (uint8_t)(((volt_without_cks
- volt_with_cks
+
2699 sclk_table
->entries
[i
].cks_voffset
) * 100 / 625) + 1);
2700 data
->smc_state_table
.Sclk_voltageOffset
[i
] = volt_offset
;
2703 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, PWR_CKS_ENABLE
,
2704 STRETCH_ENABLE
, 0x0);
2705 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, PWR_CKS_ENABLE
,
2707 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, PWR_CKS_ENABLE
,
2709 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, PWR_CKS_ENABLE
,
2712 /* Populate CKS Lookup Table */
2713 if (stretch_amount
== 1 || stretch_amount
== 2 || stretch_amount
== 5)
2714 stretch_amount2
= 0;
2715 else if (stretch_amount
== 3 || stretch_amount
== 4)
2716 stretch_amount2
= 1;
2718 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2719 PHM_PlatformCaps_ClockStretcher
);
2720 PP_ASSERT_WITH_CODE(false,
2721 "Stretch Amount in PPTable not supported\n",
2725 value
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2727 value
&= 0xFFC2FF87;
2728 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].minFreq
=
2729 fiji_clock_stretcher_lookup_table
[stretch_amount2
][0];
2730 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].maxFreq
=
2731 fiji_clock_stretcher_lookup_table
[stretch_amount2
][1];
2732 clock_freq_u16
= (uint16_t)(PP_SMC_TO_HOST_UL(data
->smc_state_table
.
2733 GraphicsLevel
[data
->smc_state_table
.GraphicsDpmLevelCount
- 1].
2734 SclkFrequency
) / 100);
2735 if (fiji_clock_stretcher_lookup_table
[stretch_amount2
][0] <
2737 fiji_clock_stretcher_lookup_table
[stretch_amount2
][1] >
2739 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2740 value
|= (fiji_clock_stretcher_lookup_table
[stretch_amount2
][3]) << 16;
2741 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2742 value
|= (fiji_clock_stretcher_lookup_table
[stretch_amount2
][2]) << 18;
2743 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2744 value
|= (fiji_clock_stretch_amount_conversion
2745 [fiji_clock_stretcher_lookup_table
[stretch_amount2
][3]]
2746 [stretch_amount
]) << 3;
2748 CONVERT_FROM_HOST_TO_SMC_US(data
->smc_state_table
.CKS_LOOKUPTable
.
2749 CKS_LOOKUPTableEntry
[0].minFreq
);
2750 CONVERT_FROM_HOST_TO_SMC_US(data
->smc_state_table
.CKS_LOOKUPTable
.
2751 CKS_LOOKUPTableEntry
[0].maxFreq
);
2752 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].setting
=
2753 fiji_clock_stretcher_lookup_table
[stretch_amount2
][2] & 0x7F;
2754 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].setting
|=
2755 (fiji_clock_stretcher_lookup_table
[stretch_amount2
][3]) << 7;
2757 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2758 ixPWR_CKS_CNTL
, value
);
2760 /* Populate DDT Lookup Table */
2761 for (i
= 0; i
< 4; i
++) {
2762 /* Assign the minimum and maximum VID stored
2763 * in the last row of Clock Stretcher Voltage Table.
2765 data
->smc_state_table
.ClockStretcherDataTable
.
2766 ClockStretcherDataTableEntry
[i
].minVID
=
2767 (uint8_t) fiji_clock_stretcher_ddt_table
[type
][i
][2];
2768 data
->smc_state_table
.ClockStretcherDataTable
.
2769 ClockStretcherDataTableEntry
[i
].maxVID
=
2770 (uint8_t) fiji_clock_stretcher_ddt_table
[type
][i
][3];
2771 /* Loop through each SCLK and check the frequency
2772 * to see if it lies within the frequency for clock stretcher.
2774 for (j
= 0; j
< data
->smc_state_table
.GraphicsDpmLevelCount
; j
++) {
2776 clock_freq
= PP_SMC_TO_HOST_UL(
2777 data
->smc_state_table
.GraphicsLevel
[j
].SclkFrequency
);
2778 /* Check the allowed frequency against the sclk level[j].
2779 * Sclk's endianness has already been converted,
2780 * and it's in 10Khz unit,
2781 * as opposed to Data table, which is in Mhz unit.
2784 (fiji_clock_stretcher_ddt_table
[type
][i
][0]) * 100) {
2787 (fiji_clock_stretcher_ddt_table
[type
][i
][1]) * 100)
2790 data
->smc_state_table
.ClockStretcherDataTable
.
2791 ClockStretcherDataTableEntry
[i
].setting
|= cks_setting
<< (j
* 2);
2793 CONVERT_FROM_HOST_TO_SMC_US(data
->smc_state_table
.
2794 ClockStretcherDataTable
.
2795 ClockStretcherDataTableEntry
[i
].setting
);
2798 value
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixPWR_CKS_CNTL
);
2799 value
&= 0xFFFFFFFE;
2800 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixPWR_CKS_CNTL
, value
);
2806 * Populates the SMC VRConfig field in DPM table.
2808 * @param hwmgr the address of the hardware manager
2809 * @param table the SMC DPM table structure to be populated
2812 static int fiji_populate_vr_config(struct pp_hwmgr
*hwmgr
,
2813 struct SMU73_Discrete_DpmTable
*table
)
2815 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2818 config
= VR_MERGED_WITH_VDDC
;
2819 table
->VRConfig
|= (config
<< VRCONF_VDDGFX_SHIFT
);
2821 /* Set Vddc Voltage Controller */
2822 if(FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
) {
2823 config
= VR_SVI2_PLANE_1
;
2824 table
->VRConfig
|= config
;
2826 PP_ASSERT_WITH_CODE(false,
2827 "VDDC should be on SVI2 control in merged mode!",);
2829 /* Set Vddci Voltage Controller */
2830 if(FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->vddci_control
) {
2831 config
= VR_SVI2_PLANE_2
; /* only in merged mode */
2832 table
->VRConfig
|= (config
<< VRCONF_VDDCI_SHIFT
);
2833 } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO
== data
->vddci_control
) {
2834 config
= VR_SMIO_PATTERN_1
;
2835 table
->VRConfig
|= (config
<< VRCONF_VDDCI_SHIFT
);
2837 config
= VR_STATIC_VOLTAGE
;
2838 table
->VRConfig
|= (config
<< VRCONF_VDDCI_SHIFT
);
2840 /* Set Mvdd Voltage Controller */
2841 if(FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->mvdd_control
) {
2842 config
= VR_SVI2_PLANE_2
;
2843 table
->VRConfig
|= (config
<< VRCONF_MVDD_SHIFT
);
2844 } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO
== data
->mvdd_control
) {
2845 config
= VR_SMIO_PATTERN_2
;
2846 table
->VRConfig
|= (config
<< VRCONF_MVDD_SHIFT
);
2848 config
= VR_STATIC_VOLTAGE
;
2849 table
->VRConfig
|= (config
<< VRCONF_MVDD_SHIFT
);
2856 * Initializes the SMC table and uploads it
2858 * @param hwmgr the address of the powerplay hardware manager.
2859 * @param pInput the pointer to input data (PowerState)
2862 static int fiji_init_smc_table(struct pp_hwmgr
*hwmgr
)
2865 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2866 struct phm_ppt_v1_information
*table_info
=
2867 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2868 struct SMU73_Discrete_DpmTable
*table
= &(data
->smc_state_table
);
2869 const struct fiji_ulv_parm
*ulv
= &(data
->ulv
);
2871 struct pp_atomctrl_gpio_pin_assignment gpio_pin
;
2873 result
= fiji_setup_default_dpm_tables(hwmgr
);
2874 PP_ASSERT_WITH_CODE(0 == result
,
2875 "Failed to setup default DPM tables!", return result
);
2877 if(FIJI_VOLTAGE_CONTROL_NONE
!= data
->voltage_control
)
2878 fiji_populate_smc_voltage_tables(hwmgr
, table
);
2880 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2881 PHM_PlatformCaps_AutomaticDCTransition
))
2882 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GPIO_DC
;
2884 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2885 PHM_PlatformCaps_StepVddc
))
2886 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_STEPVDDC
;
2888 if (data
->is_memory_gddr5
)
2889 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GDDR5
;
2891 if (ulv
->ulv_supported
&& table_info
->us_ulv_voltage_offset
) {
2892 result
= fiji_populate_ulv_state(hwmgr
, table
);
2893 PP_ASSERT_WITH_CODE(0 == result
,
2894 "Failed to initialize ULV state!", return result
);
2895 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2896 ixCG_ULV_PARAMETER
, ulv
->cg_ulv_parameter
);
2899 result
= fiji_populate_smc_link_level(hwmgr
, table
);
2900 PP_ASSERT_WITH_CODE(0 == result
,
2901 "Failed to initialize Link Level!", return result
);
2903 result
= fiji_populate_all_graphic_levels(hwmgr
);
2904 PP_ASSERT_WITH_CODE(0 == result
,
2905 "Failed to initialize Graphics Level!", return result
);
2907 result
= fiji_populate_all_memory_levels(hwmgr
);
2908 PP_ASSERT_WITH_CODE(0 == result
,
2909 "Failed to initialize Memory Level!", return result
);
2911 result
= fiji_populate_smc_acpi_level(hwmgr
, table
);
2912 PP_ASSERT_WITH_CODE(0 == result
,
2913 "Failed to initialize ACPI Level!", return result
);
2915 result
= fiji_populate_smc_vce_level(hwmgr
, table
);
2916 PP_ASSERT_WITH_CODE(0 == result
,
2917 "Failed to initialize VCE Level!", return result
);
2919 result
= fiji_populate_smc_acp_level(hwmgr
, table
);
2920 PP_ASSERT_WITH_CODE(0 == result
,
2921 "Failed to initialize ACP Level!", return result
);
2923 result
= fiji_populate_smc_samu_level(hwmgr
, table
);
2924 PP_ASSERT_WITH_CODE(0 == result
,
2925 "Failed to initialize SAMU Level!", return result
);
2927 /* Since only the initial state is completely set up at this point
2928 * (the other states are just copies of the boot state) we only
2929 * need to populate the ARB settings for the initial state.
2931 result
= fiji_program_memory_timing_parameters(hwmgr
);
2932 PP_ASSERT_WITH_CODE(0 == result
,
2933 "Failed to Write ARB settings for the initial state.", return result
);
2935 result
= fiji_populate_smc_uvd_level(hwmgr
, table
);
2936 PP_ASSERT_WITH_CODE(0 == result
,
2937 "Failed to initialize UVD Level!", return result
);
2939 result
= fiji_populate_smc_boot_level(hwmgr
, table
);
2940 PP_ASSERT_WITH_CODE(0 == result
,
2941 "Failed to initialize Boot Level!", return result
);
2943 result
= fiji_populate_smc_initailial_state(hwmgr
);
2944 PP_ASSERT_WITH_CODE(0 == result
,
2945 "Failed to initialize Boot State!", return result
);
2947 result
= fiji_populate_bapm_parameters_in_dpm_table(hwmgr
);
2948 PP_ASSERT_WITH_CODE(0 == result
,
2949 "Failed to populate BAPM Parameters!", return result
);
2951 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2952 PHM_PlatformCaps_ClockStretcher
)) {
2953 result
= fiji_populate_clock_stretcher_data_table(hwmgr
);
2954 PP_ASSERT_WITH_CODE(0 == result
,
2955 "Failed to populate Clock Stretcher Data Table!",
2959 table
->GraphicsVoltageChangeEnable
= 1;
2960 table
->GraphicsThermThrottleEnable
= 1;
2961 table
->GraphicsInterval
= 1;
2962 table
->VoltageInterval
= 1;
2963 table
->ThermalInterval
= 1;
2964 table
->TemperatureLimitHigh
=
2965 table_info
->cac_dtp_table
->usTargetOperatingTemp
*
2966 FIJI_Q88_FORMAT_CONVERSION_UNIT
;
2967 table
->TemperatureLimitLow
=
2968 (table_info
->cac_dtp_table
->usTargetOperatingTemp
- 1) *
2969 FIJI_Q88_FORMAT_CONVERSION_UNIT
;
2970 table
->MemoryVoltageChangeEnable
= 1;
2971 table
->MemoryInterval
= 1;
2972 table
->VoltageResponseTime
= 0;
2973 table
->PhaseResponseTime
= 0;
2974 table
->MemoryThermThrottleEnable
= 1;
2975 table
->PCIeBootLinkLevel
= 0; /* 0:Gen1 1:Gen2 2:Gen3*/
2976 table
->PCIeGenInterval
= 1;
2978 result
= fiji_populate_vr_config(hwmgr
, table
);
2979 PP_ASSERT_WITH_CODE(0 == result
,
2980 "Failed to populate VRConfig setting!", return result
);
2982 table
->ThermGpio
= 17;
2983 table
->SclkStepSize
= 0x4000;
2985 if (atomctrl_get_pp_assign_pin(hwmgr
, VDDC_VRHOT_GPIO_PINID
, &gpio_pin
)) {
2986 table
->VRHotGpio
= gpio_pin
.uc_gpio_pin_bit_shift
;
2987 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2988 PHM_PlatformCaps_RegulatorHot
);
2990 table
->VRHotGpio
= FIJI_UNUSED_GPIO_PIN
;
2991 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2992 PHM_PlatformCaps_RegulatorHot
);
2995 if (atomctrl_get_pp_assign_pin(hwmgr
, PP_AC_DC_SWITCH_GPIO_PINID
,
2997 table
->AcDcGpio
= gpio_pin
.uc_gpio_pin_bit_shift
;
2998 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
2999 PHM_PlatformCaps_AutomaticDCTransition
);
3001 table
->AcDcGpio
= FIJI_UNUSED_GPIO_PIN
;
3002 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3003 PHM_PlatformCaps_AutomaticDCTransition
);
3006 /* Thermal Output GPIO */
3007 if (atomctrl_get_pp_assign_pin(hwmgr
, THERMAL_INT_OUTPUT_GPIO_PINID
,
3009 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3010 PHM_PlatformCaps_ThermalOutGPIO
);
3012 table
->ThermOutGpio
= gpio_pin
.uc_gpio_pin_bit_shift
;
3014 /* For porlarity read GPIOPAD_A with assigned Gpio pin
3015 * since VBIOS will program this register to set 'inactive state',
3016 * driver can then determine 'active state' from this and
3017 * program SMU with correct polarity
3019 table
->ThermOutPolarity
= (0 == (cgs_read_register(hwmgr
->device
, mmGPIOPAD_A
) &
3020 (1 << gpio_pin
.uc_gpio_pin_bit_shift
))) ? 1:0;
3021 table
->ThermOutMode
= SMU7_THERM_OUT_MODE_THERM_ONLY
;
3023 /* if required, combine VRHot/PCC with thermal out GPIO */
3024 if(phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3025 PHM_PlatformCaps_RegulatorHot
) &&
3026 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3027 PHM_PlatformCaps_CombinePCCWithThermalSignal
))
3028 table
->ThermOutMode
= SMU7_THERM_OUT_MODE_THERM_VRHOT
;
3030 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3031 PHM_PlatformCaps_ThermalOutGPIO
);
3032 table
->ThermOutGpio
= 17;
3033 table
->ThermOutPolarity
= 1;
3034 table
->ThermOutMode
= SMU7_THERM_OUT_MODE_DISABLE
;
3037 for (i
= 0; i
< SMU73_MAX_ENTRIES_SMIO
; i
++)
3038 table
->Smio
[i
] = PP_HOST_TO_SMC_UL(table
->Smio
[i
]);
3040 CONVERT_FROM_HOST_TO_SMC_UL(table
->SystemFlags
);
3041 CONVERT_FROM_HOST_TO_SMC_UL(table
->VRConfig
);
3042 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMask1
);
3043 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMask2
);
3044 CONVERT_FROM_HOST_TO_SMC_UL(table
->SclkStepSize
);
3045 CONVERT_FROM_HOST_TO_SMC_US(table
->TemperatureLimitHigh
);
3046 CONVERT_FROM_HOST_TO_SMC_US(table
->TemperatureLimitLow
);
3047 CONVERT_FROM_HOST_TO_SMC_US(table
->VoltageResponseTime
);
3048 CONVERT_FROM_HOST_TO_SMC_US(table
->PhaseResponseTime
);
3050 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3051 result
= fiji_copy_bytes_to_smc(hwmgr
->smumgr
,
3052 data
->dpm_table_start
+
3053 offsetof(SMU73_Discrete_DpmTable
, SystemFlags
),
3054 (uint8_t *)&(table
->SystemFlags
),
3055 sizeof(SMU73_Discrete_DpmTable
) - 3 * sizeof(SMU73_PIDController
),
3057 PP_ASSERT_WITH_CODE(0 == result
,
3058 "Failed to upload dpm data to SMC memory!", return result
);
3064 * Initialize the ARB DRAM timing table's index field.
3066 * @param hwmgr the address of the powerplay hardware manager.
3069 static int fiji_init_arb_table_index(struct pp_hwmgr
*hwmgr
)
3071 const struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3075 /* This is a read-modify-write on the first byte of the ARB table.
3076 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
3077 * is the field 'current'.
3078 * This solution is ugly, but we never write the whole table only
3079 * individual fields in it.
3080 * In reality this field should not be in that structure
3081 * but in a soft register.
3083 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
3084 data
->arb_table_start
, &tmp
, data
->sram_end
);
3090 tmp
|= ((uint32_t)MC_CG_ARB_FREQ_F1
) << 24;
3092 return fiji_write_smc_sram_dword(hwmgr
->smumgr
,
3093 data
->arb_table_start
, tmp
, data
->sram_end
);
3096 static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr
*hwmgr
)
3098 if(phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3099 PHM_PlatformCaps_RegulatorHot
))
3100 return smum_send_msg_to_smc(hwmgr
->smumgr
,
3101 PPSMC_MSG_EnableVRHotGPIOInterrupt
);
3106 static int fiji_enable_sclk_control(struct pp_hwmgr
*hwmgr
)
3108 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SCLK_PWRMGT_CNTL
,
3109 SCLK_PWRMGT_OFF
, 0);
3113 static int fiji_enable_ulv(struct pp_hwmgr
*hwmgr
)
3115 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3116 struct fiji_ulv_parm
*ulv
= &(data
->ulv
);
3118 if (ulv
->ulv_supported
)
3119 return smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_EnableULV
);
3124 static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr
*hwmgr
)
3126 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3127 PHM_PlatformCaps_SclkDeepSleep
)) {
3128 if (smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_MASTER_DeepSleep_ON
))
3129 PP_ASSERT_WITH_CODE(false,
3130 "Attempt to enable Master Deep Sleep switch failed!",
3133 if (smum_send_msg_to_smc(hwmgr
->smumgr
,
3134 PPSMC_MSG_MASTER_DeepSleep_OFF
)) {
3135 PP_ASSERT_WITH_CODE(false,
3136 "Attempt to disable Master Deep Sleep switch failed!",
3144 static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
3146 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3147 uint32_t val
, val0
, val2
;
3148 uint32_t i
, cpl_cntl
, cpl_threshold
, mc_threshold
;
3150 /* enable SCLK dpm */
3151 if(!data
->sclk_dpm_key_disabled
)
3152 PP_ASSERT_WITH_CODE(
3153 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_DPM_Enable
)),
3154 "Failed to enable SCLK DPM during DPM Start Function!",
3157 /* enable MCLK dpm */
3158 if(0 == data
->mclk_dpm_key_disabled
) {
3162 /* Read per MCD tile (0 - 7) */
3163 for (i
= 0; i
< 8; i
++) {
3164 PHM_WRITE_FIELD(hwmgr
->device
, MC_CONFIG_MCD
, MC_RD_ENABLE
, i
);
3165 val
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_RESERVE_0_S
) & 0xf0000000;
3166 if (0xf0000000 != val
) {
3167 /* count number of MCQ that has channel(s) enabled */
3169 /* only harvest 3 or full 4 supported */
3170 mc_threshold
= val
? 3 : 4;
3173 PP_ASSERT_WITH_CODE(0 != cpl_threshold
,
3174 "Number of MCQ is zero!", return -EINVAL
;);
3176 mc_threshold
= ((mc_threshold
& LCAC_MC0_CNTL__MC0_THRESHOLD_MASK
) <<
3177 LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT
) |
3178 LCAC_MC0_CNTL__MC0_ENABLE_MASK
;
3179 cpl_cntl
= ((cpl_threshold
& LCAC_CPL_CNTL__CPL_THRESHOLD_MASK
) <<
3180 LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT
) |
3181 LCAC_CPL_CNTL__CPL_ENABLE_MASK
;
3182 cpl_cntl
= (cpl_cntl
| (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT
));
3183 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3184 ixLCAC_MC0_CNTL
, mc_threshold
);
3185 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3186 ixLCAC_MC1_CNTL
, mc_threshold
);
3187 if (8 == cpl_threshold
) {
3188 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3189 ixLCAC_MC2_CNTL
, mc_threshold
);
3190 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3191 ixLCAC_MC3_CNTL
, mc_threshold
);
3192 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3193 ixLCAC_MC4_CNTL
, mc_threshold
);
3194 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3195 ixLCAC_MC5_CNTL
, mc_threshold
);
3196 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3197 ixLCAC_MC6_CNTL
, mc_threshold
);
3198 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3199 ixLCAC_MC7_CNTL
, mc_threshold
);
3201 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3202 ixLCAC_CPL_CNTL
, cpl_cntl
);
3206 mc_threshold
= mc_threshold
|
3207 (1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT
);
3208 cpl_cntl
= cpl_cntl
| (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT
);
3209 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3210 ixLCAC_MC0_CNTL
, mc_threshold
);
3211 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3212 ixLCAC_MC1_CNTL
, mc_threshold
);
3213 if (8 == cpl_threshold
) {
3214 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3215 ixLCAC_MC2_CNTL
, mc_threshold
);
3216 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3217 ixLCAC_MC3_CNTL
, mc_threshold
);
3218 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3219 ixLCAC_MC4_CNTL
, mc_threshold
);
3220 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3221 ixLCAC_MC5_CNTL
, mc_threshold
);
3222 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3223 ixLCAC_MC6_CNTL
, mc_threshold
);
3224 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3225 ixLCAC_MC7_CNTL
, mc_threshold
);
3227 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3228 ixLCAC_CPL_CNTL
, cpl_cntl
);
3230 /* Program CAC_EN per MCD (0-7) Tile */
3231 val0
= val
= cgs_read_register(hwmgr
->device
, mmMC_CONFIG_MCD
);
3232 val
&= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK
|
3233 MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK
|
3234 MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK
|
3235 MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK
|
3236 MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK
|
3237 MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK
|
3238 MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK
|
3239 MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK
|
3240 MC_CONFIG_MCD__MC_RD_ENABLE_MASK
);
3242 for (i
= 0; i
< 8; i
++) {
3243 /* Enable MCD i Tile read & write */
3244 val2
= (val
| (i
<< MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT
) |
3246 cgs_write_register(hwmgr
->device
, mmMC_CONFIG_MCD
, val2
);
3247 /* Enbale CAC_ON MCD i Tile */
3248 val2
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_CNTL
);
3249 val2
|= MC_SEQ_CNTL__CAC_EN_MASK
;
3250 cgs_write_register(hwmgr
->device
, mmMC_SEQ_CNTL
, val2
);
3252 /* Set MC_CONFIG_MCD back to its default setting val0 */
3253 cgs_write_register(hwmgr
->device
, mmMC_CONFIG_MCD
, val0
);
3255 PP_ASSERT_WITH_CODE(
3256 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3257 PPSMC_MSG_MCLKDPM_Enable
)),
3258 "Failed to enable MCLK DPM during DPM Start Function!",
3264 static int fiji_start_dpm(struct pp_hwmgr
*hwmgr
)
3266 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3268 /*enable general power management */
3269 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
3270 GLOBAL_PWRMGT_EN
, 1);
3271 /* enable sclk deep sleep */
3272 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SCLK_PWRMGT_CNTL
,
3274 /* prepare for PCIE DPM */
3275 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3276 data
->soft_regs_start
+ offsetof(SMU73_SoftRegisters
,
3277 VoltageChangeTimeout
), 0x1000);
3278 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__PCIE
,
3279 SWRST_COMMAND_1
, RESETLC
, 0x0);
3281 PP_ASSERT_WITH_CODE(
3282 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3283 PPSMC_MSG_Voltage_Cntl_Enable
)),
3284 "Failed to enable voltage DPM during DPM Start Function!",
3287 if (fiji_enable_sclk_mclk_dpm(hwmgr
)) {
3288 printk(KERN_ERR
"Failed to enable Sclk DPM and Mclk DPM!");
3292 /* enable PCIE dpm */
3293 if(!data
->pcie_dpm_key_disabled
) {
3294 PP_ASSERT_WITH_CODE(
3295 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3296 PPSMC_MSG_PCIeDPM_Enable
)),
3297 "Failed to enable pcie DPM during DPM Start Function!",
3304 static void fiji_set_dpm_event_sources(struct pp_hwmgr
*hwmgr
,
3308 enum DPM_EVENT_SRC src
;
3312 printk(KERN_ERR
"Unknown throttling event sources.");
3318 case (1 << PHM_AutoThrottleSource_Thermal
):
3320 src
= DPM_EVENT_SRC_DIGITAL
;
3322 case (1 << PHM_AutoThrottleSource_External
):
3324 src
= DPM_EVENT_SRC_EXTERNAL
;
3326 case (1 << PHM_AutoThrottleSource_External
) |
3327 (1 << PHM_AutoThrottleSource_Thermal
):
3329 src
= DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL
;
3332 /* Order matters - don't enable thermal protection for the wrong source. */
3334 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_THERMAL_CTRL
,
3335 DPM_EVENT_SRC
, src
);
3336 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
3337 THERMAL_PROTECTION_DIS
,
3338 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3339 PHM_PlatformCaps_ThermalController
));
3341 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
3342 THERMAL_PROTECTION_DIS
, 1);
3345 static int fiji_enable_auto_throttle_source(struct pp_hwmgr
*hwmgr
,
3346 PHM_AutoThrottleSource source
)
3348 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3350 if (!(data
->active_auto_throttle_sources
& (1 << source
))) {
3351 data
->active_auto_throttle_sources
|= 1 << source
;
3352 fiji_set_dpm_event_sources(hwmgr
, data
->active_auto_throttle_sources
);
3357 static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr
*hwmgr
)
3359 return fiji_enable_auto_throttle_source(hwmgr
, PHM_AutoThrottleSource_Thermal
);
3362 static int fiji_enable_dpm_tasks(struct pp_hwmgr
*hwmgr
)
3364 int tmp_result
, result
= 0;
3366 tmp_result
= (!fiji_is_dpm_running(hwmgr
))? 0 : -1;
3367 PP_ASSERT_WITH_CODE(result
== 0,
3368 "DPM is already running right now, no need to enable DPM!",
3371 if (fiji_voltage_control(hwmgr
)) {
3372 tmp_result
= fiji_enable_voltage_control(hwmgr
);
3373 PP_ASSERT_WITH_CODE(tmp_result
== 0,
3374 "Failed to enable voltage control!",
3375 result
= tmp_result
);
3378 if (fiji_voltage_control(hwmgr
)) {
3379 tmp_result
= fiji_construct_voltage_tables(hwmgr
);
3380 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3381 "Failed to contruct voltage tables!",
3382 result
= tmp_result
);
3385 tmp_result
= fiji_initialize_mc_reg_table(hwmgr
);
3386 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3387 "Failed to initialize MC reg table!", result
= tmp_result
);
3389 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3390 PHM_PlatformCaps_EngineSpreadSpectrumSupport
))
3391 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
3392 GENERAL_PWRMGT
, DYN_SPREAD_SPECTRUM_EN
, 1);
3394 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3395 PHM_PlatformCaps_ThermalController
))
3396 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
3397 GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, 0);
3399 tmp_result
= fiji_program_static_screen_threshold_parameters(hwmgr
);
3400 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3401 "Failed to program static screen threshold parameters!",
3402 result
= tmp_result
);
3404 tmp_result
= fiji_enable_display_gap(hwmgr
);
3405 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3406 "Failed to enable display gap!", result
= tmp_result
);
3408 tmp_result
= fiji_program_voting_clients(hwmgr
);
3409 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3410 "Failed to program voting clients!", result
= tmp_result
);
3412 tmp_result
= fiji_process_firmware_header(hwmgr
);
3413 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3414 "Failed to process firmware header!", result
= tmp_result
);
3416 tmp_result
= fiji_initial_switch_from_arbf0_to_f1(hwmgr
);
3417 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3418 "Failed to initialize switch from ArbF0 to F1!",
3419 result
= tmp_result
);
3421 tmp_result
= fiji_init_smc_table(hwmgr
);
3422 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3423 "Failed to initialize SMC table!", result
= tmp_result
);
3425 tmp_result
= fiji_init_arb_table_index(hwmgr
);
3426 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3427 "Failed to initialize ARB table index!", result
= tmp_result
);
3429 tmp_result
= fiji_populate_pm_fuses(hwmgr
);
3430 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3431 "Failed to populate PM fuses!", result
= tmp_result
);
3433 tmp_result
= fiji_enable_vrhot_gpio_interrupt(hwmgr
);
3434 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3435 "Failed to enable VR hot GPIO interrupt!", result
= tmp_result
);
3437 tmp_result
= fiji_enable_sclk_control(hwmgr
);
3438 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3439 "Failed to enable SCLK control!", result
= tmp_result
);
3441 tmp_result
= fiji_enable_ulv(hwmgr
);
3442 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3443 "Failed to enable ULV!", result
= tmp_result
);
3445 tmp_result
= fiji_enable_deep_sleep_master_switch(hwmgr
);
3446 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3447 "Failed to enable deep sleep master switch!", result
= tmp_result
);
3449 tmp_result
= fiji_start_dpm(hwmgr
);
3450 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3451 "Failed to start DPM!", result
= tmp_result
);
3453 tmp_result
= fiji_enable_smc_cac(hwmgr
);
3454 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3455 "Failed to enable SMC CAC!", result
= tmp_result
);
3457 tmp_result
= fiji_enable_power_containment(hwmgr
);
3458 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3459 "Failed to enable power containment!", result
= tmp_result
);
3461 tmp_result
= fiji_power_control_set_level(hwmgr
);
3462 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3463 "Failed to power control set level!", result
= tmp_result
);
3465 tmp_result
= fiji_enable_thermal_auto_throttle(hwmgr
);
3466 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3467 "Failed to enable thermal auto throttle!", result
= tmp_result
);
3472 static int fiji_force_dpm_highest(struct pp_hwmgr
*hwmgr
)
3474 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3475 uint32_t level
, tmp
;
3477 if (!data
->sclk_dpm_key_disabled
) {
3478 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
3480 tmp
= data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
;
3484 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3485 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
3490 if (!data
->mclk_dpm_key_disabled
) {
3491 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
3493 tmp
= data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
;
3497 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3498 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
3503 if (!data
->pcie_dpm_key_disabled
) {
3504 if (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
) {
3506 tmp
= data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
;
3510 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3511 PPSMC_MSG_PCIeDPM_ForceLevel
,
3518 static void fiji_apply_dal_min_voltage_request(struct pp_hwmgr
*hwmgr
)
3520 struct phm_ppt_v1_information
*table_info
=
3521 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
3522 struct phm_clock_voltage_dependency_table
*table
=
3523 table_info
->vddc_dep_on_dal_pwrl
;
3524 struct phm_ppt_v1_clock_voltage_dependency_table
*vddc_table
;
3525 enum PP_DAL_POWERLEVEL dal_power_level
= hwmgr
->dal_power_level
;
3526 uint32_t req_vddc
= 0, req_volt
, i
;
3528 if (!table
&& !(dal_power_level
>= PP_DAL_POWERLEVEL_ULTRALOW
&&
3529 dal_power_level
<= PP_DAL_POWERLEVEL_PERFORMANCE
))
3532 for (i
= 0; i
< table
->count
; i
++) {
3533 if (dal_power_level
== table
->entries
[i
].clk
) {
3534 req_vddc
= table
->entries
[i
].v
;
3539 vddc_table
= table_info
->vdd_dep_on_sclk
;
3540 for (i
= 0; i
< vddc_table
->count
; i
++) {
3541 if (req_vddc
<= vddc_table
->entries
[i
].vddc
) {
3542 req_volt
= (((uint32_t)vddc_table
->entries
[i
].vddc
) * VOLTAGE_SCALE
)
3544 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3545 PPSMC_MSG_VddC_Request
, req_volt
);
3549 printk(KERN_ERR
"DAL requested level can not"
3550 " found a available voltage in VDDC DPM Table \n");
3553 static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr
*hwmgr
)
3555 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3557 fiji_apply_dal_min_voltage_request(hwmgr
);
3559 if (!data
->sclk_dpm_key_disabled
) {
3560 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
)
3561 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3562 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
3563 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
3568 static int fiji_unforce_dpm_levels(struct pp_hwmgr
*hwmgr
)
3570 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3572 if (!fiji_is_dpm_running(hwmgr
))
3575 if (!data
->pcie_dpm_key_disabled
) {
3576 smum_send_msg_to_smc(hwmgr
->smumgr
,
3577 PPSMC_MSG_PCIeDPM_UnForceLevel
);
3580 return fiji_upload_dpmlevel_enable_mask(hwmgr
);
3583 static uint32_t fiji_get_lowest_enabled_level(
3584 struct pp_hwmgr
*hwmgr
, uint32_t mask
)
3588 while(0 == (mask
& (1 << level
)))
3594 static int fiji_force_dpm_lowest(struct pp_hwmgr
*hwmgr
)
3596 struct fiji_hwmgr
*data
=
3597 (struct fiji_hwmgr
*)(hwmgr
->backend
);
3600 if (!data
->sclk_dpm_key_disabled
)
3601 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
3602 level
= fiji_get_lowest_enabled_level(hwmgr
,
3603 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
3604 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3605 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
3610 if (!data
->mclk_dpm_key_disabled
) {
3611 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
3612 level
= fiji_get_lowest_enabled_level(hwmgr
,
3613 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
3614 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3615 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
3620 if (!data
->pcie_dpm_key_disabled
) {
3621 if (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
) {
3622 level
= fiji_get_lowest_enabled_level(hwmgr
,
3623 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
);
3624 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3625 PPSMC_MSG_PCIeDPM_ForceLevel
,
3633 static int fiji_dpm_force_dpm_level(struct pp_hwmgr
*hwmgr
,
3634 enum amd_dpm_forced_level level
)
3639 case AMD_DPM_FORCED_LEVEL_HIGH
:
3640 ret
= fiji_force_dpm_highest(hwmgr
);
3644 case AMD_DPM_FORCED_LEVEL_LOW
:
3645 ret
= fiji_force_dpm_lowest(hwmgr
);
3649 case AMD_DPM_FORCED_LEVEL_AUTO
:
3650 ret
= fiji_unforce_dpm_levels(hwmgr
);
3658 hwmgr
->dpm_level
= level
;
3663 static int fiji_get_power_state_size(struct pp_hwmgr
*hwmgr
)
3665 return sizeof(struct fiji_power_state
);
3668 static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr
*hwmgr
,
3669 void *state
, struct pp_power_state
*power_state
,
3670 void *pp_table
, uint32_t classification_flag
)
3672 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3673 struct fiji_power_state
*fiji_power_state
=
3674 (struct fiji_power_state
*)(&(power_state
->hardware
));
3675 struct fiji_performance_level
*performance_level
;
3676 ATOM_Tonga_State
*state_entry
= (ATOM_Tonga_State
*)state
;
3677 ATOM_Tonga_POWERPLAYTABLE
*powerplay_table
=
3678 (ATOM_Tonga_POWERPLAYTABLE
*)pp_table
;
3679 ATOM_Tonga_SCLK_Dependency_Table
*sclk_dep_table
=
3680 (ATOM_Tonga_SCLK_Dependency_Table
*)
3681 (((unsigned long)powerplay_table
) +
3682 le16_to_cpu(powerplay_table
->usSclkDependencyTableOffset
));
3683 ATOM_Tonga_MCLK_Dependency_Table
*mclk_dep_table
=
3684 (ATOM_Tonga_MCLK_Dependency_Table
*)
3685 (((unsigned long)powerplay_table
) +
3686 le16_to_cpu(powerplay_table
->usMclkDependencyTableOffset
));
3688 /* The following fields are not initialized here: id orderedList allStatesList */
3689 power_state
->classification
.ui_label
=
3690 (le16_to_cpu(state_entry
->usClassification
) &
3691 ATOM_PPLIB_CLASSIFICATION_UI_MASK
) >>
3692 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT
;
3693 power_state
->classification
.flags
= classification_flag
;
3694 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3696 power_state
->classification
.temporary_state
= false;
3697 power_state
->classification
.to_be_deleted
= false;
3699 power_state
->validation
.disallowOnDC
=
3700 (0 != (le32_to_cpu(state_entry
->ulCapsAndSettings
) &
3701 ATOM_Tonga_DISALLOW_ON_DC
));
3703 power_state
->pcie
.lanes
= 0;
3705 power_state
->display
.disableFrameModulation
= false;
3706 power_state
->display
.limitRefreshrate
= false;
3707 power_state
->display
.enableVariBright
=
3708 (0 != (le32_to_cpu(state_entry
->ulCapsAndSettings
) &
3709 ATOM_Tonga_ENABLE_VARIBRIGHT
));
3711 power_state
->validation
.supportedPowerLevels
= 0;
3712 power_state
->uvd_clocks
.VCLK
= 0;
3713 power_state
->uvd_clocks
.DCLK
= 0;
3714 power_state
->temperatures
.min
= 0;
3715 power_state
->temperatures
.max
= 0;
3717 performance_level
= &(fiji_power_state
->performance_levels
3718 [fiji_power_state
->performance_level_count
++]);
3720 PP_ASSERT_WITH_CODE(
3721 (fiji_power_state
->performance_level_count
< SMU73_MAX_LEVELS_GRAPHICS
),
3722 "Performance levels exceeds SMC limit!",
3725 PP_ASSERT_WITH_CODE(
3726 (fiji_power_state
->performance_level_count
<=
3727 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
),
3728 "Performance levels exceeds Driver limit!",
3731 /* Performance levels are arranged from low to high. */
3732 performance_level
->memory_clock
= mclk_dep_table
->entries
3733 [state_entry
->ucMemoryClockIndexLow
].ulMclk
;
3734 performance_level
->engine_clock
= sclk_dep_table
->entries
3735 [state_entry
->ucEngineClockIndexLow
].ulSclk
;
3736 performance_level
->pcie_gen
= get_pcie_gen_support(data
->pcie_gen_cap
,
3737 state_entry
->ucPCIEGenLow
);
3738 performance_level
->pcie_lane
= get_pcie_lane_support(data
->pcie_lane_cap
,
3739 state_entry
->ucPCIELaneHigh
);
3741 performance_level
= &(fiji_power_state
->performance_levels
3742 [fiji_power_state
->performance_level_count
++]);
3743 performance_level
->memory_clock
= mclk_dep_table
->entries
3744 [state_entry
->ucMemoryClockIndexHigh
].ulMclk
;
3745 performance_level
->engine_clock
= sclk_dep_table
->entries
3746 [state_entry
->ucEngineClockIndexHigh
].ulSclk
;
3747 performance_level
->pcie_gen
= get_pcie_gen_support(data
->pcie_gen_cap
,
3748 state_entry
->ucPCIEGenHigh
);
3749 performance_level
->pcie_lane
= get_pcie_lane_support(data
->pcie_lane_cap
,
3750 state_entry
->ucPCIELaneHigh
);
3755 static int fiji_get_pp_table_entry(struct pp_hwmgr
*hwmgr
,
3756 unsigned long entry_index
, struct pp_power_state
*state
)
3759 struct fiji_power_state
*ps
;
3760 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3761 struct phm_ppt_v1_information
*table_info
=
3762 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
3763 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_mclk_table
=
3764 table_info
->vdd_dep_on_mclk
;
3766 state
->hardware
.magic
= PHM_VIslands_Magic
;
3768 ps
= (struct fiji_power_state
*)(&state
->hardware
);
3770 result
= tonga_get_powerplay_table_entry(hwmgr
, entry_index
, state
,
3771 fiji_get_pp_table_entry_callback_func
);
3773 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3774 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3775 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3777 if (dep_mclk_table
!= NULL
&& dep_mclk_table
->count
== 1) {
3778 if (dep_mclk_table
->entries
[0].clk
!=
3779 data
->vbios_boot_state
.mclk_bootup_value
)
3780 printk(KERN_ERR
"Single MCLK entry VDDCI/MCLK dependency table "
3781 "does not match VBIOS boot MCLK level");
3782 if (dep_mclk_table
->entries
[0].vddci
!=
3783 data
->vbios_boot_state
.vddci_bootup_value
)
3784 printk(KERN_ERR
"Single VDDCI entry VDDCI/MCLK dependency table "
3785 "does not match VBIOS boot VDDCI level");
3788 /* set DC compatible flag if this state supports DC */
3789 if (!state
->validation
.disallowOnDC
)
3790 ps
->dc_compatible
= true;
3792 if (state
->classification
.flags
& PP_StateClassificationFlag_ACPI
)
3793 data
->acpi_pcie_gen
= ps
->performance_levels
[0].pcie_gen
;
3795 ps
->uvd_clks
.vclk
= state
->uvd_clocks
.VCLK
;
3796 ps
->uvd_clks
.dclk
= state
->uvd_clocks
.DCLK
;
3801 switch (state
->classification
.ui_label
) {
3802 case PP_StateUILabel_Performance
:
3803 data
->use_pcie_performance_levels
= true;
3805 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3806 if (data
->pcie_gen_performance
.max
<
3807 ps
->performance_levels
[i
].pcie_gen
)
3808 data
->pcie_gen_performance
.max
=
3809 ps
->performance_levels
[i
].pcie_gen
;
3811 if (data
->pcie_gen_performance
.min
>
3812 ps
->performance_levels
[i
].pcie_gen
)
3813 data
->pcie_gen_performance
.min
=
3814 ps
->performance_levels
[i
].pcie_gen
;
3816 if (data
->pcie_lane_performance
.max
<
3817 ps
->performance_levels
[i
].pcie_lane
)
3818 data
->pcie_lane_performance
.max
=
3819 ps
->performance_levels
[i
].pcie_lane
;
3821 if (data
->pcie_lane_performance
.min
>
3822 ps
->performance_levels
[i
].pcie_lane
)
3823 data
->pcie_lane_performance
.min
=
3824 ps
->performance_levels
[i
].pcie_lane
;
3827 case PP_StateUILabel_Battery
:
3828 data
->use_pcie_power_saving_levels
= true;
3830 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3831 if (data
->pcie_gen_power_saving
.max
<
3832 ps
->performance_levels
[i
].pcie_gen
)
3833 data
->pcie_gen_power_saving
.max
=
3834 ps
->performance_levels
[i
].pcie_gen
;
3836 if (data
->pcie_gen_power_saving
.min
>
3837 ps
->performance_levels
[i
].pcie_gen
)
3838 data
->pcie_gen_power_saving
.min
=
3839 ps
->performance_levels
[i
].pcie_gen
;
3841 if (data
->pcie_lane_power_saving
.max
<
3842 ps
->performance_levels
[i
].pcie_lane
)
3843 data
->pcie_lane_power_saving
.max
=
3844 ps
->performance_levels
[i
].pcie_lane
;
3846 if (data
->pcie_lane_power_saving
.min
>
3847 ps
->performance_levels
[i
].pcie_lane
)
3848 data
->pcie_lane_power_saving
.min
=
3849 ps
->performance_levels
[i
].pcie_lane
;
3859 static int fiji_apply_state_adjust_rules(struct pp_hwmgr
*hwmgr
,
3860 struct pp_power_state
*request_ps
,
3861 const struct pp_power_state
*current_ps
)
3863 struct fiji_power_state
*fiji_ps
=
3864 cast_phw_fiji_power_state(&request_ps
->hardware
);
3867 struct PP_Clocks minimum_clocks
= {0};
3868 bool disable_mclk_switching
;
3869 bool disable_mclk_switching_for_frame_lock
;
3870 struct cgs_display_info info
= {0};
3871 const struct phm_clock_and_voltage_limits
*max_limits
;
3873 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3874 struct phm_ppt_v1_information
*table_info
=
3875 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
3877 int32_t stable_pstate_sclk
= 0, stable_pstate_mclk
= 0;
3879 data
->battery_state
= (PP_StateUILabel_Battery
==
3880 request_ps
->classification
.ui_label
);
3882 PP_ASSERT_WITH_CODE(fiji_ps
->performance_level_count
== 2,
3883 "VI should always have 2 performance levels",);
3885 max_limits
= (PP_PowerSource_AC
== hwmgr
->power_source
) ?
3886 &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
) :
3887 &(hwmgr
->dyn_state
.max_clock_voltage_on_dc
);
3889 /* Cap clock DPM tables at DC MAX if it is in DC. */
3890 if (PP_PowerSource_DC
== hwmgr
->power_source
) {
3891 for (i
= 0; i
< fiji_ps
->performance_level_count
; i
++) {
3892 if (fiji_ps
->performance_levels
[i
].memory_clock
> max_limits
->mclk
)
3893 fiji_ps
->performance_levels
[i
].memory_clock
= max_limits
->mclk
;
3894 if (fiji_ps
->performance_levels
[i
].engine_clock
> max_limits
->sclk
)
3895 fiji_ps
->performance_levels
[i
].engine_clock
= max_limits
->sclk
;
3899 fiji_ps
->vce_clks
.evclk
= hwmgr
->vce_arbiter
.evclk
;
3900 fiji_ps
->vce_clks
.ecclk
= hwmgr
->vce_arbiter
.ecclk
;
3902 fiji_ps
->acp_clk
= hwmgr
->acp_arbiter
.acpclk
;
3904 cgs_get_active_displays_info(hwmgr
->device
, &info
);
3906 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3908 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3910 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3911 PHM_PlatformCaps_StablePState
)) {
3912 max_limits
= &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
);
3913 stable_pstate_sclk
= (max_limits
->sclk
* 75) / 100;
3915 for (count
= table_info
->vdd_dep_on_sclk
->count
- 1;
3916 count
>= 0; count
--) {
3917 if (stable_pstate_sclk
>=
3918 table_info
->vdd_dep_on_sclk
->entries
[count
].clk
) {
3919 stable_pstate_sclk
=
3920 table_info
->vdd_dep_on_sclk
->entries
[count
].clk
;
3926 stable_pstate_sclk
= table_info
->vdd_dep_on_sclk
->entries
[0].clk
;
3928 stable_pstate_mclk
= max_limits
->mclk
;
3930 minimum_clocks
.engineClock
= stable_pstate_sclk
;
3931 minimum_clocks
.memoryClock
= stable_pstate_mclk
;
3934 if (minimum_clocks
.engineClock
< hwmgr
->gfx_arbiter
.sclk
)
3935 minimum_clocks
.engineClock
= hwmgr
->gfx_arbiter
.sclk
;
3937 if (minimum_clocks
.memoryClock
< hwmgr
->gfx_arbiter
.mclk
)
3938 minimum_clocks
.memoryClock
= hwmgr
->gfx_arbiter
.mclk
;
3940 fiji_ps
->sclk_threshold
= hwmgr
->gfx_arbiter
.sclk_threshold
;
3942 if (0 != hwmgr
->gfx_arbiter
.sclk_over_drive
) {
3943 PP_ASSERT_WITH_CODE((hwmgr
->gfx_arbiter
.sclk_over_drive
<=
3944 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
),
3945 "Overdrive sclk exceeds limit",
3946 hwmgr
->gfx_arbiter
.sclk_over_drive
=
3947 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
);
3949 if (hwmgr
->gfx_arbiter
.sclk_over_drive
>= hwmgr
->gfx_arbiter
.sclk
)
3950 fiji_ps
->performance_levels
[1].engine_clock
=
3951 hwmgr
->gfx_arbiter
.sclk_over_drive
;
3954 if (0 != hwmgr
->gfx_arbiter
.mclk_over_drive
) {
3955 PP_ASSERT_WITH_CODE((hwmgr
->gfx_arbiter
.mclk_over_drive
<=
3956 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
),
3957 "Overdrive mclk exceeds limit",
3958 hwmgr
->gfx_arbiter
.mclk_over_drive
=
3959 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
);
3961 if (hwmgr
->gfx_arbiter
.mclk_over_drive
>= hwmgr
->gfx_arbiter
.mclk
)
3962 fiji_ps
->performance_levels
[1].memory_clock
=
3963 hwmgr
->gfx_arbiter
.mclk_over_drive
;
3966 disable_mclk_switching_for_frame_lock
= phm_cap_enabled(
3967 hwmgr
->platform_descriptor
.platformCaps
,
3968 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock
);
3970 disable_mclk_switching
= (1 < info
.display_count
) ||
3971 disable_mclk_switching_for_frame_lock
;
3973 sclk
= fiji_ps
->performance_levels
[0].engine_clock
;
3974 mclk
= fiji_ps
->performance_levels
[0].memory_clock
;
3976 if (disable_mclk_switching
)
3977 mclk
= fiji_ps
->performance_levels
3978 [fiji_ps
->performance_level_count
- 1].memory_clock
;
3980 if (sclk
< minimum_clocks
.engineClock
)
3981 sclk
= (minimum_clocks
.engineClock
> max_limits
->sclk
) ?
3982 max_limits
->sclk
: minimum_clocks
.engineClock
;
3984 if (mclk
< minimum_clocks
.memoryClock
)
3985 mclk
= (minimum_clocks
.memoryClock
> max_limits
->mclk
) ?
3986 max_limits
->mclk
: minimum_clocks
.memoryClock
;
3988 fiji_ps
->performance_levels
[0].engine_clock
= sclk
;
3989 fiji_ps
->performance_levels
[0].memory_clock
= mclk
;
3991 fiji_ps
->performance_levels
[1].engine_clock
=
3992 (fiji_ps
->performance_levels
[1].engine_clock
>=
3993 fiji_ps
->performance_levels
[0].engine_clock
) ?
3994 fiji_ps
->performance_levels
[1].engine_clock
:
3995 fiji_ps
->performance_levels
[0].engine_clock
;
3997 if (disable_mclk_switching
) {
3998 if (mclk
< fiji_ps
->performance_levels
[1].memory_clock
)
3999 mclk
= fiji_ps
->performance_levels
[1].memory_clock
;
4001 fiji_ps
->performance_levels
[0].memory_clock
= mclk
;
4002 fiji_ps
->performance_levels
[1].memory_clock
= mclk
;
4004 if (fiji_ps
->performance_levels
[1].memory_clock
<
4005 fiji_ps
->performance_levels
[0].memory_clock
)
4006 fiji_ps
->performance_levels
[1].memory_clock
=
4007 fiji_ps
->performance_levels
[0].memory_clock
;
4010 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4011 PHM_PlatformCaps_StablePState
)) {
4012 for (i
= 0; i
< fiji_ps
->performance_level_count
; i
++) {
4013 fiji_ps
->performance_levels
[i
].engine_clock
= stable_pstate_sclk
;
4014 fiji_ps
->performance_levels
[i
].memory_clock
= stable_pstate_mclk
;
4015 fiji_ps
->performance_levels
[i
].pcie_gen
= data
->pcie_gen_performance
.max
;
4016 fiji_ps
->performance_levels
[i
].pcie_lane
= data
->pcie_gen_performance
.max
;
4023 static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr
*hwmgr
, const void *input
)
4025 const struct phm_set_power_state_input
*states
=
4026 (const struct phm_set_power_state_input
*)input
;
4027 const struct fiji_power_state
*fiji_ps
=
4028 cast_const_phw_fiji_power_state(states
->pnew_state
);
4029 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4030 struct fiji_single_dpm_table
*sclk_table
= &(data
->dpm_table
.sclk_table
);
4031 uint32_t sclk
= fiji_ps
->performance_levels
4032 [fiji_ps
->performance_level_count
- 1].engine_clock
;
4033 struct fiji_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mclk_table
);
4034 uint32_t mclk
= fiji_ps
->performance_levels
4035 [fiji_ps
->performance_level_count
- 1].memory_clock
;
4036 struct PP_Clocks min_clocks
= {0};
4038 struct cgs_display_info info
= {0};
4040 data
->need_update_smu7_dpm_table
= 0;
4042 for (i
= 0; i
< sclk_table
->count
; i
++) {
4043 if (sclk
== sclk_table
->dpm_levels
[i
].value
)
4047 if (i
>= sclk_table
->count
)
4048 data
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_SCLK
;
4050 /* TODO: Check SCLK in DAL's minimum clocks
4051 * in case DeepSleep divider update is required.
4053 if(data
->display_timing
.min_clock_in_sr
!= min_clocks
.engineClockInSR
)
4054 data
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_SCLK
;
4057 for (i
= 0; i
< mclk_table
->count
; i
++) {
4058 if (mclk
== mclk_table
->dpm_levels
[i
].value
)
4062 if (i
>= mclk_table
->count
)
4063 data
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_MCLK
;
4065 cgs_get_active_displays_info(hwmgr
->device
, &info
);
4067 if (data
->display_timing
.num_existing_displays
!= info
.display_count
)
4068 data
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_MCLK
;
4073 static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr
*hwmgr
,
4074 const struct fiji_power_state
*fiji_ps
)
4077 uint32_t sclk
, max_sclk
= 0;
4078 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4079 struct fiji_dpm_table
*dpm_table
= &data
->dpm_table
;
4081 for (i
= 0; i
< fiji_ps
->performance_level_count
; i
++) {
4082 sclk
= fiji_ps
->performance_levels
[i
].engine_clock
;
4083 if (max_sclk
< sclk
)
4087 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
4088 if (dpm_table
->sclk_table
.dpm_levels
[i
].value
== max_sclk
)
4089 return (uint16_t) ((i
>= dpm_table
->pcie_speed_table
.count
) ?
4090 dpm_table
->pcie_speed_table
.dpm_levels
4091 [dpm_table
->pcie_speed_table
.count
- 1].value
:
4092 dpm_table
->pcie_speed_table
.dpm_levels
[i
].value
);
4098 static int fiji_request_link_speed_change_before_state_change(
4099 struct pp_hwmgr
*hwmgr
, const void *input
)
4101 const struct phm_set_power_state_input
*states
=
4102 (const struct phm_set_power_state_input
*)input
;
4103 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4104 const struct fiji_power_state
*fiji_nps
=
4105 cast_const_phw_fiji_power_state(states
->pnew_state
);
4106 const struct fiji_power_state
*fiji_cps
=
4107 cast_const_phw_fiji_power_state(states
->pcurrent_state
);
4109 uint16_t target_link_speed
= fiji_get_maximum_link_speed(hwmgr
, fiji_nps
);
4110 uint16_t current_link_speed
;
4112 if (data
->force_pcie_gen
== PP_PCIEGenInvalid
)
4113 current_link_speed
= fiji_get_maximum_link_speed(hwmgr
, fiji_cps
);
4115 current_link_speed
= data
->force_pcie_gen
;
4117 data
->force_pcie_gen
= PP_PCIEGenInvalid
;
4118 data
->pspp_notify_required
= false;
4119 if (target_link_speed
> current_link_speed
) {
4120 switch(target_link_speed
) {
4122 if (0 == acpi_pcie_perf_request(hwmgr
->device
, PCIE_PERF_REQ_GEN3
, false))
4124 data
->force_pcie_gen
= PP_PCIEGen2
;
4125 if (current_link_speed
== PP_PCIEGen2
)
4128 if (0 == acpi_pcie_perf_request(hwmgr
->device
, PCIE_PERF_REQ_GEN2
, false))
4131 data
->force_pcie_gen
= fiji_get_current_pcie_speed(hwmgr
);
4135 if (target_link_speed
< current_link_speed
)
4136 data
->pspp_notify_required
= true;
4142 static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
4144 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4146 if (0 == data
->need_update_smu7_dpm_table
)
4149 if ((0 == data
->sclk_dpm_key_disabled
) &&
4150 (data
->need_update_smu7_dpm_table
&
4151 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
))) {
4152 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr
),
4153 "Trying to freeze SCLK DPM when DPM is disabled",);
4154 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4155 PPSMC_MSG_SCLKDPM_FreezeLevel
),
4156 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4160 if ((0 == data
->mclk_dpm_key_disabled
) &&
4161 (data
->need_update_smu7_dpm_table
&
4162 DPMTABLE_OD_UPDATE_MCLK
)) {
4163 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr
),
4164 "Trying to freeze MCLK DPM when DPM is disabled",);
4165 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4166 PPSMC_MSG_MCLKDPM_FreezeLevel
),
4167 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4174 static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
4175 struct pp_hwmgr
*hwmgr
, const void *input
)
4178 const struct phm_set_power_state_input
*states
=
4179 (const struct phm_set_power_state_input
*)input
;
4180 const struct fiji_power_state
*fiji_ps
=
4181 cast_const_phw_fiji_power_state(states
->pnew_state
);
4182 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4183 uint32_t sclk
= fiji_ps
->performance_levels
4184 [fiji_ps
->performance_level_count
- 1].engine_clock
;
4185 uint32_t mclk
= fiji_ps
->performance_levels
4186 [fiji_ps
->performance_level_count
- 1].memory_clock
;
4187 struct fiji_dpm_table
*dpm_table
= &data
->dpm_table
;
4189 struct fiji_dpm_table
*golden_dpm_table
= &data
->golden_dpm_table
;
4190 uint32_t dpm_count
, clock_percent
;
4193 if (0 == data
->need_update_smu7_dpm_table
)
4196 if (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_SCLK
) {
4197 dpm_table
->sclk_table
.dpm_levels
4198 [dpm_table
->sclk_table
.count
- 1].value
= sclk
;
4200 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4201 PHM_PlatformCaps_OD6PlusinACSupport
) ||
4202 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4203 PHM_PlatformCaps_OD6PlusinDCSupport
)) {
4204 /* Need to do calculation based on the golden DPM table
4205 * as the Heatmap GPU Clock axis is also based on the default values
4207 PP_ASSERT_WITH_CODE(
4208 (golden_dpm_table
->sclk_table
.dpm_levels
4209 [golden_dpm_table
->sclk_table
.count
- 1].value
!= 0),
4212 dpm_count
= dpm_table
->sclk_table
.count
< 2 ?
4213 0 : dpm_table
->sclk_table
.count
- 2;
4214 for (i
= dpm_count
; i
> 1; i
--) {
4215 if (sclk
> golden_dpm_table
->sclk_table
.dpm_levels
4216 [golden_dpm_table
->sclk_table
.count
-1].value
) {
4218 ((sclk
- golden_dpm_table
->sclk_table
.dpm_levels
4219 [golden_dpm_table
->sclk_table
.count
-1].value
) * 100) /
4220 golden_dpm_table
->sclk_table
.dpm_levels
4221 [golden_dpm_table
->sclk_table
.count
-1].value
;
4223 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
4224 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
+
4225 (golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
*
4228 } else if (golden_dpm_table
->sclk_table
.dpm_levels
4229 [dpm_table
->sclk_table
.count
-1].value
> sclk
) {
4231 ((golden_dpm_table
->sclk_table
.dpm_levels
4232 [golden_dpm_table
->sclk_table
.count
- 1].value
- sclk
) *
4234 golden_dpm_table
->sclk_table
.dpm_levels
4235 [golden_dpm_table
->sclk_table
.count
-1].value
;
4237 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
4238 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
-
4239 (golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
*
4240 clock_percent
) / 100;
4242 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
4243 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
;
4248 if (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
) {
4249 dpm_table
->mclk_table
.dpm_levels
4250 [dpm_table
->mclk_table
.count
- 1].value
= mclk
;
4252 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4253 PHM_PlatformCaps_OD6PlusinACSupport
) ||
4254 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4255 PHM_PlatformCaps_OD6PlusinDCSupport
)) {
4257 PP_ASSERT_WITH_CODE(
4258 (golden_dpm_table
->mclk_table
.dpm_levels
4259 [golden_dpm_table
->mclk_table
.count
-1].value
!= 0),
4262 dpm_count
= dpm_table
->mclk_table
.count
< 2 ?
4263 0 : dpm_table
->mclk_table
.count
- 2;
4264 for (i
= dpm_count
; i
> 1; i
--) {
4265 if (mclk
> golden_dpm_table
->mclk_table
.dpm_levels
4266 [golden_dpm_table
->mclk_table
.count
-1].value
) {
4267 clock_percent
= ((mclk
-
4268 golden_dpm_table
->mclk_table
.dpm_levels
4269 [golden_dpm_table
->mclk_table
.count
-1].value
) * 100) /
4270 golden_dpm_table
->mclk_table
.dpm_levels
4271 [golden_dpm_table
->mclk_table
.count
-1].value
;
4273 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
4274 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
+
4275 (golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
*
4276 clock_percent
) / 100;
4278 } else if (golden_dpm_table
->mclk_table
.dpm_levels
4279 [dpm_table
->mclk_table
.count
-1].value
> mclk
) {
4280 clock_percent
= ((golden_dpm_table
->mclk_table
.dpm_levels
4281 [golden_dpm_table
->mclk_table
.count
-1].value
- mclk
) * 100) /
4282 golden_dpm_table
->mclk_table
.dpm_levels
4283 [golden_dpm_table
->mclk_table
.count
-1].value
;
4285 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
4286 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
-
4287 (golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
*
4288 clock_percent
) / 100;
4290 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
4291 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
;
4296 if (data
->need_update_smu7_dpm_table
&
4297 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
)) {
4298 result
= fiji_populate_all_memory_levels(hwmgr
);
4299 PP_ASSERT_WITH_CODE((0 == result
),
4300 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4304 if (data
->need_update_smu7_dpm_table
&
4305 (DPMTABLE_OD_UPDATE_MCLK
+ DPMTABLE_UPDATE_MCLK
)) {
4306 /*populate MCLK dpm table to SMU7 */
4307 result
= fiji_populate_all_memory_levels(hwmgr
);
4308 PP_ASSERT_WITH_CODE((0 == result
),
4309 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4316 static int fiji_trim_single_dpm_states(struct pp_hwmgr
*hwmgr
,
4317 struct fiji_single_dpm_table
* dpm_table
,
4318 uint32_t low_limit
, uint32_t high_limit
)
4322 for (i
= 0; i
< dpm_table
->count
; i
++) {
4323 if ((dpm_table
->dpm_levels
[i
].value
< low_limit
) ||
4324 (dpm_table
->dpm_levels
[i
].value
> high_limit
))
4325 dpm_table
->dpm_levels
[i
].enabled
= false;
4327 dpm_table
->dpm_levels
[i
].enabled
= true;
4332 static int fiji_trim_dpm_states(struct pp_hwmgr
*hwmgr
,
4333 const struct fiji_power_state
*fiji_ps
)
4336 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4337 uint32_t high_limit_count
;
4339 PP_ASSERT_WITH_CODE((fiji_ps
->performance_level_count
>= 1),
4340 "power state did not have any performance level",
4343 high_limit_count
= (1 == fiji_ps
->performance_level_count
) ? 0 : 1;
4345 fiji_trim_single_dpm_states(hwmgr
,
4346 &(data
->dpm_table
.sclk_table
),
4347 fiji_ps
->performance_levels
[0].engine_clock
,
4348 fiji_ps
->performance_levels
[high_limit_count
].engine_clock
);
4350 fiji_trim_single_dpm_states(hwmgr
,
4351 &(data
->dpm_table
.mclk_table
),
4352 fiji_ps
->performance_levels
[0].memory_clock
,
4353 fiji_ps
->performance_levels
[high_limit_count
].memory_clock
);
4358 static int fiji_generate_dpm_level_enable_mask(
4359 struct pp_hwmgr
*hwmgr
, const void *input
)
4362 const struct phm_set_power_state_input
*states
=
4363 (const struct phm_set_power_state_input
*)input
;
4364 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4365 const struct fiji_power_state
*fiji_ps
=
4366 cast_const_phw_fiji_power_state(states
->pnew_state
);
4368 result
= fiji_trim_dpm_states(hwmgr
, fiji_ps
);
4372 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
=
4373 fiji_get_dpm_level_enable_mask_value(&data
->dpm_table
.sclk_table
);
4374 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
=
4375 fiji_get_dpm_level_enable_mask_value(&data
->dpm_table
.mclk_table
);
4376 data
->last_mclk_dpm_enable_mask
=
4377 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
;
4379 if (data
->uvd_enabled
) {
4380 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
& 1)
4381 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
&= 0xFFFFFFFE;
4384 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
=
4385 fiji_get_dpm_level_enable_mask_value(&data
->dpm_table
.pcie_speed_table
);
4390 int fiji_enable_disable_uvd_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4392 return smum_send_msg_to_smc(hwmgr
->smumgr
, enable
?
4393 (PPSMC_Msg
)PPSMC_MSG_UVDDPM_Enable
:
4394 (PPSMC_Msg
)PPSMC_MSG_UVDDPM_Disable
);
4397 int fiji_enable_disable_vce_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4399 return smum_send_msg_to_smc(hwmgr
->smumgr
, enable
?
4400 PPSMC_MSG_VCEDPM_Enable
:
4401 PPSMC_MSG_VCEDPM_Disable
);
4404 int fiji_enable_disable_samu_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4406 return smum_send_msg_to_smc(hwmgr
->smumgr
, enable
?
4407 PPSMC_MSG_SAMUDPM_Enable
:
4408 PPSMC_MSG_SAMUDPM_Disable
);
4411 int fiji_enable_disable_acp_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4413 return smum_send_msg_to_smc(hwmgr
->smumgr
, enable
?
4414 PPSMC_MSG_ACPDPM_Enable
:
4415 PPSMC_MSG_ACPDPM_Disable
);
4418 int fiji_update_uvd_dpm(struct pp_hwmgr
*hwmgr
, bool bgate
)
4420 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4421 uint32_t mm_boot_level_offset
, mm_boot_level_value
;
4422 struct phm_ppt_v1_information
*table_info
=
4423 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
4426 data
->smc_state_table
.UvdBootLevel
= 0;
4427 if (table_info
->mm_dep_table
->count
> 0)
4428 data
->smc_state_table
.UvdBootLevel
=
4429 (uint8_t) (table_info
->mm_dep_table
->count
- 1);
4430 mm_boot_level_offset
= data
->dpm_table_start
+
4431 offsetof(SMU73_Discrete_DpmTable
, UvdBootLevel
);
4432 mm_boot_level_offset
/= 4;
4433 mm_boot_level_offset
*= 4;
4434 mm_boot_level_value
= cgs_read_ind_register(hwmgr
->device
,
4435 CGS_IND_REG__SMC
, mm_boot_level_offset
);
4436 mm_boot_level_value
&= 0x00FFFFFF;
4437 mm_boot_level_value
|= data
->smc_state_table
.UvdBootLevel
<< 24;
4438 cgs_write_ind_register(hwmgr
->device
,
4439 CGS_IND_REG__SMC
, mm_boot_level_offset
, mm_boot_level_value
);
4441 if (!phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4442 PHM_PlatformCaps_UVDDPM
) ||
4443 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4444 PHM_PlatformCaps_StablePState
))
4445 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4446 PPSMC_MSG_UVDDPM_SetEnabledMask
,
4447 (uint32_t)(1 << data
->smc_state_table
.UvdBootLevel
));
4450 return fiji_enable_disable_uvd_dpm(hwmgr
, !bgate
);
4453 int fiji_update_vce_dpm(struct pp_hwmgr
*hwmgr
, const void *input
)
4455 const struct phm_set_power_state_input
*states
=
4456 (const struct phm_set_power_state_input
*)input
;
4457 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4458 const struct fiji_power_state
*fiji_nps
=
4459 cast_const_phw_fiji_power_state(states
->pnew_state
);
4460 const struct fiji_power_state
*fiji_cps
=
4461 cast_const_phw_fiji_power_state(states
->pcurrent_state
);
4463 uint32_t mm_boot_level_offset
, mm_boot_level_value
;
4464 struct phm_ppt_v1_information
*table_info
=
4465 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
4467 if (fiji_nps
->vce_clks
.evclk
>0 &&
4468 (fiji_cps
== NULL
|| fiji_cps
->vce_clks
.evclk
== 0)) {
4469 data
->smc_state_table
.VceBootLevel
=
4470 (uint8_t) (table_info
->mm_dep_table
->count
- 1);
4472 mm_boot_level_offset
= data
->dpm_table_start
+
4473 offsetof(SMU73_Discrete_DpmTable
, VceBootLevel
);
4474 mm_boot_level_offset
/= 4;
4475 mm_boot_level_offset
*= 4;
4476 mm_boot_level_value
= cgs_read_ind_register(hwmgr
->device
,
4477 CGS_IND_REG__SMC
, mm_boot_level_offset
);
4478 mm_boot_level_value
&= 0xFF00FFFF;
4479 mm_boot_level_value
|= data
->smc_state_table
.VceBootLevel
<< 16;
4480 cgs_write_ind_register(hwmgr
->device
,
4481 CGS_IND_REG__SMC
, mm_boot_level_offset
, mm_boot_level_value
);
4483 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4484 PHM_PlatformCaps_StablePState
)) {
4485 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4486 PPSMC_MSG_VCEDPM_SetEnabledMask
,
4487 (uint32_t)1 << data
->smc_state_table
.VceBootLevel
);
4489 fiji_enable_disable_vce_dpm(hwmgr
, true);
4490 } else if (fiji_nps
->vce_clks
.evclk
== 0 &&
4492 fiji_cps
->vce_clks
.evclk
> 0)
4493 fiji_enable_disable_vce_dpm(hwmgr
, false);
4499 int fiji_update_samu_dpm(struct pp_hwmgr
*hwmgr
, bool bgate
)
4501 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4502 uint32_t mm_boot_level_offset
, mm_boot_level_value
;
4503 struct phm_ppt_v1_information
*table_info
=
4504 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
4507 data
->smc_state_table
.SamuBootLevel
=
4508 (uint8_t) (table_info
->mm_dep_table
->count
- 1);
4509 mm_boot_level_offset
= data
->dpm_table_start
+
4510 offsetof(SMU73_Discrete_DpmTable
, SamuBootLevel
);
4511 mm_boot_level_offset
/= 4;
4512 mm_boot_level_offset
*= 4;
4513 mm_boot_level_value
= cgs_read_ind_register(hwmgr
->device
,
4514 CGS_IND_REG__SMC
, mm_boot_level_offset
);
4515 mm_boot_level_value
&= 0xFFFFFF00;
4516 mm_boot_level_value
|= data
->smc_state_table
.SamuBootLevel
<< 0;
4517 cgs_write_ind_register(hwmgr
->device
,
4518 CGS_IND_REG__SMC
, mm_boot_level_offset
, mm_boot_level_value
);
4520 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4521 PHM_PlatformCaps_StablePState
))
4522 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4523 PPSMC_MSG_SAMUDPM_SetEnabledMask
,
4524 (uint32_t)(1 << data
->smc_state_table
.SamuBootLevel
));
4527 return fiji_enable_disable_samu_dpm(hwmgr
, !bgate
);
4530 int fiji_update_acp_dpm(struct pp_hwmgr
*hwmgr
, bool bgate
)
4532 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4533 uint32_t mm_boot_level_offset
, mm_boot_level_value
;
4534 struct phm_ppt_v1_information
*table_info
=
4535 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
4538 data
->smc_state_table
.AcpBootLevel
=
4539 (uint8_t) (table_info
->mm_dep_table
->count
- 1);
4540 mm_boot_level_offset
= data
->dpm_table_start
+
4541 offsetof(SMU73_Discrete_DpmTable
, AcpBootLevel
);
4542 mm_boot_level_offset
/= 4;
4543 mm_boot_level_offset
*= 4;
4544 mm_boot_level_value
= cgs_read_ind_register(hwmgr
->device
,
4545 CGS_IND_REG__SMC
, mm_boot_level_offset
);
4546 mm_boot_level_value
&= 0xFFFF00FF;
4547 mm_boot_level_value
|= data
->smc_state_table
.AcpBootLevel
<< 8;
4548 cgs_write_ind_register(hwmgr
->device
,
4549 CGS_IND_REG__SMC
, mm_boot_level_offset
, mm_boot_level_value
);
4551 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4552 PHM_PlatformCaps_StablePState
))
4553 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4554 PPSMC_MSG_ACPDPM_SetEnabledMask
,
4555 (uint32_t)(1 << data
->smc_state_table
.AcpBootLevel
));
4558 return fiji_enable_disable_acp_dpm(hwmgr
, !bgate
);
4561 static int fiji_update_sclk_threshold(struct pp_hwmgr
*hwmgr
)
4563 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4566 uint32_t low_sclk_interrupt_threshold
= 0;
4568 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4569 PHM_PlatformCaps_SclkThrottleLowNotification
)
4570 && (hwmgr
->gfx_arbiter
.sclk_threshold
!=
4571 data
->low_sclk_interrupt_threshold
)) {
4572 data
->low_sclk_interrupt_threshold
=
4573 hwmgr
->gfx_arbiter
.sclk_threshold
;
4574 low_sclk_interrupt_threshold
=
4575 data
->low_sclk_interrupt_threshold
;
4577 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold
);
4579 result
= fiji_copy_bytes_to_smc(
4581 data
->dpm_table_start
+
4582 offsetof(SMU73_Discrete_DpmTable
,
4583 LowSclkInterruptThreshold
),
4584 (uint8_t *)&low_sclk_interrupt_threshold
,
4592 static int fiji_program_mem_timing_parameters(struct pp_hwmgr
*hwmgr
)
4594 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4596 if (data
->need_update_smu7_dpm_table
&
4597 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_OD_UPDATE_MCLK
))
4598 return fiji_program_memory_timing_parameters(hwmgr
);
4603 static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
4605 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4607 if (0 == data
->need_update_smu7_dpm_table
)
4610 if ((0 == data
->sclk_dpm_key_disabled
) &&
4611 (data
->need_update_smu7_dpm_table
&
4612 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
))) {
4614 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr
),
4615 "Trying to Unfreeze SCLK DPM when DPM is disabled",);
4616 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4617 PPSMC_MSG_SCLKDPM_UnfreezeLevel
),
4618 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4622 if ((0 == data
->mclk_dpm_key_disabled
) &&
4623 (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
)) {
4625 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr
),
4626 "Trying to Unfreeze MCLK DPM when DPM is disabled",);
4627 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4628 PPSMC_MSG_SCLKDPM_UnfreezeLevel
),
4629 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4633 data
->need_update_smu7_dpm_table
= 0;
4638 /* Look up the voltaged based on DAL's requested level.
4639 * and then send the requested VDDC voltage to SMC
4641 static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr
*hwmgr
)
4646 int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr
*hwmgr
)
4649 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4651 /* Apply minimum voltage based on DAL's request level */
4652 fiji_apply_dal_minimum_voltage_request(hwmgr
);
4654 if (0 == data
->sclk_dpm_key_disabled
) {
4655 /* Checking if DPM is running. If we discover hang because of this,
4656 * we should skip this message.
4658 if (!fiji_is_dpm_running(hwmgr
))
4659 printk(KERN_ERR
"[ powerplay ] "
4660 "Trying to set Enable Mask when DPM is disabled \n");
4662 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
4663 result
= smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4664 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
4665 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
4666 PP_ASSERT_WITH_CODE((0 == result
),
4667 "Set Sclk Dpm enable Mask failed", return -1);
4671 if (0 == data
->mclk_dpm_key_disabled
) {
4672 /* Checking if DPM is running. If we discover hang because of this,
4673 * we should skip this message.
4675 if (!fiji_is_dpm_running(hwmgr
))
4676 printk(KERN_ERR
"[ powerplay ]"
4677 " Trying to set Enable Mask when DPM is disabled \n");
4679 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
4680 result
= smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4681 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
4682 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
4683 PP_ASSERT_WITH_CODE((0 == result
),
4684 "Set Mclk Dpm enable Mask failed", return -1);
4691 static int fiji_notify_link_speed_change_after_state_change(
4692 struct pp_hwmgr
*hwmgr
, const void *input
)
4694 const struct phm_set_power_state_input
*states
=
4695 (const struct phm_set_power_state_input
*)input
;
4696 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4697 const struct fiji_power_state
*fiji_ps
=
4698 cast_const_phw_fiji_power_state(states
->pnew_state
);
4699 uint16_t target_link_speed
= fiji_get_maximum_link_speed(hwmgr
, fiji_ps
);
4702 if (data
->pspp_notify_required
) {
4703 if (target_link_speed
== PP_PCIEGen3
)
4704 request
= PCIE_PERF_REQ_GEN3
;
4705 else if (target_link_speed
== PP_PCIEGen2
)
4706 request
= PCIE_PERF_REQ_GEN2
;
4708 request
= PCIE_PERF_REQ_GEN1
;
4710 if(request
== PCIE_PERF_REQ_GEN1
&&
4711 fiji_get_current_pcie_speed(hwmgr
) > 0)
4714 if (acpi_pcie_perf_request(hwmgr
->device
, request
, false)) {
4715 if (PP_PCIEGen2
== target_link_speed
)
4716 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4718 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4725 static int fiji_set_power_state_tasks(struct pp_hwmgr
*hwmgr
,
4728 int tmp_result
, result
= 0;
4730 tmp_result
= fiji_find_dpm_states_clocks_in_dpm_table(hwmgr
, input
);
4731 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4732 "Failed to find DPM states clocks in DPM table!",
4733 result
= tmp_result
);
4735 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4736 PHM_PlatformCaps_PCIEPerformanceRequest
)) {
4738 fiji_request_link_speed_change_before_state_change(hwmgr
, input
);
4739 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4740 "Failed to request link speed change before state change!",
4741 result
= tmp_result
);
4744 tmp_result
= fiji_freeze_sclk_mclk_dpm(hwmgr
);
4745 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4746 "Failed to freeze SCLK MCLK DPM!", result
= tmp_result
);
4748 tmp_result
= fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr
, input
);
4749 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4750 "Failed to populate and upload SCLK MCLK DPM levels!",
4751 result
= tmp_result
);
4753 tmp_result
= fiji_generate_dpm_level_enable_mask(hwmgr
, input
);
4754 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4755 "Failed to generate DPM level enabled mask!",
4756 result
= tmp_result
);
4758 tmp_result
= fiji_update_vce_dpm(hwmgr
, input
);
4759 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4760 "Failed to update VCE DPM!",
4761 result
= tmp_result
);
4763 tmp_result
= fiji_update_sclk_threshold(hwmgr
);
4764 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4765 "Failed to update SCLK threshold!",
4766 result
= tmp_result
);
4768 tmp_result
= fiji_program_mem_timing_parameters(hwmgr
);
4769 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4770 "Failed to program memory timing parameters!",
4771 result
= tmp_result
);
4773 tmp_result
= fiji_unfreeze_sclk_mclk_dpm(hwmgr
);
4774 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4775 "Failed to unfreeze SCLK MCLK DPM!",
4776 result
= tmp_result
);
4778 tmp_result
= fiji_upload_dpm_level_enable_mask(hwmgr
);
4779 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4780 "Failed to upload DPM level enabled mask!",
4781 result
= tmp_result
);
4783 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4784 PHM_PlatformCaps_PCIEPerformanceRequest
)) {
4786 fiji_notify_link_speed_change_after_state_change(hwmgr
, input
);
4787 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4788 "Failed to notify link speed change after state change!",
4789 result
= tmp_result
);
4795 static int fiji_dpm_get_sclk(struct pp_hwmgr
*hwmgr
, bool low
)
4797 struct pp_power_state
*ps
;
4798 struct fiji_power_state
*fiji_ps
;
4803 ps
= hwmgr
->request_ps
;
4808 fiji_ps
= cast_phw_fiji_power_state(&ps
->hardware
);
4811 return fiji_ps
->performance_levels
[0].engine_clock
;
4813 return fiji_ps
->performance_levels
4814 [fiji_ps
->performance_level_count
-1].engine_clock
;
4817 static int fiji_dpm_get_mclk(struct pp_hwmgr
*hwmgr
, bool low
)
4819 struct pp_power_state
*ps
;
4820 struct fiji_power_state
*fiji_ps
;
4825 ps
= hwmgr
->request_ps
;
4830 fiji_ps
= cast_phw_fiji_power_state(&ps
->hardware
);
4833 return fiji_ps
->performance_levels
[0].memory_clock
;
4835 return fiji_ps
->performance_levels
4836 [fiji_ps
->performance_level_count
-1].memory_clock
;
4839 static void fiji_print_current_perforce_level(
4840 struct pp_hwmgr
*hwmgr
, struct seq_file
*m
)
4842 uint32_t sclk
, mclk
;
4844 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetSclkFrequency
);
4846 sclk
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
4848 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetMclkFrequency
);
4850 mclk
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
4851 seq_printf(m
, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
4852 mclk
/ 100, sclk
/ 100);
4855 static const struct pp_hwmgr_func fiji_hwmgr_funcs
= {
4856 .backend_init
= &fiji_hwmgr_backend_init
,
4857 .backend_fini
= &tonga_hwmgr_backend_fini
,
4858 .asic_setup
= &fiji_setup_asic_task
,
4859 .dynamic_state_management_enable
= &fiji_enable_dpm_tasks
,
4860 .force_dpm_level
= &fiji_dpm_force_dpm_level
,
4861 .get_num_of_pp_table_entries
= &tonga_get_number_of_powerplay_table_entries
,
4862 .get_power_state_size
= &fiji_get_power_state_size
,
4863 .get_pp_table_entry
= &fiji_get_pp_table_entry
,
4864 .patch_boot_state
= &fiji_patch_boot_state
,
4865 .apply_state_adjust_rules
= &fiji_apply_state_adjust_rules
,
4866 .power_state_set
= &fiji_set_power_state_tasks
,
4867 .get_sclk
= &fiji_dpm_get_sclk
,
4868 .get_mclk
= &fiji_dpm_get_mclk
,
4869 .print_current_perforce_level
= &fiji_print_current_perforce_level
,
4870 .powergate_uvd
= &fiji_phm_powergate_uvd
,
4871 .powergate_vce
= &fiji_phm_powergate_vce
,
4872 .disable_clock_power_gating
= &fiji_phm_disable_clock_power_gating
,
4875 int fiji_hwmgr_init(struct pp_hwmgr
*hwmgr
)
4877 struct fiji_hwmgr
*data
;
4880 data
= kzalloc(sizeof(struct fiji_hwmgr
), GFP_KERNEL
);
4884 hwmgr
->backend
= data
;
4885 hwmgr
->hwmgr_func
= &fiji_hwmgr_funcs
;
4886 hwmgr
->pptable_func
= &tonga_pptable_funcs
;