projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/amd/powerplay/fiji: enable pcie and mclk forcing for low
[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / fiji_hwmgr.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/fb.h>
26 #include "linux/delay.h"
27
28 #include "hwmgr.h"
29 #include "fiji_smumgr.h"
30 #include "atombios.h"
31 #include "hardwaremanager.h"
32 #include "ppatomctrl.h"
33 #include "atombios.h"
34 #include "cgs_common.h"
35 #include "fiji_dyn_defaults.h"
36 #include "fiji_powertune.h"
37 #include "smu73.h"
38 #include "smu/smu_7_1_3_d.h"
39 #include "smu/smu_7_1_3_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
44 #include "dce/dce_10_0_d.h"
45 #include "dce/dce_10_0_sh_mask.h"
46 #include "pppcielanes.h"
47 #include "fiji_hwmgr.h"
48 #include "tonga_processpptables.h"
49 #include "tonga_pptable.h"
50 #include "pp_debug.h"
51 #include "pp_acpi.h"
52
53 #define VOLTAGE_SCALE 4
54 #define SMC_RAM_END 0x40000
55 #define VDDC_VDDCI_DELTA 300
56
57 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
58 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
59 #define MC_SEQ_MISC0_GDDR5_VALUE 5
60
61 #define MC_CG_ARB_FREQ_F0 0x0a /* boot-up default */
62 #define MC_CG_ARB_FREQ_F1 0x0b
63 #define MC_CG_ARB_FREQ_F2 0x0c
64 #define MC_CG_ARB_FREQ_F3 0x0d
65
66 /* From smc_reg.h */
67 #define SMC_CG_IND_START 0xc0030000
68 #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND */
69
70 #define VOLTAGE_SCALE 4
71 #define VOLTAGE_VID_OFFSET_SCALE1 625
72 #define VOLTAGE_VID_OFFSET_SCALE2 100
73
74 #define VDDC_VDDCI_DELTA 300
75
76 #define ixSWRST_COMMAND_1 0x1400103
77 #define MC_SEQ_CNTL__CAC_EN_MASK 0x40000000
78
79 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
80 enum DPM_EVENT_SRC {
81 DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */
82 DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */
83 DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */
84 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */
85 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */
86 };
87
88 enum DISPLAY_GAP {
89 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
90 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
91 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. */
92 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
93 };
94
95 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
96 * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
97 */
98 uint16_t fiji_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
99 {600, 1050, 6, 1} };
100
101 /* [FF, SS] type, [] 4 voltage ranges, and
102 * [Floor Freq, Boundary Freq, VID min , VID max]
103 */
104 uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
105 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
106 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
107
108 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
109 * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
110 */
111 uint8_t fiji_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
112 {0, 2, 4, 5, 6, 5} };
113
114 const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
115
116 struct fiji_power_state *cast_phw_fiji_power_state(
117 struct pp_hw_power_state *hw_ps)
118 {
119 PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
120 "Invalid Powerstate Type!",
121 return NULL;);
122
123 return (struct fiji_power_state *)hw_ps;
124 }
125
126 const struct fiji_power_state *cast_const_phw_fiji_power_state(
127 const struct pp_hw_power_state *hw_ps)
128 {
129 PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
130 "Invalid Powerstate Type!",
131 return NULL;);
132
133 return (const struct fiji_power_state *)hw_ps;
134 }
135
136 static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
137 {
138 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
139 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
140 ? true : false;
141 }
142
143 static void fiji_init_dpm_defaults(struct pp_hwmgr *hwmgr)
144 {
145 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
146 struct fiji_ulv_parm *ulv = &data->ulv;
147
148 ulv->cg_ulv_parameter = PPFIJI_CGULVPARAMETER_DFLT;
149 data->voting_rights_clients0 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0;
150 data->voting_rights_clients1 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1;
151 data->voting_rights_clients2 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2;
152 data->voting_rights_clients3 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3;
153 data->voting_rights_clients4 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4;
154 data->voting_rights_clients5 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5;
155 data->voting_rights_clients6 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6;
156 data->voting_rights_clients7 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7;
157
158 data->static_screen_threshold_unit =
159 PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT;
160 data->static_screen_threshold =
161 PPFIJI_STATICSCREENTHRESHOLD_DFLT;
162
163 /* Unset ABM cap as it moved to DAL.
164 * Add PHM_PlatformCaps_NonABMSupportInPPLib
165 * for re-direct ABM related request to DAL
166 */
167 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
168 PHM_PlatformCaps_ABM);
169 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
170 PHM_PlatformCaps_NonABMSupportInPPLib);
171
172 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
173 PHM_PlatformCaps_DynamicACTiming);
174
175 fiji_initialize_power_tune_defaults(hwmgr);
176
177 data->mclk_stutter_mode_threshold = 60000;
178 data->pcie_gen_performance.max = PP_PCIEGen1;
179 data->pcie_gen_performance.min = PP_PCIEGen3;
180 data->pcie_gen_power_saving.max = PP_PCIEGen1;
181 data->pcie_gen_power_saving.min = PP_PCIEGen3;
182 data->pcie_lane_performance.max = 0;
183 data->pcie_lane_performance.min = 16;
184 data->pcie_lane_power_saving.max = 0;
185 data->pcie_lane_power_saving.min = 16;
186
187 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
188 PHM_PlatformCaps_DynamicUVDState);
189 }
190
191 static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
192 phm_ppt_v1_voltage_lookup_table *lookup_table,
193 uint16_t virtual_voltage_id, int32_t *sclk)
194 {
195 uint8_t entryId;
196 uint8_t voltageId;
197 struct phm_ppt_v1_information *table_info =
198 (struct phm_ppt_v1_information *)(hwmgr->pptable);
199
200 PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
201
202 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
203 for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
204 voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
205 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
206 break;
207 }
208
209 PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
210 "Can't find requested voltage id in vdd_dep_on_sclk table!",
211 return -EINVAL;
212 );
213
214 *sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
215
216 return 0;
217 }
218
219 /**
220 * Get Leakage VDDC based on leakage ID.
221 *
222 * @param hwmgr the address of the powerplay hardware manager.
223 * @return always 0
224 */
225 static int fiji_get_evv_voltages(struct pp_hwmgr *hwmgr)
226 {
227 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
228 uint16_t vv_id;
229 uint16_t vddc = 0;
230 uint16_t evv_default = 1150;
231 uint16_t i, j;
232 uint32_t sclk = 0;
233 struct phm_ppt_v1_information *table_info =
234 (struct phm_ppt_v1_information *)hwmgr->pptable;
235 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
236 table_info->vdd_dep_on_sclk;
237 int result;
238
239 for (i = 0; i < FIJI_MAX_LEAKAGE_COUNT; i++) {
240 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
241 if (!fiji_get_sclk_for_voltage_evv(hwmgr,
242 table_info->vddc_lookup_table, vv_id, &sclk)) {
243 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
244 PHM_PlatformCaps_ClockStretcher)) {
245 for (j = 1; j < sclk_table->count; j++) {
246 if (sclk_table->entries[j].clk == sclk &&
247 sclk_table->entries[j].cks_enable == 0) {
248 sclk += 5000;
249 break;
250 }
251 }
252 }
253
254 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
255 PHM_PlatformCaps_EnableDriverEVV))
256 result = atomctrl_calculate_voltage_evv_on_sclk(hwmgr,
257 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc, i, true);
258 else
259 result = -EINVAL;
260
261 if (result)
262 result = atomctrl_get_voltage_evv_on_sclk(hwmgr,
263 VOLTAGE_TYPE_VDDC, sclk,vv_id, &vddc);
264
265 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
266 PP_ASSERT_WITH_CODE((vddc < 2000),
267 "Invalid VDDC value, greater than 2v!", result = -EINVAL;);
268
269 if (result)
270 /* 1.15V is the default safe value for Fiji */
271 vddc = evv_default;
272
273 /* the voltage should not be zero nor equal to leakage ID */
274 if (vddc != 0 && vddc != vv_id) {
275 data->vddc_leakage.actual_voltage
276 [data->vddc_leakage.count] = vddc;
277 data->vddc_leakage.leakage_id
278 [data->vddc_leakage.count] = vv_id;
279 data->vddc_leakage.count++;
280 }
281 }
282 }
283 return 0;
284 }
285
286 /**
287 * Change virtual leakage voltage to actual value.
288 *
289 * @param hwmgr the address of the powerplay hardware manager.
290 * @param pointer to changing voltage
291 * @param pointer to leakage table
292 */
293 static void fiji_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
294 uint16_t *voltage, struct fiji_leakage_voltage *leakage_table)
295 {
296 uint32_t index;
297
298 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
299 for (index = 0; index < leakage_table->count; index++) {
300 /* if this voltage matches a leakage voltage ID */
301 /* patch with actual leakage voltage */
302 if (leakage_table->leakage_id[index] == *voltage) {
303 *voltage = leakage_table->actual_voltage[index];
304 break;
305 }
306 }
307
308 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
309 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
310 }
311
312 /**
313 * Patch voltage lookup table by EVV leakages.
314 *
315 * @param hwmgr the address of the powerplay hardware manager.
316 * @param pointer to voltage lookup table
317 * @param pointer to leakage table
318 * @return always 0
319 */
320 static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
321 phm_ppt_v1_voltage_lookup_table *lookup_table,
322 struct fiji_leakage_voltage *leakage_table)
323 {
324 uint32_t i;
325
326 for (i = 0; i < lookup_table->count; i++)
327 fiji_patch_with_vdd_leakage(hwmgr,
328 &lookup_table->entries[i].us_vdd, leakage_table);
329
330 return 0;
331 }
332
333 static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
334 struct pp_hwmgr *hwmgr, struct fiji_leakage_voltage *leakage_table,
335 uint16_t *vddc)
336 {
337 struct phm_ppt_v1_information *table_info =
338 (struct phm_ppt_v1_information *)(hwmgr->pptable);
339 fiji_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
340 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
341 table_info->max_clock_voltage_on_dc.vddc;
342 return 0;
343 }
344
345 static int fiji_patch_voltage_dependency_tables_with_lookup_table(
346 struct pp_hwmgr *hwmgr)
347 {
348 uint8_t entryId;
349 uint8_t voltageId;
350 struct phm_ppt_v1_information *table_info =
351 (struct phm_ppt_v1_information *)(hwmgr->pptable);
352
353 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
354 table_info->vdd_dep_on_sclk;
355 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
356 table_info->vdd_dep_on_mclk;
357 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
358 table_info->mm_dep_table;
359
360 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
361 voltageId = sclk_table->entries[entryId].vddInd;
362 sclk_table->entries[entryId].vddc =
363 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
364 }
365
366 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
367 voltageId = mclk_table->entries[entryId].vddInd;
368 mclk_table->entries[entryId].vddc =
369 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
370 }
371
372 for (entryId = 0; entryId < mm_table->count; ++entryId) {
373 voltageId = mm_table->entries[entryId].vddcInd;
374 mm_table->entries[entryId].vddc =
375 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
376 }
377
378 return 0;
379
380 }
381
382 static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
383 {
384 /* Need to determine if we need calculated voltage. */
385 return 0;
386 }
387
388 static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
389 {
390 /* Need to determine if we need calculated voltage from mm table. */
391 return 0;
392 }
393
394 static int fiji_sort_lookup_table(struct pp_hwmgr *hwmgr,
395 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
396 {
397 uint32_t table_size, i, j;
398 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
399 table_size = lookup_table->count;
400
401 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
402 "Lookup table is empty", return -EINVAL);
403
404 /* Sorting voltages */
405 for (i = 0; i < table_size - 1; i++) {
406 for (j = i + 1; j > 0; j--) {
407 if (lookup_table->entries[j].us_vdd <
408 lookup_table->entries[j - 1].us_vdd) {
409 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
410 lookup_table->entries[j - 1] = lookup_table->entries[j];
411 lookup_table->entries[j] = tmp_voltage_lookup_record;
412 }
413 }
414 }
415
416 return 0;
417 }
418
419 static int fiji_complete_dependency_tables(struct pp_hwmgr *hwmgr)
420 {
421 int result = 0;
422 int tmp_result;
423 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
424 struct phm_ppt_v1_information *table_info =
425 (struct phm_ppt_v1_information *)(hwmgr->pptable);
426
427 tmp_result = fiji_patch_lookup_table_with_leakage(hwmgr,
428 table_info->vddc_lookup_table, &(data->vddc_leakage));
429 if (tmp_result)
430 result = tmp_result;
431
432 tmp_result = fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
433 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
434 if (tmp_result)
435 result = tmp_result;
436
437 tmp_result = fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
438 if (tmp_result)
439 result = tmp_result;
440
441 tmp_result = fiji_calc_voltage_dependency_tables(hwmgr);
442 if (tmp_result)
443 result = tmp_result;
444
445 tmp_result = fiji_calc_mm_voltage_dependency_table(hwmgr);
446 if (tmp_result)
447 result = tmp_result;
448
449 tmp_result = fiji_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
450 if(tmp_result)
451 result = tmp_result;
452
453 return result;
454 }
455
456 static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
457 {
458 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
459 struct phm_ppt_v1_information *table_info =
460 (struct phm_ppt_v1_information *)(hwmgr->pptable);
461
462 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
463 table_info->vdd_dep_on_sclk;
464 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
465 table_info->vdd_dep_on_mclk;
466
467 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
468 "VDD dependency on SCLK table is missing. \
469 This table is mandatory", return -EINVAL);
470 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
471 "VDD dependency on SCLK table has to have is missing. \
472 This table is mandatory", return -EINVAL);
473
474 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
475 "VDD dependency on MCLK table is missing. \
476 This table is mandatory", return -EINVAL);
477 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
478 "VDD dependency on MCLK table has to have is missing. \
479 This table is mandatory", return -EINVAL);
480
481 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
482 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->
483 entries[allowed_sclk_vdd_table->count - 1].vddc;
484
485 table_info->max_clock_voltage_on_ac.sclk =
486 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
487 table_info->max_clock_voltage_on_ac.mclk =
488 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
489 table_info->max_clock_voltage_on_ac.vddc =
490 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
491 table_info->max_clock_voltage_on_ac.vddci =
492 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
493
494 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
495 table_info->max_clock_voltage_on_ac.sclk;
496 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
497 table_info->max_clock_voltage_on_ac.mclk;
498 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
499 table_info->max_clock_voltage_on_ac.vddc;
500 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
501 table_info->max_clock_voltage_on_ac.vddci;
502
503 return 0;
504 }
505
506 static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
507 {
508 uint32_t speedCntl = 0;
509
510 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
511 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
512 ixPCIE_LC_SPEED_CNTL);
513 return((uint16_t)PHM_GET_FIELD(speedCntl,
514 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
515 }
516
517 static int fiji_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
518 {
519 uint32_t link_width;
520
521 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
522 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
523 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
524
525 PP_ASSERT_WITH_CODE((7 >= link_width),
526 "Invalid PCIe lane width!", return 0);
527
528 return decode_pcie_lane_width(link_width);
529 }
530
531 /** Patch the Boot State to match VBIOS boot clocks and voltage.
532 *
533 * @param hwmgr Pointer to the hardware manager.
534 * @param pPowerState The address of the PowerState instance being created.
535 *
536 */
537 static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
538 struct pp_hw_power_state *hw_ps)
539 {
540 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
541 struct fiji_power_state *ps = (struct fiji_power_state *)hw_ps;
542 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
543 uint16_t size;
544 uint8_t frev, crev;
545 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
546
547 /* First retrieve the Boot clocks and VDDC from the firmware info table.
548 * We assume here that fw_info is unchanged if this call fails.
549 */
550 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
551 hwmgr->device, index,
552 &size, &frev, &crev);
553 if (!fw_info)
554 /* During a test, there is no firmware info table. */
555 return 0;
556
557 /* Patch the state. */
558 data->vbios_boot_state.sclk_bootup_value =
559 le32_to_cpu(fw_info->ulDefaultEngineClock);
560 data->vbios_boot_state.mclk_bootup_value =
561 le32_to_cpu(fw_info->ulDefaultMemoryClock);
562 data->vbios_boot_state.mvdd_bootup_value =
563 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
564 data->vbios_boot_state.vddc_bootup_value =
565 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
566 data->vbios_boot_state.vddci_bootup_value =
567 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
568 data->vbios_boot_state.pcie_gen_bootup_value =
569 fiji_get_current_pcie_speed(hwmgr);
570 data->vbios_boot_state.pcie_lane_bootup_value =
571 (uint16_t)fiji_get_current_pcie_lane_number(hwmgr);
572
573 /* set boot power state */
574 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
575 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
576 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
577 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
578
579 return 0;
580 }
581
582 static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
583 {
584 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
585 uint32_t i;
586 struct phm_ppt_v1_information *table_info =
587 (struct phm_ppt_v1_information *)(hwmgr->pptable);
588 bool stay_in_boot;
589 int result;
590
591 data->dll_default_on = false;
592 data->sram_end = SMC_RAM_END;
593
594 for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
595 data->activity_target[i] = FIJI_AT_DFLT;
596
597 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
598
599 data->mclk_activity_target = PPFIJI_MCLK_TARGETACTIVITY_DFLT;
600 data->mclk_dpm0_activity_target = 0xa;
601
602 data->sclk_dpm_key_disabled = 0;
603 data->mclk_dpm_key_disabled = 0;
604 data->pcie_dpm_key_disabled = 0;
605
606 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
607 PHM_PlatformCaps_UnTabledHardwareInterface);
608 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
609 PHM_PlatformCaps_TablelessHardwareInterface);
610
611 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
612 PHM_PlatformCaps_SclkDeepSleep);
613
614 data->gpio_debug = 0;
615
616 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
617 PHM_PlatformCaps_DynamicPatchPowerState);
618
619 /* need to set voltage control types before EVV patching */
620 data->voltage_control = FIJI_VOLTAGE_CONTROL_NONE;
621 data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
622 data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;
623
624 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
625 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
626 data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
627
628 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
629 PHM_PlatformCaps_EnableMVDDControl))
630 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
631 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
632 data->mvdd_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
633
634 if (data->mvdd_control == FIJI_VOLTAGE_CONTROL_NONE)
635 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
636 PHM_PlatformCaps_EnableMVDDControl);
637
638 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
639 PHM_PlatformCaps_ControlVDDCI)) {
640 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
641 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
642 data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
643 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
644 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
645 data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
646 }
647
648 if (data->vddci_control == FIJI_VOLTAGE_CONTROL_NONE)
649 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
650 PHM_PlatformCaps_ControlVDDCI);
651
652 if (table_info && table_info->cac_dtp_table->usClockStretchAmount)
653 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
654 PHM_PlatformCaps_ClockStretcher);
655
656 fiji_init_dpm_defaults(hwmgr);
657
658 /* Get leakage voltage based on leakage ID. */
659 fiji_get_evv_voltages(hwmgr);
660
661 /* Patch our voltage dependency table with actual leakage voltage
662 * We need to perform leakage translation before it's used by other functions
663 */
664 fiji_complete_dependency_tables(hwmgr);
665
666 /* Parse pptable data read from VBIOS */
667 fiji_set_private_data_based_on_pptable(hwmgr);
668
669 /* ULV Support */
670 data->ulv.ulv_supported = true; /* ULV feature is enabled by default */
671
672 /* Initalize Dynamic State Adjustment Rule Settings */
673 result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
674
675 if (!result) {
676 data->uvd_enabled = false;
677 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
678 PHM_PlatformCaps_EnableSMU7ThermalManagement);
679 data->vddc_phase_shed_control = false;
680 }
681
682 stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
683 PHM_PlatformCaps_StayInBootState);
684
685 if (0 == result) {
686 data->is_tlu_enabled = 0;
687 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
688 FIJI_MAX_HARDWARE_POWERLEVELS;
689 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
690 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
691
692 data->pcie_gen_cap = 0x30007;
693 data->pcie_lane_cap = 0x2f0000;
694 } else {
695 /* Ignore return value in here, we are cleaning up a mess. */
696 tonga_hwmgr_backend_fini(hwmgr);
697 }
698
699 return 0;
700 }
701
702 /**
703 * Read clock related registers.
704 *
705 * @param hwmgr the address of the powerplay hardware manager.
706 * @return always 0
707 */
708 static int fiji_read_clock_registers(struct pp_hwmgr *hwmgr)
709 {
710 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
711
712 data->clock_registers.vCG_SPLL_FUNC_CNTL =
713 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
714 ixCG_SPLL_FUNC_CNTL);
715 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
716 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
717 ixCG_SPLL_FUNC_CNTL_2);
718 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
719 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
720 ixCG_SPLL_FUNC_CNTL_3);
721 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
722 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
723 ixCG_SPLL_FUNC_CNTL_4);
724 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
725 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
726 ixCG_SPLL_SPREAD_SPECTRUM);
727 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
728 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
729 ixCG_SPLL_SPREAD_SPECTRUM_2);
730
731 return 0;
732 }
733
734 /**
735 * Find out if memory is GDDR5.
736 *
737 * @param hwmgr the address of the powerplay hardware manager.
738 * @return always 0
739 */
740 static int fiji_get_memory_type(struct pp_hwmgr *hwmgr)
741 {
742 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
743 uint32_t temp;
744
745 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
746
747 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
748 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
749 MC_SEQ_MISC0_GDDR5_SHIFT));
750
751 return 0;
752 }
753
754 /**
755 * Enables Dynamic Power Management by SMC
756 *
757 * @param hwmgr the address of the powerplay hardware manager.
758 * @return always 0
759 */
760 static int fiji_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
761 {
762 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
763 GENERAL_PWRMGT, STATIC_PM_EN, 1);
764
765 return 0;
766 }
767
768 /**
769 * Initialize PowerGating States for different engines
770 *
771 * @param hwmgr the address of the powerplay hardware manager.
772 * @return always 0
773 */
774 static int fiji_init_power_gate_state(struct pp_hwmgr *hwmgr)
775 {
776 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
777
778 data->uvd_power_gated = false;
779 data->vce_power_gated = false;
780 data->samu_power_gated = false;
781 data->acp_power_gated = false;
782 data->pg_acp_init = true;
783
784 return 0;
785 }
786
787 static int fiji_init_sclk_threshold(struct pp_hwmgr *hwmgr)
788 {
789 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
790 data->low_sclk_interrupt_threshold = 0;
791
792 return 0;
793 }
794
795 static int fiji_setup_asic_task(struct pp_hwmgr *hwmgr)
796 {
797 int tmp_result, result = 0;
798
799 tmp_result = fiji_read_clock_registers(hwmgr);
800 PP_ASSERT_WITH_CODE((0 == tmp_result),
801 "Failed to read clock registers!", result = tmp_result);
802
803 tmp_result = fiji_get_memory_type(hwmgr);
804 PP_ASSERT_WITH_CODE((0 == tmp_result),
805 "Failed to get memory type!", result = tmp_result);
806
807 tmp_result = fiji_enable_acpi_power_management(hwmgr);
808 PP_ASSERT_WITH_CODE((0 == tmp_result),
809 "Failed to enable ACPI power management!", result = tmp_result);
810
811 tmp_result = fiji_init_power_gate_state(hwmgr);
812 PP_ASSERT_WITH_CODE((0 == tmp_result),
813 "Failed to init power gate state!", result = tmp_result);
814
815 tmp_result = tonga_get_mc_microcode_version(hwmgr);
816 PP_ASSERT_WITH_CODE((0 == tmp_result),
817 "Failed to get MC microcode version!", result = tmp_result);
818
819 tmp_result = fiji_init_sclk_threshold(hwmgr);
820 PP_ASSERT_WITH_CODE((0 == tmp_result),
821 "Failed to init sclk threshold!", result = tmp_result);
822
823 return result;
824 }
825
826 /**
827 * Checks if we want to support voltage control
828 *
829 * @param hwmgr the address of the powerplay hardware manager.
830 */
831 static bool fiji_voltage_control(const struct pp_hwmgr *hwmgr)
832 {
833 const struct fiji_hwmgr *data =
834 (const struct fiji_hwmgr *)(hwmgr->backend);
835
836 return (FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control);
837 }
838
839 /**
840 * Enable voltage control
841 *
842 * @param hwmgr the address of the powerplay hardware manager.
843 * @return always 0
844 */
845 static int fiji_enable_voltage_control(struct pp_hwmgr *hwmgr)
846 {
847 /* enable voltage control */
848 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
849 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
850
851 return 0;
852 }
853
854 /**
855 * Remove repeated voltage values and create table with unique values.
856 *
857 * @param hwmgr the address of the powerplay hardware manager.
858 * @param vol_table the pointer to changing voltage table
859 * @return 0 in success
860 */
861
862 static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
863 struct pp_atomctrl_voltage_table *vol_table)
864 {
865 uint32_t i, j;
866 uint16_t vvalue;
867 bool found = false;
868 struct pp_atomctrl_voltage_table *table;
869
870 PP_ASSERT_WITH_CODE((NULL != vol_table),
871 "Voltage Table empty.", return -EINVAL);
872 table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
873 GFP_KERNEL);
874
875 if (NULL == table)
876 return -EINVAL;
877
878 table->mask_low = vol_table->mask_low;
879 table->phase_delay = vol_table->phase_delay;
880
881 for (i = 0; i < vol_table->count; i++) {
882 vvalue = vol_table->entries[i].value;
883 found = false;
884
885 for (j = 0; j < table->count; j++) {
886 if (vvalue == table->entries[j].value) {
887 found = true;
888 break;
889 }
890 }
891
892 if (!found) {
893 table->entries[table->count].value = vvalue;
894 table->entries[table->count].smio_low =
895 vol_table->entries[i].smio_low;
896 table->count++;
897 }
898 }
899
900 memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
901 kfree(table);
902
903 return 0;
904 }
905 static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
906 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
907 {
908 uint32_t i;
909 int result;
910 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
911 struct pp_atomctrl_voltage_table *vol_table = &(data->mvdd_voltage_table);
912
913 PP_ASSERT_WITH_CODE((0 != dep_table->count),
914 "Voltage Dependency Table empty.", return -EINVAL);
915
916 vol_table->mask_low = 0;
917 vol_table->phase_delay = 0;
918 vol_table->count = dep_table->count;
919
920 for (i = 0; i < dep_table->count; i++) {
921 vol_table->entries[i].value = dep_table->entries[i].mvdd;
922 vol_table->entries[i].smio_low = 0;
923 }
924
925 result = fiji_trim_voltage_table(hwmgr, vol_table);
926 PP_ASSERT_WITH_CODE((0 == result),
927 "Failed to trim MVDD table.", return result);
928
929 return 0;
930 }
931
932 static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr *hwmgr,
933 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
934 {
935 uint32_t i;
936 int result;
937 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
938 struct pp_atomctrl_voltage_table *vol_table = &(data->vddci_voltage_table);
939
940 PP_ASSERT_WITH_CODE((0 != dep_table->count),
941 "Voltage Dependency Table empty.", return -EINVAL);
942
943 vol_table->mask_low = 0;
944 vol_table->phase_delay = 0;
945 vol_table->count = dep_table->count;
946
947 for (i = 0; i < dep_table->count; i++) {
948 vol_table->entries[i].value = dep_table->entries[i].vddci;
949 vol_table->entries[i].smio_low = 0;
950 }
951
952 result = fiji_trim_voltage_table(hwmgr, vol_table);
953 PP_ASSERT_WITH_CODE((0 == result),
954 "Failed to trim VDDCI table.", return result);
955
956 return 0;
957 }
958
959 static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr *hwmgr,
960 phm_ppt_v1_voltage_lookup_table *lookup_table)
961 {
962 int i = 0;
963 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
964 struct pp_atomctrl_voltage_table *vol_table = &(data->vddc_voltage_table);
965
966 PP_ASSERT_WITH_CODE((0 != lookup_table->count),
967 "Voltage Lookup Table empty.", return -EINVAL);
968
969 vol_table->mask_low = 0;
970 vol_table->phase_delay = 0;
971
972 vol_table->count = lookup_table->count;
973
974 for (i = 0; i < vol_table->count; i++) {
975 vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
976 vol_table->entries[i].smio_low = 0;
977 }
978
979 return 0;
980 }
981
982 /* ---- Voltage Tables ----
983 * If the voltage table would be bigger than
984 * what will fit into the state table on
985 * the SMC keep only the higher entries.
986 */
987 static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr *hwmgr,
988 uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table)
989 {
990 unsigned int i, diff;
991
992 if (vol_table->count <= max_vol_steps)
993 return;
994
995 diff = vol_table->count - max_vol_steps;
996
997 for (i = 0; i < max_vol_steps; i++)
998 vol_table->entries[i] = vol_table->entries[i + diff];
999
1000 vol_table->count = max_vol_steps;
1001
1002 return;
1003 }
1004
1005 /**
1006 * Create Voltage Tables.
1007 *
1008 * @param hwmgr the address of the powerplay hardware manager.
1009 * @return always 0
1010 */
1011 static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1012 {
1013 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1014 struct phm_ppt_v1_information *table_info =
1015 (struct phm_ppt_v1_information *)hwmgr->pptable;
1016 int result;
1017
1018 if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1019 result = atomctrl_get_voltage_table_v3(hwmgr,
1020 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
1021 &(data->mvdd_voltage_table));
1022 PP_ASSERT_WITH_CODE((0 == result),
1023 "Failed to retrieve MVDD table.",
1024 return result);
1025 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1026 result = fiji_get_svi2_mvdd_voltage_table(hwmgr,
1027 table_info->vdd_dep_on_mclk);
1028 PP_ASSERT_WITH_CODE((0 == result),
1029 "Failed to retrieve SVI2 MVDD table from dependancy table.",
1030 return result;);
1031 }
1032
1033 if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1034 result = atomctrl_get_voltage_table_v3(hwmgr,
1035 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
1036 &(data->vddci_voltage_table));
1037 PP_ASSERT_WITH_CODE((0 == result),
1038 "Failed to retrieve VDDCI table.",
1039 return result);
1040 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1041 result = fiji_get_svi2_vddci_voltage_table(hwmgr,
1042 table_info->vdd_dep_on_mclk);
1043 PP_ASSERT_WITH_CODE((0 == result),
1044 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
1045 return result);
1046 }
1047
1048 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1049 result = fiji_get_svi2_vdd_voltage_table(hwmgr,
1050 table_info->vddc_lookup_table);
1051 PP_ASSERT_WITH_CODE((0 == result),
1052 "Failed to retrieve SVI2 VDDC table from lookup table.",
1053 return result);
1054 }
1055
1056 PP_ASSERT_WITH_CODE(
1057 (data->vddc_voltage_table.count <= (SMU73_MAX_LEVELS_VDDC)),
1058 "Too many voltage values for VDDC. Trimming to fit state table.",
1059 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1060 SMU73_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)));
1061
1062 PP_ASSERT_WITH_CODE(
1063 (data->vddci_voltage_table.count <= (SMU73_MAX_LEVELS_VDDCI)),
1064 "Too many voltage values for VDDCI. Trimming to fit state table.",
1065 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1066 SMU73_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)));
1067
1068 PP_ASSERT_WITH_CODE(
1069 (data->mvdd_voltage_table.count <= (SMU73_MAX_LEVELS_MVDD)),
1070 "Too many voltage values for MVDD. Trimming to fit state table.",
1071 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1072 SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)));
1073
1074 return 0;
1075 }
1076
1077 static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
1078 {
1079 /* Program additional LP registers
1080 * that are no longer programmed by VBIOS
1081 */
1082 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
1083 cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
1084 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
1085 cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
1086 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
1087 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
1088 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
1089 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
1090 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
1091 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
1092 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
1093 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
1094 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
1095 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
1096
1097 return 0;
1098 }
1099
1100 /**
1101 * Programs static screed detection parameters
1102 *
1103 * @param hwmgr the address of the powerplay hardware manager.
1104 * @return always 0
1105 */
1106 static int fiji_program_static_screen_threshold_parameters(
1107 struct pp_hwmgr *hwmgr)
1108 {
1109 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1110
1111 /* Set static screen threshold unit */
1112 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1113 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
1114 data->static_screen_threshold_unit);
1115 /* Set static screen threshold */
1116 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1117 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
1118 data->static_screen_threshold);
1119
1120 return 0;
1121 }
1122
1123 /**
1124 * Setup display gap for glitch free memory clock switching.
1125 *
1126 * @param hwmgr the address of the powerplay hardware manager.
1127 * @return always 0
1128 */
1129 static int fiji_enable_display_gap(struct pp_hwmgr *hwmgr)
1130 {
1131 uint32_t displayGap =
1132 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1133 ixCG_DISPLAY_GAP_CNTL);
1134
1135 displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1136 DISP_GAP, DISPLAY_GAP_IGNORE);
1137
1138 displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1139 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
1140
1141 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1142 ixCG_DISPLAY_GAP_CNTL, displayGap);
1143
1144 return 0;
1145 }
1146
1147 /**
1148 * Programs activity state transition voting clients
1149 *
1150 * @param hwmgr the address of the powerplay hardware manager.
1151 * @return always 0
1152 */
1153 static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr)
1154 {
1155 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1156
1157 /* Clear reset for voting clients before enabling DPM */
1158 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1159 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
1160 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1161 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
1162
1163 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1164 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
1165 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1166 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
1167 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1168 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
1169 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1170 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
1171 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1172 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
1173 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1174 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
1175 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1176 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
1177 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1178 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
1179
1180 return 0;
1181 }
1182
1183 /**
1184 * Get the location of various tables inside the FW image.
1185 *
1186 * @param hwmgr the address of the powerplay hardware manager.
1187 * @return always 0
1188 */
1189 static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
1190 {
1191 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1192 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
1193 uint32_t tmp;
1194 int result;
1195 bool error = false;
1196
1197 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1198 SMU7_FIRMWARE_HEADER_LOCATION +
1199 offsetof(SMU73_Firmware_Header, DpmTable),
1200 &tmp, data->sram_end);
1201
1202 if (0 == result)
1203 data->dpm_table_start = tmp;
1204
1205 error |= (0 != result);
1206
1207 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1208 SMU7_FIRMWARE_HEADER_LOCATION +
1209 offsetof(SMU73_Firmware_Header, SoftRegisters),
1210 &tmp, data->sram_end);
1211
1212 if (!result) {
1213 data->soft_regs_start = tmp;
1214 smu_data->soft_regs_start = tmp;
1215 }
1216
1217 error |= (0 != result);
1218
1219 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1220 SMU7_FIRMWARE_HEADER_LOCATION +
1221 offsetof(SMU73_Firmware_Header, mcRegisterTable),
1222 &tmp, data->sram_end);
1223
1224 if (!result)
1225 data->mc_reg_table_start = tmp;
1226
1227 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1228 SMU7_FIRMWARE_HEADER_LOCATION +
1229 offsetof(SMU73_Firmware_Header, FanTable),
1230 &tmp, data->sram_end);
1231
1232 if (!result)
1233 data->fan_table_start = tmp;
1234
1235 error |= (0 != result);
1236
1237 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1238 SMU7_FIRMWARE_HEADER_LOCATION +
1239 offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
1240 &tmp, data->sram_end);
1241
1242 if (!result)
1243 data->arb_table_start = tmp;
1244
1245 error |= (0 != result);
1246
1247 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1248 SMU7_FIRMWARE_HEADER_LOCATION +
1249 offsetof(SMU73_Firmware_Header, Version),
1250 &tmp, data->sram_end);
1251
1252 if (!result)
1253 hwmgr->microcode_version_info.SMC = tmp;
1254
1255 error |= (0 != result);
1256
1257 return error ? -1 : 0;
1258 }
1259
1260 /* Copy one arb setting to another and then switch the active set.
1261 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
1262 */
1263 static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
1264 uint32_t arb_src, uint32_t arb_dest)
1265 {
1266 uint32_t mc_arb_dram_timing;
1267 uint32_t mc_arb_dram_timing2;
1268 uint32_t burst_time;
1269 uint32_t mc_cg_config;
1270
1271 switch (arb_src) {
1272 case MC_CG_ARB_FREQ_F0:
1273 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1274 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1275 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1276 break;
1277 case MC_CG_ARB_FREQ_F1:
1278 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
1279 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
1280 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
1281 break;
1282 default:
1283 return -EINVAL;
1284 }
1285
1286 switch (arb_dest) {
1287 case MC_CG_ARB_FREQ_F0:
1288 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
1289 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
1290 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
1291 break;
1292 case MC_CG_ARB_FREQ_F1:
1293 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
1294 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
1295 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
1296 break;
1297 default:
1298 return -EINVAL;
1299 }
1300
1301 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
1302 mc_cg_config |= 0x0000000F;
1303 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
1304 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
1305
1306 return 0;
1307 }
1308
1309 /**
1310 * Initial switch from ARB F0->F1
1311 *
1312 * @param hwmgr the address of the powerplay hardware manager.
1313 * @return always 0
1314 * This function is to be called from the SetPowerState table.
1315 */
1316 static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
1317 {
1318 return fiji_copy_and_switch_arb_sets(hwmgr,
1319 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1320 }
1321
1322 static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr,
1323 struct fiji_single_dpm_table *dpm_table, uint32_t count)
1324 {
1325 int i;
1326 PP_ASSERT_WITH_CODE(count <= MAX_REGULAR_DPM_NUMBER,
1327 "Fatal error, can not set up single DPM table entries "
1328 "to exceed max number!",);
1329
1330 dpm_table->count = count;
1331 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
1332 dpm_table->dpm_levels[i].enabled = false;
1333
1334 return 0;
1335 }
1336
1337 static void fiji_setup_pcie_table_entry(
1338 struct fiji_single_dpm_table *dpm_table,
1339 uint32_t index, uint32_t pcie_gen,
1340 uint32_t pcie_lanes)
1341 {
1342 dpm_table->dpm_levels[index].value = pcie_gen;
1343 dpm_table->dpm_levels[index].param1 = pcie_lanes;
1344 dpm_table->dpm_levels[index].enabled = 1;
1345 }
1346
1347 static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1348 {
1349 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1350 struct phm_ppt_v1_information *table_info =
1351 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1352 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1353 uint32_t i, max_entry;
1354
1355 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
1356 data->use_pcie_power_saving_levels), "No pcie performance levels!",
1357 return -EINVAL);
1358
1359 if (data->use_pcie_performance_levels &&
1360 !data->use_pcie_power_saving_levels) {
1361 data->pcie_gen_power_saving = data->pcie_gen_performance;
1362 data->pcie_lane_power_saving = data->pcie_lane_performance;
1363 } else if (!data->use_pcie_performance_levels &&
1364 data->use_pcie_power_saving_levels) {
1365 data->pcie_gen_performance = data->pcie_gen_power_saving;
1366 data->pcie_lane_performance = data->pcie_lane_power_saving;
1367 }
1368
1369 fiji_reset_single_dpm_table(hwmgr,
1370 &data->dpm_table.pcie_speed_table, SMU73_MAX_LEVELS_LINK);
1371
1372 if (pcie_table != NULL) {
1373 /* max_entry is used to make sure we reserve one PCIE level
1374 * for boot level (fix for A+A PSPP issue).
1375 * If PCIE table from PPTable have ULV entry + 8 entries,
1376 * then ignore the last entry.*/
1377 max_entry = (SMU73_MAX_LEVELS_LINK < pcie_table->count) ?
1378 SMU73_MAX_LEVELS_LINK : pcie_table->count;
1379 for (i = 1; i < max_entry; i++) {
1380 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
1381 get_pcie_gen_support(data->pcie_gen_cap,
1382 pcie_table->entries[i].gen_speed),
1383 get_pcie_lane_support(data->pcie_lane_cap,
1384 pcie_table->entries[i].lane_width));
1385 }
1386 data->dpm_table.pcie_speed_table.count = max_entry - 1;
1387 } else {
1388 /* Hardcode Pcie Table */
1389 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
1390 get_pcie_gen_support(data->pcie_gen_cap,
1391 PP_Min_PCIEGen),
1392 get_pcie_lane_support(data->pcie_lane_cap,
1393 PP_Max_PCIELane));
1394 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
1395 get_pcie_gen_support(data->pcie_gen_cap,
1396 PP_Min_PCIEGen),
1397 get_pcie_lane_support(data->pcie_lane_cap,
1398 PP_Max_PCIELane));
1399 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
1400 get_pcie_gen_support(data->pcie_gen_cap,
1401 PP_Max_PCIEGen),
1402 get_pcie_lane_support(data->pcie_lane_cap,
1403 PP_Max_PCIELane));
1404 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
1405 get_pcie_gen_support(data->pcie_gen_cap,
1406 PP_Max_PCIEGen),
1407 get_pcie_lane_support(data->pcie_lane_cap,
1408 PP_Max_PCIELane));
1409 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
1410 get_pcie_gen_support(data->pcie_gen_cap,
1411 PP_Max_PCIEGen),
1412 get_pcie_lane_support(data->pcie_lane_cap,
1413 PP_Max_PCIELane));
1414 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
1415 get_pcie_gen_support(data->pcie_gen_cap,
1416 PP_Max_PCIEGen),
1417 get_pcie_lane_support(data->pcie_lane_cap,
1418 PP_Max_PCIELane));
1419
1420 data->dpm_table.pcie_speed_table.count = 6;
1421 }
1422 /* Populate last level for boot PCIE level, but do not increment count. */
1423 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
1424 data->dpm_table.pcie_speed_table.count,
1425 get_pcie_gen_support(data->pcie_gen_cap,
1426 PP_Min_PCIEGen),
1427 get_pcie_lane_support(data->pcie_lane_cap,
1428 PP_Max_PCIELane));
1429
1430 return 0;
1431 }
1432
1433 /*
1434 * This function is to initalize all DPM state tables
1435 * for SMU7 based on the dependency table.
1436 * Dynamic state patching function will then trim these
1437 * state tables to the allowed range based
1438 * on the power policy or external client requests,
1439 * such as UVD request, etc.
1440 */
1441 static int fiji_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1442 {
1443 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1444 struct phm_ppt_v1_information *table_info =
1445 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1446 uint32_t i;
1447
1448 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
1449 table_info->vdd_dep_on_sclk;
1450 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1451 table_info->vdd_dep_on_mclk;
1452
1453 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
1454 "SCLK dependency table is missing. This table is mandatory",
1455 return -EINVAL);
1456 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
1457 "SCLK dependency table has to have is missing. "
1458 "This table is mandatory",
1459 return -EINVAL);
1460
1461 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
1462 "MCLK dependency table is missing. This table is mandatory",
1463 return -EINVAL);
1464 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1465 "MCLK dependency table has to have is missing. "
1466 "This table is mandatory",
1467 return -EINVAL);
1468
1469 /* clear the state table to reset everything to default */
1470 fiji_reset_single_dpm_table(hwmgr,
1471 &data->dpm_table.sclk_table, SMU73_MAX_LEVELS_GRAPHICS);
1472 fiji_reset_single_dpm_table(hwmgr,
1473 &data->dpm_table.mclk_table, SMU73_MAX_LEVELS_MEMORY);
1474
1475 /* Initialize Sclk DPM table based on allow Sclk values */
1476 data->dpm_table.sclk_table.count = 0;
1477 for (i = 0; i < dep_sclk_table->count; i++) {
1478 if (i == 0 || data->dpm_table.sclk_table.dpm_levels
1479 [data->dpm_table.sclk_table.count - 1].value !=
1480 dep_sclk_table->entries[i].clk) {
1481 data->dpm_table.sclk_table.dpm_levels
1482 [data->dpm_table.sclk_table.count].value =
1483 dep_sclk_table->entries[i].clk;
1484 data->dpm_table.sclk_table.dpm_levels
1485 [data->dpm_table.sclk_table.count].enabled =
1486 (i == 0) ? true : false;
1487 data->dpm_table.sclk_table.count++;
1488 }
1489 }
1490
1491 /* Initialize Mclk DPM table based on allow Mclk values */
1492 data->dpm_table.mclk_table.count = 0;
1493 for (i=0; i<dep_mclk_table->count; i++) {
1494 if ( i==0 || data->dpm_table.mclk_table.dpm_levels
1495 [data->dpm_table.mclk_table.count - 1].value !=
1496 dep_mclk_table->entries[i].clk) {
1497 data->dpm_table.mclk_table.dpm_levels
1498 [data->dpm_table.mclk_table.count].value =
1499 dep_mclk_table->entries[i].clk;
1500 data->dpm_table.mclk_table.dpm_levels
1501 [data->dpm_table.mclk_table.count].enabled =
1502 (i == 0) ? true : false;
1503 data->dpm_table.mclk_table.count++;
1504 }
1505 }
1506
1507 /* setup PCIE gen speed levels */
1508 fiji_setup_default_pcie_table(hwmgr);
1509
1510 /* save a copy of the default DPM table */
1511 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1512 sizeof(struct fiji_dpm_table));
1513
1514 return 0;
1515 }
1516
1517 /**
1518 * @brief PhwFiji_GetVoltageOrder
1519 * Returns index of requested voltage record in lookup(table)
1520 * @param lookup_table - lookup list to search in
1521 * @param voltage - voltage to look for
1522 * @return 0 on success
1523 */
1524 uint8_t fiji_get_voltage_index(
1525 struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
1526 {
1527 uint8_t count = (uint8_t) (lookup_table->count);
1528 uint8_t i;
1529
1530 PP_ASSERT_WITH_CODE((NULL != lookup_table),
1531 "Lookup Table empty.", return 0);
1532 PP_ASSERT_WITH_CODE((0 != count),
1533 "Lookup Table empty.", return 0);
1534
1535 for (i = 0; i < lookup_table->count; i++) {
1536 /* find first voltage equal or bigger than requested */
1537 if (lookup_table->entries[i].us_vdd >= voltage)
1538 return i;
1539 }
1540 /* voltage is bigger than max voltage in the table */
1541 return i - 1;
1542 }
1543
1544 /**
1545 * Preparation of vddc and vddgfx CAC tables for SMC.
1546 *
1547 * @param hwmgr the address of the hardware manager
1548 * @param table the SMC DPM table structure to be populated
1549 * @return always 0
1550 */
1551 static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
1552 struct SMU73_Discrete_DpmTable *table)
1553 {
1554 uint32_t count;
1555 uint8_t index;
1556 int result = 0;
1557 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1558 struct phm_ppt_v1_information *table_info =
1559 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1560 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
1561 table_info->vddc_lookup_table;
1562 /* tables is already swapped, so in order to use the value from it,
1563 * we need to swap it back.
1564 * We are populating vddc CAC data to BapmVddc table
1565 * in split and merged mode
1566 */
1567 for( count = 0; count<lookup_table->count; count++) {
1568 index = fiji_get_voltage_index(lookup_table,
1569 data->vddc_voltage_table.entries[count].value);
1570 table->BapmVddcVidLoSidd[count] = (uint8_t) ((6200 -
1571 (lookup_table->entries[index].us_cac_low *
1572 VOLTAGE_SCALE)) / 25);
1573 table->BapmVddcVidHiSidd[count] = (uint8_t) ((6200 -
1574 (lookup_table->entries[index].us_cac_high *
1575 VOLTAGE_SCALE)) / 25);
1576 }
1577
1578 return result;
1579 }
1580
1581 /**
1582 * Preparation of voltage tables for SMC.
1583 *
1584 * @param hwmgr the address of the hardware manager
1585 * @param table the SMC DPM table structure to be populated
1586 * @return always 0
1587 */
1588
1589 int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1590 struct SMU73_Discrete_DpmTable *table)
1591 {
1592 int result;
1593
1594 result = fiji_populate_cac_table(hwmgr, table);
1595 PP_ASSERT_WITH_CODE(0 == result,
1596 "can not populate CAC voltage tables to SMC",
1597 return -EINVAL);
1598
1599 return 0;
1600 }
1601
1602 static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
1603 struct SMU73_Discrete_Ulv *state)
1604 {
1605 int result = 0;
1606 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1607 struct phm_ppt_v1_information *table_info =
1608 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1609
1610 state->CcPwrDynRm = 0;
1611 state->CcPwrDynRm1 = 0;
1612
1613 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
1614 state->VddcOffsetVid = (uint8_t)( table_info->us_ulv_voltage_offset *
1615 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1 );
1616
1617 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
1618
1619 if (!result) {
1620 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
1621 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
1622 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
1623 }
1624 return result;
1625 }
1626
1627 static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
1628 struct SMU73_Discrete_DpmTable *table)
1629 {
1630 return fiji_populate_ulv_level(hwmgr, &table->Ulv);
1631 }
1632
1633 static int32_t fiji_get_dpm_level_enable_mask_value(
1634 struct fiji_single_dpm_table* dpm_table)
1635 {
1636 int32_t i;
1637 int32_t mask = 0;
1638
1639 for (i = dpm_table->count; i > 0; i--) {
1640 mask = mask << 1;
1641 if (dpm_table->dpm_levels[i - 1].enabled)
1642 mask |= 0x1;
1643 else
1644 mask &= 0xFFFFFFFE;
1645 }
1646 return mask;
1647 }
1648
1649 static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
1650 struct SMU73_Discrete_DpmTable *table)
1651 {
1652 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1653 struct fiji_dpm_table *dpm_table = &data->dpm_table;
1654 int i;
1655
1656 /* Index (dpm_table->pcie_speed_table.count)
1657 * is reserved for PCIE boot level. */
1658 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1659 table->LinkLevel[i].PcieGenSpeed =
1660 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1661 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
1662 dpm_table->pcie_speed_table.dpm_levels[i].param1);
1663 table->LinkLevel[i].EnabledForActivity = 1;
1664 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
1665 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
1666 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
1667 }
1668
1669 data->smc_state_table.LinkLevelCount =
1670 (uint8_t)dpm_table->pcie_speed_table.count;
1671 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1672 fiji_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1673
1674 return 0;
1675 }
1676
1677 /**
1678 * Calculates the SCLK dividers using the provided engine clock
1679 *
1680 * @param hwmgr the address of the hardware manager
1681 * @param clock the engine clock to use to populate the structure
1682 * @param sclk the SMC SCLK structure to be populated
1683 */
1684 static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
1685 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
1686 {
1687 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1688 struct pp_atomctrl_clock_dividers_vi dividers;
1689 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1690 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1691 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1692 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1693 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1694 uint32_t ref_clock;
1695 uint32_t ref_divider;
1696 uint32_t fbdiv;
1697 int result;
1698
1699 /* get the engine clock dividers for this clock value */
1700 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);
1701
1702 PP_ASSERT_WITH_CODE(result == 0,
1703 "Error retrieving Engine Clock dividers from VBIOS.",
1704 return result);
1705
1706 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
1707 ref_clock = atomctrl_get_reference_clock(hwmgr);
1708 ref_divider = 1 + dividers.uc_pll_ref_div;
1709
1710 /* low 14 bits is fraction and high 12 bits is divider */
1711 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
1712
1713 /* SPLL_FUNC_CNTL setup */
1714 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1715 SPLL_REF_DIV, dividers.uc_pll_ref_div);
1716 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1717 SPLL_PDIV_A, dividers.uc_pll_post_div);
1718
1719 /* SPLL_FUNC_CNTL_3 setup*/
1720 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1721 SPLL_FB_DIV, fbdiv);
1722
1723 /* set to use fractional accumulation*/
1724 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1725 SPLL_DITHEN, 1);
1726
1727 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1728 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
1729 struct pp_atomctrl_internal_ss_info ssInfo;
1730
1731 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
1732 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
1733 vco_freq, &ssInfo)) {
1734 /*
1735 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
1736 * ss_info.speed_spectrum_rate -- in unit of khz
1737 *
1738 * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
1739 */
1740 uint32_t clk_s = ref_clock * 5 /
1741 (ref_divider * ssInfo.speed_spectrum_rate);
1742 /* clkv = 2 * D * fbdiv / NS */
1743 uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
1744 fbdiv / (clk_s * 10000);
1745
1746 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1747 CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
1748 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1749 CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
1750 cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
1751 CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
1752 }
1753 }
1754
1755 sclk->SclkFrequency = clock;
1756 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
1757 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
1758 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
1759 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
1760 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
1761
1762 return 0;
1763 }
1764
1765 static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci)
1766 {
1767 uint32_t i;
1768 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1769 struct pp_atomctrl_voltage_table *vddci_table =
1770 &(data->vddci_voltage_table);
1771
1772 for (i = 0; i < vddci_table->count; i++) {
1773 if (vddci_table->entries[i].value >= vddci)
1774 return vddci_table->entries[i].value;
1775 }
1776
1777 PP_ASSERT_WITH_CODE(false,
1778 "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
1779 return vddci_table->entries[i].value);
1780 }
1781
1782 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1783 struct phm_ppt_v1_clock_voltage_dependency_table* dep_table,
1784 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1785 {
1786 uint32_t i;
1787 uint16_t vddci;
1788 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1789
1790 *voltage = *mvdd = 0;
1791
1792 /* clock - voltage dependency table is empty table */
1793 if (dep_table->count == 0)
1794 return -EINVAL;
1795
1796 for (i = 0; i < dep_table->count; i++) {
1797 /* find first sclk bigger than request */
1798 if (dep_table->entries[i].clk >= clock) {
1799 *voltage |= (dep_table->entries[i].vddc *
1800 VOLTAGE_SCALE) << VDDC_SHIFT;
1801 if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1802 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1803 VOLTAGE_SCALE) << VDDCI_SHIFT;
1804 else if (dep_table->entries[i].vddci)
1805 *voltage |= (dep_table->entries[i].vddci *
1806 VOLTAGE_SCALE) << VDDCI_SHIFT;
1807 else {
1808 vddci = fiji_find_closest_vddci(hwmgr,
1809 (dep_table->entries[i].vddc -
1810 (uint16_t)data->vddc_vddci_delta));
1811 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1812 }
1813
1814 if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1815 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1816 VOLTAGE_SCALE;
1817 else if (dep_table->entries[i].mvdd)
1818 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1819 VOLTAGE_SCALE;
1820
1821 *voltage |= 1 << PHASES_SHIFT;
1822 return 0;
1823 }
1824 }
1825
1826 /* sclk is bigger than max sclk in the dependence table */
1827 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1828
1829 if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1830 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1831 VOLTAGE_SCALE) << VDDCI_SHIFT;
1832 else if (dep_table->entries[i-1].vddci) {
1833 vddci = fiji_find_closest_vddci(hwmgr,
1834 (dep_table->entries[i].vddc -
1835 (uint16_t)data->vddc_vddci_delta));
1836 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1837 }
1838
1839 if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1840 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1841 else if (dep_table->entries[i].mvdd)
1842 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1843
1844 return 0;
1845 }
1846 /**
1847 * Populates single SMC SCLK structure using the provided engine clock
1848 *
1849 * @param hwmgr the address of the hardware manager
1850 * @param clock the engine clock to use to populate the structure
1851 * @param sclk the SMC SCLK structure to be populated
1852 */
1853
1854 static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1855 uint32_t clock, uint16_t sclk_al_threshold,
1856 struct SMU73_Discrete_GraphicsLevel *level)
1857 {
1858 int result;
1859 /* PP_Clocks minClocks; */
1860 uint32_t threshold, mvdd;
1861 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1862 struct phm_ppt_v1_information *table_info =
1863 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1864
1865 result = fiji_calculate_sclk_params(hwmgr, clock, level);
1866
1867 /* populate graphics levels */
1868 result = fiji_get_dependency_volt_by_clk(hwmgr,
1869 table_info->vdd_dep_on_sclk, clock,
1870 &level->MinVoltage, &mvdd);
1871 PP_ASSERT_WITH_CODE((0 == result),
1872 "can not find VDDC voltage value for "
1873 "VDDC engine clock dependency table",
1874 return result);
1875
1876 level->SclkFrequency = clock;
1877 level->ActivityLevel = sclk_al_threshold;
1878 level->CcPwrDynRm = 0;
1879 level->CcPwrDynRm1 = 0;
1880 level->EnabledForActivity = 0;
1881 level->EnabledForThrottle = 1;
1882 level->UpHyst = 10;
1883 level->DownHyst = 0;
1884 level->VoltageDownHyst = 0;
1885 level->PowerThrottle = 0;
1886
1887 threshold = clock * data->fast_watermark_threshold / 100;
1888
1889 /*
1890 * TODO: get minimum clocks from dal configaration
1891 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1892 */
1893 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1894
1895 /* get level->DeepSleepDivId
1896 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1897 {
1898 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1899 } */
1900
1901 /* Default to slow, highest DPM level will be
1902 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1903 */
1904 level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1905
1906 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1907 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
1908 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1909 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
1910 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
1911 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
1912 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
1913 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1914 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1915
1916 return 0;
1917 }
1918 /**
1919 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1920 *
1921 * @param hwmgr the address of the hardware manager
1922 */
1923 static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1924 {
1925 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1926 struct fiji_dpm_table *dpm_table = &data->dpm_table;
1927 struct phm_ppt_v1_information *table_info =
1928 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1929 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1930 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1931 int result = 0;
1932 uint32_t array = data->dpm_table_start +
1933 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
1934 uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
1935 SMU73_MAX_LEVELS_GRAPHICS;
1936 struct SMU73_Discrete_GraphicsLevel *levels =
1937 data->smc_state_table.GraphicsLevel;
1938 uint32_t i, max_entry;
1939 uint8_t hightest_pcie_level_enabled = 0,
1940 lowest_pcie_level_enabled = 0,
1941 mid_pcie_level_enabled = 0,
1942 count = 0;
1943
1944 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1945 result = fiji_populate_single_graphic_level(hwmgr,
1946 dpm_table->sclk_table.dpm_levels[i].value,
1947 (uint16_t)data->activity_target[i],
1948 &levels[i]);
1949 if (result)
1950 return result;
1951
1952 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1953 if (i > 1)
1954 levels[i].DeepSleepDivId = 0;
1955 }
1956
1957 /* Only enable level 0 for now.*/
1958 levels[0].EnabledForActivity = 1;
1959
1960 /* set highest level watermark to high */
1961 levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
1962 PPSMC_DISPLAY_WATERMARK_HIGH;
1963
1964 data->smc_state_table.GraphicsDpmLevelCount =
1965 (uint8_t)dpm_table->sclk_table.count;
1966 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1967 fiji_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1968
1969 if (pcie_table != NULL) {
1970 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1971 "There must be 1 or more PCIE levels defined in PPTable.",
1972 return -EINVAL);
1973 max_entry = pcie_entry_cnt - 1;
1974 for (i = 0; i < dpm_table->sclk_table.count; i++)
1975 levels[i].pcieDpmLevel =
1976 (uint8_t) ((i < max_entry)? i : max_entry);
1977 } else {
1978 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1979 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1980 (1 << (hightest_pcie_level_enabled + 1))) != 0 ))
1981 hightest_pcie_level_enabled++;
1982
1983 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1984 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1985 (1 << lowest_pcie_level_enabled)) == 0 ))
1986 lowest_pcie_level_enabled++;
1987
1988 while ((count < hightest_pcie_level_enabled) &&
1989 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1990 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0 ))
1991 count++;
1992
1993 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1+ count) <
1994 hightest_pcie_level_enabled?
1995 (lowest_pcie_level_enabled + 1 + count) :
1996 hightest_pcie_level_enabled;
1997
1998 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1999 for(i = 2; i < dpm_table->sclk_table.count; i++)
2000 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
2001
2002 /* set pcieDpmLevel to lowest_pcie_level_enabled */
2003 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
2004
2005 /* set pcieDpmLevel to mid_pcie_level_enabled */
2006 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
2007 }
2008 /* level count will send to smc once at init smc table and never change */
2009 result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2010 (uint32_t)array_size, data->sram_end);
2011
2012 return result;
2013 }
2014
2015 /**
2016 * MCLK Frequency Ratio
2017 * SEQ_CG_RESP Bit[31:24] - 0x0
2018 * Bit[27:24] \96 DDR3 Frequency ratio
2019 * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz
2020 * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz
2021 * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz
2022 * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz
2023 * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz
2024 * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz
2025 * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz
2026 * 400 < 0x7 <= 450MHz, 800 < 0xF
2027 */
2028 static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
2029 {
2030 if (mem_clock <= 10000) return 0x0;
2031 if (mem_clock <= 15000) return 0x1;
2032 if (mem_clock <= 20000) return 0x2;
2033 if (mem_clock <= 25000) return 0x3;
2034 if (mem_clock <= 30000) return 0x4;
2035 if (mem_clock <= 35000) return 0x5;
2036 if (mem_clock <= 40000) return 0x6;
2037 if (mem_clock <= 45000) return 0x7;
2038 if (mem_clock <= 50000) return 0x8;
2039 if (mem_clock <= 55000) return 0x9;
2040 if (mem_clock <= 60000) return 0xa;
2041 if (mem_clock <= 65000) return 0xb;
2042 if (mem_clock <= 70000) return 0xc;
2043 if (mem_clock <= 75000) return 0xd;
2044 if (mem_clock <= 80000) return 0xe;
2045 /* mem_clock > 800MHz */
2046 return 0xf;
2047 }
2048
2049 /**
2050 * Populates the SMC MCLK structure using the provided memory clock
2051 *
2052 * @param hwmgr the address of the hardware manager
2053 * @param clock the memory clock to use to populate the structure
2054 * @param sclk the SMC SCLK structure to be populated
2055 */
2056 static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
2057 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
2058 {
2059 struct pp_atomctrl_memory_clock_param mem_param;
2060 int result;
2061
2062 result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
2063 PP_ASSERT_WITH_CODE((0 == result),
2064 "Failed to get Memory PLL Dividers.",);
2065
2066 /* Save the result data to outpupt memory level structure */
2067 mclk->MclkFrequency = clock;
2068 mclk->MclkDivider = (uint8_t)mem_param.mpll_post_divider;
2069 mclk->FreqRange = fiji_get_mclk_frequency_ratio(clock);
2070
2071 return result;
2072 }
2073
2074 static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
2075 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
2076 {
2077 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2078 struct phm_ppt_v1_information *table_info =
2079 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2080 int result = 0;
2081
2082 if (table_info->vdd_dep_on_mclk) {
2083 result = fiji_get_dependency_volt_by_clk(hwmgr,
2084 table_info->vdd_dep_on_mclk, clock,
2085 &mem_level->MinVoltage, &mem_level->MinMvdd);
2086 PP_ASSERT_WITH_CODE((0 == result),
2087 "can not find MinVddc voltage value from memory "
2088 "VDDC voltage dependency table", return result);
2089 }
2090
2091 mem_level->EnabledForThrottle = 1;
2092 mem_level->EnabledForActivity = 0;
2093 mem_level->UpHyst = 0;
2094 mem_level->DownHyst = 100;
2095 mem_level->VoltageDownHyst = 0;
2096 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2097 mem_level->StutterEnable = false;
2098
2099 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2100
2101 /* enable stutter mode if all the follow condition applied
2102 * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
2103 * &(data->DisplayTiming.numExistingDisplays));
2104 */
2105 data->display_timing.num_existing_displays = 1;
2106
2107 if ((data->mclk_stutter_mode_threshold) &&
2108 (clock <= data->mclk_stutter_mode_threshold) &&
2109 (!data->is_uvd_enabled) &&
2110 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
2111 STUTTER_ENABLE) & 0x1))
2112 mem_level->StutterEnable = true;
2113
2114 result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
2115 if (!result) {
2116 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
2117 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
2118 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
2119 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
2120 }
2121 return result;
2122 }
2123
2124 /**
2125 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2126 *
2127 * @param hwmgr the address of the hardware manager
2128 */
2129 static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2130 {
2131 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2132 struct fiji_dpm_table *dpm_table = &data->dpm_table;
2133 int result;
2134 /* populate MCLK dpm table to SMU7 */
2135 uint32_t array = data->dpm_table_start +
2136 offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
2137 uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
2138 SMU73_MAX_LEVELS_MEMORY;
2139 struct SMU73_Discrete_MemoryLevel *levels =
2140 data->smc_state_table.MemoryLevel;
2141 uint32_t i;
2142
2143 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2144 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2145 "can not populate memory level as memory clock is zero",
2146 return -EINVAL);
2147 result = fiji_populate_single_memory_level(hwmgr,
2148 dpm_table->mclk_table.dpm_levels[i].value,
2149 &levels[i]);
2150 if (result)
2151 return result;
2152 }
2153
2154 /* Only enable level 0 for now. */
2155 levels[0].EnabledForActivity = 1;
2156
2157 /* in order to prevent MC activity from stutter mode to push DPM up.
2158 * the UVD change complements this by putting the MCLK in
2159 * a higher state by default such that we are not effected by
2160 * up threshold or and MCLK DPM latency.
2161 */
2162 levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
2163 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
2164
2165 data->smc_state_table.MemoryDpmLevelCount =
2166 (uint8_t)dpm_table->mclk_table.count;
2167 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
2168 fiji_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2169 /* set highest level watermark to high */
2170 levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
2171 PPSMC_DISPLAY_WATERMARK_HIGH;
2172
2173 /* level count will send to smc once at init smc table and never change */
2174 result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2175 (uint32_t)array_size, data->sram_end);
2176
2177 return result;
2178 }
2179
2180 /**
2181 * Populates the SMC MVDD structure using the provided memory clock.
2182 *
2183 * @param hwmgr the address of the hardware manager
2184 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2185 * @param voltage the SMC VOLTAGE structure to be populated
2186 */
2187 int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
2188 uint32_t mclk, SMIO_Pattern *smio_pat)
2189 {
2190 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2191 struct phm_ppt_v1_information *table_info =
2192 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2193 uint32_t i = 0;
2194
2195 if (FIJI_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2196 /* find mvdd value which clock is more than request */
2197 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
2198 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
2199 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
2200 break;
2201 }
2202 }
2203 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
2204 "MVDD Voltage is outside the supported range.",
2205 return -EINVAL);
2206 } else
2207 return -EINVAL;
2208
2209 return 0;
2210 }
2211
2212 static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
2213 SMU73_Discrete_DpmTable *table)
2214 {
2215 int result = 0;
2216 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2217 struct phm_ppt_v1_information *table_info =
2218 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2219 struct pp_atomctrl_clock_dividers_vi dividers;
2220 SMIO_Pattern vol_level;
2221 uint32_t mvdd;
2222 uint16_t us_mvdd;
2223 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2224 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2225
2226 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2227
2228 if (!data->sclk_dpm_key_disabled) {
2229 /* Get MinVoltage and Frequency from DPM0,
2230 * already converted to SMC_UL */
2231 table->ACPILevel.SclkFrequency =
2232 data->dpm_table.sclk_table.dpm_levels[0].value;
2233 result = fiji_get_dependency_volt_by_clk(hwmgr,
2234 table_info->vdd_dep_on_sclk,
2235 table->ACPILevel.SclkFrequency,
2236 &table->ACPILevel.MinVoltage, &mvdd);
2237 PP_ASSERT_WITH_CODE((0 == result),
2238 "Cannot find ACPI VDDC voltage value "
2239 "in Clock Dependency Table",);
2240 } else {
2241 table->ACPILevel.SclkFrequency =
2242 data->vbios_boot_state.sclk_bootup_value;
2243 table->ACPILevel.MinVoltage =
2244 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
2245 }
2246
2247 /* get the engine clock dividers for this clock value */
2248 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2249 table->ACPILevel.SclkFrequency, &dividers);
2250 PP_ASSERT_WITH_CODE(result == 0,
2251 "Error retrieving Engine Clock dividers from VBIOS.",
2252 return result);
2253
2254 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2255 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2256 table->ACPILevel.DeepSleepDivId = 0;
2257
2258 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2259 SPLL_PWRON, 0);
2260 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2261 SPLL_RESET, 1);
2262 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
2263 SCLK_MUX_SEL, 4);
2264
2265 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2266 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2267 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2268 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2269 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2270 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2271 table->ACPILevel.CcPwrDynRm = 0;
2272 table->ACPILevel.CcPwrDynRm1 = 0;
2273
2274 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2275 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2276 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
2277 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2278 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2279 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2280 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2281 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2282 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2283 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2284 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2285
2286 if (!data->mclk_dpm_key_disabled) {
2287 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
2288 table->MemoryACPILevel.MclkFrequency =
2289 data->dpm_table.mclk_table.dpm_levels[0].value;
2290 result = fiji_get_dependency_volt_by_clk(hwmgr,
2291 table_info->vdd_dep_on_mclk,
2292 table->MemoryACPILevel.MclkFrequency,
2293 &table->MemoryACPILevel.MinVoltage, &mvdd);
2294 PP_ASSERT_WITH_CODE((0 == result),
2295 "Cannot find ACPI VDDCI voltage value "
2296 "in Clock Dependency Table",);
2297 } else {
2298 table->MemoryACPILevel.MclkFrequency =
2299 data->vbios_boot_state.mclk_bootup_value;
2300 table->MemoryACPILevel.MinVoltage =
2301 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
2302 }
2303
2304 us_mvdd = 0;
2305 if ((FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
2306 (data->mclk_dpm_key_disabled))
2307 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
2308 else {
2309 if (!fiji_populate_mvdd_value(hwmgr,
2310 data->dpm_table.mclk_table.dpm_levels[0].value,
2311 &vol_level))
2312 us_mvdd = vol_level.Voltage;
2313 }
2314
2315 table->MemoryACPILevel.MinMvdd =
2316 PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
2317
2318 table->MemoryACPILevel.EnabledForThrottle = 0;
2319 table->MemoryACPILevel.EnabledForActivity = 0;
2320 table->MemoryACPILevel.UpHyst = 0;
2321 table->MemoryACPILevel.DownHyst = 100;
2322 table->MemoryACPILevel.VoltageDownHyst = 0;
2323 table->MemoryACPILevel.ActivityLevel =
2324 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2325
2326 table->MemoryACPILevel.StutterEnable = false;
2327 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
2328 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
2329
2330 return result;
2331 }
2332
2333 static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
2334 SMU73_Discrete_DpmTable *table)
2335 {
2336 int result = -EINVAL;
2337 uint8_t count;
2338 struct pp_atomctrl_clock_dividers_vi dividers;
2339 struct phm_ppt_v1_information *table_info =
2340 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2341 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2342 table_info->mm_dep_table;
2343 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2344
2345 table->VceLevelCount = (uint8_t)(mm_table->count);
2346 table->VceBootLevel = 0;
2347
2348 for(count = 0; count < table->VceLevelCount; count++) {
2349 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
2350 table->VceLevel[count].MinVoltage |=
2351 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
2352 table->VceLevel[count].MinVoltage |=
2353 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
2354 VOLTAGE_SCALE) << VDDCI_SHIFT;
2355 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2356
2357 /*retrieve divider value for VBIOS */
2358 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2359 table->VceLevel[count].Frequency, &dividers);
2360 PP_ASSERT_WITH_CODE((0 == result),
2361 "can not find divide id for VCE engine clock",
2362 return result);
2363
2364 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2365
2366 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
2367 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
2368 }
2369 return result;
2370 }
2371
2372 static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
2373 SMU73_Discrete_DpmTable *table)
2374 {
2375 int result = -EINVAL;
2376 uint8_t count;
2377 struct pp_atomctrl_clock_dividers_vi dividers;
2378 struct phm_ppt_v1_information *table_info =
2379 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2380 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2381 table_info->mm_dep_table;
2382 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2383
2384 table->AcpLevelCount = (uint8_t)(mm_table->count);
2385 table->AcpBootLevel = 0;
2386
2387 for (count = 0; count < table->AcpLevelCount; count++) {
2388 table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
2389 table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2390 VOLTAGE_SCALE) << VDDC_SHIFT;
2391 table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2392 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2393 table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2394
2395 /* retrieve divider value for VBIOS */
2396 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2397 table->AcpLevel[count].Frequency, &dividers);
2398 PP_ASSERT_WITH_CODE((0 == result),
2399 "can not find divide id for engine clock", return result);
2400
2401 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2402
2403 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
2404 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
2405 }
2406 return result;
2407 }
2408
2409 static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
2410 SMU73_Discrete_DpmTable *table)
2411 {
2412 int result = -EINVAL;
2413 uint8_t count;
2414 struct pp_atomctrl_clock_dividers_vi dividers;
2415 struct phm_ppt_v1_information *table_info =
2416 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2417 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2418 table_info->mm_dep_table;
2419 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2420
2421 table->SamuBootLevel = 0;
2422 table->SamuLevelCount = (uint8_t)(mm_table->count);
2423
2424 for (count = 0; count < table->SamuLevelCount; count++) {
2425 /* not sure whether we need evclk or not */
2426 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
2427 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2428 VOLTAGE_SCALE) << VDDC_SHIFT;
2429 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2430 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2431 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2432
2433 /* retrieve divider value for VBIOS */
2434 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2435 table->SamuLevel[count].Frequency, &dividers);
2436 PP_ASSERT_WITH_CODE((0 == result),
2437 "can not find divide id for samu clock", return result);
2438
2439 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2440
2441 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
2442 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
2443 }
2444 return result;
2445 }
2446
2447 static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
2448 int32_t eng_clock, int32_t mem_clock,
2449 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
2450 {
2451 uint32_t dram_timing;
2452 uint32_t dram_timing2;
2453 uint32_t burstTime;
2454 ULONG state, trrds, trrdl;
2455 int result;
2456
2457 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
2458 eng_clock, mem_clock);
2459 PP_ASSERT_WITH_CODE(result == 0,
2460 "Error calling VBIOS to set DRAM_TIMING.", return result);
2461
2462 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
2463 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
2464 burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
2465
2466 state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
2467 trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
2468 trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
2469
2470 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
2471 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
2472 arb_regs->McArbBurstTime = (uint8_t)burstTime;
2473 arb_regs->TRRDS = (uint8_t)trrds;
2474 arb_regs->TRRDL = (uint8_t)trrdl;
2475
2476 return 0;
2477 }
2478
2479 static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
2480 {
2481 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2482 struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
2483 uint32_t i, j;
2484 int result = 0;
2485
2486 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
2487 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2488 result = fiji_populate_memory_timing_parameters(hwmgr,
2489 data->dpm_table.sclk_table.dpm_levels[i].value,
2490 data->dpm_table.mclk_table.dpm_levels[j].value,
2491 &arb_regs.entries[i][j]);
2492 if (result)
2493 break;
2494 }
2495 }
2496
2497 if (!result)
2498 result = fiji_copy_bytes_to_smc(
2499 hwmgr->smumgr,
2500 data->arb_table_start,
2501 (uint8_t *)&arb_regs,
2502 sizeof(SMU73_Discrete_MCArbDramTimingTable),
2503 data->sram_end);
2504 return result;
2505 }
2506
2507 static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
2508 struct SMU73_Discrete_DpmTable *table)
2509 {
2510 int result = -EINVAL;
2511 uint8_t count;
2512 struct pp_atomctrl_clock_dividers_vi dividers;
2513 struct phm_ppt_v1_information *table_info =
2514 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2515 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2516 table_info->mm_dep_table;
2517 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2518
2519 table->UvdLevelCount = (uint8_t)(mm_table->count);
2520 table->UvdBootLevel = 0;
2521
2522 for (count = 0; count < table->UvdLevelCount; count++) {
2523 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
2524 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
2525 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2526 VOLTAGE_SCALE) << VDDC_SHIFT;
2527 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2528 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2529 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2530
2531 /* retrieve divider value for VBIOS */
2532 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2533 table->UvdLevel[count].VclkFrequency, &dividers);
2534 PP_ASSERT_WITH_CODE((0 == result),
2535 "can not find divide id for Vclk clock", return result);
2536
2537 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
2538
2539 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2540 table->UvdLevel[count].DclkFrequency, &dividers);
2541 PP_ASSERT_WITH_CODE((0 == result),
2542 "can not find divide id for Dclk clock", return result);
2543
2544 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
2545
2546 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
2547 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
2548 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
2549
2550 }
2551 return result;
2552 }
2553
2554 static int fiji_find_boot_level(struct fiji_single_dpm_table *table,
2555 uint32_t value, uint32_t *boot_level)
2556 {
2557 int result = -EINVAL;
2558 uint32_t i;
2559
2560 for (i = 0; i < table->count; i++) {
2561 if (value == table->dpm_levels[i].value) {
2562 *boot_level = i;
2563 result = 0;
2564 }
2565 }
2566 return result;
2567 }
2568
2569 static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2570 struct SMU73_Discrete_DpmTable *table)
2571 {
2572 int result = 0;
2573 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2574
2575 table->GraphicsBootLevel = 0;
2576 table->MemoryBootLevel = 0;
2577
2578 /* find boot level from dpm table */
2579 result = fiji_find_boot_level(&(data->dpm_table.sclk_table),
2580 data->vbios_boot_state.sclk_bootup_value,
2581 (uint32_t *)&(table->GraphicsBootLevel));
2582
2583 result = fiji_find_boot_level(&(data->dpm_table.mclk_table),
2584 data->vbios_boot_state.mclk_bootup_value,
2585 (uint32_t *)&(table->MemoryBootLevel));
2586
2587 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
2588 VOLTAGE_SCALE;
2589 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
2590 VOLTAGE_SCALE;
2591 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
2592 VOLTAGE_SCALE;
2593
2594 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
2595 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
2596 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2597
2598 return 0;
2599 }
2600
2601 static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
2602 {
2603 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2604 struct phm_ppt_v1_information *table_info =
2605 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2606 uint8_t count, level;
2607
2608 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
2609 for (level = 0; level < count; level++) {
2610 if(table_info->vdd_dep_on_sclk->entries[level].clk >=
2611 data->vbios_boot_state.sclk_bootup_value) {
2612 data->smc_state_table.GraphicsBootLevel = level;
2613 break;
2614 }
2615 }
2616
2617 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
2618 for (level = 0; level < count; level++) {
2619 if(table_info->vdd_dep_on_mclk->entries[level].clk >=
2620 data->vbios_boot_state.mclk_bootup_value) {
2621 data->smc_state_table.MemoryBootLevel = level;
2622 break;
2623 }
2624 }
2625
2626 return 0;
2627 }
2628
2629 static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2630 {
2631 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
2632 volt_with_cks, value;
2633 uint16_t clock_freq_u16;
2634 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2635 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
2636 volt_offset = 0;
2637 struct phm_ppt_v1_information *table_info =
2638 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2639 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2640 table_info->vdd_dep_on_sclk;
2641
2642 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
2643
2644 /* Read SMU_Eefuse to read and calculate RO and determine
2645 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
2646 */
2647 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2648 ixSMU_EFUSE_0 + (146 * 4));
2649 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2650 ixSMU_EFUSE_0 + (148 * 4));
2651 efuse &= 0xFF000000;
2652 efuse = efuse >> 24;
2653 efuse2 &= 0xF;
2654
2655 if (efuse2 == 1)
2656 ro = (2300 - 1350) * efuse / 255 + 1350;
2657 else
2658 ro = (2500 - 1000) * efuse / 255 + 1000;
2659
2660 if (ro >= 1660)
2661 type = 0;
2662 else
2663 type = 1;
2664
2665 /* Populate Stretch amount */
2666 data->smc_state_table.ClockStretcherAmount = stretch_amount;
2667
2668 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
2669 for (i = 0; i < sclk_table->count; i++) {
2670 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
2671 sclk_table->entries[i].cks_enable << i;
2672 volt_without_cks = (uint32_t)((14041 *
2673 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
2674 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
2675 volt_with_cks = (uint32_t)((13946 *
2676 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
2677 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
2678 if (volt_without_cks >= volt_with_cks)
2679 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
2680 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
2681 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
2682 }
2683
2684 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2685 STRETCH_ENABLE, 0x0);
2686 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2687 masterReset, 0x1);
2688 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2689 staticEnable, 0x1);
2690 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2691 masterReset, 0x0);
2692
2693 /* Populate CKS Lookup Table */
2694 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
2695 stretch_amount2 = 0;
2696 else if (stretch_amount == 3 || stretch_amount == 4)
2697 stretch_amount2 = 1;
2698 else {
2699 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2700 PHM_PlatformCaps_ClockStretcher);
2701 PP_ASSERT_WITH_CODE(false,
2702 "Stretch Amount in PPTable not supported\n",
2703 return -EINVAL);
2704 }
2705
2706 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2707 ixPWR_CKS_CNTL);
2708 value &= 0xFFC2FF87;
2709 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
2710 fiji_clock_stretcher_lookup_table[stretch_amount2][0];
2711 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
2712 fiji_clock_stretcher_lookup_table[stretch_amount2][1];
2713 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
2714 GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].
2715 SclkFrequency) / 100);
2716 if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
2717 clock_freq_u16 &&
2718 fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
2719 clock_freq_u16) {
2720 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2721 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
2722 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2723 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
2724 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2725 value |= (fiji_clock_stretch_amount_conversion
2726 [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
2727 [stretch_amount]) << 3;
2728 }
2729 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2730 CKS_LOOKUPTableEntry[0].minFreq);
2731 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2732 CKS_LOOKUPTableEntry[0].maxFreq);
2733 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
2734 fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
2735 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
2736 (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
2737
2738 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2739 ixPWR_CKS_CNTL, value);
2740
2741 /* Populate DDT Lookup Table */
2742 for (i = 0; i < 4; i++) {
2743 /* Assign the minimum and maximum VID stored
2744 * in the last row of Clock Stretcher Voltage Table.
2745 */
2746 data->smc_state_table.ClockStretcherDataTable.
2747 ClockStretcherDataTableEntry[i].minVID =
2748 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
2749 data->smc_state_table.ClockStretcherDataTable.
2750 ClockStretcherDataTableEntry[i].maxVID =
2751 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
2752 /* Loop through each SCLK and check the frequency
2753 * to see if it lies within the frequency for clock stretcher.
2754 */
2755 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
2756 cks_setting = 0;
2757 clock_freq = PP_SMC_TO_HOST_UL(
2758 data->smc_state_table.GraphicsLevel[j].SclkFrequency);
2759 /* Check the allowed frequency against the sclk level[j].
2760 * Sclk's endianness has already been converted,
2761 * and it's in 10Khz unit,
2762 * as opposed to Data table, which is in Mhz unit.
2763 */
2764 if (clock_freq >=
2765 (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
2766 cks_setting |= 0x2;
2767 if (clock_freq <
2768 (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
2769 cks_setting |= 0x1;
2770 }
2771 data->smc_state_table.ClockStretcherDataTable.
2772 ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
2773 }
2774 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.
2775 ClockStretcherDataTable.
2776 ClockStretcherDataTableEntry[i].setting);
2777 }
2778
2779 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
2780 value &= 0xFFFFFFFE;
2781 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
2782
2783 return 0;
2784 }
2785
2786 /**
2787 * Populates the SMC VRConfig field in DPM table.
2788 *
2789 * @param hwmgr the address of the hardware manager
2790 * @param table the SMC DPM table structure to be populated
2791 * @return always 0
2792 */
2793 static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
2794 struct SMU73_Discrete_DpmTable *table)
2795 {
2796 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2797 uint16_t config;
2798
2799 config = VR_MERGED_WITH_VDDC;
2800 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
2801
2802 /* Set Vddc Voltage Controller */
2803 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
2804 config = VR_SVI2_PLANE_1;
2805 table->VRConfig |= config;
2806 } else {
2807 PP_ASSERT_WITH_CODE(false,
2808 "VDDC should be on SVI2 control in merged mode!",);
2809 }
2810 /* Set Vddci Voltage Controller */
2811 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
2812 config = VR_SVI2_PLANE_2; /* only in merged mode */
2813 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2814 } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
2815 config = VR_SMIO_PATTERN_1;
2816 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2817 } else {
2818 config = VR_STATIC_VOLTAGE;
2819 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2820 }
2821 /* Set Mvdd Voltage Controller */
2822 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
2823 config = VR_SVI2_PLANE_2;
2824 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2825 } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
2826 config = VR_SMIO_PATTERN_2;
2827 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2828 } else {
2829 config = VR_STATIC_VOLTAGE;
2830 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2831 }
2832
2833 return 0;
2834 }
2835
2836 /**
2837 * Initializes the SMC table and uploads it
2838 *
2839 * @param hwmgr the address of the powerplay hardware manager.
2840 * @param pInput the pointer to input data (PowerState)
2841 * @return always 0
2842 */
2843 static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
2844 {
2845 int result;
2846 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2847 struct phm_ppt_v1_information *table_info =
2848 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2849 struct SMU73_Discrete_DpmTable *table = &(data->smc_state_table);
2850 const struct fiji_ulv_parm *ulv = &(data->ulv);
2851 uint8_t i;
2852 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2853
2854 result = fiji_setup_default_dpm_tables(hwmgr);
2855 PP_ASSERT_WITH_CODE(0 == result,
2856 "Failed to setup default DPM tables!", return result);
2857
2858 if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
2859 fiji_populate_smc_voltage_tables(hwmgr, table);
2860
2861 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2862 PHM_PlatformCaps_AutomaticDCTransition))
2863 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2864
2865 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2866 PHM_PlatformCaps_StepVddc))
2867 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2868
2869 if (data->is_memory_gddr5)
2870 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2871
2872 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2873 result = fiji_populate_ulv_state(hwmgr, table);
2874 PP_ASSERT_WITH_CODE(0 == result,
2875 "Failed to initialize ULV state!", return result);
2876 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2877 ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
2878 }
2879
2880 result = fiji_populate_smc_link_level(hwmgr, table);
2881 PP_ASSERT_WITH_CODE(0 == result,
2882 "Failed to initialize Link Level!", return result);
2883
2884 result = fiji_populate_all_graphic_levels(hwmgr);
2885 PP_ASSERT_WITH_CODE(0 == result,
2886 "Failed to initialize Graphics Level!", return result);
2887
2888 result = fiji_populate_all_memory_levels(hwmgr);
2889 PP_ASSERT_WITH_CODE(0 == result,
2890 "Failed to initialize Memory Level!", return result);
2891
2892 result = fiji_populate_smc_acpi_level(hwmgr, table);
2893 PP_ASSERT_WITH_CODE(0 == result,
2894 "Failed to initialize ACPI Level!", return result);
2895
2896 result = fiji_populate_smc_vce_level(hwmgr, table);
2897 PP_ASSERT_WITH_CODE(0 == result,
2898 "Failed to initialize VCE Level!", return result);
2899
2900 result = fiji_populate_smc_acp_level(hwmgr, table);
2901 PP_ASSERT_WITH_CODE(0 == result,
2902 "Failed to initialize ACP Level!", return result);
2903
2904 result = fiji_populate_smc_samu_level(hwmgr, table);
2905 PP_ASSERT_WITH_CODE(0 == result,
2906 "Failed to initialize SAMU Level!", return result);
2907
2908 /* Since only the initial state is completely set up at this point
2909 * (the other states are just copies of the boot state) we only
2910 * need to populate the ARB settings for the initial state.
2911 */
2912 result = fiji_program_memory_timing_parameters(hwmgr);
2913 PP_ASSERT_WITH_CODE(0 == result,
2914 "Failed to Write ARB settings for the initial state.", return result);
2915
2916 result = fiji_populate_smc_uvd_level(hwmgr, table);
2917 PP_ASSERT_WITH_CODE(0 == result,
2918 "Failed to initialize UVD Level!", return result);
2919
2920 result = fiji_populate_smc_boot_level(hwmgr, table);
2921 PP_ASSERT_WITH_CODE(0 == result,
2922 "Failed to initialize Boot Level!", return result);
2923
2924 result = fiji_populate_smc_initailial_state(hwmgr);
2925 PP_ASSERT_WITH_CODE(0 == result,
2926 "Failed to initialize Boot State!", return result);
2927
2928 result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
2929 PP_ASSERT_WITH_CODE(0 == result,
2930 "Failed to populate BAPM Parameters!", return result);
2931
2932 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2933 PHM_PlatformCaps_ClockStretcher)) {
2934 result = fiji_populate_clock_stretcher_data_table(hwmgr);
2935 PP_ASSERT_WITH_CODE(0 == result,
2936 "Failed to populate Clock Stretcher Data Table!",
2937 return result);
2938 }
2939
2940 table->GraphicsVoltageChangeEnable = 1;
2941 table->GraphicsThermThrottleEnable = 1;
2942 table->GraphicsInterval = 1;
2943 table->VoltageInterval = 1;
2944 table->ThermalInterval = 1;
2945 table->TemperatureLimitHigh =
2946 table_info->cac_dtp_table->usTargetOperatingTemp *
2947 FIJI_Q88_FORMAT_CONVERSION_UNIT;
2948 table->TemperatureLimitLow =
2949 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2950 FIJI_Q88_FORMAT_CONVERSION_UNIT;
2951 table->MemoryVoltageChangeEnable = 1;
2952 table->MemoryInterval = 1;
2953 table->VoltageResponseTime = 0;
2954 table->PhaseResponseTime = 0;
2955 table->MemoryThermThrottleEnable = 1;
2956 table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/
2957 table->PCIeGenInterval = 1;
2958
2959 result = fiji_populate_vr_config(hwmgr, table);
2960 PP_ASSERT_WITH_CODE(0 == result,
2961 "Failed to populate VRConfig setting!", return result);
2962
2963 table->ThermGpio = 17;
2964 table->SclkStepSize = 0x4000;
2965
2966 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2967 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2968 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2969 PHM_PlatformCaps_RegulatorHot);
2970 } else {
2971 table->VRHotGpio = FIJI_UNUSED_GPIO_PIN;
2972 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2973 PHM_PlatformCaps_RegulatorHot);
2974 }
2975
2976 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2977 &gpio_pin)) {
2978 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2979 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2980 PHM_PlatformCaps_AutomaticDCTransition);
2981 } else {
2982 table->AcDcGpio = FIJI_UNUSED_GPIO_PIN;
2983 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2984 PHM_PlatformCaps_AutomaticDCTransition);
2985 }
2986
2987 /* Thermal Output GPIO */
2988 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2989 &gpio_pin)) {
2990 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2991 PHM_PlatformCaps_ThermalOutGPIO);
2992
2993 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2994
2995 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2996 * since VBIOS will program this register to set 'inactive state',
2997 * driver can then determine 'active state' from this and
2998 * program SMU with correct polarity
2999 */
3000 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3001 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
3002 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3003
3004 /* if required, combine VRHot/PCC with thermal out GPIO */
3005 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3006 PHM_PlatformCaps_RegulatorHot) &&
3007 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3008 PHM_PlatformCaps_CombinePCCWithThermalSignal))
3009 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3010 } else {
3011 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3012 PHM_PlatformCaps_ThermalOutGPIO);
3013 table->ThermOutGpio = 17;
3014 table->ThermOutPolarity = 1;
3015 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3016 }
3017
3018 for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
3019 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3020
3021 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3022 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3023 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3024 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3025 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3026 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3027 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3028 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3029 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3030
3031 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3032 result = fiji_copy_bytes_to_smc(hwmgr->smumgr,
3033 data->dpm_table_start +
3034 offsetof(SMU73_Discrete_DpmTable, SystemFlags),
3035 (uint8_t *)&(table->SystemFlags),
3036 sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
3037 data->sram_end);
3038 PP_ASSERT_WITH_CODE(0 == result,
3039 "Failed to upload dpm data to SMC memory!", return result);
3040
3041 return 0;
3042 }
3043
3044 /**
3045 * Initialize the ARB DRAM timing table's index field.
3046 *
3047 * @param hwmgr the address of the powerplay hardware manager.
3048 * @return always 0
3049 */
3050 static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
3051 {
3052 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3053 uint32_t tmp;
3054 int result;
3055
3056 /* This is a read-modify-write on the first byte of the ARB table.
3057 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
3058 * is the field 'current'.
3059 * This solution is ugly, but we never write the whole table only
3060 * individual fields in it.
3061 * In reality this field should not be in that structure
3062 * but in a soft register.
3063 */
3064 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
3065 data->arb_table_start, &tmp, data->sram_end);
3066
3067 if (result)
3068 return result;
3069
3070 tmp &= 0x00FFFFFF;
3071 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
3072
3073 return fiji_write_smc_sram_dword(hwmgr->smumgr,
3074 data->arb_table_start, tmp, data->sram_end);
3075 }
3076
3077 static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
3078 {
3079 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3080 PHM_PlatformCaps_RegulatorHot))
3081 return smum_send_msg_to_smc(hwmgr->smumgr,
3082 PPSMC_MSG_EnableVRHotGPIOInterrupt);
3083
3084 return 0;
3085 }
3086
3087 static int fiji_enable_sclk_control(struct pp_hwmgr *hwmgr)
3088 {
3089 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3090 SCLK_PWRMGT_OFF, 0);
3091 return 0;
3092 }
3093
3094 static int fiji_enable_ulv(struct pp_hwmgr *hwmgr)
3095 {
3096 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3097 struct fiji_ulv_parm *ulv = &(data->ulv);
3098
3099 if (ulv->ulv_supported)
3100 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
3101
3102 return 0;
3103 }
3104
3105 static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
3106 {
3107 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3108 PHM_PlatformCaps_SclkDeepSleep)) {
3109 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
3110 PP_ASSERT_WITH_CODE(false,
3111 "Attempt to enable Master Deep Sleep switch failed!",
3112 return -1);
3113 } else {
3114 if (smum_send_msg_to_smc(hwmgr->smumgr,
3115 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
3116 PP_ASSERT_WITH_CODE(false,
3117 "Attempt to disable Master Deep Sleep switch failed!",
3118 return -1);
3119 }
3120 }
3121
3122 return 0;
3123 }
3124
3125 static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3126 {
3127 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3128 uint32_t val, val0, val2;
3129 uint32_t i, cpl_cntl, cpl_threshold, mc_threshold;
3130
3131 /* enable SCLK dpm */
3132 if(!data->sclk_dpm_key_disabled)
3133 PP_ASSERT_WITH_CODE(
3134 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
3135 "Failed to enable SCLK DPM during DPM Start Function!",
3136 return -1);
3137
3138 /* enable MCLK dpm */
3139 if(0 == data->mclk_dpm_key_disabled) {
3140 cpl_threshold = 0;
3141 mc_threshold = 0;
3142
3143 /* Read per MCD tile (0 - 7) */
3144 for (i = 0; i < 8; i++) {
3145 PHM_WRITE_FIELD(hwmgr->device, MC_CONFIG_MCD, MC_RD_ENABLE, i);
3146 val = cgs_read_register(hwmgr->device, mmMC_SEQ_RESERVE_0_S) & 0xf0000000;
3147 if (0xf0000000 != val) {
3148 /* count number of MCQ that has channel(s) enabled */
3149 cpl_threshold++;
3150 /* only harvest 3 or full 4 supported */
3151 mc_threshold = val ? 3 : 4;
3152 }
3153 }
3154 PP_ASSERT_WITH_CODE(0 != cpl_threshold,
3155 "Number of MCQ is zero!", return -EINVAL;);
3156
3157 mc_threshold = ((mc_threshold & LCAC_MC0_CNTL__MC0_THRESHOLD_MASK) <<
3158 LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT) |
3159 LCAC_MC0_CNTL__MC0_ENABLE_MASK;
3160 cpl_cntl = ((cpl_threshold & LCAC_CPL_CNTL__CPL_THRESHOLD_MASK) <<
3161 LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT) |
3162 LCAC_CPL_CNTL__CPL_ENABLE_MASK;
3163 cpl_cntl = (cpl_cntl | (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT));
3164 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3165 ixLCAC_MC0_CNTL, mc_threshold);
3166 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3167 ixLCAC_MC1_CNTL, mc_threshold);
3168 if (8 == cpl_threshold) {
3169 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3170 ixLCAC_MC2_CNTL, mc_threshold);
3171 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3172 ixLCAC_MC3_CNTL, mc_threshold);
3173 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3174 ixLCAC_MC4_CNTL, mc_threshold);
3175 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3176 ixLCAC_MC5_CNTL, mc_threshold);
3177 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3178 ixLCAC_MC6_CNTL, mc_threshold);
3179 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3180 ixLCAC_MC7_CNTL, mc_threshold);
3181 }
3182 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3183 ixLCAC_CPL_CNTL, cpl_cntl);
3184
3185 udelay(5);
3186
3187 mc_threshold = mc_threshold |
3188 (1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT);
3189 cpl_cntl = cpl_cntl | (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT);
3190 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3191 ixLCAC_MC0_CNTL, mc_threshold);
3192 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3193 ixLCAC_MC1_CNTL, mc_threshold);
3194 if (8 == cpl_threshold) {
3195 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3196 ixLCAC_MC2_CNTL, mc_threshold);
3197 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3198 ixLCAC_MC3_CNTL, mc_threshold);
3199 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3200 ixLCAC_MC4_CNTL, mc_threshold);
3201 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3202 ixLCAC_MC5_CNTL, mc_threshold);
3203 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3204 ixLCAC_MC6_CNTL, mc_threshold);
3205 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3206 ixLCAC_MC7_CNTL, mc_threshold);
3207 }
3208 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3209 ixLCAC_CPL_CNTL, cpl_cntl);
3210
3211 /* Program CAC_EN per MCD (0-7) Tile */
3212 val0 = val = cgs_read_register(hwmgr->device, mmMC_CONFIG_MCD);
3213 val &= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK |
3214 MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK |
3215 MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK |
3216 MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK |
3217 MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK |
3218 MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK |
3219 MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK |
3220 MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK |
3221 MC_CONFIG_MCD__MC_RD_ENABLE_MASK);
3222
3223 for (i = 0; i < 8; i++) {
3224 /* Enable MCD i Tile read & write */
3225 val2 = (val | (i << MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT) |
3226 (1 << i));
3227 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val2);
3228 /* Enbale CAC_ON MCD i Tile */
3229 val2 = cgs_read_register(hwmgr->device, mmMC_SEQ_CNTL);
3230 val2 |= MC_SEQ_CNTL__CAC_EN_MASK;
3231 cgs_write_register(hwmgr->device, mmMC_SEQ_CNTL, val2);
3232 }
3233 /* Set MC_CONFIG_MCD back to its default setting val0 */
3234 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val0);
3235
3236 PP_ASSERT_WITH_CODE(
3237 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3238 PPSMC_MSG_MCLKDPM_Enable)),
3239 "Failed to enable MCLK DPM during DPM Start Function!",
3240 return -1);
3241 }
3242 return 0;
3243 }
3244
3245 static int fiji_start_dpm(struct pp_hwmgr *hwmgr)
3246 {
3247 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3248
3249 /*enable general power management */
3250 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3251 GLOBAL_PWRMGT_EN, 1);
3252 /* enable sclk deep sleep */
3253 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3254 DYNAMIC_PM_EN, 1);
3255 /* prepare for PCIE DPM */
3256 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3257 data->soft_regs_start + offsetof(SMU73_SoftRegisters,
3258 VoltageChangeTimeout), 0x1000);
3259 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
3260 SWRST_COMMAND_1, RESETLC, 0x0);
3261
3262 PP_ASSERT_WITH_CODE(
3263 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3264 PPSMC_MSG_Voltage_Cntl_Enable)),
3265 "Failed to enable voltage DPM during DPM Start Function!",
3266 return -1);
3267
3268 if (fiji_enable_sclk_mclk_dpm(hwmgr)) {
3269 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
3270 return -1;
3271 }
3272
3273 /* enable PCIE dpm */
3274 if(!data->pcie_dpm_key_disabled) {
3275 PP_ASSERT_WITH_CODE(
3276 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3277 PPSMC_MSG_PCIeDPM_Enable)),
3278 "Failed to enable pcie DPM during DPM Start Function!",
3279 return -1);
3280 }
3281
3282 return 0;
3283 }
3284
3285 static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
3286 uint32_t sources)
3287 {
3288 bool protection;
3289 enum DPM_EVENT_SRC src;
3290
3291 switch (sources) {
3292 default:
3293 printk(KERN_ERR "Unknown throttling event sources.");
3294 /* fall through */
3295 case 0:
3296 protection = false;
3297 /* src is unused */
3298 break;
3299 case (1 << PHM_AutoThrottleSource_Thermal):
3300 protection = true;
3301 src = DPM_EVENT_SRC_DIGITAL;
3302 break;
3303 case (1 << PHM_AutoThrottleSource_External):
3304 protection = true;
3305 src = DPM_EVENT_SRC_EXTERNAL;
3306 break;
3307 case (1 << PHM_AutoThrottleSource_External) |
3308 (1 << PHM_AutoThrottleSource_Thermal):
3309 protection = true;
3310 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
3311 break;
3312 }
3313 /* Order matters - don't enable thermal protection for the wrong source. */
3314 if (protection) {
3315 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
3316 DPM_EVENT_SRC, src);
3317 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3318 THERMAL_PROTECTION_DIS,
3319 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3320 PHM_PlatformCaps_ThermalController));
3321 } else
3322 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3323 THERMAL_PROTECTION_DIS, 1);
3324 }
3325
3326 static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
3327 PHM_AutoThrottleSource source)
3328 {
3329 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3330
3331 if (!(data->active_auto_throttle_sources & (1 << source))) {
3332 data->active_auto_throttle_sources |= 1 << source;
3333 fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
3334 }
3335 return 0;
3336 }
3337
3338 static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
3339 {
3340 return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
3341 }
3342
3343 static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3344 {
3345 int tmp_result, result = 0;
3346
3347 tmp_result = (!fiji_is_dpm_running(hwmgr))? 0 : -1;
3348 PP_ASSERT_WITH_CODE(result == 0,
3349 "DPM is already running right now, no need to enable DPM!",
3350 return 0);
3351
3352 if (fiji_voltage_control(hwmgr)) {
3353 tmp_result = fiji_enable_voltage_control(hwmgr);
3354 PP_ASSERT_WITH_CODE(tmp_result == 0,
3355 "Failed to enable voltage control!",
3356 result = tmp_result);
3357 }
3358
3359 if (fiji_voltage_control(hwmgr)) {
3360 tmp_result = fiji_construct_voltage_tables(hwmgr);
3361 PP_ASSERT_WITH_CODE((0 == tmp_result),
3362 "Failed to contruct voltage tables!",
3363 result = tmp_result);
3364 }
3365
3366 tmp_result = fiji_initialize_mc_reg_table(hwmgr);
3367 PP_ASSERT_WITH_CODE((0 == tmp_result),
3368 "Failed to initialize MC reg table!", result = tmp_result);
3369
3370 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3371 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
3372 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3373 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
3374
3375 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3376 PHM_PlatformCaps_ThermalController))
3377 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3378 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
3379
3380 tmp_result = fiji_program_static_screen_threshold_parameters(hwmgr);
3381 PP_ASSERT_WITH_CODE((0 == tmp_result),
3382 "Failed to program static screen threshold parameters!",
3383 result = tmp_result);
3384
3385 tmp_result = fiji_enable_display_gap(hwmgr);
3386 PP_ASSERT_WITH_CODE((0 == tmp_result),
3387 "Failed to enable display gap!", result = tmp_result);
3388
3389 tmp_result = fiji_program_voting_clients(hwmgr);
3390 PP_ASSERT_WITH_CODE((0 == tmp_result),
3391 "Failed to program voting clients!", result = tmp_result);
3392
3393 tmp_result = fiji_process_firmware_header(hwmgr);
3394 PP_ASSERT_WITH_CODE((0 == tmp_result),
3395 "Failed to process firmware header!", result = tmp_result);
3396
3397 tmp_result = fiji_initial_switch_from_arbf0_to_f1(hwmgr);
3398 PP_ASSERT_WITH_CODE((0 == tmp_result),
3399 "Failed to initialize switch from ArbF0 to F1!",
3400 result = tmp_result);
3401
3402 tmp_result = fiji_init_smc_table(hwmgr);
3403 PP_ASSERT_WITH_CODE((0 == tmp_result),
3404 "Failed to initialize SMC table!", result = tmp_result);
3405
3406 tmp_result = fiji_init_arb_table_index(hwmgr);
3407 PP_ASSERT_WITH_CODE((0 == tmp_result),
3408 "Failed to initialize ARB table index!", result = tmp_result);
3409
3410 tmp_result = fiji_populate_pm_fuses(hwmgr);
3411 PP_ASSERT_WITH_CODE((0 == tmp_result),
3412 "Failed to populate PM fuses!", result = tmp_result);
3413
3414 tmp_result = fiji_enable_vrhot_gpio_interrupt(hwmgr);
3415 PP_ASSERT_WITH_CODE((0 == tmp_result),
3416 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
3417
3418 tmp_result = fiji_enable_sclk_control(hwmgr);
3419 PP_ASSERT_WITH_CODE((0 == tmp_result),
3420 "Failed to enable SCLK control!", result = tmp_result);
3421
3422 tmp_result = fiji_enable_ulv(hwmgr);
3423 PP_ASSERT_WITH_CODE((0 == tmp_result),
3424 "Failed to enable ULV!", result = tmp_result);
3425
3426 tmp_result = fiji_enable_deep_sleep_master_switch(hwmgr);
3427 PP_ASSERT_WITH_CODE((0 == tmp_result),
3428 "Failed to enable deep sleep master switch!", result = tmp_result);
3429
3430 tmp_result = fiji_start_dpm(hwmgr);
3431 PP_ASSERT_WITH_CODE((0 == tmp_result),
3432 "Failed to start DPM!", result = tmp_result);
3433
3434 tmp_result = fiji_enable_smc_cac(hwmgr);
3435 PP_ASSERT_WITH_CODE((0 == tmp_result),
3436 "Failed to enable SMC CAC!", result = tmp_result);
3437
3438 tmp_result = fiji_enable_power_containment(hwmgr);
3439 PP_ASSERT_WITH_CODE((0 == tmp_result),
3440 "Failed to enable power containment!", result = tmp_result);
3441
3442 tmp_result = fiji_power_control_set_level(hwmgr);
3443 PP_ASSERT_WITH_CODE((0 == tmp_result),
3444 "Failed to power control set level!", result = tmp_result);
3445
3446 tmp_result = fiji_enable_thermal_auto_throttle(hwmgr);
3447 PP_ASSERT_WITH_CODE((0 == tmp_result),
3448 "Failed to enable thermal auto throttle!", result = tmp_result);
3449
3450 return result;
3451 }
3452
3453 static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
3454 {
3455 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3456 uint32_t level, tmp;
3457
3458 if (!data->sclk_dpm_key_disabled) {
3459 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3460 level = 0;
3461 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3462 while (tmp >>= 1)
3463 level++;
3464 if (level)
3465 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3466 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3467 (1 << level));
3468 }
3469 }
3470
3471 if (!data->mclk_dpm_key_disabled) {
3472 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3473 level = 0;
3474 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3475 while (tmp >>= 1)
3476 level++;
3477 if (level)
3478 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3479 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3480 (1 << level));
3481 }
3482 }
3483
3484 if (!data->pcie_dpm_key_disabled) {
3485 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3486 level = 0;
3487 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3488 while (tmp >>= 1)
3489 level++;
3490 if (level)
3491 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3492 PPSMC_MSG_PCIeDPM_ForceLevel,
3493 (1 << level));
3494 }
3495 }
3496 return 0;
3497 }
3498
3499 static void fiji_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
3500 {
3501 struct phm_ppt_v1_information *table_info =
3502 (struct phm_ppt_v1_information *)hwmgr->pptable;
3503 struct phm_clock_voltage_dependency_table *table =
3504 table_info->vddc_dep_on_dal_pwrl;
3505 struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
3506 enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
3507 uint32_t req_vddc = 0, req_volt, i;
3508
3509 if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
3510 dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
3511 return;
3512
3513 for (i= 0; i < table->count; i++) {
3514 if (dal_power_level == table->entries[i].clk) {
3515 req_vddc = table->entries[i].v;
3516 break;
3517 }
3518 }
3519
3520 vddc_table = table_info->vdd_dep_on_sclk;
3521 for (i= 0; i < vddc_table->count; i++) {
3522 if (req_vddc <= vddc_table->entries[i].vddc) {
3523 req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
3524 << VDDC_SHIFT;
3525 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3526 PPSMC_MSG_VddC_Request, req_volt);
3527 return;
3528 }
3529 }
3530 printk(KERN_ERR "DAL requested level can not"
3531 " found a available voltage in VDDC DPM Table \n");
3532 }
3533
3534 static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr)
3535 {
3536 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3537
3538 fiji_apply_dal_min_voltage_request(hwmgr);
3539
3540 if (!data->sclk_dpm_key_disabled) {
3541 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3542 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3543 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3544 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3545 }
3546 return 0;
3547 }
3548
3549 static int fiji_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3550 {
3551 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3552
3553 if (!fiji_is_dpm_running(hwmgr))
3554 return -EINVAL;
3555
3556 if (!data->pcie_dpm_key_disabled) {
3557 smum_send_msg_to_smc(hwmgr->smumgr,
3558 PPSMC_MSG_PCIeDPM_UnForceLevel);
3559 }
3560
3561 return fiji_upload_dpmlevel_enable_mask(hwmgr);
3562 }
3563
3564 static uint32_t fiji_get_lowest_enabled_level(
3565 struct pp_hwmgr *hwmgr, uint32_t mask)
3566 {
3567 uint32_t level = 0;
3568
3569 while(0 == (mask & (1 << level)))
3570 level++;
3571
3572 return level;
3573 }
3574
3575 static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3576 {
3577 struct fiji_hwmgr *data =
3578 (struct fiji_hwmgr *)(hwmgr->backend);
3579 uint32_t level;
3580
3581 if (!data->sclk_dpm_key_disabled)
3582 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3583 level = fiji_get_lowest_enabled_level(hwmgr,
3584 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3585 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3586 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3587 (1 << level));
3588
3589 }
3590
3591 if (!data->mclk_dpm_key_disabled) {
3592 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3593 level = fiji_get_lowest_enabled_level(hwmgr,
3594 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3595 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3596 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3597 (1 << level));
3598 }
3599 }
3600
3601 if (!data->pcie_dpm_key_disabled) {
3602 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3603 level = fiji_get_lowest_enabled_level(hwmgr,
3604 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3605 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3606 PPSMC_MSG_PCIeDPM_ForceLevel,
3607 (1 << level));
3608 }
3609 }
3610
3611 return 0;
3612
3613 }
3614 static int fiji_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
3615 enum amd_dpm_forced_level level)
3616 {
3617 int ret = 0;
3618
3619 switch (level) {
3620 case AMD_DPM_FORCED_LEVEL_HIGH:
3621 ret = fiji_force_dpm_highest(hwmgr);
3622 if (ret)
3623 return ret;
3624 break;
3625 case AMD_DPM_FORCED_LEVEL_LOW:
3626 ret = fiji_force_dpm_lowest(hwmgr);
3627 if (ret)
3628 return ret;
3629 break;
3630 case AMD_DPM_FORCED_LEVEL_AUTO:
3631 ret = fiji_unforce_dpm_levels(hwmgr);
3632 if (ret)
3633 return ret;
3634 break;
3635 default:
3636 break;
3637 }
3638
3639 hwmgr->dpm_level = level;
3640
3641 return ret;
3642 }
3643
3644 static int fiji_get_power_state_size(struct pp_hwmgr *hwmgr)
3645 {
3646 return sizeof(struct fiji_power_state);
3647 }
3648
3649 static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3650 void *state, struct pp_power_state *power_state,
3651 void *pp_table, uint32_t classification_flag)
3652 {
3653 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3654 struct fiji_power_state *fiji_power_state =
3655 (struct fiji_power_state *)(&(power_state->hardware));
3656 struct fiji_performance_level *performance_level;
3657 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3658 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3659 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3660 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3661 (ATOM_Tonga_SCLK_Dependency_Table *)
3662 (((unsigned long)powerplay_table) +
3663 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3664 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3665 (ATOM_Tonga_MCLK_Dependency_Table *)
3666 (((unsigned long)powerplay_table) +
3667 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3668
3669 /* The following fields are not initialized here: id orderedList allStatesList */
3670 power_state->classification.ui_label =
3671 (le16_to_cpu(state_entry->usClassification) &
3672 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3673 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3674 power_state->classification.flags = classification_flag;
3675 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3676
3677 power_state->classification.temporary_state = false;
3678 power_state->classification.to_be_deleted = false;
3679
3680 power_state->validation.disallowOnDC =
3681 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3682 ATOM_Tonga_DISALLOW_ON_DC));
3683
3684 power_state->pcie.lanes = 0;
3685
3686 power_state->display.disableFrameModulation = false;
3687 power_state->display.limitRefreshrate = false;
3688 power_state->display.enableVariBright =
3689 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3690 ATOM_Tonga_ENABLE_VARIBRIGHT));
3691
3692 power_state->validation.supportedPowerLevels = 0;
3693 power_state->uvd_clocks.VCLK = 0;
3694 power_state->uvd_clocks.DCLK = 0;
3695 power_state->temperatures.min = 0;
3696 power_state->temperatures.max = 0;
3697
3698 performance_level = &(fiji_power_state->performance_levels
3699 [fiji_power_state->performance_level_count++]);
3700
3701 PP_ASSERT_WITH_CODE(
3702 (fiji_power_state->performance_level_count < SMU73_MAX_LEVELS_GRAPHICS),
3703 "Performance levels exceeds SMC limit!",
3704 return -1);
3705
3706 PP_ASSERT_WITH_CODE(
3707 (fiji_power_state->performance_level_count <=
3708 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3709 "Performance levels exceeds Driver limit!",
3710 return -1);
3711
3712 /* Performance levels are arranged from low to high. */
3713 performance_level->memory_clock = mclk_dep_table->entries
3714 [state_entry->ucMemoryClockIndexLow].ulMclk;
3715 performance_level->engine_clock = sclk_dep_table->entries
3716 [state_entry->ucEngineClockIndexLow].ulSclk;
3717 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3718 state_entry->ucPCIEGenLow);
3719 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3720 state_entry->ucPCIELaneHigh);
3721
3722 performance_level = &(fiji_power_state->performance_levels
3723 [fiji_power_state->performance_level_count++]);
3724 performance_level->memory_clock = mclk_dep_table->entries
3725 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3726 performance_level->engine_clock = sclk_dep_table->entries
3727 [state_entry->ucEngineClockIndexHigh].ulSclk;
3728 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3729 state_entry->ucPCIEGenHigh);
3730 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3731 state_entry->ucPCIELaneHigh);
3732
3733 return 0;
3734 }
3735
3736 static int fiji_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3737 unsigned long entry_index, struct pp_power_state *state)
3738 {
3739 int result;
3740 struct fiji_power_state *ps;
3741 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3742 struct phm_ppt_v1_information *table_info =
3743 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3744 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3745 table_info->vdd_dep_on_mclk;
3746
3747 state->hardware.magic = PHM_VIslands_Magic;
3748
3749 ps = (struct fiji_power_state *)(&state->hardware);
3750
3751 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3752 fiji_get_pp_table_entry_callback_func);
3753
3754 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3755 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3756 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3757 */
3758 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3759 if (dep_mclk_table->entries[0].clk !=
3760 data->vbios_boot_state.mclk_bootup_value)
3761 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3762 "does not match VBIOS boot MCLK level");
3763 if (dep_mclk_table->entries[0].vddci !=
3764 data->vbios_boot_state.vddci_bootup_value)
3765 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3766 "does not match VBIOS boot VDDCI level");
3767 }
3768
3769 /* set DC compatible flag if this state supports DC */
3770 if (!state->validation.disallowOnDC)
3771 ps->dc_compatible = true;
3772
3773 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3774 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3775
3776 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3777 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3778
3779 if (!result) {
3780 uint32_t i;
3781
3782 switch (state->classification.ui_label) {
3783 case PP_StateUILabel_Performance:
3784 data->use_pcie_performance_levels = true;
3785
3786 for (i = 0; i < ps->performance_level_count; i++) {
3787 if (data->pcie_gen_performance.max <
3788 ps->performance_levels[i].pcie_gen)
3789 data->pcie_gen_performance.max =
3790 ps->performance_levels[i].pcie_gen;
3791
3792 if (data->pcie_gen_performance.min >
3793 ps->performance_levels[i].pcie_gen)
3794 data->pcie_gen_performance.min =
3795 ps->performance_levels[i].pcie_gen;
3796
3797 if (data->pcie_lane_performance.max <
3798 ps->performance_levels[i].pcie_lane)
3799 data->pcie_lane_performance.max =
3800 ps->performance_levels[i].pcie_lane;
3801
3802 if (data->pcie_lane_performance.min >
3803 ps->performance_levels[i].pcie_lane)
3804 data->pcie_lane_performance.min =
3805 ps->performance_levels[i].pcie_lane;
3806 }
3807 break;
3808 case PP_StateUILabel_Battery:
3809 data->use_pcie_power_saving_levels = true;
3810
3811 for (i = 0; i < ps->performance_level_count; i++) {
3812 if (data->pcie_gen_power_saving.max <
3813 ps->performance_levels[i].pcie_gen)
3814 data->pcie_gen_power_saving.max =
3815 ps->performance_levels[i].pcie_gen;
3816
3817 if (data->pcie_gen_power_saving.min >
3818 ps->performance_levels[i].pcie_gen)
3819 data->pcie_gen_power_saving.min =
3820 ps->performance_levels[i].pcie_gen;
3821
3822 if (data->pcie_lane_power_saving.max <
3823 ps->performance_levels[i].pcie_lane)
3824 data->pcie_lane_power_saving.max =
3825 ps->performance_levels[i].pcie_lane;
3826
3827 if (data->pcie_lane_power_saving.min >
3828 ps->performance_levels[i].pcie_lane)
3829 data->pcie_lane_power_saving.min =
3830 ps->performance_levels[i].pcie_lane;
3831 }
3832 break;
3833 default:
3834 break;
3835 }
3836 }
3837 return 0;
3838 }
3839
3840 static int fiji_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3841 struct pp_power_state *request_ps,
3842 const struct pp_power_state *current_ps)
3843 {
3844 struct fiji_power_state *fiji_ps =
3845 cast_phw_fiji_power_state(&request_ps->hardware);
3846 uint32_t sclk;
3847 uint32_t mclk;
3848 struct PP_Clocks minimum_clocks = {0};
3849 bool disable_mclk_switching;
3850 bool disable_mclk_switching_for_frame_lock;
3851 struct cgs_display_info info = {0};
3852 const struct phm_clock_and_voltage_limits *max_limits;
3853 uint32_t i;
3854 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3855 struct phm_ppt_v1_information *table_info =
3856 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3857 int32_t count;
3858 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3859
3860 data->battery_state = (PP_StateUILabel_Battery ==
3861 request_ps->classification.ui_label);
3862
3863 PP_ASSERT_WITH_CODE(fiji_ps->performance_level_count == 2,
3864 "VI should always have 2 performance levels",);
3865
3866 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3867 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3868 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3869
3870 /* Cap clock DPM tables at DC MAX if it is in DC. */
3871 if (PP_PowerSource_DC == hwmgr->power_source) {
3872 for (i = 0; i < fiji_ps->performance_level_count; i++) {
3873 if (fiji_ps->performance_levels[i].memory_clock > max_limits->mclk)
3874 fiji_ps->performance_levels[i].memory_clock = max_limits->mclk;
3875 if (fiji_ps->performance_levels[i].engine_clock > max_limits->sclk)
3876 fiji_ps->performance_levels[i].engine_clock = max_limits->sclk;
3877 }
3878 }
3879
3880 fiji_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3881 fiji_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3882
3883 fiji_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
3884
3885 cgs_get_active_displays_info(hwmgr->device, &info);
3886
3887 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3888
3889 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3890
3891 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3892 PHM_PlatformCaps_StablePState)) {
3893 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3894 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3895
3896 for (count = table_info->vdd_dep_on_sclk->count - 1;
3897 count >= 0; count--) {
3898 if (stable_pstate_sclk >=
3899 table_info->vdd_dep_on_sclk->entries[count].clk) {
3900 stable_pstate_sclk =
3901 table_info->vdd_dep_on_sclk->entries[count].clk;
3902 break;
3903 }
3904 }
3905
3906 if (count < 0)
3907 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3908
3909 stable_pstate_mclk = max_limits->mclk;
3910
3911 minimum_clocks.engineClock = stable_pstate_sclk;
3912 minimum_clocks.memoryClock = stable_pstate_mclk;
3913 }
3914
3915 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3916 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3917
3918 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3919 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3920
3921 fiji_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3922
3923 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3924 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3925 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3926 "Overdrive sclk exceeds limit",
3927 hwmgr->gfx_arbiter.sclk_over_drive =
3928 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3929
3930 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3931 fiji_ps->performance_levels[1].engine_clock =
3932 hwmgr->gfx_arbiter.sclk_over_drive;
3933 }
3934
3935 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3936 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3937 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3938 "Overdrive mclk exceeds limit",
3939 hwmgr->gfx_arbiter.mclk_over_drive =
3940 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3941
3942 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3943 fiji_ps->performance_levels[1].memory_clock =
3944 hwmgr->gfx_arbiter.mclk_over_drive;
3945 }
3946
3947 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3948 hwmgr->platform_descriptor.platformCaps,
3949 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3950
3951 disable_mclk_switching = (1 < info.display_count) ||
3952 disable_mclk_switching_for_frame_lock;
3953
3954 sclk = fiji_ps->performance_levels[0].engine_clock;
3955 mclk = fiji_ps->performance_levels[0].memory_clock;
3956
3957 if (disable_mclk_switching)
3958 mclk = fiji_ps->performance_levels
3959 [fiji_ps->performance_level_count - 1].memory_clock;
3960
3961 if (sclk < minimum_clocks.engineClock)
3962 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3963 max_limits->sclk : minimum_clocks.engineClock;
3964
3965 if (mclk < minimum_clocks.memoryClock)
3966 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3967 max_limits->mclk : minimum_clocks.memoryClock;
3968
3969 fiji_ps->performance_levels[0].engine_clock = sclk;
3970 fiji_ps->performance_levels[0].memory_clock = mclk;
3971
3972 fiji_ps->performance_levels[1].engine_clock =
3973 (fiji_ps->performance_levels[1].engine_clock >=
3974 fiji_ps->performance_levels[0].engine_clock) ?
3975 fiji_ps->performance_levels[1].engine_clock :
3976 fiji_ps->performance_levels[0].engine_clock;
3977
3978 if (disable_mclk_switching) {
3979 if (mclk < fiji_ps->performance_levels[1].memory_clock)
3980 mclk = fiji_ps->performance_levels[1].memory_clock;
3981
3982 fiji_ps->performance_levels[0].memory_clock = mclk;
3983 fiji_ps->performance_levels[1].memory_clock = mclk;
3984 } else {
3985 if (fiji_ps->performance_levels[1].memory_clock <
3986 fiji_ps->performance_levels[0].memory_clock)
3987 fiji_ps->performance_levels[1].memory_clock =
3988 fiji_ps->performance_levels[0].memory_clock;
3989 }
3990
3991 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3992 PHM_PlatformCaps_StablePState)) {
3993 for (i = 0; i < fiji_ps->performance_level_count; i++) {
3994 fiji_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3995 fiji_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3996 fiji_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3997 fiji_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3998 }
3999 }
4000
4001 return 0;
4002 }
4003
4004 static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4005 {
4006 const struct phm_set_power_state_input *states =
4007 (const struct phm_set_power_state_input *)input;
4008 const struct fiji_power_state *fiji_ps =
4009 cast_const_phw_fiji_power_state(states->pnew_state);
4010 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4011 struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4012 uint32_t sclk = fiji_ps->performance_levels
4013 [fiji_ps->performance_level_count - 1].engine_clock;
4014 struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4015 uint32_t mclk = fiji_ps->performance_levels
4016 [fiji_ps->performance_level_count - 1].memory_clock;
4017 struct PP_Clocks min_clocks = {0};
4018 uint32_t i;
4019 struct cgs_display_info info = {0};
4020
4021 data->need_update_smu7_dpm_table = 0;
4022
4023 for (i = 0; i < sclk_table->count; i++) {
4024 if (sclk == sclk_table->dpm_levels[i].value)
4025 break;
4026 }
4027
4028 if (i >= sclk_table->count)
4029 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4030 else {
4031 /* TODO: Check SCLK in DAL's minimum clocks
4032 * in case DeepSleep divider update is required.
4033 */
4034 if(data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR)
4035 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4036 }
4037
4038 for (i = 0; i < mclk_table->count; i++) {
4039 if (mclk == mclk_table->dpm_levels[i].value)
4040 break;
4041 }
4042
4043 if (i >= mclk_table->count)
4044 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4045
4046 cgs_get_active_displays_info(hwmgr->device, &info);
4047
4048 if (data->display_timing.num_existing_displays != info.display_count)
4049 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4050
4051 return 0;
4052 }
4053
4054 static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4055 const struct fiji_power_state *fiji_ps)
4056 {
4057 uint32_t i;
4058 uint32_t sclk, max_sclk = 0;
4059 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4060 struct fiji_dpm_table *dpm_table = &data->dpm_table;
4061
4062 for (i = 0; i < fiji_ps->performance_level_count; i++) {
4063 sclk = fiji_ps->performance_levels[i].engine_clock;
4064 if (max_sclk < sclk)
4065 max_sclk = sclk;
4066 }
4067
4068 for (i = 0; i < dpm_table->sclk_table.count; i++) {
4069 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4070 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4071 dpm_table->pcie_speed_table.dpm_levels
4072 [dpm_table->pcie_speed_table.count - 1].value :
4073 dpm_table->pcie_speed_table.dpm_levels[i].value);
4074 }
4075
4076 return 0;
4077 }
4078
4079 static int fiji_request_link_speed_change_before_state_change(
4080 struct pp_hwmgr *hwmgr, const void *input)
4081 {
4082 const struct phm_set_power_state_input *states =
4083 (const struct phm_set_power_state_input *)input;
4084 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4085 const struct fiji_power_state *fiji_nps =
4086 cast_const_phw_fiji_power_state(states->pnew_state);
4087 const struct fiji_power_state *fiji_cps =
4088 cast_const_phw_fiji_power_state(states->pcurrent_state);
4089
4090 uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_nps);
4091 uint16_t current_link_speed;
4092
4093 if (data->force_pcie_gen == PP_PCIEGenInvalid)
4094 current_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_cps);
4095 else
4096 current_link_speed = data->force_pcie_gen;
4097
4098 data->force_pcie_gen = PP_PCIEGenInvalid;
4099 data->pspp_notify_required = false;
4100 if (target_link_speed > current_link_speed) {
4101 switch(target_link_speed) {
4102 case PP_PCIEGen3:
4103 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4104 break;
4105 data->force_pcie_gen = PP_PCIEGen2;
4106 if (current_link_speed == PP_PCIEGen2)
4107 break;
4108 case PP_PCIEGen2:
4109 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4110 break;
4111 default:
4112 data->force_pcie_gen = fiji_get_current_pcie_speed(hwmgr);
4113 break;
4114 }
4115 } else {
4116 if (target_link_speed < current_link_speed)
4117 data->pspp_notify_required = true;
4118 }
4119
4120 return 0;
4121 }
4122
4123 static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4124 {
4125 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4126
4127 if (0 == data->need_update_smu7_dpm_table)
4128 return 0;
4129
4130 if ((0 == data->sclk_dpm_key_disabled) &&
4131 (data->need_update_smu7_dpm_table &
4132 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4133 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4134 "Trying to freeze SCLK DPM when DPM is disabled",);
4135 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4136 PPSMC_MSG_SCLKDPM_FreezeLevel),
4137 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4138 return -1);
4139 }
4140
4141 if ((0 == data->mclk_dpm_key_disabled) &&
4142 (data->need_update_smu7_dpm_table &
4143 DPMTABLE_OD_UPDATE_MCLK)) {
4144 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4145 "Trying to freeze MCLK DPM when DPM is disabled",);
4146 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4147 PPSMC_MSG_MCLKDPM_FreezeLevel),
4148 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4149 return -1);
4150 }
4151
4152 return 0;
4153 }
4154
4155 static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
4156 struct pp_hwmgr *hwmgr, const void *input)
4157 {
4158 int result = 0;
4159 const struct phm_set_power_state_input *states =
4160 (const struct phm_set_power_state_input *)input;
4161 const struct fiji_power_state *fiji_ps =
4162 cast_const_phw_fiji_power_state(states->pnew_state);
4163 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4164 uint32_t sclk = fiji_ps->performance_levels
4165 [fiji_ps->performance_level_count - 1].engine_clock;
4166 uint32_t mclk = fiji_ps->performance_levels
4167 [fiji_ps->performance_level_count - 1].memory_clock;
4168 struct fiji_dpm_table *dpm_table = &data->dpm_table;
4169
4170 struct fiji_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4171 uint32_t dpm_count, clock_percent;
4172 uint32_t i;
4173
4174 if (0 == data->need_update_smu7_dpm_table)
4175 return 0;
4176
4177 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4178 dpm_table->sclk_table.dpm_levels
4179 [dpm_table->sclk_table.count - 1].value = sclk;
4180
4181 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4182 PHM_PlatformCaps_OD6PlusinACSupport) ||
4183 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4184 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4185 /* Need to do calculation based on the golden DPM table
4186 * as the Heatmap GPU Clock axis is also based on the default values
4187 */
4188 PP_ASSERT_WITH_CODE(
4189 (golden_dpm_table->sclk_table.dpm_levels
4190 [golden_dpm_table->sclk_table.count - 1].value != 0),
4191 "Divide by 0!",
4192 return -1);
4193 dpm_count = dpm_table->sclk_table.count < 2 ?
4194 0 : dpm_table->sclk_table.count - 2;
4195 for (i = dpm_count; i > 1; i--) {
4196 if (sclk > golden_dpm_table->sclk_table.dpm_levels
4197 [golden_dpm_table->sclk_table.count-1].value) {
4198 clock_percent =
4199 ((sclk - golden_dpm_table->sclk_table.dpm_levels
4200 [golden_dpm_table->sclk_table.count-1].value) * 100) /
4201 golden_dpm_table->sclk_table.dpm_levels
4202 [golden_dpm_table->sclk_table.count-1].value;
4203
4204 dpm_table->sclk_table.dpm_levels[i].value =
4205 golden_dpm_table->sclk_table.dpm_levels[i].value +
4206 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4207 clock_percent)/100;
4208
4209 } else if (golden_dpm_table->sclk_table.dpm_levels
4210 [dpm_table->sclk_table.count-1].value > sclk) {
4211 clock_percent =
4212 ((golden_dpm_table->sclk_table.dpm_levels
4213 [golden_dpm_table->sclk_table.count - 1].value - sclk) *
4214 100) /
4215 golden_dpm_table->sclk_table.dpm_levels
4216 [golden_dpm_table->sclk_table.count-1].value;
4217
4218 dpm_table->sclk_table.dpm_levels[i].value =
4219 golden_dpm_table->sclk_table.dpm_levels[i].value -
4220 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4221 clock_percent) / 100;
4222 } else
4223 dpm_table->sclk_table.dpm_levels[i].value =
4224 golden_dpm_table->sclk_table.dpm_levels[i].value;
4225 }
4226 }
4227 }
4228
4229 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4230 dpm_table->mclk_table.dpm_levels
4231 [dpm_table->mclk_table.count - 1].value = mclk;
4232
4233 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4234 PHM_PlatformCaps_OD6PlusinACSupport) ||
4235 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4236 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4237
4238 PP_ASSERT_WITH_CODE(
4239 (golden_dpm_table->mclk_table.dpm_levels
4240 [golden_dpm_table->mclk_table.count-1].value != 0),
4241 "Divide by 0!",
4242 return -1);
4243 dpm_count = dpm_table->mclk_table.count < 2 ?
4244 0 : dpm_table->mclk_table.count - 2;
4245 for (i = dpm_count; i > 1; i--) {
4246 if (mclk > golden_dpm_table->mclk_table.dpm_levels
4247 [golden_dpm_table->mclk_table.count-1].value) {
4248 clock_percent = ((mclk -
4249 golden_dpm_table->mclk_table.dpm_levels
4250 [golden_dpm_table->mclk_table.count-1].value) * 100) /
4251 golden_dpm_table->mclk_table.dpm_levels
4252 [golden_dpm_table->mclk_table.count-1].value;
4253
4254 dpm_table->mclk_table.dpm_levels[i].value =
4255 golden_dpm_table->mclk_table.dpm_levels[i].value +
4256 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4257 clock_percent) / 100;
4258
4259 } else if (golden_dpm_table->mclk_table.dpm_levels
4260 [dpm_table->mclk_table.count-1].value > mclk) {
4261 clock_percent = ((golden_dpm_table->mclk_table.dpm_levels
4262 [golden_dpm_table->mclk_table.count-1].value - mclk) * 100) /
4263 golden_dpm_table->mclk_table.dpm_levels
4264 [golden_dpm_table->mclk_table.count-1].value;
4265
4266 dpm_table->mclk_table.dpm_levels[i].value =
4267 golden_dpm_table->mclk_table.dpm_levels[i].value -
4268 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4269 clock_percent) / 100;
4270 } else
4271 dpm_table->mclk_table.dpm_levels[i].value =
4272 golden_dpm_table->mclk_table.dpm_levels[i].value;
4273 }
4274 }
4275 }
4276
4277 if (data->need_update_smu7_dpm_table &
4278 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4279 result = fiji_populate_all_memory_levels(hwmgr);
4280 PP_ASSERT_WITH_CODE((0 == result),
4281 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4282 return result);
4283 }
4284
4285 if (data->need_update_smu7_dpm_table &
4286 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4287 /*populate MCLK dpm table to SMU7 */
4288 result = fiji_populate_all_memory_levels(hwmgr);
4289 PP_ASSERT_WITH_CODE((0 == result),
4290 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4291 return result);
4292 }
4293
4294 return result;
4295 }
4296
4297 static int fiji_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4298 struct fiji_single_dpm_table * dpm_table,
4299 uint32_t low_limit, uint32_t high_limit)
4300 {
4301 uint32_t i;
4302
4303 for (i = 0; i < dpm_table->count; i++) {
4304 if ((dpm_table->dpm_levels[i].value < low_limit) ||
4305 (dpm_table->dpm_levels[i].value > high_limit))
4306 dpm_table->dpm_levels[i].enabled = false;
4307 else
4308 dpm_table->dpm_levels[i].enabled = true;
4309 }
4310 return 0;
4311 }
4312
4313 static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr,
4314 const struct fiji_power_state *fiji_ps)
4315 {
4316 int result = 0;
4317 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4318 uint32_t high_limit_count;
4319
4320 PP_ASSERT_WITH_CODE((fiji_ps->performance_level_count >= 1),
4321 "power state did not have any performance level",
4322 return -1);
4323
4324 high_limit_count = (1 == fiji_ps->performance_level_count) ? 0 : 1;
4325
4326 fiji_trim_single_dpm_states(hwmgr,
4327 &(data->dpm_table.sclk_table),
4328 fiji_ps->performance_levels[0].engine_clock,
4329 fiji_ps->performance_levels[high_limit_count].engine_clock);
4330
4331 fiji_trim_single_dpm_states(hwmgr,
4332 &(data->dpm_table.mclk_table),
4333 fiji_ps->performance_levels[0].memory_clock,
4334 fiji_ps->performance_levels[high_limit_count].memory_clock);
4335
4336 return result;
4337 }
4338
4339 static int fiji_generate_dpm_level_enable_mask(
4340 struct pp_hwmgr *hwmgr, const void *input)
4341 {
4342 int result;
4343 const struct phm_set_power_state_input *states =
4344 (const struct phm_set_power_state_input *)input;
4345 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4346 const struct fiji_power_state *fiji_ps =
4347 cast_const_phw_fiji_power_state(states->pnew_state);
4348
4349 result = fiji_trim_dpm_states(hwmgr, fiji_ps);
4350 if (result)
4351 return result;
4352
4353 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4354 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4355 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4356 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4357 data->last_mclk_dpm_enable_mask =
4358 data->dpm_level_enable_mask.mclk_dpm_enable_mask;
4359
4360 if (data->uvd_enabled) {
4361 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4362 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4363 }
4364
4365 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4366 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4367
4368 return 0;
4369 }
4370
4371 static int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4372 {
4373 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4374 PPSMC_MSG_VCEDPM_Enable :
4375 PPSMC_MSG_VCEDPM_Disable);
4376 }
4377
4378 static int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4379 {
4380 const struct phm_set_power_state_input *states =
4381 (const struct phm_set_power_state_input *)input;
4382 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4383 const struct fiji_power_state *fiji_nps =
4384 cast_const_phw_fiji_power_state(states->pnew_state);
4385 const struct fiji_power_state *fiji_cps =
4386 cast_const_phw_fiji_power_state(states->pcurrent_state);
4387
4388 uint32_t mm_boot_level_offset, mm_boot_level_value;
4389 struct phm_ppt_v1_information *table_info =
4390 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4391
4392 if (fiji_nps->vce_clks.evclk >0 &&
4393 (fiji_cps == NULL || fiji_cps->vce_clks.evclk == 0)) {
4394 data->smc_state_table.VceBootLevel =
4395 (uint8_t) (table_info->mm_dep_table->count - 1);
4396
4397 mm_boot_level_offset = data->dpm_table_start +
4398 offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
4399 mm_boot_level_offset /= 4;
4400 mm_boot_level_offset *= 4;
4401 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4402 CGS_IND_REG__SMC, mm_boot_level_offset);
4403 mm_boot_level_value &= 0xFF00FFFF;
4404 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4405 cgs_write_ind_register(hwmgr->device,
4406 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4407
4408 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4409 PHM_PlatformCaps_StablePState)) {
4410 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4411 PPSMC_MSG_VCEDPM_SetEnabledMask,
4412 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4413
4414 fiji_enable_disable_vce_dpm(hwmgr, true);
4415 } else if (fiji_nps->vce_clks.evclk == 0 &&
4416 fiji_cps != NULL &&
4417 fiji_cps->vce_clks.evclk > 0)
4418 fiji_enable_disable_vce_dpm(hwmgr, false);
4419 }
4420
4421 return 0;
4422 }
4423
4424 static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4425 {
4426 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4427
4428 int result = 0;
4429 uint32_t low_sclk_interrupt_threshold = 0;
4430
4431 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4432 PHM_PlatformCaps_SclkThrottleLowNotification)
4433 && (hwmgr->gfx_arbiter.sclk_threshold !=
4434 data->low_sclk_interrupt_threshold)) {
4435 data->low_sclk_interrupt_threshold =
4436 hwmgr->gfx_arbiter.sclk_threshold;
4437 low_sclk_interrupt_threshold =
4438 data->low_sclk_interrupt_threshold;
4439
4440 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4441
4442 result = fiji_copy_bytes_to_smc(
4443 hwmgr->smumgr,
4444 data->dpm_table_start +
4445 offsetof(SMU73_Discrete_DpmTable,
4446 LowSclkInterruptThreshold),
4447 (uint8_t *)&low_sclk_interrupt_threshold,
4448 sizeof(uint32_t),
4449 data->sram_end);
4450 }
4451
4452 return result;
4453 }
4454
4455 static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4456 {
4457 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4458
4459 if (data->need_update_smu7_dpm_table &
4460 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4461 return fiji_program_memory_timing_parameters(hwmgr);
4462
4463 return 0;
4464 }
4465
4466 static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4467 {
4468 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4469
4470 if (0 == data->need_update_smu7_dpm_table)
4471 return 0;
4472
4473 if ((0 == data->sclk_dpm_key_disabled) &&
4474 (data->need_update_smu7_dpm_table &
4475 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4476
4477 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4478 "Trying to Unfreeze SCLK DPM when DPM is disabled",);
4479 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4480 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4481 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4482 return -1);
4483 }
4484
4485 if ((0 == data->mclk_dpm_key_disabled) &&
4486 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4487
4488 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4489 "Trying to Unfreeze MCLK DPM when DPM is disabled",);
4490 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4491 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4492 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4493 return -1);
4494 }
4495
4496 data->need_update_smu7_dpm_table = 0;
4497
4498 return 0;
4499 }
4500
4501 /* Look up the voltaged based on DAL's requested level.
4502 * and then send the requested VDDC voltage to SMC
4503 */
4504 static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
4505 {
4506 return;
4507 }
4508
4509 int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
4510 {
4511 int result;
4512 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4513
4514 /* Apply minimum voltage based on DAL's request level */
4515 fiji_apply_dal_minimum_voltage_request(hwmgr);
4516
4517 if (0 == data->sclk_dpm_key_disabled) {
4518 /* Checking if DPM is running. If we discover hang because of this,
4519 * we should skip this message.
4520 */
4521 if (!fiji_is_dpm_running(hwmgr))
4522 printk(KERN_ERR "[ powerplay ] "
4523 "Trying to set Enable Mask when DPM is disabled \n");
4524
4525 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4526 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4527 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4528 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4529 PP_ASSERT_WITH_CODE((0 == result),
4530 "Set Sclk Dpm enable Mask failed", return -1);
4531 }
4532 }
4533
4534 if (0 == data->mclk_dpm_key_disabled) {
4535 /* Checking if DPM is running. If we discover hang because of this,
4536 * we should skip this message.
4537 */
4538 if (!fiji_is_dpm_running(hwmgr))
4539 printk(KERN_ERR "[ powerplay ]"
4540 " Trying to set Enable Mask when DPM is disabled \n");
4541
4542 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4543 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4544 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4545 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
4546 PP_ASSERT_WITH_CODE((0 == result),
4547 "Set Mclk Dpm enable Mask failed", return -1);
4548 }
4549 }
4550
4551 return 0;
4552 }
4553
4554 static int fiji_notify_link_speed_change_after_state_change(
4555 struct pp_hwmgr *hwmgr, const void *input)
4556 {
4557 const struct phm_set_power_state_input *states =
4558 (const struct phm_set_power_state_input *)input;
4559 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4560 const struct fiji_power_state *fiji_ps =
4561 cast_const_phw_fiji_power_state(states->pnew_state);
4562 uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_ps);
4563 uint8_t request;
4564
4565 if (data->pspp_notify_required) {
4566 if (target_link_speed == PP_PCIEGen3)
4567 request = PCIE_PERF_REQ_GEN3;
4568 else if (target_link_speed == PP_PCIEGen2)
4569 request = PCIE_PERF_REQ_GEN2;
4570 else
4571 request = PCIE_PERF_REQ_GEN1;
4572
4573 if(request == PCIE_PERF_REQ_GEN1 &&
4574 fiji_get_current_pcie_speed(hwmgr) > 0)
4575 return 0;
4576
4577 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4578 if (PP_PCIEGen2 == target_link_speed)
4579 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4580 else
4581 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4582 }
4583 }
4584
4585 return 0;
4586 }
4587
4588 static int fiji_set_power_state_tasks(struct pp_hwmgr *hwmgr,
4589 const void *input)
4590 {
4591 int tmp_result, result = 0;
4592
4593 tmp_result = fiji_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4594 PP_ASSERT_WITH_CODE((0 == tmp_result),
4595 "Failed to find DPM states clocks in DPM table!",
4596 result = tmp_result);
4597
4598 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4599 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4600 tmp_result =
4601 fiji_request_link_speed_change_before_state_change(hwmgr, input);
4602 PP_ASSERT_WITH_CODE((0 == tmp_result),
4603 "Failed to request link speed change before state change!",
4604 result = tmp_result);
4605 }
4606
4607 tmp_result = fiji_freeze_sclk_mclk_dpm(hwmgr);
4608 PP_ASSERT_WITH_CODE((0 == tmp_result),
4609 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4610
4611 tmp_result = fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4612 PP_ASSERT_WITH_CODE((0 == tmp_result),
4613 "Failed to populate and upload SCLK MCLK DPM levels!",
4614 result = tmp_result);
4615
4616 tmp_result = fiji_generate_dpm_level_enable_mask(hwmgr, input);
4617 PP_ASSERT_WITH_CODE((0 == tmp_result),
4618 "Failed to generate DPM level enabled mask!",
4619 result = tmp_result);
4620
4621 tmp_result = fiji_update_vce_dpm(hwmgr, input);
4622 PP_ASSERT_WITH_CODE((0 == tmp_result),
4623 "Failed to update VCE DPM!",
4624 result = tmp_result);
4625
4626 tmp_result = fiji_update_sclk_threshold(hwmgr);
4627 PP_ASSERT_WITH_CODE((0 == tmp_result),
4628 "Failed to update SCLK threshold!",
4629 result = tmp_result);
4630
4631 tmp_result = fiji_program_mem_timing_parameters(hwmgr);
4632 PP_ASSERT_WITH_CODE((0 == tmp_result),
4633 "Failed to program memory timing parameters!",
4634 result = tmp_result);
4635
4636 tmp_result = fiji_unfreeze_sclk_mclk_dpm(hwmgr);
4637 PP_ASSERT_WITH_CODE((0 == tmp_result),
4638 "Failed to unfreeze SCLK MCLK DPM!",
4639 result = tmp_result);
4640
4641 tmp_result = fiji_upload_dpm_level_enable_mask(hwmgr);
4642 PP_ASSERT_WITH_CODE((0 == tmp_result),
4643 "Failed to upload DPM level enabled mask!",
4644 result = tmp_result);
4645
4646 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4647 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4648 tmp_result =
4649 fiji_notify_link_speed_change_after_state_change(hwmgr, input);
4650 PP_ASSERT_WITH_CODE((0 == tmp_result),
4651 "Failed to notify link speed change after state change!",
4652 result = tmp_result);
4653 }
4654
4655 return result;
4656 }
4657
4658 static int fiji_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4659 {
4660 struct pp_power_state *ps;
4661 struct fiji_power_state *fiji_ps;
4662
4663 if (hwmgr == NULL)
4664 return -EINVAL;
4665
4666 ps = hwmgr->request_ps;
4667
4668 if (ps == NULL)
4669 return -EINVAL;
4670
4671 fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4672
4673 if (low)
4674 return fiji_ps->performance_levels[0].engine_clock;
4675 else
4676 return fiji_ps->performance_levels
4677 [fiji_ps->performance_level_count-1].engine_clock;
4678 }
4679
4680 static int fiji_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4681 {
4682 struct pp_power_state *ps;
4683 struct fiji_power_state *fiji_ps;
4684
4685 if (hwmgr == NULL)
4686 return -EINVAL;
4687
4688 ps = hwmgr->request_ps;
4689
4690 if (ps == NULL)
4691 return -EINVAL;
4692
4693 fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4694
4695 if (low)
4696 return fiji_ps->performance_levels[0].memory_clock;
4697 else
4698 return fiji_ps->performance_levels
4699 [fiji_ps->performance_level_count-1].memory_clock;
4700 }
4701
4702 static void fiji_print_current_perforce_level(
4703 struct pp_hwmgr *hwmgr, struct seq_file *m)
4704 {
4705 uint32_t sclk, mclk;
4706
4707 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4708
4709 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4710
4711 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4712
4713 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4714 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
4715 mclk / 100, sclk / 100);
4716 }
4717
4718 static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
4719 .backend_init = &fiji_hwmgr_backend_init,
4720 .backend_fini = &tonga_hwmgr_backend_fini,
4721 .asic_setup = &fiji_setup_asic_task,
4722 .dynamic_state_management_enable = &fiji_enable_dpm_tasks,
4723 .force_dpm_level = &fiji_dpm_force_dpm_level,
4724 .get_num_of_pp_table_entries = &tonga_get_number_of_powerplay_table_entries,
4725 .get_power_state_size = &fiji_get_power_state_size,
4726 .get_pp_table_entry = &fiji_get_pp_table_entry,
4727 .patch_boot_state = &fiji_patch_boot_state,
4728 .apply_state_adjust_rules = &fiji_apply_state_adjust_rules,
4729 .power_state_set = &fiji_set_power_state_tasks,
4730 .get_sclk = &fiji_dpm_get_sclk,
4731 .get_mclk = &fiji_dpm_get_mclk,
4732 .print_current_perforce_level = &fiji_print_current_perforce_level,
4733 };
4734
4735 int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
4736 {
4737 struct fiji_hwmgr *data;
4738 int ret = 0;
4739
4740 data = kzalloc(sizeof(struct fiji_hwmgr), GFP_KERNEL);
4741 if (data == NULL)
4742 return -ENOMEM;
4743
4744 hwmgr->backend = data;
4745 hwmgr->hwmgr_func = &fiji_hwmgr_funcs;
4746 hwmgr->pptable_func = &tonga_pptable_funcs;
4747 return ret;
4748 }
Linux kernel - Deliverables
This page took 0.129708 seconds and 6 git commands to generate.