2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/slab.h>
26 #include "linux/delay.h"
29 #include "fiji_smumgr.h"
31 #include "hardwaremanager.h"
32 #include "ppatomctrl.h"
34 #include "cgs_common.h"
35 #include "fiji_dyn_defaults.h"
36 #include "fiji_powertune.h"
38 #include "smu/smu_7_1_3_d.h"
39 #include "smu/smu_7_1_3_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
44 #include "dce/dce_10_0_d.h"
45 #include "dce/dce_10_0_sh_mask.h"
46 #include "pppcielanes.h"
47 #include "fiji_hwmgr.h"
48 #include "tonga_processpptables.h"
49 #include "tonga_pptable.h"
52 #include "amd_pcie_helpers.h"
53 #include "cgs_linux.h"
54 #include "ppinterrupt.h"
56 #include "fiji_clockpowergating.h"
57 #include "fiji_thermal.h"
59 #define VOLTAGE_SCALE 4
60 #define SMC_RAM_END 0x40000
61 #define VDDC_VDDCI_DELTA 300
63 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
64 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
65 #define MC_SEQ_MISC0_GDDR5_VALUE 5
67 #define MC_CG_ARB_FREQ_F0 0x0a /* boot-up default */
68 #define MC_CG_ARB_FREQ_F1 0x0b
69 #define MC_CG_ARB_FREQ_F2 0x0c
70 #define MC_CG_ARB_FREQ_F3 0x0d
73 #define SMC_CG_IND_START 0xc0030000
74 #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND */
76 #define VOLTAGE_SCALE 4
77 #define VOLTAGE_VID_OFFSET_SCALE1 625
78 #define VOLTAGE_VID_OFFSET_SCALE2 100
80 #define VDDC_VDDCI_DELTA 300
82 #define ixSWRST_COMMAND_1 0x1400103
83 #define MC_SEQ_CNTL__CAC_EN_MASK 0x40000000
85 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
87 DPM_EVENT_SRC_ANALOG
= 0, /* Internal analog trip point */
88 DPM_EVENT_SRC_EXTERNAL
= 1, /* External (GPIO 17) signal */
89 DPM_EVENT_SRC_DIGITAL
= 2, /* Internal digital trip point (DIG_THERM_DPM) */
90 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3, /* Internal analog or external */
91 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL
= 4 /* Internal digital or external */
95 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
96 * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
98 uint16_t fiji_clock_stretcher_lookup_table
[2][4] = { {600, 1050, 3, 0},
101 /* [FF, SS] type, [] 4 voltage ranges, and
102 * [Floor Freq, Boundary Freq, VID min , VID max]
104 uint32_t fiji_clock_stretcher_ddt_table
[2][4][4] =
105 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
106 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
108 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
109 * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
111 uint8_t fiji_clock_stretch_amount_conversion
[2][6] = { {0, 1, 3, 2, 4, 5},
112 {0, 2, 4, 5, 6, 5} };
114 const unsigned long PhwFiji_Magic
= (unsigned long)(PHM_VIslands_Magic
);
116 struct fiji_power_state
*cast_phw_fiji_power_state(
117 struct pp_hw_power_state
*hw_ps
)
119 PP_ASSERT_WITH_CODE((PhwFiji_Magic
== hw_ps
->magic
),
120 "Invalid Powerstate Type!",
123 return (struct fiji_power_state
*)hw_ps
;
126 const struct fiji_power_state
*cast_const_phw_fiji_power_state(
127 const struct pp_hw_power_state
*hw_ps
)
129 PP_ASSERT_WITH_CODE((PhwFiji_Magic
== hw_ps
->magic
),
130 "Invalid Powerstate Type!",
133 return (const struct fiji_power_state
*)hw_ps
;
136 static bool fiji_is_dpm_running(struct pp_hwmgr
*hwmgr
)
138 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr
->device
,
139 CGS_IND_REG__SMC
, FEATURE_STATUS
, VOLTAGE_CONTROLLER_ON
))
143 static void fiji_init_dpm_defaults(struct pp_hwmgr
*hwmgr
)
145 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
146 struct fiji_ulv_parm
*ulv
= &data
->ulv
;
148 ulv
->cg_ulv_parameter
= PPFIJI_CGULVPARAMETER_DFLT
;
149 data
->voting_rights_clients0
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0
;
150 data
->voting_rights_clients1
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1
;
151 data
->voting_rights_clients2
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2
;
152 data
->voting_rights_clients3
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3
;
153 data
->voting_rights_clients4
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4
;
154 data
->voting_rights_clients5
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5
;
155 data
->voting_rights_clients6
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6
;
156 data
->voting_rights_clients7
= PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7
;
158 data
->static_screen_threshold_unit
=
159 PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT
;
160 data
->static_screen_threshold
=
161 PPFIJI_STATICSCREENTHRESHOLD_DFLT
;
163 /* Unset ABM cap as it moved to DAL.
164 * Add PHM_PlatformCaps_NonABMSupportInPPLib
165 * for re-direct ABM related request to DAL
167 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
168 PHM_PlatformCaps_ABM
);
169 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
170 PHM_PlatformCaps_NonABMSupportInPPLib
);
172 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
173 PHM_PlatformCaps_DynamicACTiming
);
175 fiji_initialize_power_tune_defaults(hwmgr
);
177 data
->mclk_stutter_mode_threshold
= 60000;
178 data
->pcie_gen_performance
.max
= PP_PCIEGen1
;
179 data
->pcie_gen_performance
.min
= PP_PCIEGen3
;
180 data
->pcie_gen_power_saving
.max
= PP_PCIEGen1
;
181 data
->pcie_gen_power_saving
.min
= PP_PCIEGen3
;
182 data
->pcie_lane_performance
.max
= 0;
183 data
->pcie_lane_performance
.min
= 16;
184 data
->pcie_lane_power_saving
.max
= 0;
185 data
->pcie_lane_power_saving
.min
= 16;
187 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
188 PHM_PlatformCaps_DynamicUVDState
);
191 static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr
*hwmgr
,
192 phm_ppt_v1_voltage_lookup_table
*lookup_table
,
193 uint16_t virtual_voltage_id
, int32_t *sclk
)
197 struct phm_ppt_v1_information
*table_info
=
198 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
200 PP_ASSERT_WITH_CODE(lookup_table
->count
!= 0, "Lookup table is empty", return -EINVAL
);
202 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
203 for (entryId
= 0; entryId
< table_info
->vdd_dep_on_sclk
->count
; entryId
++) {
204 voltageId
= table_info
->vdd_dep_on_sclk
->entries
[entryId
].vddInd
;
205 if (lookup_table
->entries
[voltageId
].us_vdd
== virtual_voltage_id
)
209 PP_ASSERT_WITH_CODE(entryId
< table_info
->vdd_dep_on_sclk
->count
,
210 "Can't find requested voltage id in vdd_dep_on_sclk table!",
214 *sclk
= table_info
->vdd_dep_on_sclk
->entries
[entryId
].clk
;
220 * Get Leakage VDDC based on leakage ID.
222 * @param hwmgr the address of the powerplay hardware manager.
225 static int fiji_get_evv_voltages(struct pp_hwmgr
*hwmgr
)
227 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
230 uint16_t evv_default
= 1150;
233 struct phm_ppt_v1_information
*table_info
=
234 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
235 struct phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
=
236 table_info
->vdd_dep_on_sclk
;
239 for (i
= 0; i
< FIJI_MAX_LEAKAGE_COUNT
; i
++) {
240 vv_id
= ATOM_VIRTUAL_VOLTAGE_ID0
+ i
;
241 if (!fiji_get_sclk_for_voltage_evv(hwmgr
,
242 table_info
->vddc_lookup_table
, vv_id
, &sclk
)) {
243 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
244 PHM_PlatformCaps_ClockStretcher
)) {
245 for (j
= 1; j
< sclk_table
->count
; j
++) {
246 if (sclk_table
->entries
[j
].clk
== sclk
&&
247 sclk_table
->entries
[j
].cks_enable
== 0) {
254 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
255 PHM_PlatformCaps_EnableDriverEVV
))
256 result
= atomctrl_calculate_voltage_evv_on_sclk(hwmgr
,
257 VOLTAGE_TYPE_VDDC
, sclk
, vv_id
, &vddc
, i
, true);
262 result
= atomctrl_get_voltage_evv_on_sclk(hwmgr
,
263 VOLTAGE_TYPE_VDDC
, sclk
,vv_id
, &vddc
);
265 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
266 PP_ASSERT_WITH_CODE((vddc
< 2000),
267 "Invalid VDDC value, greater than 2v!", result
= -EINVAL
;);
270 /* 1.15V is the default safe value for Fiji */
273 /* the voltage should not be zero nor equal to leakage ID */
274 if (vddc
!= 0 && vddc
!= vv_id
) {
275 data
->vddc_leakage
.actual_voltage
276 [data
->vddc_leakage
.count
] = vddc
;
277 data
->vddc_leakage
.leakage_id
278 [data
->vddc_leakage
.count
] = vv_id
;
279 data
->vddc_leakage
.count
++;
287 * Change virtual leakage voltage to actual value.
289 * @param hwmgr the address of the powerplay hardware manager.
290 * @param pointer to changing voltage
291 * @param pointer to leakage table
293 static void fiji_patch_with_vdd_leakage(struct pp_hwmgr
*hwmgr
,
294 uint16_t *voltage
, struct fiji_leakage_voltage
*leakage_table
)
298 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
299 for (index
= 0; index
< leakage_table
->count
; index
++) {
300 /* if this voltage matches a leakage voltage ID */
301 /* patch with actual leakage voltage */
302 if (leakage_table
->leakage_id
[index
] == *voltage
) {
303 *voltage
= leakage_table
->actual_voltage
[index
];
308 if (*voltage
> ATOM_VIRTUAL_VOLTAGE_ID0
)
309 printk(KERN_ERR
"Voltage value looks like a Leakage ID but it's not patched \n");
313 * Patch voltage lookup table by EVV leakages.
315 * @param hwmgr the address of the powerplay hardware manager.
316 * @param pointer to voltage lookup table
317 * @param pointer to leakage table
320 static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr
*hwmgr
,
321 phm_ppt_v1_voltage_lookup_table
*lookup_table
,
322 struct fiji_leakage_voltage
*leakage_table
)
326 for (i
= 0; i
< lookup_table
->count
; i
++)
327 fiji_patch_with_vdd_leakage(hwmgr
,
328 &lookup_table
->entries
[i
].us_vdd
, leakage_table
);
333 static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
334 struct pp_hwmgr
*hwmgr
, struct fiji_leakage_voltage
*leakage_table
,
337 struct phm_ppt_v1_information
*table_info
=
338 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
339 fiji_patch_with_vdd_leakage(hwmgr
, (uint16_t *)vddc
, leakage_table
);
340 hwmgr
->dyn_state
.max_clock_voltage_on_dc
.vddc
=
341 table_info
->max_clock_voltage_on_dc
.vddc
;
345 static int fiji_patch_voltage_dependency_tables_with_lookup_table(
346 struct pp_hwmgr
*hwmgr
)
350 struct phm_ppt_v1_information
*table_info
=
351 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
353 struct phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
=
354 table_info
->vdd_dep_on_sclk
;
355 struct phm_ppt_v1_clock_voltage_dependency_table
*mclk_table
=
356 table_info
->vdd_dep_on_mclk
;
357 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
358 table_info
->mm_dep_table
;
360 for (entryId
= 0; entryId
< sclk_table
->count
; ++entryId
) {
361 voltageId
= sclk_table
->entries
[entryId
].vddInd
;
362 sclk_table
->entries
[entryId
].vddc
=
363 table_info
->vddc_lookup_table
->entries
[voltageId
].us_vdd
;
366 for (entryId
= 0; entryId
< mclk_table
->count
; ++entryId
) {
367 voltageId
= mclk_table
->entries
[entryId
].vddInd
;
368 mclk_table
->entries
[entryId
].vddc
=
369 table_info
->vddc_lookup_table
->entries
[voltageId
].us_vdd
;
372 for (entryId
= 0; entryId
< mm_table
->count
; ++entryId
) {
373 voltageId
= mm_table
->entries
[entryId
].vddcInd
;
374 mm_table
->entries
[entryId
].vddc
=
375 table_info
->vddc_lookup_table
->entries
[voltageId
].us_vdd
;
382 static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr
*hwmgr
)
384 /* Need to determine if we need calculated voltage. */
388 static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr
*hwmgr
)
390 /* Need to determine if we need calculated voltage from mm table. */
394 static int fiji_sort_lookup_table(struct pp_hwmgr
*hwmgr
,
395 struct phm_ppt_v1_voltage_lookup_table
*lookup_table
)
397 uint32_t table_size
, i
, j
;
398 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record
;
399 table_size
= lookup_table
->count
;
401 PP_ASSERT_WITH_CODE(0 != lookup_table
->count
,
402 "Lookup table is empty", return -EINVAL
);
404 /* Sorting voltages */
405 for (i
= 0; i
< table_size
- 1; i
++) {
406 for (j
= i
+ 1; j
> 0; j
--) {
407 if (lookup_table
->entries
[j
].us_vdd
<
408 lookup_table
->entries
[j
- 1].us_vdd
) {
409 tmp_voltage_lookup_record
= lookup_table
->entries
[j
- 1];
410 lookup_table
->entries
[j
- 1] = lookup_table
->entries
[j
];
411 lookup_table
->entries
[j
] = tmp_voltage_lookup_record
;
419 static int fiji_complete_dependency_tables(struct pp_hwmgr
*hwmgr
)
423 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
424 struct phm_ppt_v1_information
*table_info
=
425 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
427 tmp_result
= fiji_patch_lookup_table_with_leakage(hwmgr
,
428 table_info
->vddc_lookup_table
, &(data
->vddc_leakage
));
432 tmp_result
= fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr
,
433 &(data
->vddc_leakage
), &table_info
->max_clock_voltage_on_dc
.vddc
);
437 tmp_result
= fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr
);
441 tmp_result
= fiji_calc_voltage_dependency_tables(hwmgr
);
445 tmp_result
= fiji_calc_mm_voltage_dependency_table(hwmgr
);
449 tmp_result
= fiji_sort_lookup_table(hwmgr
, table_info
->vddc_lookup_table
);
456 static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr
*hwmgr
)
458 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
459 struct phm_ppt_v1_information
*table_info
=
460 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
462 struct phm_ppt_v1_clock_voltage_dependency_table
*allowed_sclk_vdd_table
=
463 table_info
->vdd_dep_on_sclk
;
464 struct phm_ppt_v1_clock_voltage_dependency_table
*allowed_mclk_vdd_table
=
465 table_info
->vdd_dep_on_mclk
;
467 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table
!= NULL
,
468 "VDD dependency on SCLK table is missing. \
469 This table is mandatory", return -EINVAL
);
470 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table
->count
>= 1,
471 "VDD dependency on SCLK table has to have is missing. \
472 This table is mandatory", return -EINVAL
);
474 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table
!= NULL
,
475 "VDD dependency on MCLK table is missing. \
476 This table is mandatory", return -EINVAL
);
477 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table
->count
>= 1,
478 "VDD dependency on MCLK table has to have is missing. \
479 This table is mandatory", return -EINVAL
);
481 data
->min_vddc_in_pptable
= (uint16_t)allowed_sclk_vdd_table
->entries
[0].vddc
;
482 data
->max_vddc_in_pptable
= (uint16_t)allowed_sclk_vdd_table
->
483 entries
[allowed_sclk_vdd_table
->count
- 1].vddc
;
485 table_info
->max_clock_voltage_on_ac
.sclk
=
486 allowed_sclk_vdd_table
->entries
[allowed_sclk_vdd_table
->count
- 1].clk
;
487 table_info
->max_clock_voltage_on_ac
.mclk
=
488 allowed_mclk_vdd_table
->entries
[allowed_mclk_vdd_table
->count
- 1].clk
;
489 table_info
->max_clock_voltage_on_ac
.vddc
=
490 allowed_sclk_vdd_table
->entries
[allowed_sclk_vdd_table
->count
- 1].vddc
;
491 table_info
->max_clock_voltage_on_ac
.vddci
=
492 allowed_mclk_vdd_table
->entries
[allowed_mclk_vdd_table
->count
- 1].vddci
;
494 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.sclk
=
495 table_info
->max_clock_voltage_on_ac
.sclk
;
496 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.mclk
=
497 table_info
->max_clock_voltage_on_ac
.mclk
;
498 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddc
=
499 table_info
->max_clock_voltage_on_ac
.vddc
;
500 hwmgr
->dyn_state
.max_clock_voltage_on_ac
.vddci
=
501 table_info
->max_clock_voltage_on_ac
.vddci
;
506 static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr
*hwmgr
)
508 uint32_t speedCntl
= 0;
510 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
511 speedCntl
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__PCIE
,
512 ixPCIE_LC_SPEED_CNTL
);
513 return((uint16_t)PHM_GET_FIELD(speedCntl
,
514 PCIE_LC_SPEED_CNTL
, LC_CURRENT_DATA_RATE
));
517 static int fiji_get_current_pcie_lane_number(struct pp_hwmgr
*hwmgr
)
521 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
522 link_width
= PHM_READ_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__PCIE
,
523 PCIE_LC_LINK_WIDTH_CNTL
, LC_LINK_WIDTH_RD
);
525 PP_ASSERT_WITH_CODE((7 >= link_width
),
526 "Invalid PCIe lane width!", return 0);
528 return decode_pcie_lane_width(link_width
);
531 /** Patch the Boot State to match VBIOS boot clocks and voltage.
533 * @param hwmgr Pointer to the hardware manager.
534 * @param pPowerState The address of the PowerState instance being created.
537 static int fiji_patch_boot_state(struct pp_hwmgr
*hwmgr
,
538 struct pp_hw_power_state
*hw_ps
)
540 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
541 struct fiji_power_state
*ps
= (struct fiji_power_state
*)hw_ps
;
542 ATOM_FIRMWARE_INFO_V2_2
*fw_info
;
545 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
547 /* First retrieve the Boot clocks and VDDC from the firmware info table.
548 * We assume here that fw_info is unchanged if this call fails.
550 fw_info
= (ATOM_FIRMWARE_INFO_V2_2
*)cgs_atom_get_data_table(
551 hwmgr
->device
, index
,
552 &size
, &frev
, &crev
);
554 /* During a test, there is no firmware info table. */
557 /* Patch the state. */
558 data
->vbios_boot_state
.sclk_bootup_value
=
559 le32_to_cpu(fw_info
->ulDefaultEngineClock
);
560 data
->vbios_boot_state
.mclk_bootup_value
=
561 le32_to_cpu(fw_info
->ulDefaultMemoryClock
);
562 data
->vbios_boot_state
.mvdd_bootup_value
=
563 le16_to_cpu(fw_info
->usBootUpMVDDCVoltage
);
564 data
->vbios_boot_state
.vddc_bootup_value
=
565 le16_to_cpu(fw_info
->usBootUpVDDCVoltage
);
566 data
->vbios_boot_state
.vddci_bootup_value
=
567 le16_to_cpu(fw_info
->usBootUpVDDCIVoltage
);
568 data
->vbios_boot_state
.pcie_gen_bootup_value
=
569 fiji_get_current_pcie_speed(hwmgr
);
570 data
->vbios_boot_state
.pcie_lane_bootup_value
=
571 (uint16_t)fiji_get_current_pcie_lane_number(hwmgr
);
573 /* set boot power state */
574 ps
->performance_levels
[0].memory_clock
= data
->vbios_boot_state
.mclk_bootup_value
;
575 ps
->performance_levels
[0].engine_clock
= data
->vbios_boot_state
.sclk_bootup_value
;
576 ps
->performance_levels
[0].pcie_gen
= data
->vbios_boot_state
.pcie_gen_bootup_value
;
577 ps
->performance_levels
[0].pcie_lane
= data
->vbios_boot_state
.pcie_lane_bootup_value
;
582 static int fiji_hwmgr_backend_init(struct pp_hwmgr
*hwmgr
)
584 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
586 struct phm_ppt_v1_information
*table_info
=
587 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
591 data
->dll_default_on
= false;
592 data
->sram_end
= SMC_RAM_END
;
594 for (i
= 0; i
< SMU73_MAX_LEVELS_GRAPHICS
; i
++)
595 data
->activity_target
[i
] = FIJI_AT_DFLT
;
597 data
->vddc_vddci_delta
= VDDC_VDDCI_DELTA
;
599 data
->mclk_activity_target
= PPFIJI_MCLK_TARGETACTIVITY_DFLT
;
600 data
->mclk_dpm0_activity_target
= 0xa;
602 data
->sclk_dpm_key_disabled
= 0;
603 data
->mclk_dpm_key_disabled
= 0;
604 data
->pcie_dpm_key_disabled
= 0;
606 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
607 PHM_PlatformCaps_UnTabledHardwareInterface
);
608 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
609 PHM_PlatformCaps_TablelessHardwareInterface
);
611 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
612 PHM_PlatformCaps_SclkDeepSleep
);
614 data
->gpio_debug
= 0;
616 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
617 PHM_PlatformCaps_DynamicPatchPowerState
);
619 /* need to set voltage control types before EVV patching */
620 data
->voltage_control
= FIJI_VOLTAGE_CONTROL_NONE
;
621 data
->vddci_control
= FIJI_VOLTAGE_CONTROL_NONE
;
622 data
->mvdd_control
= FIJI_VOLTAGE_CONTROL_NONE
;
624 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
625 VOLTAGE_TYPE_VDDC
, VOLTAGE_OBJ_SVID2
))
626 data
->voltage_control
= FIJI_VOLTAGE_CONTROL_BY_SVID2
;
628 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
629 PHM_PlatformCaps_EnableMVDDControl
))
630 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
631 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_GPIO_LUT
))
632 data
->mvdd_control
= FIJI_VOLTAGE_CONTROL_BY_GPIO
;
634 if (data
->mvdd_control
== FIJI_VOLTAGE_CONTROL_NONE
)
635 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
636 PHM_PlatformCaps_EnableMVDDControl
);
638 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
639 PHM_PlatformCaps_ControlVDDCI
)) {
640 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
641 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
))
642 data
->vddci_control
= FIJI_VOLTAGE_CONTROL_BY_GPIO
;
643 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr
,
644 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_SVID2
))
645 data
->vddci_control
= FIJI_VOLTAGE_CONTROL_BY_SVID2
;
648 if (data
->vddci_control
== FIJI_VOLTAGE_CONTROL_NONE
)
649 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
650 PHM_PlatformCaps_ControlVDDCI
);
652 if (table_info
&& table_info
->cac_dtp_table
->usClockStretchAmount
)
653 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
654 PHM_PlatformCaps_ClockStretcher
);
656 fiji_init_dpm_defaults(hwmgr
);
658 /* Get leakage voltage based on leakage ID. */
659 fiji_get_evv_voltages(hwmgr
);
661 /* Patch our voltage dependency table with actual leakage voltage
662 * We need to perform leakage translation before it's used by other functions
664 fiji_complete_dependency_tables(hwmgr
);
666 /* Parse pptable data read from VBIOS */
667 fiji_set_private_data_based_on_pptable(hwmgr
);
670 data
->ulv
.ulv_supported
= true; /* ULV feature is enabled by default */
672 /* Initalize Dynamic State Adjustment Rule Settings */
673 result
= tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr
);
676 data
->uvd_enabled
= false;
677 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
678 PHM_PlatformCaps_EnableSMU7ThermalManagement
);
679 data
->vddc_phase_shed_control
= false;
682 stay_in_boot
= phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
683 PHM_PlatformCaps_StayInBootState
);
686 struct cgs_system_info sys_info
= {0};
688 data
->is_tlu_enabled
= 0;
689 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
=
690 FIJI_MAX_HARDWARE_POWERLEVELS
;
691 hwmgr
->platform_descriptor
.hardwarePerformanceLevels
= 2;
692 hwmgr
->platform_descriptor
.minimumClocksReductionPercentage
= 50;
694 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
695 PHM_PlatformCaps_FanSpeedInTableIsRPM
);
697 if (table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
&&
698 hwmgr
->thermal_controller
.
699 advanceFanControlParameters
.ucFanControlMode
) {
700 hwmgr
->thermal_controller
.advanceFanControlParameters
.usMaxFanPWM
=
701 hwmgr
->thermal_controller
.advanceFanControlParameters
.usDefaultMaxFanPWM
;
702 hwmgr
->thermal_controller
.advanceFanControlParameters
.usMaxFanRPM
=
703 hwmgr
->thermal_controller
.advanceFanControlParameters
.usDefaultMaxFanRPM
;
704 hwmgr
->dyn_state
.cac_dtp_table
->usOperatingTempMinLimit
=
705 table_info
->cac_dtp_table
->usOperatingTempMinLimit
;
706 hwmgr
->dyn_state
.cac_dtp_table
->usOperatingTempMaxLimit
=
707 table_info
->cac_dtp_table
->usOperatingTempMaxLimit
;
708 hwmgr
->dyn_state
.cac_dtp_table
->usDefaultTargetOperatingTemp
=
709 table_info
->cac_dtp_table
->usDefaultTargetOperatingTemp
;
710 hwmgr
->dyn_state
.cac_dtp_table
->usOperatingTempStep
=
711 table_info
->cac_dtp_table
->usOperatingTempStep
;
712 hwmgr
->dyn_state
.cac_dtp_table
->usTargetOperatingTemp
=
713 table_info
->cac_dtp_table
->usTargetOperatingTemp
;
715 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
716 PHM_PlatformCaps_ODFuzzyFanControlSupport
);
719 sys_info
.size
= sizeof(struct cgs_system_info
);
720 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_GEN_INFO
;
721 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
723 data
->pcie_gen_cap
= 0x30007;
725 data
->pcie_gen_cap
= (uint32_t)sys_info
.value
;
726 if (data
->pcie_gen_cap
& CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3
)
727 data
->pcie_spc_cap
= 20;
728 sys_info
.size
= sizeof(struct cgs_system_info
);
729 sys_info
.info_id
= CGS_SYSTEM_INFO_PCIE_MLW
;
730 result
= cgs_query_system_info(hwmgr
->device
, &sys_info
);
732 data
->pcie_lane_cap
= 0x2f0000;
734 data
->pcie_lane_cap
= (uint32_t)sys_info
.value
;
736 /* Ignore return value in here, we are cleaning up a mess. */
737 tonga_hwmgr_backend_fini(hwmgr
);
744 * Read clock related registers.
746 * @param hwmgr the address of the powerplay hardware manager.
749 static int fiji_read_clock_registers(struct pp_hwmgr
*hwmgr
)
751 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
753 data
->clock_registers
.vCG_SPLL_FUNC_CNTL
=
754 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
755 ixCG_SPLL_FUNC_CNTL
);
756 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_2
=
757 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
758 ixCG_SPLL_FUNC_CNTL_2
);
759 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
=
760 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
761 ixCG_SPLL_FUNC_CNTL_3
);
762 data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
=
763 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
764 ixCG_SPLL_FUNC_CNTL_4
);
765 data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
=
766 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
767 ixCG_SPLL_SPREAD_SPECTRUM
);
768 data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
=
769 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
770 ixCG_SPLL_SPREAD_SPECTRUM_2
);
776 * Find out if memory is GDDR5.
778 * @param hwmgr the address of the powerplay hardware manager.
781 static int fiji_get_memory_type(struct pp_hwmgr
*hwmgr
)
783 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
786 temp
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC0
);
788 data
->is_memory_gddr5
= (MC_SEQ_MISC0_GDDR5_VALUE
==
789 ((temp
& MC_SEQ_MISC0_GDDR5_MASK
) >>
790 MC_SEQ_MISC0_GDDR5_SHIFT
));
796 * Enables Dynamic Power Management by SMC
798 * @param hwmgr the address of the powerplay hardware manager.
801 static int fiji_enable_acpi_power_management(struct pp_hwmgr
*hwmgr
)
803 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
804 GENERAL_PWRMGT
, STATIC_PM_EN
, 1);
810 * Initialize PowerGating States for different engines
812 * @param hwmgr the address of the powerplay hardware manager.
815 static int fiji_init_power_gate_state(struct pp_hwmgr
*hwmgr
)
817 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
819 data
->uvd_power_gated
= false;
820 data
->vce_power_gated
= false;
821 data
->samu_power_gated
= false;
822 data
->acp_power_gated
= false;
823 data
->pg_acp_init
= true;
828 static int fiji_init_sclk_threshold(struct pp_hwmgr
*hwmgr
)
830 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
831 data
->low_sclk_interrupt_threshold
= 0;
836 static int fiji_setup_asic_task(struct pp_hwmgr
*hwmgr
)
838 int tmp_result
, result
= 0;
840 tmp_result
= fiji_read_clock_registers(hwmgr
);
841 PP_ASSERT_WITH_CODE((0 == tmp_result
),
842 "Failed to read clock registers!", result
= tmp_result
);
844 tmp_result
= fiji_get_memory_type(hwmgr
);
845 PP_ASSERT_WITH_CODE((0 == tmp_result
),
846 "Failed to get memory type!", result
= tmp_result
);
848 tmp_result
= fiji_enable_acpi_power_management(hwmgr
);
849 PP_ASSERT_WITH_CODE((0 == tmp_result
),
850 "Failed to enable ACPI power management!", result
= tmp_result
);
852 tmp_result
= fiji_init_power_gate_state(hwmgr
);
853 PP_ASSERT_WITH_CODE((0 == tmp_result
),
854 "Failed to init power gate state!", result
= tmp_result
);
856 tmp_result
= tonga_get_mc_microcode_version(hwmgr
);
857 PP_ASSERT_WITH_CODE((0 == tmp_result
),
858 "Failed to get MC microcode version!", result
= tmp_result
);
860 tmp_result
= fiji_init_sclk_threshold(hwmgr
);
861 PP_ASSERT_WITH_CODE((0 == tmp_result
),
862 "Failed to init sclk threshold!", result
= tmp_result
);
868 * Checks if we want to support voltage control
870 * @param hwmgr the address of the powerplay hardware manager.
872 static bool fiji_voltage_control(const struct pp_hwmgr
*hwmgr
)
874 const struct fiji_hwmgr
*data
=
875 (const struct fiji_hwmgr
*)(hwmgr
->backend
);
877 return (FIJI_VOLTAGE_CONTROL_NONE
!= data
->voltage_control
);
881 * Enable voltage control
883 * @param hwmgr the address of the powerplay hardware manager.
886 static int fiji_enable_voltage_control(struct pp_hwmgr
*hwmgr
)
888 /* enable voltage control */
889 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
890 GENERAL_PWRMGT
, VOLT_PWRMGT_EN
, 1);
896 * Remove repeated voltage values and create table with unique values.
898 * @param hwmgr the address of the powerplay hardware manager.
899 * @param vol_table the pointer to changing voltage table
900 * @return 0 in success
903 static int fiji_trim_voltage_table(struct pp_hwmgr
*hwmgr
,
904 struct pp_atomctrl_voltage_table
*vol_table
)
909 struct pp_atomctrl_voltage_table
*table
;
911 PP_ASSERT_WITH_CODE((NULL
!= vol_table
),
912 "Voltage Table empty.", return -EINVAL
);
913 table
= kzalloc(sizeof(struct pp_atomctrl_voltage_table
),
919 table
->mask_low
= vol_table
->mask_low
;
920 table
->phase_delay
= vol_table
->phase_delay
;
922 for (i
= 0; i
< vol_table
->count
; i
++) {
923 vvalue
= vol_table
->entries
[i
].value
;
926 for (j
= 0; j
< table
->count
; j
++) {
927 if (vvalue
== table
->entries
[j
].value
) {
934 table
->entries
[table
->count
].value
= vvalue
;
935 table
->entries
[table
->count
].smio_low
=
936 vol_table
->entries
[i
].smio_low
;
941 memcpy(vol_table
, table
, sizeof(struct pp_atomctrl_voltage_table
));
947 static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr
*hwmgr
,
948 phm_ppt_v1_clock_voltage_dependency_table
*dep_table
)
952 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
953 struct pp_atomctrl_voltage_table
*vol_table
= &(data
->mvdd_voltage_table
);
955 PP_ASSERT_WITH_CODE((0 != dep_table
->count
),
956 "Voltage Dependency Table empty.", return -EINVAL
);
958 vol_table
->mask_low
= 0;
959 vol_table
->phase_delay
= 0;
960 vol_table
->count
= dep_table
->count
;
962 for (i
= 0; i
< dep_table
->count
; i
++) {
963 vol_table
->entries
[i
].value
= dep_table
->entries
[i
].mvdd
;
964 vol_table
->entries
[i
].smio_low
= 0;
967 result
= fiji_trim_voltage_table(hwmgr
, vol_table
);
968 PP_ASSERT_WITH_CODE((0 == result
),
969 "Failed to trim MVDD table.", return result
);
974 static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr
*hwmgr
,
975 phm_ppt_v1_clock_voltage_dependency_table
*dep_table
)
979 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
980 struct pp_atomctrl_voltage_table
*vol_table
= &(data
->vddci_voltage_table
);
982 PP_ASSERT_WITH_CODE((0 != dep_table
->count
),
983 "Voltage Dependency Table empty.", return -EINVAL
);
985 vol_table
->mask_low
= 0;
986 vol_table
->phase_delay
= 0;
987 vol_table
->count
= dep_table
->count
;
989 for (i
= 0; i
< dep_table
->count
; i
++) {
990 vol_table
->entries
[i
].value
= dep_table
->entries
[i
].vddci
;
991 vol_table
->entries
[i
].smio_low
= 0;
994 result
= fiji_trim_voltage_table(hwmgr
, vol_table
);
995 PP_ASSERT_WITH_CODE((0 == result
),
996 "Failed to trim VDDCI table.", return result
);
1001 static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr
*hwmgr
,
1002 phm_ppt_v1_voltage_lookup_table
*lookup_table
)
1005 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1006 struct pp_atomctrl_voltage_table
*vol_table
= &(data
->vddc_voltage_table
);
1008 PP_ASSERT_WITH_CODE((0 != lookup_table
->count
),
1009 "Voltage Lookup Table empty.", return -EINVAL
);
1011 vol_table
->mask_low
= 0;
1012 vol_table
->phase_delay
= 0;
1014 vol_table
->count
= lookup_table
->count
;
1016 for (i
= 0; i
< vol_table
->count
; i
++) {
1017 vol_table
->entries
[i
].value
= lookup_table
->entries
[i
].us_vdd
;
1018 vol_table
->entries
[i
].smio_low
= 0;
1024 /* ---- Voltage Tables ----
1025 * If the voltage table would be bigger than
1026 * what will fit into the state table on
1027 * the SMC keep only the higher entries.
1029 static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr
*hwmgr
,
1030 uint32_t max_vol_steps
, struct pp_atomctrl_voltage_table
*vol_table
)
1032 unsigned int i
, diff
;
1034 if (vol_table
->count
<= max_vol_steps
)
1037 diff
= vol_table
->count
- max_vol_steps
;
1039 for (i
= 0; i
< max_vol_steps
; i
++)
1040 vol_table
->entries
[i
] = vol_table
->entries
[i
+ diff
];
1042 vol_table
->count
= max_vol_steps
;
1048 * Create Voltage Tables.
1050 * @param hwmgr the address of the powerplay hardware manager.
1053 static int fiji_construct_voltage_tables(struct pp_hwmgr
*hwmgr
)
1055 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1056 struct phm_ppt_v1_information
*table_info
=
1057 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
1060 if (FIJI_VOLTAGE_CONTROL_BY_GPIO
== data
->mvdd_control
) {
1061 result
= atomctrl_get_voltage_table_v3(hwmgr
,
1062 VOLTAGE_TYPE_MVDDC
, VOLTAGE_OBJ_GPIO_LUT
,
1063 &(data
->mvdd_voltage_table
));
1064 PP_ASSERT_WITH_CODE((0 == result
),
1065 "Failed to retrieve MVDD table.",
1067 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->mvdd_control
) {
1068 result
= fiji_get_svi2_mvdd_voltage_table(hwmgr
,
1069 table_info
->vdd_dep_on_mclk
);
1070 PP_ASSERT_WITH_CODE((0 == result
),
1071 "Failed to retrieve SVI2 MVDD table from dependancy table.",
1075 if (FIJI_VOLTAGE_CONTROL_BY_GPIO
== data
->vddci_control
) {
1076 result
= atomctrl_get_voltage_table_v3(hwmgr
,
1077 VOLTAGE_TYPE_VDDCI
, VOLTAGE_OBJ_GPIO_LUT
,
1078 &(data
->vddci_voltage_table
));
1079 PP_ASSERT_WITH_CODE((0 == result
),
1080 "Failed to retrieve VDDCI table.",
1082 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->vddci_control
) {
1083 result
= fiji_get_svi2_vddci_voltage_table(hwmgr
,
1084 table_info
->vdd_dep_on_mclk
);
1085 PP_ASSERT_WITH_CODE((0 == result
),
1086 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
1090 if(FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
) {
1091 result
= fiji_get_svi2_vdd_voltage_table(hwmgr
,
1092 table_info
->vddc_lookup_table
);
1093 PP_ASSERT_WITH_CODE((0 == result
),
1094 "Failed to retrieve SVI2 VDDC table from lookup table.",
1098 PP_ASSERT_WITH_CODE(
1099 (data
->vddc_voltage_table
.count
<= (SMU73_MAX_LEVELS_VDDC
)),
1100 "Too many voltage values for VDDC. Trimming to fit state table.",
1101 fiji_trim_voltage_table_to_fit_state_table(hwmgr
,
1102 SMU73_MAX_LEVELS_VDDC
, &(data
->vddc_voltage_table
)));
1104 PP_ASSERT_WITH_CODE(
1105 (data
->vddci_voltage_table
.count
<= (SMU73_MAX_LEVELS_VDDCI
)),
1106 "Too many voltage values for VDDCI. Trimming to fit state table.",
1107 fiji_trim_voltage_table_to_fit_state_table(hwmgr
,
1108 SMU73_MAX_LEVELS_VDDCI
, &(data
->vddci_voltage_table
)));
1110 PP_ASSERT_WITH_CODE(
1111 (data
->mvdd_voltage_table
.count
<= (SMU73_MAX_LEVELS_MVDD
)),
1112 "Too many voltage values for MVDD. Trimming to fit state table.",
1113 fiji_trim_voltage_table_to_fit_state_table(hwmgr
,
1114 SMU73_MAX_LEVELS_MVDD
, &(data
->mvdd_voltage_table
)));
1119 static int fiji_initialize_mc_reg_table(struct pp_hwmgr
*hwmgr
)
1121 /* Program additional LP registers
1122 * that are no longer programmed by VBIOS
1124 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RAS_TIMING_LP
,
1125 cgs_read_register(hwmgr
->device
, mmMC_SEQ_RAS_TIMING
));
1126 cgs_write_register(hwmgr
->device
, mmMC_SEQ_CAS_TIMING_LP
,
1127 cgs_read_register(hwmgr
->device
, mmMC_SEQ_CAS_TIMING
));
1128 cgs_write_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING2_LP
,
1129 cgs_read_register(hwmgr
->device
, mmMC_SEQ_MISC_TIMING2
));
1130 cgs_write_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D1_LP
,
1131 cgs_read_register(hwmgr
->device
, mmMC_SEQ_WR_CTL_D1
));
1132 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D0_LP
,
1133 cgs_read_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D0
));
1134 cgs_write_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D1_LP
,
1135 cgs_read_register(hwmgr
->device
, mmMC_SEQ_RD_CTL_D1
));
1136 cgs_write_register(hwmgr
->device
, mmMC_SEQ_PMG_TIMING_LP
,
1137 cgs_read_register(hwmgr
->device
, mmMC_SEQ_PMG_TIMING
));
1143 * Programs static screed detection parameters
1145 * @param hwmgr the address of the powerplay hardware manager.
1148 static int fiji_program_static_screen_threshold_parameters(
1149 struct pp_hwmgr
*hwmgr
)
1151 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1153 /* Set static screen threshold unit */
1154 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1155 CG_STATIC_SCREEN_PARAMETER
, STATIC_SCREEN_THRESHOLD_UNIT
,
1156 data
->static_screen_threshold_unit
);
1157 /* Set static screen threshold */
1158 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1159 CG_STATIC_SCREEN_PARAMETER
, STATIC_SCREEN_THRESHOLD
,
1160 data
->static_screen_threshold
);
1166 * Setup display gap for glitch free memory clock switching.
1168 * @param hwmgr the address of the powerplay hardware manager.
1171 static int fiji_enable_display_gap(struct pp_hwmgr
*hwmgr
)
1173 uint32_t displayGap
=
1174 cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1175 ixCG_DISPLAY_GAP_CNTL
);
1177 displayGap
= PHM_SET_FIELD(displayGap
, CG_DISPLAY_GAP_CNTL
,
1178 DISP_GAP
, DISPLAY_GAP_IGNORE
);
1180 displayGap
= PHM_SET_FIELD(displayGap
, CG_DISPLAY_GAP_CNTL
,
1181 DISP_GAP_MCHG
, DISPLAY_GAP_VBLANK
);
1183 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1184 ixCG_DISPLAY_GAP_CNTL
, displayGap
);
1190 * Programs activity state transition voting clients
1192 * @param hwmgr the address of the powerplay hardware manager.
1195 static int fiji_program_voting_clients(struct pp_hwmgr
*hwmgr
)
1197 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1199 /* Clear reset for voting clients before enabling DPM */
1200 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1201 SCLK_PWRMGT_CNTL
, RESET_SCLK_CNT
, 0);
1202 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
1203 SCLK_PWRMGT_CNTL
, RESET_BUSY_CNT
, 0);
1205 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1206 ixCG_FREQ_TRAN_VOTING_0
, data
->voting_rights_clients0
);
1207 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1208 ixCG_FREQ_TRAN_VOTING_1
, data
->voting_rights_clients1
);
1209 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1210 ixCG_FREQ_TRAN_VOTING_2
, data
->voting_rights_clients2
);
1211 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1212 ixCG_FREQ_TRAN_VOTING_3
, data
->voting_rights_clients3
);
1213 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1214 ixCG_FREQ_TRAN_VOTING_4
, data
->voting_rights_clients4
);
1215 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1216 ixCG_FREQ_TRAN_VOTING_5
, data
->voting_rights_clients5
);
1217 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1218 ixCG_FREQ_TRAN_VOTING_6
, data
->voting_rights_clients6
);
1219 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
1220 ixCG_FREQ_TRAN_VOTING_7
, data
->voting_rights_clients7
);
1226 * Get the location of various tables inside the FW image.
1228 * @param hwmgr the address of the powerplay hardware manager.
1231 static int fiji_process_firmware_header(struct pp_hwmgr
*hwmgr
)
1233 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1234 struct fiji_smumgr
*smu_data
= (struct fiji_smumgr
*)(hwmgr
->smumgr
->backend
);
1239 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1240 SMU7_FIRMWARE_HEADER_LOCATION
+
1241 offsetof(SMU73_Firmware_Header
, DpmTable
),
1242 &tmp
, data
->sram_end
);
1245 data
->dpm_table_start
= tmp
;
1247 error
|= (0 != result
);
1249 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1250 SMU7_FIRMWARE_HEADER_LOCATION
+
1251 offsetof(SMU73_Firmware_Header
, SoftRegisters
),
1252 &tmp
, data
->sram_end
);
1255 data
->soft_regs_start
= tmp
;
1256 smu_data
->soft_regs_start
= tmp
;
1259 error
|= (0 != result
);
1261 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1262 SMU7_FIRMWARE_HEADER_LOCATION
+
1263 offsetof(SMU73_Firmware_Header
, mcRegisterTable
),
1264 &tmp
, data
->sram_end
);
1267 data
->mc_reg_table_start
= tmp
;
1269 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1270 SMU7_FIRMWARE_HEADER_LOCATION
+
1271 offsetof(SMU73_Firmware_Header
, FanTable
),
1272 &tmp
, data
->sram_end
);
1275 data
->fan_table_start
= tmp
;
1277 error
|= (0 != result
);
1279 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1280 SMU7_FIRMWARE_HEADER_LOCATION
+
1281 offsetof(SMU73_Firmware_Header
, mcArbDramTimingTable
),
1282 &tmp
, data
->sram_end
);
1285 data
->arb_table_start
= tmp
;
1287 error
|= (0 != result
);
1289 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
1290 SMU7_FIRMWARE_HEADER_LOCATION
+
1291 offsetof(SMU73_Firmware_Header
, Version
),
1292 &tmp
, data
->sram_end
);
1295 hwmgr
->microcode_version_info
.SMC
= tmp
;
1297 error
|= (0 != result
);
1299 return error
? -1 : 0;
1302 /* Copy one arb setting to another and then switch the active set.
1303 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
1305 static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr
*hwmgr
,
1306 uint32_t arb_src
, uint32_t arb_dest
)
1308 uint32_t mc_arb_dram_timing
;
1309 uint32_t mc_arb_dram_timing2
;
1310 uint32_t burst_time
;
1311 uint32_t mc_cg_config
;
1314 case MC_CG_ARB_FREQ_F0
:
1315 mc_arb_dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
);
1316 mc_arb_dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
);
1317 burst_time
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
);
1319 case MC_CG_ARB_FREQ_F1
:
1320 mc_arb_dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING_1
);
1321 mc_arb_dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2_1
);
1322 burst_time
= PHM_READ_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE1
);
1329 case MC_CG_ARB_FREQ_F0
:
1330 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
, mc_arb_dram_timing
);
1331 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
, mc_arb_dram_timing2
);
1332 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE0
, burst_time
);
1334 case MC_CG_ARB_FREQ_F1
:
1335 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING_1
, mc_arb_dram_timing
);
1336 cgs_write_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2_1
, mc_arb_dram_timing2
);
1337 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_BURST_TIME
, STATE1
, burst_time
);
1343 mc_cg_config
= cgs_read_register(hwmgr
->device
, mmMC_CG_CONFIG
);
1344 mc_cg_config
|= 0x0000000F;
1345 cgs_write_register(hwmgr
->device
, mmMC_CG_CONFIG
, mc_cg_config
);
1346 PHM_WRITE_FIELD(hwmgr
->device
, MC_ARB_CG
, CG_ARB_REQ
, arb_dest
);
1352 * Initial switch from ARB F0->F1
1354 * @param hwmgr the address of the powerplay hardware manager.
1356 * This function is to be called from the SetPowerState table.
1358 static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr
*hwmgr
)
1360 return fiji_copy_and_switch_arb_sets(hwmgr
,
1361 MC_CG_ARB_FREQ_F0
, MC_CG_ARB_FREQ_F1
);
1364 static int fiji_reset_single_dpm_table(struct pp_hwmgr
*hwmgr
,
1365 struct fiji_single_dpm_table
*dpm_table
, uint32_t count
)
1368 PP_ASSERT_WITH_CODE(count
<= MAX_REGULAR_DPM_NUMBER
,
1369 "Fatal error, can not set up single DPM table entries "
1370 "to exceed max number!",);
1372 dpm_table
->count
= count
;
1373 for (i
= 0; i
< MAX_REGULAR_DPM_NUMBER
; i
++)
1374 dpm_table
->dpm_levels
[i
].enabled
= false;
1379 static void fiji_setup_pcie_table_entry(
1380 struct fiji_single_dpm_table
*dpm_table
,
1381 uint32_t index
, uint32_t pcie_gen
,
1382 uint32_t pcie_lanes
)
1384 dpm_table
->dpm_levels
[index
].value
= pcie_gen
;
1385 dpm_table
->dpm_levels
[index
].param1
= pcie_lanes
;
1386 dpm_table
->dpm_levels
[index
].enabled
= 1;
1389 static int fiji_setup_default_pcie_table(struct pp_hwmgr
*hwmgr
)
1391 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1392 struct phm_ppt_v1_information
*table_info
=
1393 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1394 struct phm_ppt_v1_pcie_table
*pcie_table
= table_info
->pcie_table
;
1395 uint32_t i
, max_entry
;
1397 PP_ASSERT_WITH_CODE((data
->use_pcie_performance_levels
||
1398 data
->use_pcie_power_saving_levels
), "No pcie performance levels!",
1401 if (data
->use_pcie_performance_levels
&&
1402 !data
->use_pcie_power_saving_levels
) {
1403 data
->pcie_gen_power_saving
= data
->pcie_gen_performance
;
1404 data
->pcie_lane_power_saving
= data
->pcie_lane_performance
;
1405 } else if (!data
->use_pcie_performance_levels
&&
1406 data
->use_pcie_power_saving_levels
) {
1407 data
->pcie_gen_performance
= data
->pcie_gen_power_saving
;
1408 data
->pcie_lane_performance
= data
->pcie_lane_power_saving
;
1411 fiji_reset_single_dpm_table(hwmgr
,
1412 &data
->dpm_table
.pcie_speed_table
, SMU73_MAX_LEVELS_LINK
);
1414 if (pcie_table
!= NULL
) {
1415 /* max_entry is used to make sure we reserve one PCIE level
1416 * for boot level (fix for A+A PSPP issue).
1417 * If PCIE table from PPTable have ULV entry + 8 entries,
1418 * then ignore the last entry.*/
1419 max_entry
= (SMU73_MAX_LEVELS_LINK
< pcie_table
->count
) ?
1420 SMU73_MAX_LEVELS_LINK
: pcie_table
->count
;
1421 for (i
= 1; i
< max_entry
; i
++) {
1422 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, i
- 1,
1423 get_pcie_gen_support(data
->pcie_gen_cap
,
1424 pcie_table
->entries
[i
].gen_speed
),
1425 get_pcie_lane_support(data
->pcie_lane_cap
,
1426 pcie_table
->entries
[i
].lane_width
));
1428 data
->dpm_table
.pcie_speed_table
.count
= max_entry
- 1;
1430 /* Hardcode Pcie Table */
1431 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 0,
1432 get_pcie_gen_support(data
->pcie_gen_cap
,
1434 get_pcie_lane_support(data
->pcie_lane_cap
,
1436 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 1,
1437 get_pcie_gen_support(data
->pcie_gen_cap
,
1439 get_pcie_lane_support(data
->pcie_lane_cap
,
1441 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 2,
1442 get_pcie_gen_support(data
->pcie_gen_cap
,
1444 get_pcie_lane_support(data
->pcie_lane_cap
,
1446 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 3,
1447 get_pcie_gen_support(data
->pcie_gen_cap
,
1449 get_pcie_lane_support(data
->pcie_lane_cap
,
1451 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 4,
1452 get_pcie_gen_support(data
->pcie_gen_cap
,
1454 get_pcie_lane_support(data
->pcie_lane_cap
,
1456 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
, 5,
1457 get_pcie_gen_support(data
->pcie_gen_cap
,
1459 get_pcie_lane_support(data
->pcie_lane_cap
,
1462 data
->dpm_table
.pcie_speed_table
.count
= 6;
1464 /* Populate last level for boot PCIE level, but do not increment count. */
1465 fiji_setup_pcie_table_entry(&data
->dpm_table
.pcie_speed_table
,
1466 data
->dpm_table
.pcie_speed_table
.count
,
1467 get_pcie_gen_support(data
->pcie_gen_cap
,
1469 get_pcie_lane_support(data
->pcie_lane_cap
,
1476 * This function is to initalize all DPM state tables
1477 * for SMU7 based on the dependency table.
1478 * Dynamic state patching function will then trim these
1479 * state tables to the allowed range based
1480 * on the power policy or external client requests,
1481 * such as UVD request, etc.
1483 static int fiji_setup_default_dpm_tables(struct pp_hwmgr
*hwmgr
)
1485 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1486 struct phm_ppt_v1_information
*table_info
=
1487 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1490 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_sclk_table
=
1491 table_info
->vdd_dep_on_sclk
;
1492 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_mclk_table
=
1493 table_info
->vdd_dep_on_mclk
;
1495 PP_ASSERT_WITH_CODE(dep_sclk_table
!= NULL
,
1496 "SCLK dependency table is missing. This table is mandatory",
1498 PP_ASSERT_WITH_CODE(dep_sclk_table
->count
>= 1,
1499 "SCLK dependency table has to have is missing. "
1500 "This table is mandatory",
1503 PP_ASSERT_WITH_CODE(dep_mclk_table
!= NULL
,
1504 "MCLK dependency table is missing. This table is mandatory",
1506 PP_ASSERT_WITH_CODE(dep_mclk_table
->count
>= 1,
1507 "MCLK dependency table has to have is missing. "
1508 "This table is mandatory",
1511 /* clear the state table to reset everything to default */
1512 fiji_reset_single_dpm_table(hwmgr
,
1513 &data
->dpm_table
.sclk_table
, SMU73_MAX_LEVELS_GRAPHICS
);
1514 fiji_reset_single_dpm_table(hwmgr
,
1515 &data
->dpm_table
.mclk_table
, SMU73_MAX_LEVELS_MEMORY
);
1517 /* Initialize Sclk DPM table based on allow Sclk values */
1518 data
->dpm_table
.sclk_table
.count
= 0;
1519 for (i
= 0; i
< dep_sclk_table
->count
; i
++) {
1520 if (i
== 0 || data
->dpm_table
.sclk_table
.dpm_levels
1521 [data
->dpm_table
.sclk_table
.count
- 1].value
!=
1522 dep_sclk_table
->entries
[i
].clk
) {
1523 data
->dpm_table
.sclk_table
.dpm_levels
1524 [data
->dpm_table
.sclk_table
.count
].value
=
1525 dep_sclk_table
->entries
[i
].clk
;
1526 data
->dpm_table
.sclk_table
.dpm_levels
1527 [data
->dpm_table
.sclk_table
.count
].enabled
=
1528 (i
== 0) ? true : false;
1529 data
->dpm_table
.sclk_table
.count
++;
1533 /* Initialize Mclk DPM table based on allow Mclk values */
1534 data
->dpm_table
.mclk_table
.count
= 0;
1535 for (i
=0; i
<dep_mclk_table
->count
; i
++) {
1536 if ( i
==0 || data
->dpm_table
.mclk_table
.dpm_levels
1537 [data
->dpm_table
.mclk_table
.count
- 1].value
!=
1538 dep_mclk_table
->entries
[i
].clk
) {
1539 data
->dpm_table
.mclk_table
.dpm_levels
1540 [data
->dpm_table
.mclk_table
.count
].value
=
1541 dep_mclk_table
->entries
[i
].clk
;
1542 data
->dpm_table
.mclk_table
.dpm_levels
1543 [data
->dpm_table
.mclk_table
.count
].enabled
=
1544 (i
== 0) ? true : false;
1545 data
->dpm_table
.mclk_table
.count
++;
1549 /* setup PCIE gen speed levels */
1550 fiji_setup_default_pcie_table(hwmgr
);
1552 /* save a copy of the default DPM table */
1553 memcpy(&(data
->golden_dpm_table
), &(data
->dpm_table
),
1554 sizeof(struct fiji_dpm_table
));
1560 * @brief PhwFiji_GetVoltageOrder
1561 * Returns index of requested voltage record in lookup(table)
1562 * @param lookup_table - lookup list to search in
1563 * @param voltage - voltage to look for
1564 * @return 0 on success
1566 uint8_t fiji_get_voltage_index(
1567 struct phm_ppt_v1_voltage_lookup_table
*lookup_table
, uint16_t voltage
)
1569 uint8_t count
= (uint8_t) (lookup_table
->count
);
1572 PP_ASSERT_WITH_CODE((NULL
!= lookup_table
),
1573 "Lookup Table empty.", return 0);
1574 PP_ASSERT_WITH_CODE((0 != count
),
1575 "Lookup Table empty.", return 0);
1577 for (i
= 0; i
< lookup_table
->count
; i
++) {
1578 /* find first voltage equal or bigger than requested */
1579 if (lookup_table
->entries
[i
].us_vdd
>= voltage
)
1582 /* voltage is bigger than max voltage in the table */
1587 * Preparation of vddc and vddgfx CAC tables for SMC.
1589 * @param hwmgr the address of the hardware manager
1590 * @param table the SMC DPM table structure to be populated
1593 static int fiji_populate_cac_table(struct pp_hwmgr
*hwmgr
,
1594 struct SMU73_Discrete_DpmTable
*table
)
1599 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1600 struct phm_ppt_v1_information
*table_info
=
1601 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1602 struct phm_ppt_v1_voltage_lookup_table
*lookup_table
=
1603 table_info
->vddc_lookup_table
;
1604 /* tables is already swapped, so in order to use the value from it,
1605 * we need to swap it back.
1606 * We are populating vddc CAC data to BapmVddc table
1607 * in split and merged mode
1609 for( count
= 0; count
<lookup_table
->count
; count
++) {
1610 index
= fiji_get_voltage_index(lookup_table
,
1611 data
->vddc_voltage_table
.entries
[count
].value
);
1612 table
->BapmVddcVidLoSidd
[count
] = (uint8_t) ((6200 -
1613 (lookup_table
->entries
[index
].us_cac_low
*
1614 VOLTAGE_SCALE
)) / 25);
1615 table
->BapmVddcVidHiSidd
[count
] = (uint8_t) ((6200 -
1616 (lookup_table
->entries
[index
].us_cac_high
*
1617 VOLTAGE_SCALE
)) / 25);
1624 * Preparation of voltage tables for SMC.
1626 * @param hwmgr the address of the hardware manager
1627 * @param table the SMC DPM table structure to be populated
1631 int fiji_populate_smc_voltage_tables(struct pp_hwmgr
*hwmgr
,
1632 struct SMU73_Discrete_DpmTable
*table
)
1636 result
= fiji_populate_cac_table(hwmgr
, table
);
1637 PP_ASSERT_WITH_CODE(0 == result
,
1638 "can not populate CAC voltage tables to SMC",
1644 static int fiji_populate_ulv_level(struct pp_hwmgr
*hwmgr
,
1645 struct SMU73_Discrete_Ulv
*state
)
1648 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1649 struct phm_ppt_v1_information
*table_info
=
1650 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1652 state
->CcPwrDynRm
= 0;
1653 state
->CcPwrDynRm1
= 0;
1655 state
->VddcOffset
= (uint16_t) table_info
->us_ulv_voltage_offset
;
1656 state
->VddcOffsetVid
= (uint8_t)( table_info
->us_ulv_voltage_offset
*
1657 VOLTAGE_VID_OFFSET_SCALE2
/ VOLTAGE_VID_OFFSET_SCALE1
);
1659 state
->VddcPhase
= (data
->vddc_phase_shed_control
) ? 0 : 1;
1662 CONVERT_FROM_HOST_TO_SMC_UL(state
->CcPwrDynRm
);
1663 CONVERT_FROM_HOST_TO_SMC_UL(state
->CcPwrDynRm1
);
1664 CONVERT_FROM_HOST_TO_SMC_US(state
->VddcOffset
);
1669 static int fiji_populate_ulv_state(struct pp_hwmgr
*hwmgr
,
1670 struct SMU73_Discrete_DpmTable
*table
)
1672 return fiji_populate_ulv_level(hwmgr
, &table
->Ulv
);
1675 static int32_t fiji_get_dpm_level_enable_mask_value(
1676 struct fiji_single_dpm_table
* dpm_table
)
1681 for (i
= dpm_table
->count
; i
> 0; i
--) {
1683 if (dpm_table
->dpm_levels
[i
- 1].enabled
)
1691 static int fiji_populate_smc_link_level(struct pp_hwmgr
*hwmgr
,
1692 struct SMU73_Discrete_DpmTable
*table
)
1694 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1695 struct fiji_dpm_table
*dpm_table
= &data
->dpm_table
;
1698 /* Index (dpm_table->pcie_speed_table.count)
1699 * is reserved for PCIE boot level. */
1700 for (i
= 0; i
<= dpm_table
->pcie_speed_table
.count
; i
++) {
1701 table
->LinkLevel
[i
].PcieGenSpeed
=
1702 (uint8_t)dpm_table
->pcie_speed_table
.dpm_levels
[i
].value
;
1703 table
->LinkLevel
[i
].PcieLaneCount
= (uint8_t)encode_pcie_lane_width(
1704 dpm_table
->pcie_speed_table
.dpm_levels
[i
].param1
);
1705 table
->LinkLevel
[i
].EnabledForActivity
= 1;
1706 table
->LinkLevel
[i
].SPC
= (uint8_t)(data
->pcie_spc_cap
& 0xff);
1707 table
->LinkLevel
[i
].DownThreshold
= PP_HOST_TO_SMC_UL(5);
1708 table
->LinkLevel
[i
].UpThreshold
= PP_HOST_TO_SMC_UL(30);
1711 data
->smc_state_table
.LinkLevelCount
=
1712 (uint8_t)dpm_table
->pcie_speed_table
.count
;
1713 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
=
1714 fiji_get_dpm_level_enable_mask_value(&dpm_table
->pcie_speed_table
);
1720 * Calculates the SCLK dividers using the provided engine clock
1722 * @param hwmgr the address of the hardware manager
1723 * @param clock the engine clock to use to populate the structure
1724 * @param sclk the SMC SCLK structure to be populated
1726 static int fiji_calculate_sclk_params(struct pp_hwmgr
*hwmgr
,
1727 uint32_t clock
, struct SMU73_Discrete_GraphicsLevel
*sclk
)
1729 const struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1730 struct pp_atomctrl_clock_dividers_vi dividers
;
1731 uint32_t spll_func_cntl
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL
;
1732 uint32_t spll_func_cntl_3
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
;
1733 uint32_t spll_func_cntl_4
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
;
1734 uint32_t cg_spll_spread_spectrum
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
;
1735 uint32_t cg_spll_spread_spectrum_2
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
;
1737 uint32_t ref_divider
;
1741 /* get the engine clock dividers for this clock value */
1742 result
= atomctrl_get_engine_pll_dividers_vi(hwmgr
, clock
, ÷rs
);
1744 PP_ASSERT_WITH_CODE(result
== 0,
1745 "Error retrieving Engine Clock dividers from VBIOS.",
1748 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
1749 ref_clock
= atomctrl_get_reference_clock(hwmgr
);
1750 ref_divider
= 1 + dividers
.uc_pll_ref_div
;
1752 /* low 14 bits is fraction and high 12 bits is divider */
1753 fbdiv
= dividers
.ul_fb_div
.ul_fb_divider
& 0x3FFFFFF;
1755 /* SPLL_FUNC_CNTL setup */
1756 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
, CG_SPLL_FUNC_CNTL
,
1757 SPLL_REF_DIV
, dividers
.uc_pll_ref_div
);
1758 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
, CG_SPLL_FUNC_CNTL
,
1759 SPLL_PDIV_A
, dividers
.uc_pll_post_div
);
1761 /* SPLL_FUNC_CNTL_3 setup*/
1762 spll_func_cntl_3
= PHM_SET_FIELD(spll_func_cntl_3
, CG_SPLL_FUNC_CNTL_3
,
1763 SPLL_FB_DIV
, fbdiv
);
1765 /* set to use fractional accumulation*/
1766 spll_func_cntl_3
= PHM_SET_FIELD(spll_func_cntl_3
, CG_SPLL_FUNC_CNTL_3
,
1769 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
1770 PHM_PlatformCaps_EngineSpreadSpectrumSupport
)) {
1771 struct pp_atomctrl_internal_ss_info ssInfo
;
1773 uint32_t vco_freq
= clock
* dividers
.uc_pll_post_div
;
1774 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr
,
1775 vco_freq
, &ssInfo
)) {
1777 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
1778 * ss_info.speed_spectrum_rate -- in unit of khz
1780 * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
1782 uint32_t clk_s
= ref_clock
* 5 /
1783 (ref_divider
* ssInfo
.speed_spectrum_rate
);
1784 /* clkv = 2 * D * fbdiv / NS */
1785 uint32_t clk_v
= 4 * ssInfo
.speed_spectrum_percentage
*
1786 fbdiv
/ (clk_s
* 10000);
1788 cg_spll_spread_spectrum
= PHM_SET_FIELD(cg_spll_spread_spectrum
,
1789 CG_SPLL_SPREAD_SPECTRUM
, CLKS
, clk_s
);
1790 cg_spll_spread_spectrum
= PHM_SET_FIELD(cg_spll_spread_spectrum
,
1791 CG_SPLL_SPREAD_SPECTRUM
, SSEN
, 1);
1792 cg_spll_spread_spectrum_2
= PHM_SET_FIELD(cg_spll_spread_spectrum_2
,
1793 CG_SPLL_SPREAD_SPECTRUM_2
, CLKV
, clk_v
);
1797 sclk
->SclkFrequency
= clock
;
1798 sclk
->CgSpllFuncCntl3
= spll_func_cntl_3
;
1799 sclk
->CgSpllFuncCntl4
= spll_func_cntl_4
;
1800 sclk
->SpllSpreadSpectrum
= cg_spll_spread_spectrum
;
1801 sclk
->SpllSpreadSpectrum2
= cg_spll_spread_spectrum_2
;
1802 sclk
->SclkDid
= (uint8_t)dividers
.pll_post_divider
;
1807 static uint16_t fiji_find_closest_vddci(struct pp_hwmgr
*hwmgr
, uint16_t vddci
)
1810 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1811 struct pp_atomctrl_voltage_table
*vddci_table
=
1812 &(data
->vddci_voltage_table
);
1814 for (i
= 0; i
< vddci_table
->count
; i
++) {
1815 if (vddci_table
->entries
[i
].value
>= vddci
)
1816 return vddci_table
->entries
[i
].value
;
1819 PP_ASSERT_WITH_CODE(false,
1820 "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
1821 return vddci_table
->entries
[i
].value
);
1824 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr
*hwmgr
,
1825 struct phm_ppt_v1_clock_voltage_dependency_table
* dep_table
,
1826 uint32_t clock
, SMU_VoltageLevel
*voltage
, uint32_t *mvdd
)
1830 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1832 *voltage
= *mvdd
= 0;
1834 /* clock - voltage dependency table is empty table */
1835 if (dep_table
->count
== 0)
1838 for (i
= 0; i
< dep_table
->count
; i
++) {
1839 /* find first sclk bigger than request */
1840 if (dep_table
->entries
[i
].clk
>= clock
) {
1841 *voltage
|= (dep_table
->entries
[i
].vddc
*
1842 VOLTAGE_SCALE
) << VDDC_SHIFT
;
1843 if (FIJI_VOLTAGE_CONTROL_NONE
== data
->vddci_control
)
1844 *voltage
|= (data
->vbios_boot_state
.vddci_bootup_value
*
1845 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1846 else if (dep_table
->entries
[i
].vddci
)
1847 *voltage
|= (dep_table
->entries
[i
].vddci
*
1848 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1850 vddci
= fiji_find_closest_vddci(hwmgr
,
1851 (dep_table
->entries
[i
].vddc
-
1852 (uint16_t)data
->vddc_vddci_delta
));
1853 *voltage
|= (vddci
* VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1856 if (FIJI_VOLTAGE_CONTROL_NONE
== data
->mvdd_control
)
1857 *mvdd
= data
->vbios_boot_state
.mvdd_bootup_value
*
1859 else if (dep_table
->entries
[i
].mvdd
)
1860 *mvdd
= (uint32_t) dep_table
->entries
[i
].mvdd
*
1863 *voltage
|= 1 << PHASES_SHIFT
;
1868 /* sclk is bigger than max sclk in the dependence table */
1869 *voltage
|= (dep_table
->entries
[i
- 1].vddc
* VOLTAGE_SCALE
) << VDDC_SHIFT
;
1871 if (FIJI_VOLTAGE_CONTROL_NONE
== data
->vddci_control
)
1872 *voltage
|= (data
->vbios_boot_state
.vddci_bootup_value
*
1873 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1874 else if (dep_table
->entries
[i
-1].vddci
) {
1875 vddci
= fiji_find_closest_vddci(hwmgr
,
1876 (dep_table
->entries
[i
].vddc
-
1877 (uint16_t)data
->vddc_vddci_delta
));
1878 *voltage
|= (vddci
* VOLTAGE_SCALE
) << VDDCI_SHIFT
;
1881 if (FIJI_VOLTAGE_CONTROL_NONE
== data
->mvdd_control
)
1882 *mvdd
= data
->vbios_boot_state
.mvdd_bootup_value
* VOLTAGE_SCALE
;
1883 else if (dep_table
->entries
[i
].mvdd
)
1884 *mvdd
= (uint32_t) dep_table
->entries
[i
- 1].mvdd
* VOLTAGE_SCALE
;
1889 * Populates single SMC SCLK structure using the provided engine clock
1891 * @param hwmgr the address of the hardware manager
1892 * @param clock the engine clock to use to populate the structure
1893 * @param sclk the SMC SCLK structure to be populated
1896 static int fiji_populate_single_graphic_level(struct pp_hwmgr
*hwmgr
,
1897 uint32_t clock
, uint16_t sclk_al_threshold
,
1898 struct SMU73_Discrete_GraphicsLevel
*level
)
1901 /* PP_Clocks minClocks; */
1902 uint32_t threshold
, mvdd
;
1903 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1904 struct phm_ppt_v1_information
*table_info
=
1905 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1907 result
= fiji_calculate_sclk_params(hwmgr
, clock
, level
);
1909 /* populate graphics levels */
1910 result
= fiji_get_dependency_volt_by_clk(hwmgr
,
1911 table_info
->vdd_dep_on_sclk
, clock
,
1912 &level
->MinVoltage
, &mvdd
);
1913 PP_ASSERT_WITH_CODE((0 == result
),
1914 "can not find VDDC voltage value for "
1915 "VDDC engine clock dependency table",
1918 level
->SclkFrequency
= clock
;
1919 level
->ActivityLevel
= sclk_al_threshold
;
1920 level
->CcPwrDynRm
= 0;
1921 level
->CcPwrDynRm1
= 0;
1922 level
->EnabledForActivity
= 0;
1923 level
->EnabledForThrottle
= 1;
1925 level
->DownHyst
= 0;
1926 level
->VoltageDownHyst
= 0;
1927 level
->PowerThrottle
= 0;
1929 threshold
= clock
* data
->fast_watermark_threshold
/ 100;
1932 * TODO: get minimum clocks from dal configaration
1933 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1935 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1937 /* get level->DeepSleepDivId
1938 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1940 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1943 /* Default to slow, highest DPM level will be
1944 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1946 level
->DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
1948 CONVERT_FROM_HOST_TO_SMC_UL(level
->MinVoltage
);
1949 CONVERT_FROM_HOST_TO_SMC_UL(level
->SclkFrequency
);
1950 CONVERT_FROM_HOST_TO_SMC_US(level
->ActivityLevel
);
1951 CONVERT_FROM_HOST_TO_SMC_UL(level
->CgSpllFuncCntl3
);
1952 CONVERT_FROM_HOST_TO_SMC_UL(level
->CgSpllFuncCntl4
);
1953 CONVERT_FROM_HOST_TO_SMC_UL(level
->SpllSpreadSpectrum
);
1954 CONVERT_FROM_HOST_TO_SMC_UL(level
->SpllSpreadSpectrum2
);
1955 CONVERT_FROM_HOST_TO_SMC_UL(level
->CcPwrDynRm
);
1956 CONVERT_FROM_HOST_TO_SMC_UL(level
->CcPwrDynRm1
);
1961 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1963 * @param hwmgr the address of the hardware manager
1965 static int fiji_populate_all_graphic_levels(struct pp_hwmgr
*hwmgr
)
1967 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
1968 struct fiji_dpm_table
*dpm_table
= &data
->dpm_table
;
1969 struct phm_ppt_v1_information
*table_info
=
1970 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
1971 struct phm_ppt_v1_pcie_table
*pcie_table
= table_info
->pcie_table
;
1972 uint8_t pcie_entry_cnt
= (uint8_t) data
->dpm_table
.pcie_speed_table
.count
;
1974 uint32_t array
= data
->dpm_table_start
+
1975 offsetof(SMU73_Discrete_DpmTable
, GraphicsLevel
);
1976 uint32_t array_size
= sizeof(struct SMU73_Discrete_GraphicsLevel
) *
1977 SMU73_MAX_LEVELS_GRAPHICS
;
1978 struct SMU73_Discrete_GraphicsLevel
*levels
=
1979 data
->smc_state_table
.GraphicsLevel
;
1980 uint32_t i
, max_entry
;
1981 uint8_t hightest_pcie_level_enabled
= 0,
1982 lowest_pcie_level_enabled
= 0,
1983 mid_pcie_level_enabled
= 0,
1986 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
1987 result
= fiji_populate_single_graphic_level(hwmgr
,
1988 dpm_table
->sclk_table
.dpm_levels
[i
].value
,
1989 (uint16_t)data
->activity_target
[i
],
1994 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1996 levels
[i
].DeepSleepDivId
= 0;
1999 /* Only enable level 0 for now.*/
2000 levels
[0].EnabledForActivity
= 1;
2002 /* set highest level watermark to high */
2003 levels
[dpm_table
->sclk_table
.count
- 1].DisplayWatermark
=
2004 PPSMC_DISPLAY_WATERMARK_HIGH
;
2006 data
->smc_state_table
.GraphicsDpmLevelCount
=
2007 (uint8_t)dpm_table
->sclk_table
.count
;
2008 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
=
2009 fiji_get_dpm_level_enable_mask_value(&dpm_table
->sclk_table
);
2011 if (pcie_table
!= NULL
) {
2012 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt
),
2013 "There must be 1 or more PCIE levels defined in PPTable.",
2015 max_entry
= pcie_entry_cnt
- 1;
2016 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++)
2017 levels
[i
].pcieDpmLevel
=
2018 (uint8_t) ((i
< max_entry
)? i
: max_entry
);
2020 while (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&&
2021 ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
2022 (1 << (hightest_pcie_level_enabled
+ 1))) != 0 ))
2023 hightest_pcie_level_enabled
++;
2025 while (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&&
2026 ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
2027 (1 << lowest_pcie_level_enabled
)) == 0 ))
2028 lowest_pcie_level_enabled
++;
2030 while ((count
< hightest_pcie_level_enabled
) &&
2031 ((data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
&
2032 (1 << (lowest_pcie_level_enabled
+ 1 + count
))) == 0 ))
2035 mid_pcie_level_enabled
= (lowest_pcie_level_enabled
+ 1+ count
) <
2036 hightest_pcie_level_enabled
?
2037 (lowest_pcie_level_enabled
+ 1 + count
) :
2038 hightest_pcie_level_enabled
;
2040 /* set pcieDpmLevel to hightest_pcie_level_enabled */
2041 for(i
= 2; i
< dpm_table
->sclk_table
.count
; i
++)
2042 levels
[i
].pcieDpmLevel
= hightest_pcie_level_enabled
;
2044 /* set pcieDpmLevel to lowest_pcie_level_enabled */
2045 levels
[0].pcieDpmLevel
= lowest_pcie_level_enabled
;
2047 /* set pcieDpmLevel to mid_pcie_level_enabled */
2048 levels
[1].pcieDpmLevel
= mid_pcie_level_enabled
;
2050 /* level count will send to smc once at init smc table and never change */
2051 result
= fiji_copy_bytes_to_smc(hwmgr
->smumgr
, array
, (uint8_t *)levels
,
2052 (uint32_t)array_size
, data
->sram_end
);
2058 * MCLK Frequency Ratio
2059 * SEQ_CG_RESP Bit[31:24] - 0x0
2060 * Bit[27:24] \96 DDR3 Frequency ratio
2061 * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz
2062 * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz
2063 * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz
2064 * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz
2065 * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz
2066 * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz
2067 * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz
2068 * 400 < 0x7 <= 450MHz, 800 < 0xF
2070 static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock
)
2072 if (mem_clock
<= 10000) return 0x0;
2073 if (mem_clock
<= 15000) return 0x1;
2074 if (mem_clock
<= 20000) return 0x2;
2075 if (mem_clock
<= 25000) return 0x3;
2076 if (mem_clock
<= 30000) return 0x4;
2077 if (mem_clock
<= 35000) return 0x5;
2078 if (mem_clock
<= 40000) return 0x6;
2079 if (mem_clock
<= 45000) return 0x7;
2080 if (mem_clock
<= 50000) return 0x8;
2081 if (mem_clock
<= 55000) return 0x9;
2082 if (mem_clock
<= 60000) return 0xa;
2083 if (mem_clock
<= 65000) return 0xb;
2084 if (mem_clock
<= 70000) return 0xc;
2085 if (mem_clock
<= 75000) return 0xd;
2086 if (mem_clock
<= 80000) return 0xe;
2087 /* mem_clock > 800MHz */
2092 * Populates the SMC MCLK structure using the provided memory clock
2094 * @param hwmgr the address of the hardware manager
2095 * @param clock the memory clock to use to populate the structure
2096 * @param sclk the SMC SCLK structure to be populated
2098 static int fiji_calculate_mclk_params(struct pp_hwmgr
*hwmgr
,
2099 uint32_t clock
, struct SMU73_Discrete_MemoryLevel
*mclk
)
2101 struct pp_atomctrl_memory_clock_param mem_param
;
2104 result
= atomctrl_get_memory_pll_dividers_vi(hwmgr
, clock
, &mem_param
);
2105 PP_ASSERT_WITH_CODE((0 == result
),
2106 "Failed to get Memory PLL Dividers.",);
2108 /* Save the result data to outpupt memory level structure */
2109 mclk
->MclkFrequency
= clock
;
2110 mclk
->MclkDivider
= (uint8_t)mem_param
.mpll_post_divider
;
2111 mclk
->FreqRange
= fiji_get_mclk_frequency_ratio(clock
);
2116 static int fiji_populate_single_memory_level(struct pp_hwmgr
*hwmgr
,
2117 uint32_t clock
, struct SMU73_Discrete_MemoryLevel
*mem_level
)
2119 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2120 struct phm_ppt_v1_information
*table_info
=
2121 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2124 if (table_info
->vdd_dep_on_mclk
) {
2125 result
= fiji_get_dependency_volt_by_clk(hwmgr
,
2126 table_info
->vdd_dep_on_mclk
, clock
,
2127 &mem_level
->MinVoltage
, &mem_level
->MinMvdd
);
2128 PP_ASSERT_WITH_CODE((0 == result
),
2129 "can not find MinVddc voltage value from memory "
2130 "VDDC voltage dependency table", return result
);
2133 mem_level
->EnabledForThrottle
= 1;
2134 mem_level
->EnabledForActivity
= 0;
2135 mem_level
->UpHyst
= 0;
2136 mem_level
->DownHyst
= 100;
2137 mem_level
->VoltageDownHyst
= 0;
2138 mem_level
->ActivityLevel
= (uint16_t)data
->mclk_activity_target
;
2139 mem_level
->StutterEnable
= false;
2141 mem_level
->DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
2143 /* enable stutter mode if all the follow condition applied
2144 * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
2145 * &(data->DisplayTiming.numExistingDisplays));
2147 data
->display_timing
.num_existing_displays
= 1;
2149 if ((data
->mclk_stutter_mode_threshold
) &&
2150 (clock
<= data
->mclk_stutter_mode_threshold
) &&
2151 (!data
->is_uvd_enabled
) &&
2152 (PHM_READ_FIELD(hwmgr
->device
, DPG_PIPE_STUTTER_CONTROL
,
2153 STUTTER_ENABLE
) & 0x1))
2154 mem_level
->StutterEnable
= true;
2156 result
= fiji_calculate_mclk_params(hwmgr
, clock
, mem_level
);
2158 CONVERT_FROM_HOST_TO_SMC_UL(mem_level
->MinMvdd
);
2159 CONVERT_FROM_HOST_TO_SMC_UL(mem_level
->MclkFrequency
);
2160 CONVERT_FROM_HOST_TO_SMC_US(mem_level
->ActivityLevel
);
2161 CONVERT_FROM_HOST_TO_SMC_UL(mem_level
->MinVoltage
);
2167 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2169 * @param hwmgr the address of the hardware manager
2171 static int fiji_populate_all_memory_levels(struct pp_hwmgr
*hwmgr
)
2173 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2174 struct fiji_dpm_table
*dpm_table
= &data
->dpm_table
;
2176 /* populate MCLK dpm table to SMU7 */
2177 uint32_t array
= data
->dpm_table_start
+
2178 offsetof(SMU73_Discrete_DpmTable
, MemoryLevel
);
2179 uint32_t array_size
= sizeof(SMU73_Discrete_MemoryLevel
) *
2180 SMU73_MAX_LEVELS_MEMORY
;
2181 struct SMU73_Discrete_MemoryLevel
*levels
=
2182 data
->smc_state_table
.MemoryLevel
;
2185 for (i
= 0; i
< dpm_table
->mclk_table
.count
; i
++) {
2186 PP_ASSERT_WITH_CODE((0 != dpm_table
->mclk_table
.dpm_levels
[i
].value
),
2187 "can not populate memory level as memory clock is zero",
2189 result
= fiji_populate_single_memory_level(hwmgr
,
2190 dpm_table
->mclk_table
.dpm_levels
[i
].value
,
2196 /* Only enable level 0 for now. */
2197 levels
[0].EnabledForActivity
= 1;
2199 /* in order to prevent MC activity from stutter mode to push DPM up.
2200 * the UVD change complements this by putting the MCLK in
2201 * a higher state by default such that we are not effected by
2202 * up threshold or and MCLK DPM latency.
2204 levels
[0].ActivityLevel
= (uint16_t)data
->mclk_dpm0_activity_target
;
2205 CONVERT_FROM_HOST_TO_SMC_US(levels
[0].ActivityLevel
);
2207 data
->smc_state_table
.MemoryDpmLevelCount
=
2208 (uint8_t)dpm_table
->mclk_table
.count
;
2209 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
=
2210 fiji_get_dpm_level_enable_mask_value(&dpm_table
->mclk_table
);
2211 /* set highest level watermark to high */
2212 levels
[dpm_table
->mclk_table
.count
- 1].DisplayWatermark
=
2213 PPSMC_DISPLAY_WATERMARK_HIGH
;
2215 /* level count will send to smc once at init smc table and never change */
2216 result
= fiji_copy_bytes_to_smc(hwmgr
->smumgr
, array
, (uint8_t *)levels
,
2217 (uint32_t)array_size
, data
->sram_end
);
2223 * Populates the SMC MVDD structure using the provided memory clock.
2225 * @param hwmgr the address of the hardware manager
2226 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2227 * @param voltage the SMC VOLTAGE structure to be populated
2229 int fiji_populate_mvdd_value(struct pp_hwmgr
*hwmgr
,
2230 uint32_t mclk
, SMIO_Pattern
*smio_pat
)
2232 const struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2233 struct phm_ppt_v1_information
*table_info
=
2234 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2237 if (FIJI_VOLTAGE_CONTROL_NONE
!= data
->mvdd_control
) {
2238 /* find mvdd value which clock is more than request */
2239 for (i
= 0; i
< table_info
->vdd_dep_on_mclk
->count
; i
++) {
2240 if (mclk
<= table_info
->vdd_dep_on_mclk
->entries
[i
].clk
) {
2241 smio_pat
->Voltage
= data
->mvdd_voltage_table
.entries
[i
].value
;
2245 PP_ASSERT_WITH_CODE(i
< table_info
->vdd_dep_on_mclk
->count
,
2246 "MVDD Voltage is outside the supported range.",
2254 static int fiji_populate_smc_acpi_level(struct pp_hwmgr
*hwmgr
,
2255 SMU73_Discrete_DpmTable
*table
)
2258 const struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2259 struct phm_ppt_v1_information
*table_info
=
2260 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2261 struct pp_atomctrl_clock_dividers_vi dividers
;
2262 SMIO_Pattern vol_level
;
2265 uint32_t spll_func_cntl
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL
;
2266 uint32_t spll_func_cntl_2
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_2
;
2268 table
->ACPILevel
.Flags
&= ~PPSMC_SWSTATE_FLAG_DC
;
2270 if (!data
->sclk_dpm_key_disabled
) {
2271 /* Get MinVoltage and Frequency from DPM0,
2272 * already converted to SMC_UL */
2273 table
->ACPILevel
.SclkFrequency
=
2274 data
->dpm_table
.sclk_table
.dpm_levels
[0].value
;
2275 result
= fiji_get_dependency_volt_by_clk(hwmgr
,
2276 table_info
->vdd_dep_on_sclk
,
2277 table
->ACPILevel
.SclkFrequency
,
2278 &table
->ACPILevel
.MinVoltage
, &mvdd
);
2279 PP_ASSERT_WITH_CODE((0 == result
),
2280 "Cannot find ACPI VDDC voltage value "
2281 "in Clock Dependency Table",);
2283 table
->ACPILevel
.SclkFrequency
=
2284 data
->vbios_boot_state
.sclk_bootup_value
;
2285 table
->ACPILevel
.MinVoltage
=
2286 data
->vbios_boot_state
.vddc_bootup_value
* VOLTAGE_SCALE
;
2289 /* get the engine clock dividers for this clock value */
2290 result
= atomctrl_get_engine_pll_dividers_vi(hwmgr
,
2291 table
->ACPILevel
.SclkFrequency
, ÷rs
);
2292 PP_ASSERT_WITH_CODE(result
== 0,
2293 "Error retrieving Engine Clock dividers from VBIOS.",
2296 table
->ACPILevel
.SclkDid
= (uint8_t)dividers
.pll_post_divider
;
2297 table
->ACPILevel
.DisplayWatermark
= PPSMC_DISPLAY_WATERMARK_LOW
;
2298 table
->ACPILevel
.DeepSleepDivId
= 0;
2300 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
, CG_SPLL_FUNC_CNTL
,
2302 spll_func_cntl
= PHM_SET_FIELD(spll_func_cntl
, CG_SPLL_FUNC_CNTL
,
2304 spll_func_cntl_2
= PHM_SET_FIELD(spll_func_cntl_2
, CG_SPLL_FUNC_CNTL_2
,
2307 table
->ACPILevel
.CgSpllFuncCntl
= spll_func_cntl
;
2308 table
->ACPILevel
.CgSpllFuncCntl2
= spll_func_cntl_2
;
2309 table
->ACPILevel
.CgSpllFuncCntl3
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_3
;
2310 table
->ACPILevel
.CgSpllFuncCntl4
= data
->clock_registers
.vCG_SPLL_FUNC_CNTL_4
;
2311 table
->ACPILevel
.SpllSpreadSpectrum
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM
;
2312 table
->ACPILevel
.SpllSpreadSpectrum2
= data
->clock_registers
.vCG_SPLL_SPREAD_SPECTRUM_2
;
2313 table
->ACPILevel
.CcPwrDynRm
= 0;
2314 table
->ACPILevel
.CcPwrDynRm1
= 0;
2316 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.Flags
);
2317 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SclkFrequency
);
2318 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.MinVoltage
);
2319 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl
);
2320 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl2
);
2321 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl3
);
2322 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CgSpllFuncCntl4
);
2323 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SpllSpreadSpectrum
);
2324 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.SpllSpreadSpectrum2
);
2325 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CcPwrDynRm
);
2326 CONVERT_FROM_HOST_TO_SMC_UL(table
->ACPILevel
.CcPwrDynRm1
);
2328 if (!data
->mclk_dpm_key_disabled
) {
2329 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
2330 table
->MemoryACPILevel
.MclkFrequency
=
2331 data
->dpm_table
.mclk_table
.dpm_levels
[0].value
;
2332 result
= fiji_get_dependency_volt_by_clk(hwmgr
,
2333 table_info
->vdd_dep_on_mclk
,
2334 table
->MemoryACPILevel
.MclkFrequency
,
2335 &table
->MemoryACPILevel
.MinVoltage
, &mvdd
);
2336 PP_ASSERT_WITH_CODE((0 == result
),
2337 "Cannot find ACPI VDDCI voltage value "
2338 "in Clock Dependency Table",);
2340 table
->MemoryACPILevel
.MclkFrequency
=
2341 data
->vbios_boot_state
.mclk_bootup_value
;
2342 table
->MemoryACPILevel
.MinVoltage
=
2343 data
->vbios_boot_state
.vddci_bootup_value
* VOLTAGE_SCALE
;
2347 if ((FIJI_VOLTAGE_CONTROL_NONE
== data
->mvdd_control
) ||
2348 (data
->mclk_dpm_key_disabled
))
2349 us_mvdd
= data
->vbios_boot_state
.mvdd_bootup_value
;
2351 if (!fiji_populate_mvdd_value(hwmgr
,
2352 data
->dpm_table
.mclk_table
.dpm_levels
[0].value
,
2354 us_mvdd
= vol_level
.Voltage
;
2357 table
->MemoryACPILevel
.MinMvdd
=
2358 PP_HOST_TO_SMC_UL(us_mvdd
* VOLTAGE_SCALE
);
2360 table
->MemoryACPILevel
.EnabledForThrottle
= 0;
2361 table
->MemoryACPILevel
.EnabledForActivity
= 0;
2362 table
->MemoryACPILevel
.UpHyst
= 0;
2363 table
->MemoryACPILevel
.DownHyst
= 100;
2364 table
->MemoryACPILevel
.VoltageDownHyst
= 0;
2365 table
->MemoryACPILevel
.ActivityLevel
=
2366 PP_HOST_TO_SMC_US((uint16_t)data
->mclk_activity_target
);
2368 table
->MemoryACPILevel
.StutterEnable
= false;
2369 CONVERT_FROM_HOST_TO_SMC_UL(table
->MemoryACPILevel
.MclkFrequency
);
2370 CONVERT_FROM_HOST_TO_SMC_UL(table
->MemoryACPILevel
.MinVoltage
);
2375 static int fiji_populate_smc_vce_level(struct pp_hwmgr
*hwmgr
,
2376 SMU73_Discrete_DpmTable
*table
)
2378 int result
= -EINVAL
;
2380 struct pp_atomctrl_clock_dividers_vi dividers
;
2381 struct phm_ppt_v1_information
*table_info
=
2382 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2383 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
2384 table_info
->mm_dep_table
;
2385 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2387 table
->VceLevelCount
= (uint8_t)(mm_table
->count
);
2388 table
->VceBootLevel
= 0;
2390 for(count
= 0; count
< table
->VceLevelCount
; count
++) {
2391 table
->VceLevel
[count
].Frequency
= mm_table
->entries
[count
].eclk
;
2392 table
->VceLevel
[count
].MinVoltage
|=
2393 (mm_table
->entries
[count
].vddc
* VOLTAGE_SCALE
) << VDDC_SHIFT
;
2394 table
->VceLevel
[count
].MinVoltage
|=
2395 ((mm_table
->entries
[count
].vddc
- data
->vddc_vddci_delta
) *
2396 VOLTAGE_SCALE
) << VDDCI_SHIFT
;
2397 table
->VceLevel
[count
].MinVoltage
|= 1 << PHASES_SHIFT
;
2399 /*retrieve divider value for VBIOS */
2400 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
2401 table
->VceLevel
[count
].Frequency
, ÷rs
);
2402 PP_ASSERT_WITH_CODE((0 == result
),
2403 "can not find divide id for VCE engine clock",
2406 table
->VceLevel
[count
].Divider
= (uint8_t)dividers
.pll_post_divider
;
2408 CONVERT_FROM_HOST_TO_SMC_UL(table
->VceLevel
[count
].Frequency
);
2409 CONVERT_FROM_HOST_TO_SMC_UL(table
->VceLevel
[count
].MinVoltage
);
2414 static int fiji_populate_smc_acp_level(struct pp_hwmgr
*hwmgr
,
2415 SMU73_Discrete_DpmTable
*table
)
2417 int result
= -EINVAL
;
2419 struct pp_atomctrl_clock_dividers_vi dividers
;
2420 struct phm_ppt_v1_information
*table_info
=
2421 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2422 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
2423 table_info
->mm_dep_table
;
2424 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2426 table
->AcpLevelCount
= (uint8_t)(mm_table
->count
);
2427 table
->AcpBootLevel
= 0;
2429 for (count
= 0; count
< table
->AcpLevelCount
; count
++) {
2430 table
->AcpLevel
[count
].Frequency
= mm_table
->entries
[count
].aclk
;
2431 table
->AcpLevel
[count
].MinVoltage
|= (mm_table
->entries
[count
].vddc
*
2432 VOLTAGE_SCALE
) << VDDC_SHIFT
;
2433 table
->AcpLevel
[count
].MinVoltage
|= ((mm_table
->entries
[count
].vddc
-
2434 data
->vddc_vddci_delta
) * VOLTAGE_SCALE
) << VDDCI_SHIFT
;
2435 table
->AcpLevel
[count
].MinVoltage
|= 1 << PHASES_SHIFT
;
2437 /* retrieve divider value for VBIOS */
2438 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
2439 table
->AcpLevel
[count
].Frequency
, ÷rs
);
2440 PP_ASSERT_WITH_CODE((0 == result
),
2441 "can not find divide id for engine clock", return result
);
2443 table
->AcpLevel
[count
].Divider
= (uint8_t)dividers
.pll_post_divider
;
2445 CONVERT_FROM_HOST_TO_SMC_UL(table
->AcpLevel
[count
].Frequency
);
2446 CONVERT_FROM_HOST_TO_SMC_UL(table
->AcpLevel
[count
].MinVoltage
);
2451 static int fiji_populate_smc_samu_level(struct pp_hwmgr
*hwmgr
,
2452 SMU73_Discrete_DpmTable
*table
)
2454 int result
= -EINVAL
;
2456 struct pp_atomctrl_clock_dividers_vi dividers
;
2457 struct phm_ppt_v1_information
*table_info
=
2458 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2459 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
2460 table_info
->mm_dep_table
;
2461 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2463 table
->SamuBootLevel
= 0;
2464 table
->SamuLevelCount
= (uint8_t)(mm_table
->count
);
2466 for (count
= 0; count
< table
->SamuLevelCount
; count
++) {
2467 /* not sure whether we need evclk or not */
2468 table
->SamuLevel
[count
].Frequency
= mm_table
->entries
[count
].samclock
;
2469 table
->SamuLevel
[count
].MinVoltage
|= (mm_table
->entries
[count
].vddc
*
2470 VOLTAGE_SCALE
) << VDDC_SHIFT
;
2471 table
->SamuLevel
[count
].MinVoltage
|= ((mm_table
->entries
[count
].vddc
-
2472 data
->vddc_vddci_delta
) * VOLTAGE_SCALE
) << VDDCI_SHIFT
;
2473 table
->SamuLevel
[count
].MinVoltage
|= 1 << PHASES_SHIFT
;
2475 /* retrieve divider value for VBIOS */
2476 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
2477 table
->SamuLevel
[count
].Frequency
, ÷rs
);
2478 PP_ASSERT_WITH_CODE((0 == result
),
2479 "can not find divide id for samu clock", return result
);
2481 table
->SamuLevel
[count
].Divider
= (uint8_t)dividers
.pll_post_divider
;
2483 CONVERT_FROM_HOST_TO_SMC_UL(table
->SamuLevel
[count
].Frequency
);
2484 CONVERT_FROM_HOST_TO_SMC_UL(table
->SamuLevel
[count
].MinVoltage
);
2489 static int fiji_populate_memory_timing_parameters(struct pp_hwmgr
*hwmgr
,
2490 int32_t eng_clock
, int32_t mem_clock
,
2491 struct SMU73_Discrete_MCArbDramTimingTableEntry
*arb_regs
)
2493 uint32_t dram_timing
;
2494 uint32_t dram_timing2
;
2496 ULONG state
, trrds
, trrdl
;
2499 result
= atomctrl_set_engine_dram_timings_rv770(hwmgr
,
2500 eng_clock
, mem_clock
);
2501 PP_ASSERT_WITH_CODE(result
== 0,
2502 "Error calling VBIOS to set DRAM_TIMING.", return result
);
2504 dram_timing
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING
);
2505 dram_timing2
= cgs_read_register(hwmgr
->device
, mmMC_ARB_DRAM_TIMING2
);
2506 burstTime
= cgs_read_register(hwmgr
->device
, mmMC_ARB_BURST_TIME
);
2508 state
= PHM_GET_FIELD(burstTime
, MC_ARB_BURST_TIME
, STATE0
);
2509 trrds
= PHM_GET_FIELD(burstTime
, MC_ARB_BURST_TIME
, TRRDS0
);
2510 trrdl
= PHM_GET_FIELD(burstTime
, MC_ARB_BURST_TIME
, TRRDL0
);
2512 arb_regs
->McArbDramTiming
= PP_HOST_TO_SMC_UL(dram_timing
);
2513 arb_regs
->McArbDramTiming2
= PP_HOST_TO_SMC_UL(dram_timing2
);
2514 arb_regs
->McArbBurstTime
= (uint8_t)burstTime
;
2515 arb_regs
->TRRDS
= (uint8_t)trrds
;
2516 arb_regs
->TRRDL
= (uint8_t)trrdl
;
2521 static int fiji_program_memory_timing_parameters(struct pp_hwmgr
*hwmgr
)
2523 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2524 struct SMU73_Discrete_MCArbDramTimingTable arb_regs
;
2528 for (i
= 0; i
< data
->dpm_table
.sclk_table
.count
; i
++) {
2529 for (j
= 0; j
< data
->dpm_table
.mclk_table
.count
; j
++) {
2530 result
= fiji_populate_memory_timing_parameters(hwmgr
,
2531 data
->dpm_table
.sclk_table
.dpm_levels
[i
].value
,
2532 data
->dpm_table
.mclk_table
.dpm_levels
[j
].value
,
2533 &arb_regs
.entries
[i
][j
]);
2540 result
= fiji_copy_bytes_to_smc(
2542 data
->arb_table_start
,
2543 (uint8_t *)&arb_regs
,
2544 sizeof(SMU73_Discrete_MCArbDramTimingTable
),
2549 static int fiji_populate_smc_uvd_level(struct pp_hwmgr
*hwmgr
,
2550 struct SMU73_Discrete_DpmTable
*table
)
2552 int result
= -EINVAL
;
2554 struct pp_atomctrl_clock_dividers_vi dividers
;
2555 struct phm_ppt_v1_information
*table_info
=
2556 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2557 struct phm_ppt_v1_mm_clock_voltage_dependency_table
*mm_table
=
2558 table_info
->mm_dep_table
;
2559 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2561 table
->UvdLevelCount
= (uint8_t)(mm_table
->count
);
2562 table
->UvdBootLevel
= 0;
2564 for (count
= 0; count
< table
->UvdLevelCount
; count
++) {
2565 table
->UvdLevel
[count
].VclkFrequency
= mm_table
->entries
[count
].vclk
;
2566 table
->UvdLevel
[count
].DclkFrequency
= mm_table
->entries
[count
].dclk
;
2567 table
->UvdLevel
[count
].MinVoltage
|= (mm_table
->entries
[count
].vddc
*
2568 VOLTAGE_SCALE
) << VDDC_SHIFT
;
2569 table
->UvdLevel
[count
].MinVoltage
|= ((mm_table
->entries
[count
].vddc
-
2570 data
->vddc_vddci_delta
) * VOLTAGE_SCALE
) << VDDCI_SHIFT
;
2571 table
->UvdLevel
[count
].MinVoltage
|= 1 << PHASES_SHIFT
;
2573 /* retrieve divider value for VBIOS */
2574 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
2575 table
->UvdLevel
[count
].VclkFrequency
, ÷rs
);
2576 PP_ASSERT_WITH_CODE((0 == result
),
2577 "can not find divide id for Vclk clock", return result
);
2579 table
->UvdLevel
[count
].VclkDivider
= (uint8_t)dividers
.pll_post_divider
;
2581 result
= atomctrl_get_dfs_pll_dividers_vi(hwmgr
,
2582 table
->UvdLevel
[count
].DclkFrequency
, ÷rs
);
2583 PP_ASSERT_WITH_CODE((0 == result
),
2584 "can not find divide id for Dclk clock", return result
);
2586 table
->UvdLevel
[count
].DclkDivider
= (uint8_t)dividers
.pll_post_divider
;
2588 CONVERT_FROM_HOST_TO_SMC_UL(table
->UvdLevel
[count
].VclkFrequency
);
2589 CONVERT_FROM_HOST_TO_SMC_UL(table
->UvdLevel
[count
].DclkFrequency
);
2590 CONVERT_FROM_HOST_TO_SMC_UL(table
->UvdLevel
[count
].MinVoltage
);
2596 static int fiji_find_boot_level(struct fiji_single_dpm_table
*table
,
2597 uint32_t value
, uint32_t *boot_level
)
2599 int result
= -EINVAL
;
2602 for (i
= 0; i
< table
->count
; i
++) {
2603 if (value
== table
->dpm_levels
[i
].value
) {
2611 static int fiji_populate_smc_boot_level(struct pp_hwmgr
*hwmgr
,
2612 struct SMU73_Discrete_DpmTable
*table
)
2615 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2617 table
->GraphicsBootLevel
= 0;
2618 table
->MemoryBootLevel
= 0;
2620 /* find boot level from dpm table */
2621 result
= fiji_find_boot_level(&(data
->dpm_table
.sclk_table
),
2622 data
->vbios_boot_state
.sclk_bootup_value
,
2623 (uint32_t *)&(table
->GraphicsBootLevel
));
2625 result
= fiji_find_boot_level(&(data
->dpm_table
.mclk_table
),
2626 data
->vbios_boot_state
.mclk_bootup_value
,
2627 (uint32_t *)&(table
->MemoryBootLevel
));
2629 table
->BootVddc
= data
->vbios_boot_state
.vddc_bootup_value
*
2631 table
->BootVddci
= data
->vbios_boot_state
.vddci_bootup_value
*
2633 table
->BootMVdd
= data
->vbios_boot_state
.mvdd_bootup_value
*
2636 CONVERT_FROM_HOST_TO_SMC_US(table
->BootVddc
);
2637 CONVERT_FROM_HOST_TO_SMC_US(table
->BootVddci
);
2638 CONVERT_FROM_HOST_TO_SMC_US(table
->BootMVdd
);
2643 static int fiji_populate_smc_initailial_state(struct pp_hwmgr
*hwmgr
)
2645 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2646 struct phm_ppt_v1_information
*table_info
=
2647 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2648 uint8_t count
, level
;
2650 count
= (uint8_t)(table_info
->vdd_dep_on_sclk
->count
);
2651 for (level
= 0; level
< count
; level
++) {
2652 if(table_info
->vdd_dep_on_sclk
->entries
[level
].clk
>=
2653 data
->vbios_boot_state
.sclk_bootup_value
) {
2654 data
->smc_state_table
.GraphicsBootLevel
= level
;
2659 count
= (uint8_t)(table_info
->vdd_dep_on_mclk
->count
);
2660 for (level
= 0; level
< count
; level
++) {
2661 if(table_info
->vdd_dep_on_mclk
->entries
[level
].clk
>=
2662 data
->vbios_boot_state
.mclk_bootup_value
) {
2663 data
->smc_state_table
.MemoryBootLevel
= level
;
2671 static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr
*hwmgr
)
2673 uint32_t ro
, efuse
, efuse2
, clock_freq
, volt_without_cks
,
2674 volt_with_cks
, value
;
2675 uint16_t clock_freq_u16
;
2676 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2677 uint8_t type
, i
, j
, cks_setting
, stretch_amount
, stretch_amount2
,
2679 struct phm_ppt_v1_information
*table_info
=
2680 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2681 struct phm_ppt_v1_clock_voltage_dependency_table
*sclk_table
=
2682 table_info
->vdd_dep_on_sclk
;
2684 stretch_amount
= (uint8_t)table_info
->cac_dtp_table
->usClockStretchAmount
;
2686 /* Read SMU_Eefuse to read and calculate RO and determine
2687 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
2689 efuse
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2690 ixSMU_EFUSE_0
+ (146 * 4));
2691 efuse2
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2692 ixSMU_EFUSE_0
+ (148 * 4));
2693 efuse
&= 0xFF000000;
2694 efuse
= efuse
>> 24;
2698 ro
= (2300 - 1350) * efuse
/ 255 + 1350;
2700 ro
= (2500 - 1000) * efuse
/ 255 + 1000;
2707 /* Populate Stretch amount */
2708 data
->smc_state_table
.ClockStretcherAmount
= stretch_amount
;
2710 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
2711 for (i
= 0; i
< sclk_table
->count
; i
++) {
2712 data
->smc_state_table
.Sclk_CKS_masterEn0_7
|=
2713 sclk_table
->entries
[i
].cks_enable
<< i
;
2714 volt_without_cks
= (uint32_t)((14041 *
2715 (sclk_table
->entries
[i
].clk
/100) / 10000 + 3571 + 75 - ro
) * 1000 /
2716 (4026 - (13924 * (sclk_table
->entries
[i
].clk
/100) / 10000)));
2717 volt_with_cks
= (uint32_t)((13946 *
2718 (sclk_table
->entries
[i
].clk
/100) / 10000 + 3320 + 45 - ro
) * 1000 /
2719 (3664 - (11454 * (sclk_table
->entries
[i
].clk
/100) / 10000)));
2720 if (volt_without_cks
>= volt_with_cks
)
2721 volt_offset
= (uint8_t)(((volt_without_cks
- volt_with_cks
+
2722 sclk_table
->entries
[i
].cks_voffset
) * 100 / 625) + 1);
2723 data
->smc_state_table
.Sclk_voltageOffset
[i
] = volt_offset
;
2726 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, PWR_CKS_ENABLE
,
2727 STRETCH_ENABLE
, 0x0);
2728 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, PWR_CKS_ENABLE
,
2730 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, PWR_CKS_ENABLE
,
2732 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, PWR_CKS_ENABLE
,
2735 /* Populate CKS Lookup Table */
2736 if (stretch_amount
== 1 || stretch_amount
== 2 || stretch_amount
== 5)
2737 stretch_amount2
= 0;
2738 else if (stretch_amount
== 3 || stretch_amount
== 4)
2739 stretch_amount2
= 1;
2741 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
2742 PHM_PlatformCaps_ClockStretcher
);
2743 PP_ASSERT_WITH_CODE(false,
2744 "Stretch Amount in PPTable not supported\n",
2748 value
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2750 value
&= 0xFFC2FF87;
2751 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].minFreq
=
2752 fiji_clock_stretcher_lookup_table
[stretch_amount2
][0];
2753 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].maxFreq
=
2754 fiji_clock_stretcher_lookup_table
[stretch_amount2
][1];
2755 clock_freq_u16
= (uint16_t)(PP_SMC_TO_HOST_UL(data
->smc_state_table
.
2756 GraphicsLevel
[data
->smc_state_table
.GraphicsDpmLevelCount
- 1].
2757 SclkFrequency
) / 100);
2758 if (fiji_clock_stretcher_lookup_table
[stretch_amount2
][0] <
2760 fiji_clock_stretcher_lookup_table
[stretch_amount2
][1] >
2762 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2763 value
|= (fiji_clock_stretcher_lookup_table
[stretch_amount2
][3]) << 16;
2764 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2765 value
|= (fiji_clock_stretcher_lookup_table
[stretch_amount2
][2]) << 18;
2766 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2767 value
|= (fiji_clock_stretch_amount_conversion
2768 [fiji_clock_stretcher_lookup_table
[stretch_amount2
][3]]
2769 [stretch_amount
]) << 3;
2771 CONVERT_FROM_HOST_TO_SMC_US(data
->smc_state_table
.CKS_LOOKUPTable
.
2772 CKS_LOOKUPTableEntry
[0].minFreq
);
2773 CONVERT_FROM_HOST_TO_SMC_US(data
->smc_state_table
.CKS_LOOKUPTable
.
2774 CKS_LOOKUPTableEntry
[0].maxFreq
);
2775 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].setting
=
2776 fiji_clock_stretcher_lookup_table
[stretch_amount2
][2] & 0x7F;
2777 data
->smc_state_table
.CKS_LOOKUPTable
.CKS_LOOKUPTableEntry
[0].setting
|=
2778 (fiji_clock_stretcher_lookup_table
[stretch_amount2
][3]) << 7;
2780 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2781 ixPWR_CKS_CNTL
, value
);
2783 /* Populate DDT Lookup Table */
2784 for (i
= 0; i
< 4; i
++) {
2785 /* Assign the minimum and maximum VID stored
2786 * in the last row of Clock Stretcher Voltage Table.
2788 data
->smc_state_table
.ClockStretcherDataTable
.
2789 ClockStretcherDataTableEntry
[i
].minVID
=
2790 (uint8_t) fiji_clock_stretcher_ddt_table
[type
][i
][2];
2791 data
->smc_state_table
.ClockStretcherDataTable
.
2792 ClockStretcherDataTableEntry
[i
].maxVID
=
2793 (uint8_t) fiji_clock_stretcher_ddt_table
[type
][i
][3];
2794 /* Loop through each SCLK and check the frequency
2795 * to see if it lies within the frequency for clock stretcher.
2797 for (j
= 0; j
< data
->smc_state_table
.GraphicsDpmLevelCount
; j
++) {
2799 clock_freq
= PP_SMC_TO_HOST_UL(
2800 data
->smc_state_table
.GraphicsLevel
[j
].SclkFrequency
);
2801 /* Check the allowed frequency against the sclk level[j].
2802 * Sclk's endianness has already been converted,
2803 * and it's in 10Khz unit,
2804 * as opposed to Data table, which is in Mhz unit.
2807 (fiji_clock_stretcher_ddt_table
[type
][i
][0]) * 100) {
2810 (fiji_clock_stretcher_ddt_table
[type
][i
][1]) * 100)
2813 data
->smc_state_table
.ClockStretcherDataTable
.
2814 ClockStretcherDataTableEntry
[i
].setting
|= cks_setting
<< (j
* 2);
2816 CONVERT_FROM_HOST_TO_SMC_US(data
->smc_state_table
.
2817 ClockStretcherDataTable
.
2818 ClockStretcherDataTableEntry
[i
].setting
);
2821 value
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixPWR_CKS_CNTL
);
2822 value
&= 0xFFFFFFFE;
2823 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, ixPWR_CKS_CNTL
, value
);
2829 * Populates the SMC VRConfig field in DPM table.
2831 * @param hwmgr the address of the hardware manager
2832 * @param table the SMC DPM table structure to be populated
2835 static int fiji_populate_vr_config(struct pp_hwmgr
*hwmgr
,
2836 struct SMU73_Discrete_DpmTable
*table
)
2838 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2841 config
= VR_MERGED_WITH_VDDC
;
2842 table
->VRConfig
|= (config
<< VRCONF_VDDGFX_SHIFT
);
2844 /* Set Vddc Voltage Controller */
2845 if(FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->voltage_control
) {
2846 config
= VR_SVI2_PLANE_1
;
2847 table
->VRConfig
|= config
;
2849 PP_ASSERT_WITH_CODE(false,
2850 "VDDC should be on SVI2 control in merged mode!",);
2852 /* Set Vddci Voltage Controller */
2853 if(FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->vddci_control
) {
2854 config
= VR_SVI2_PLANE_2
; /* only in merged mode */
2855 table
->VRConfig
|= (config
<< VRCONF_VDDCI_SHIFT
);
2856 } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO
== data
->vddci_control
) {
2857 config
= VR_SMIO_PATTERN_1
;
2858 table
->VRConfig
|= (config
<< VRCONF_VDDCI_SHIFT
);
2860 config
= VR_STATIC_VOLTAGE
;
2861 table
->VRConfig
|= (config
<< VRCONF_VDDCI_SHIFT
);
2863 /* Set Mvdd Voltage Controller */
2864 if(FIJI_VOLTAGE_CONTROL_BY_SVID2
== data
->mvdd_control
) {
2865 config
= VR_SVI2_PLANE_2
;
2866 table
->VRConfig
|= (config
<< VRCONF_MVDD_SHIFT
);
2867 } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO
== data
->mvdd_control
) {
2868 config
= VR_SMIO_PATTERN_2
;
2869 table
->VRConfig
|= (config
<< VRCONF_MVDD_SHIFT
);
2871 config
= VR_STATIC_VOLTAGE
;
2872 table
->VRConfig
|= (config
<< VRCONF_MVDD_SHIFT
);
2879 * Initializes the SMC table and uploads it
2881 * @param hwmgr the address of the powerplay hardware manager.
2882 * @param pInput the pointer to input data (PowerState)
2885 static int fiji_init_smc_table(struct pp_hwmgr
*hwmgr
)
2888 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
2889 struct phm_ppt_v1_information
*table_info
=
2890 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
2891 struct SMU73_Discrete_DpmTable
*table
= &(data
->smc_state_table
);
2892 const struct fiji_ulv_parm
*ulv
= &(data
->ulv
);
2894 struct pp_atomctrl_gpio_pin_assignment gpio_pin
;
2896 result
= fiji_setup_default_dpm_tables(hwmgr
);
2897 PP_ASSERT_WITH_CODE(0 == result
,
2898 "Failed to setup default DPM tables!", return result
);
2900 if(FIJI_VOLTAGE_CONTROL_NONE
!= data
->voltage_control
)
2901 fiji_populate_smc_voltage_tables(hwmgr
, table
);
2903 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2904 PHM_PlatformCaps_AutomaticDCTransition
))
2905 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GPIO_DC
;
2907 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2908 PHM_PlatformCaps_StepVddc
))
2909 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_STEPVDDC
;
2911 if (data
->is_memory_gddr5
)
2912 table
->SystemFlags
|= PPSMC_SYSTEMFLAG_GDDR5
;
2914 if (ulv
->ulv_supported
&& table_info
->us_ulv_voltage_offset
) {
2915 result
= fiji_populate_ulv_state(hwmgr
, table
);
2916 PP_ASSERT_WITH_CODE(0 == result
,
2917 "Failed to initialize ULV state!", return result
);
2918 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
2919 ixCG_ULV_PARAMETER
, ulv
->cg_ulv_parameter
);
2922 result
= fiji_populate_smc_link_level(hwmgr
, table
);
2923 PP_ASSERT_WITH_CODE(0 == result
,
2924 "Failed to initialize Link Level!", return result
);
2926 result
= fiji_populate_all_graphic_levels(hwmgr
);
2927 PP_ASSERT_WITH_CODE(0 == result
,
2928 "Failed to initialize Graphics Level!", return result
);
2930 result
= fiji_populate_all_memory_levels(hwmgr
);
2931 PP_ASSERT_WITH_CODE(0 == result
,
2932 "Failed to initialize Memory Level!", return result
);
2934 result
= fiji_populate_smc_acpi_level(hwmgr
, table
);
2935 PP_ASSERT_WITH_CODE(0 == result
,
2936 "Failed to initialize ACPI Level!", return result
);
2938 result
= fiji_populate_smc_vce_level(hwmgr
, table
);
2939 PP_ASSERT_WITH_CODE(0 == result
,
2940 "Failed to initialize VCE Level!", return result
);
2942 result
= fiji_populate_smc_acp_level(hwmgr
, table
);
2943 PP_ASSERT_WITH_CODE(0 == result
,
2944 "Failed to initialize ACP Level!", return result
);
2946 result
= fiji_populate_smc_samu_level(hwmgr
, table
);
2947 PP_ASSERT_WITH_CODE(0 == result
,
2948 "Failed to initialize SAMU Level!", return result
);
2950 /* Since only the initial state is completely set up at this point
2951 * (the other states are just copies of the boot state) we only
2952 * need to populate the ARB settings for the initial state.
2954 result
= fiji_program_memory_timing_parameters(hwmgr
);
2955 PP_ASSERT_WITH_CODE(0 == result
,
2956 "Failed to Write ARB settings for the initial state.", return result
);
2958 result
= fiji_populate_smc_uvd_level(hwmgr
, table
);
2959 PP_ASSERT_WITH_CODE(0 == result
,
2960 "Failed to initialize UVD Level!", return result
);
2962 result
= fiji_populate_smc_boot_level(hwmgr
, table
);
2963 PP_ASSERT_WITH_CODE(0 == result
,
2964 "Failed to initialize Boot Level!", return result
);
2966 result
= fiji_populate_smc_initailial_state(hwmgr
);
2967 PP_ASSERT_WITH_CODE(0 == result
,
2968 "Failed to initialize Boot State!", return result
);
2970 result
= fiji_populate_bapm_parameters_in_dpm_table(hwmgr
);
2971 PP_ASSERT_WITH_CODE(0 == result
,
2972 "Failed to populate BAPM Parameters!", return result
);
2974 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
2975 PHM_PlatformCaps_ClockStretcher
)) {
2976 result
= fiji_populate_clock_stretcher_data_table(hwmgr
);
2977 PP_ASSERT_WITH_CODE(0 == result
,
2978 "Failed to populate Clock Stretcher Data Table!",
2982 table
->GraphicsVoltageChangeEnable
= 1;
2983 table
->GraphicsThermThrottleEnable
= 1;
2984 table
->GraphicsInterval
= 1;
2985 table
->VoltageInterval
= 1;
2986 table
->ThermalInterval
= 1;
2987 table
->TemperatureLimitHigh
=
2988 table_info
->cac_dtp_table
->usTargetOperatingTemp
*
2989 FIJI_Q88_FORMAT_CONVERSION_UNIT
;
2990 table
->TemperatureLimitLow
=
2991 (table_info
->cac_dtp_table
->usTargetOperatingTemp
- 1) *
2992 FIJI_Q88_FORMAT_CONVERSION_UNIT
;
2993 table
->MemoryVoltageChangeEnable
= 1;
2994 table
->MemoryInterval
= 1;
2995 table
->VoltageResponseTime
= 0;
2996 table
->PhaseResponseTime
= 0;
2997 table
->MemoryThermThrottleEnable
= 1;
2998 table
->PCIeBootLinkLevel
= 0; /* 0:Gen1 1:Gen2 2:Gen3*/
2999 table
->PCIeGenInterval
= 1;
3001 result
= fiji_populate_vr_config(hwmgr
, table
);
3002 PP_ASSERT_WITH_CODE(0 == result
,
3003 "Failed to populate VRConfig setting!", return result
);
3005 table
->ThermGpio
= 17;
3006 table
->SclkStepSize
= 0x4000;
3008 if (atomctrl_get_pp_assign_pin(hwmgr
, VDDC_VRHOT_GPIO_PINID
, &gpio_pin
)) {
3009 table
->VRHotGpio
= gpio_pin
.uc_gpio_pin_bit_shift
;
3010 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3011 PHM_PlatformCaps_RegulatorHot
);
3013 table
->VRHotGpio
= FIJI_UNUSED_GPIO_PIN
;
3014 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3015 PHM_PlatformCaps_RegulatorHot
);
3018 if (atomctrl_get_pp_assign_pin(hwmgr
, PP_AC_DC_SWITCH_GPIO_PINID
,
3020 table
->AcDcGpio
= gpio_pin
.uc_gpio_pin_bit_shift
;
3021 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3022 PHM_PlatformCaps_AutomaticDCTransition
);
3024 table
->AcDcGpio
= FIJI_UNUSED_GPIO_PIN
;
3025 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3026 PHM_PlatformCaps_AutomaticDCTransition
);
3029 /* Thermal Output GPIO */
3030 if (atomctrl_get_pp_assign_pin(hwmgr
, THERMAL_INT_OUTPUT_GPIO_PINID
,
3032 phm_cap_set(hwmgr
->platform_descriptor
.platformCaps
,
3033 PHM_PlatformCaps_ThermalOutGPIO
);
3035 table
->ThermOutGpio
= gpio_pin
.uc_gpio_pin_bit_shift
;
3037 /* For porlarity read GPIOPAD_A with assigned Gpio pin
3038 * since VBIOS will program this register to set 'inactive state',
3039 * driver can then determine 'active state' from this and
3040 * program SMU with correct polarity
3042 table
->ThermOutPolarity
= (0 == (cgs_read_register(hwmgr
->device
, mmGPIOPAD_A
) &
3043 (1 << gpio_pin
.uc_gpio_pin_bit_shift
))) ? 1:0;
3044 table
->ThermOutMode
= SMU7_THERM_OUT_MODE_THERM_ONLY
;
3046 /* if required, combine VRHot/PCC with thermal out GPIO */
3047 if(phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3048 PHM_PlatformCaps_RegulatorHot
) &&
3049 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3050 PHM_PlatformCaps_CombinePCCWithThermalSignal
))
3051 table
->ThermOutMode
= SMU7_THERM_OUT_MODE_THERM_VRHOT
;
3053 phm_cap_unset(hwmgr
->platform_descriptor
.platformCaps
,
3054 PHM_PlatformCaps_ThermalOutGPIO
);
3055 table
->ThermOutGpio
= 17;
3056 table
->ThermOutPolarity
= 1;
3057 table
->ThermOutMode
= SMU7_THERM_OUT_MODE_DISABLE
;
3060 for (i
= 0; i
< SMU73_MAX_ENTRIES_SMIO
; i
++)
3061 table
->Smio
[i
] = PP_HOST_TO_SMC_UL(table
->Smio
[i
]);
3063 CONVERT_FROM_HOST_TO_SMC_UL(table
->SystemFlags
);
3064 CONVERT_FROM_HOST_TO_SMC_UL(table
->VRConfig
);
3065 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMask1
);
3066 CONVERT_FROM_HOST_TO_SMC_UL(table
->SmioMask2
);
3067 CONVERT_FROM_HOST_TO_SMC_UL(table
->SclkStepSize
);
3068 CONVERT_FROM_HOST_TO_SMC_US(table
->TemperatureLimitHigh
);
3069 CONVERT_FROM_HOST_TO_SMC_US(table
->TemperatureLimitLow
);
3070 CONVERT_FROM_HOST_TO_SMC_US(table
->VoltageResponseTime
);
3071 CONVERT_FROM_HOST_TO_SMC_US(table
->PhaseResponseTime
);
3073 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3074 result
= fiji_copy_bytes_to_smc(hwmgr
->smumgr
,
3075 data
->dpm_table_start
+
3076 offsetof(SMU73_Discrete_DpmTable
, SystemFlags
),
3077 (uint8_t *)&(table
->SystemFlags
),
3078 sizeof(SMU73_Discrete_DpmTable
) - 3 * sizeof(SMU73_PIDController
),
3080 PP_ASSERT_WITH_CODE(0 == result
,
3081 "Failed to upload dpm data to SMC memory!", return result
);
3087 * Initialize the ARB DRAM timing table's index field.
3089 * @param hwmgr the address of the powerplay hardware manager.
3092 static int fiji_init_arb_table_index(struct pp_hwmgr
*hwmgr
)
3094 const struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3098 /* This is a read-modify-write on the first byte of the ARB table.
3099 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
3100 * is the field 'current'.
3101 * This solution is ugly, but we never write the whole table only
3102 * individual fields in it.
3103 * In reality this field should not be in that structure
3104 * but in a soft register.
3106 result
= fiji_read_smc_sram_dword(hwmgr
->smumgr
,
3107 data
->arb_table_start
, &tmp
, data
->sram_end
);
3113 tmp
|= ((uint32_t)MC_CG_ARB_FREQ_F1
) << 24;
3115 return fiji_write_smc_sram_dword(hwmgr
->smumgr
,
3116 data
->arb_table_start
, tmp
, data
->sram_end
);
3119 static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr
*hwmgr
)
3121 if(phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3122 PHM_PlatformCaps_RegulatorHot
))
3123 return smum_send_msg_to_smc(hwmgr
->smumgr
,
3124 PPSMC_MSG_EnableVRHotGPIOInterrupt
);
3129 static int fiji_enable_sclk_control(struct pp_hwmgr
*hwmgr
)
3131 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SCLK_PWRMGT_CNTL
,
3132 SCLK_PWRMGT_OFF
, 0);
3136 static int fiji_enable_ulv(struct pp_hwmgr
*hwmgr
)
3138 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3139 struct fiji_ulv_parm
*ulv
= &(data
->ulv
);
3141 if (ulv
->ulv_supported
)
3142 return smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_EnableULV
);
3147 static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr
*hwmgr
)
3149 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3150 PHM_PlatformCaps_SclkDeepSleep
)) {
3151 if (smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_MASTER_DeepSleep_ON
))
3152 PP_ASSERT_WITH_CODE(false,
3153 "Attempt to enable Master Deep Sleep switch failed!",
3156 if (smum_send_msg_to_smc(hwmgr
->smumgr
,
3157 PPSMC_MSG_MASTER_DeepSleep_OFF
)) {
3158 PP_ASSERT_WITH_CODE(false,
3159 "Attempt to disable Master Deep Sleep switch failed!",
3167 static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
3169 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3170 uint32_t val
, val0
, val2
;
3171 uint32_t i
, cpl_cntl
, cpl_threshold
, mc_threshold
;
3173 /* enable SCLK dpm */
3174 if(!data
->sclk_dpm_key_disabled
)
3175 PP_ASSERT_WITH_CODE(
3176 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_DPM_Enable
)),
3177 "Failed to enable SCLK DPM during DPM Start Function!",
3180 /* enable MCLK dpm */
3181 if(0 == data
->mclk_dpm_key_disabled
) {
3185 /* Read per MCD tile (0 - 7) */
3186 for (i
= 0; i
< 8; i
++) {
3187 PHM_WRITE_FIELD(hwmgr
->device
, MC_CONFIG_MCD
, MC_RD_ENABLE
, i
);
3188 val
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_RESERVE_0_S
) & 0xf0000000;
3189 if (0xf0000000 != val
) {
3190 /* count number of MCQ that has channel(s) enabled */
3192 /* only harvest 3 or full 4 supported */
3193 mc_threshold
= val
? 3 : 4;
3196 PP_ASSERT_WITH_CODE(0 != cpl_threshold
,
3197 "Number of MCQ is zero!", return -EINVAL
;);
3199 mc_threshold
= ((mc_threshold
& LCAC_MC0_CNTL__MC0_THRESHOLD_MASK
) <<
3200 LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT
) |
3201 LCAC_MC0_CNTL__MC0_ENABLE_MASK
;
3202 cpl_cntl
= ((cpl_threshold
& LCAC_CPL_CNTL__CPL_THRESHOLD_MASK
) <<
3203 LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT
) |
3204 LCAC_CPL_CNTL__CPL_ENABLE_MASK
;
3205 cpl_cntl
= (cpl_cntl
| (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT
));
3206 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3207 ixLCAC_MC0_CNTL
, mc_threshold
);
3208 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3209 ixLCAC_MC1_CNTL
, mc_threshold
);
3210 if (8 == cpl_threshold
) {
3211 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3212 ixLCAC_MC2_CNTL
, mc_threshold
);
3213 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3214 ixLCAC_MC3_CNTL
, mc_threshold
);
3215 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3216 ixLCAC_MC4_CNTL
, mc_threshold
);
3217 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3218 ixLCAC_MC5_CNTL
, mc_threshold
);
3219 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3220 ixLCAC_MC6_CNTL
, mc_threshold
);
3221 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3222 ixLCAC_MC7_CNTL
, mc_threshold
);
3224 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3225 ixLCAC_CPL_CNTL
, cpl_cntl
);
3229 mc_threshold
= mc_threshold
|
3230 (1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT
);
3231 cpl_cntl
= cpl_cntl
| (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT
);
3232 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3233 ixLCAC_MC0_CNTL
, mc_threshold
);
3234 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3235 ixLCAC_MC1_CNTL
, mc_threshold
);
3236 if (8 == cpl_threshold
) {
3237 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3238 ixLCAC_MC2_CNTL
, mc_threshold
);
3239 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3240 ixLCAC_MC3_CNTL
, mc_threshold
);
3241 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3242 ixLCAC_MC4_CNTL
, mc_threshold
);
3243 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3244 ixLCAC_MC5_CNTL
, mc_threshold
);
3245 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3246 ixLCAC_MC6_CNTL
, mc_threshold
);
3247 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3248 ixLCAC_MC7_CNTL
, mc_threshold
);
3250 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3251 ixLCAC_CPL_CNTL
, cpl_cntl
);
3253 /* Program CAC_EN per MCD (0-7) Tile */
3254 val0
= val
= cgs_read_register(hwmgr
->device
, mmMC_CONFIG_MCD
);
3255 val
&= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK
|
3256 MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK
|
3257 MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK
|
3258 MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK
|
3259 MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK
|
3260 MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK
|
3261 MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK
|
3262 MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK
|
3263 MC_CONFIG_MCD__MC_RD_ENABLE_MASK
);
3265 for (i
= 0; i
< 8; i
++) {
3266 /* Enable MCD i Tile read & write */
3267 val2
= (val
| (i
<< MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT
) |
3269 cgs_write_register(hwmgr
->device
, mmMC_CONFIG_MCD
, val2
);
3270 /* Enbale CAC_ON MCD i Tile */
3271 val2
= cgs_read_register(hwmgr
->device
, mmMC_SEQ_CNTL
);
3272 val2
|= MC_SEQ_CNTL__CAC_EN_MASK
;
3273 cgs_write_register(hwmgr
->device
, mmMC_SEQ_CNTL
, val2
);
3275 /* Set MC_CONFIG_MCD back to its default setting val0 */
3276 cgs_write_register(hwmgr
->device
, mmMC_CONFIG_MCD
, val0
);
3278 PP_ASSERT_WITH_CODE(
3279 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3280 PPSMC_MSG_MCLKDPM_Enable
)),
3281 "Failed to enable MCLK DPM during DPM Start Function!",
3287 static int fiji_start_dpm(struct pp_hwmgr
*hwmgr
)
3289 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3291 /*enable general power management */
3292 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
3293 GLOBAL_PWRMGT_EN
, 1);
3294 /* enable sclk deep sleep */
3295 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, SCLK_PWRMGT_CNTL
,
3297 /* prepare for PCIE DPM */
3298 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
3299 data
->soft_regs_start
+ offsetof(SMU73_SoftRegisters
,
3300 VoltageChangeTimeout
), 0x1000);
3301 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__PCIE
,
3302 SWRST_COMMAND_1
, RESETLC
, 0x0);
3304 PP_ASSERT_WITH_CODE(
3305 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3306 PPSMC_MSG_Voltage_Cntl_Enable
)),
3307 "Failed to enable voltage DPM during DPM Start Function!",
3310 if (fiji_enable_sclk_mclk_dpm(hwmgr
)) {
3311 printk(KERN_ERR
"Failed to enable Sclk DPM and Mclk DPM!");
3315 /* enable PCIE dpm */
3316 if(!data
->pcie_dpm_key_disabled
) {
3317 PP_ASSERT_WITH_CODE(
3318 (0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
3319 PPSMC_MSG_PCIeDPM_Enable
)),
3320 "Failed to enable pcie DPM during DPM Start Function!",
3327 static void fiji_set_dpm_event_sources(struct pp_hwmgr
*hwmgr
,
3331 enum DPM_EVENT_SRC src
;
3335 printk(KERN_ERR
"Unknown throttling event sources.");
3341 case (1 << PHM_AutoThrottleSource_Thermal
):
3343 src
= DPM_EVENT_SRC_DIGITAL
;
3345 case (1 << PHM_AutoThrottleSource_External
):
3347 src
= DPM_EVENT_SRC_EXTERNAL
;
3349 case (1 << PHM_AutoThrottleSource_External
) |
3350 (1 << PHM_AutoThrottleSource_Thermal
):
3352 src
= DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL
;
3355 /* Order matters - don't enable thermal protection for the wrong source. */
3357 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, CG_THERMAL_CTRL
,
3358 DPM_EVENT_SRC
, src
);
3359 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
3360 THERMAL_PROTECTION_DIS
,
3361 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3362 PHM_PlatformCaps_ThermalController
));
3364 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
, GENERAL_PWRMGT
,
3365 THERMAL_PROTECTION_DIS
, 1);
3368 static int fiji_enable_auto_throttle_source(struct pp_hwmgr
*hwmgr
,
3369 PHM_AutoThrottleSource source
)
3371 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3373 if (!(data
->active_auto_throttle_sources
& (1 << source
))) {
3374 data
->active_auto_throttle_sources
|= 1 << source
;
3375 fiji_set_dpm_event_sources(hwmgr
, data
->active_auto_throttle_sources
);
3380 static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr
*hwmgr
)
3382 return fiji_enable_auto_throttle_source(hwmgr
, PHM_AutoThrottleSource_Thermal
);
3385 static int fiji_enable_dpm_tasks(struct pp_hwmgr
*hwmgr
)
3387 int tmp_result
, result
= 0;
3389 tmp_result
= (!fiji_is_dpm_running(hwmgr
))? 0 : -1;
3390 PP_ASSERT_WITH_CODE(result
== 0,
3391 "DPM is already running right now, no need to enable DPM!",
3394 if (fiji_voltage_control(hwmgr
)) {
3395 tmp_result
= fiji_enable_voltage_control(hwmgr
);
3396 PP_ASSERT_WITH_CODE(tmp_result
== 0,
3397 "Failed to enable voltage control!",
3398 result
= tmp_result
);
3401 if (fiji_voltage_control(hwmgr
)) {
3402 tmp_result
= fiji_construct_voltage_tables(hwmgr
);
3403 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3404 "Failed to contruct voltage tables!",
3405 result
= tmp_result
);
3408 tmp_result
= fiji_initialize_mc_reg_table(hwmgr
);
3409 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3410 "Failed to initialize MC reg table!", result
= tmp_result
);
3412 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3413 PHM_PlatformCaps_EngineSpreadSpectrumSupport
))
3414 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
3415 GENERAL_PWRMGT
, DYN_SPREAD_SPECTRUM_EN
, 1);
3417 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3418 PHM_PlatformCaps_ThermalController
))
3419 PHM_WRITE_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
3420 GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, 0);
3422 tmp_result
= fiji_program_static_screen_threshold_parameters(hwmgr
);
3423 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3424 "Failed to program static screen threshold parameters!",
3425 result
= tmp_result
);
3427 tmp_result
= fiji_enable_display_gap(hwmgr
);
3428 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3429 "Failed to enable display gap!", result
= tmp_result
);
3431 tmp_result
= fiji_program_voting_clients(hwmgr
);
3432 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3433 "Failed to program voting clients!", result
= tmp_result
);
3435 tmp_result
= fiji_process_firmware_header(hwmgr
);
3436 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3437 "Failed to process firmware header!", result
= tmp_result
);
3439 tmp_result
= fiji_initial_switch_from_arbf0_to_f1(hwmgr
);
3440 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3441 "Failed to initialize switch from ArbF0 to F1!",
3442 result
= tmp_result
);
3444 tmp_result
= fiji_init_smc_table(hwmgr
);
3445 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3446 "Failed to initialize SMC table!", result
= tmp_result
);
3448 tmp_result
= fiji_init_arb_table_index(hwmgr
);
3449 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3450 "Failed to initialize ARB table index!", result
= tmp_result
);
3452 tmp_result
= fiji_populate_pm_fuses(hwmgr
);
3453 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3454 "Failed to populate PM fuses!", result
= tmp_result
);
3456 tmp_result
= fiji_enable_vrhot_gpio_interrupt(hwmgr
);
3457 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3458 "Failed to enable VR hot GPIO interrupt!", result
= tmp_result
);
3460 tmp_result
= tonga_notify_smc_display_change(hwmgr
, false);
3461 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3462 "Failed to notify no display!", result
= tmp_result
);
3464 tmp_result
= fiji_enable_sclk_control(hwmgr
);
3465 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3466 "Failed to enable SCLK control!", result
= tmp_result
);
3468 tmp_result
= fiji_enable_ulv(hwmgr
);
3469 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3470 "Failed to enable ULV!", result
= tmp_result
);
3472 tmp_result
= fiji_enable_deep_sleep_master_switch(hwmgr
);
3473 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3474 "Failed to enable deep sleep master switch!", result
= tmp_result
);
3476 tmp_result
= fiji_start_dpm(hwmgr
);
3477 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3478 "Failed to start DPM!", result
= tmp_result
);
3480 tmp_result
= fiji_enable_smc_cac(hwmgr
);
3481 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3482 "Failed to enable SMC CAC!", result
= tmp_result
);
3484 tmp_result
= fiji_enable_power_containment(hwmgr
);
3485 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3486 "Failed to enable power containment!", result
= tmp_result
);
3488 tmp_result
= fiji_power_control_set_level(hwmgr
);
3489 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3490 "Failed to power control set level!", result
= tmp_result
);
3492 tmp_result
= fiji_enable_thermal_auto_throttle(hwmgr
);
3493 PP_ASSERT_WITH_CODE((0 == tmp_result
),
3494 "Failed to enable thermal auto throttle!", result
= tmp_result
);
3499 static int fiji_force_dpm_highest(struct pp_hwmgr
*hwmgr
)
3501 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3502 uint32_t level
, tmp
;
3504 if (!data
->sclk_dpm_key_disabled
) {
3505 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
3507 tmp
= data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
;
3511 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3512 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
3517 if (!data
->mclk_dpm_key_disabled
) {
3518 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
3520 tmp
= data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
;
3524 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3525 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
3530 if (!data
->pcie_dpm_key_disabled
) {
3531 if (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
) {
3533 tmp
= data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
;
3537 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3538 PPSMC_MSG_PCIeDPM_ForceLevel
,
3545 static void fiji_apply_dal_min_voltage_request(struct pp_hwmgr
*hwmgr
)
3547 struct phm_ppt_v1_information
*table_info
=
3548 (struct phm_ppt_v1_information
*)hwmgr
->pptable
;
3549 struct phm_clock_voltage_dependency_table
*table
=
3550 table_info
->vddc_dep_on_dal_pwrl
;
3551 struct phm_ppt_v1_clock_voltage_dependency_table
*vddc_table
;
3552 enum PP_DAL_POWERLEVEL dal_power_level
= hwmgr
->dal_power_level
;
3553 uint32_t req_vddc
= 0, req_volt
, i
;
3555 if (!table
&& !(dal_power_level
>= PP_DAL_POWERLEVEL_ULTRALOW
&&
3556 dal_power_level
<= PP_DAL_POWERLEVEL_PERFORMANCE
))
3559 for (i
= 0; i
< table
->count
; i
++) {
3560 if (dal_power_level
== table
->entries
[i
].clk
) {
3561 req_vddc
= table
->entries
[i
].v
;
3566 vddc_table
= table_info
->vdd_dep_on_sclk
;
3567 for (i
= 0; i
< vddc_table
->count
; i
++) {
3568 if (req_vddc
<= vddc_table
->entries
[i
].vddc
) {
3569 req_volt
= (((uint32_t)vddc_table
->entries
[i
].vddc
) * VOLTAGE_SCALE
)
3571 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3572 PPSMC_MSG_VddC_Request
, req_volt
);
3576 printk(KERN_ERR
"DAL requested level can not"
3577 " found a available voltage in VDDC DPM Table \n");
3580 static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr
*hwmgr
)
3582 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3584 fiji_apply_dal_min_voltage_request(hwmgr
);
3586 if (!data
->sclk_dpm_key_disabled
) {
3587 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
)
3588 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3589 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
3590 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
3595 static int fiji_unforce_dpm_levels(struct pp_hwmgr
*hwmgr
)
3597 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3599 if (!fiji_is_dpm_running(hwmgr
))
3602 if (!data
->pcie_dpm_key_disabled
) {
3603 smum_send_msg_to_smc(hwmgr
->smumgr
,
3604 PPSMC_MSG_PCIeDPM_UnForceLevel
);
3607 return fiji_upload_dpmlevel_enable_mask(hwmgr
);
3610 static uint32_t fiji_get_lowest_enabled_level(
3611 struct pp_hwmgr
*hwmgr
, uint32_t mask
)
3615 while(0 == (mask
& (1 << level
)))
3621 static int fiji_force_dpm_lowest(struct pp_hwmgr
*hwmgr
)
3623 struct fiji_hwmgr
*data
=
3624 (struct fiji_hwmgr
*)(hwmgr
->backend
);
3627 if (!data
->sclk_dpm_key_disabled
)
3628 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
3629 level
= fiji_get_lowest_enabled_level(hwmgr
,
3630 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
3631 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3632 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
3637 if (!data
->mclk_dpm_key_disabled
) {
3638 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
3639 level
= fiji_get_lowest_enabled_level(hwmgr
,
3640 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
3641 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3642 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
3647 if (!data
->pcie_dpm_key_disabled
) {
3648 if (data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
) {
3649 level
= fiji_get_lowest_enabled_level(hwmgr
,
3650 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
);
3651 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
3652 PPSMC_MSG_PCIeDPM_ForceLevel
,
3660 static int fiji_dpm_force_dpm_level(struct pp_hwmgr
*hwmgr
,
3661 enum amd_dpm_forced_level level
)
3666 case AMD_DPM_FORCED_LEVEL_HIGH
:
3667 ret
= fiji_force_dpm_highest(hwmgr
);
3671 case AMD_DPM_FORCED_LEVEL_LOW
:
3672 ret
= fiji_force_dpm_lowest(hwmgr
);
3676 case AMD_DPM_FORCED_LEVEL_AUTO
:
3677 ret
= fiji_unforce_dpm_levels(hwmgr
);
3685 hwmgr
->dpm_level
= level
;
3690 static int fiji_get_power_state_size(struct pp_hwmgr
*hwmgr
)
3692 return sizeof(struct fiji_power_state
);
3695 static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr
*hwmgr
,
3696 void *state
, struct pp_power_state
*power_state
,
3697 void *pp_table
, uint32_t classification_flag
)
3699 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3700 struct fiji_power_state
*fiji_power_state
=
3701 (struct fiji_power_state
*)(&(power_state
->hardware
));
3702 struct fiji_performance_level
*performance_level
;
3703 ATOM_Tonga_State
*state_entry
= (ATOM_Tonga_State
*)state
;
3704 ATOM_Tonga_POWERPLAYTABLE
*powerplay_table
=
3705 (ATOM_Tonga_POWERPLAYTABLE
*)pp_table
;
3706 ATOM_Tonga_SCLK_Dependency_Table
*sclk_dep_table
=
3707 (ATOM_Tonga_SCLK_Dependency_Table
*)
3708 (((unsigned long)powerplay_table
) +
3709 le16_to_cpu(powerplay_table
->usSclkDependencyTableOffset
));
3710 ATOM_Tonga_MCLK_Dependency_Table
*mclk_dep_table
=
3711 (ATOM_Tonga_MCLK_Dependency_Table
*)
3712 (((unsigned long)powerplay_table
) +
3713 le16_to_cpu(powerplay_table
->usMclkDependencyTableOffset
));
3715 /* The following fields are not initialized here: id orderedList allStatesList */
3716 power_state
->classification
.ui_label
=
3717 (le16_to_cpu(state_entry
->usClassification
) &
3718 ATOM_PPLIB_CLASSIFICATION_UI_MASK
) >>
3719 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT
;
3720 power_state
->classification
.flags
= classification_flag
;
3721 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3723 power_state
->classification
.temporary_state
= false;
3724 power_state
->classification
.to_be_deleted
= false;
3726 power_state
->validation
.disallowOnDC
=
3727 (0 != (le32_to_cpu(state_entry
->ulCapsAndSettings
) &
3728 ATOM_Tonga_DISALLOW_ON_DC
));
3730 power_state
->pcie
.lanes
= 0;
3732 power_state
->display
.disableFrameModulation
= false;
3733 power_state
->display
.limitRefreshrate
= false;
3734 power_state
->display
.enableVariBright
=
3735 (0 != (le32_to_cpu(state_entry
->ulCapsAndSettings
) &
3736 ATOM_Tonga_ENABLE_VARIBRIGHT
));
3738 power_state
->validation
.supportedPowerLevels
= 0;
3739 power_state
->uvd_clocks
.VCLK
= 0;
3740 power_state
->uvd_clocks
.DCLK
= 0;
3741 power_state
->temperatures
.min
= 0;
3742 power_state
->temperatures
.max
= 0;
3744 performance_level
= &(fiji_power_state
->performance_levels
3745 [fiji_power_state
->performance_level_count
++]);
3747 PP_ASSERT_WITH_CODE(
3748 (fiji_power_state
->performance_level_count
< SMU73_MAX_LEVELS_GRAPHICS
),
3749 "Performance levels exceeds SMC limit!",
3752 PP_ASSERT_WITH_CODE(
3753 (fiji_power_state
->performance_level_count
<=
3754 hwmgr
->platform_descriptor
.hardwareActivityPerformanceLevels
),
3755 "Performance levels exceeds Driver limit!",
3758 /* Performance levels are arranged from low to high. */
3759 performance_level
->memory_clock
= mclk_dep_table
->entries
3760 [state_entry
->ucMemoryClockIndexLow
].ulMclk
;
3761 performance_level
->engine_clock
= sclk_dep_table
->entries
3762 [state_entry
->ucEngineClockIndexLow
].ulSclk
;
3763 performance_level
->pcie_gen
= get_pcie_gen_support(data
->pcie_gen_cap
,
3764 state_entry
->ucPCIEGenLow
);
3765 performance_level
->pcie_lane
= get_pcie_lane_support(data
->pcie_lane_cap
,
3766 state_entry
->ucPCIELaneHigh
);
3768 performance_level
= &(fiji_power_state
->performance_levels
3769 [fiji_power_state
->performance_level_count
++]);
3770 performance_level
->memory_clock
= mclk_dep_table
->entries
3771 [state_entry
->ucMemoryClockIndexHigh
].ulMclk
;
3772 performance_level
->engine_clock
= sclk_dep_table
->entries
3773 [state_entry
->ucEngineClockIndexHigh
].ulSclk
;
3774 performance_level
->pcie_gen
= get_pcie_gen_support(data
->pcie_gen_cap
,
3775 state_entry
->ucPCIEGenHigh
);
3776 performance_level
->pcie_lane
= get_pcie_lane_support(data
->pcie_lane_cap
,
3777 state_entry
->ucPCIELaneHigh
);
3782 static int fiji_get_pp_table_entry(struct pp_hwmgr
*hwmgr
,
3783 unsigned long entry_index
, struct pp_power_state
*state
)
3786 struct fiji_power_state
*ps
;
3787 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3788 struct phm_ppt_v1_information
*table_info
=
3789 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
3790 struct phm_ppt_v1_clock_voltage_dependency_table
*dep_mclk_table
=
3791 table_info
->vdd_dep_on_mclk
;
3793 state
->hardware
.magic
= PHM_VIslands_Magic
;
3795 ps
= (struct fiji_power_state
*)(&state
->hardware
);
3797 result
= tonga_get_powerplay_table_entry(hwmgr
, entry_index
, state
,
3798 fiji_get_pp_table_entry_callback_func
);
3800 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3801 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3802 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3804 if (dep_mclk_table
!= NULL
&& dep_mclk_table
->count
== 1) {
3805 if (dep_mclk_table
->entries
[0].clk
!=
3806 data
->vbios_boot_state
.mclk_bootup_value
)
3807 printk(KERN_ERR
"Single MCLK entry VDDCI/MCLK dependency table "
3808 "does not match VBIOS boot MCLK level");
3809 if (dep_mclk_table
->entries
[0].vddci
!=
3810 data
->vbios_boot_state
.vddci_bootup_value
)
3811 printk(KERN_ERR
"Single VDDCI entry VDDCI/MCLK dependency table "
3812 "does not match VBIOS boot VDDCI level");
3815 /* set DC compatible flag if this state supports DC */
3816 if (!state
->validation
.disallowOnDC
)
3817 ps
->dc_compatible
= true;
3819 if (state
->classification
.flags
& PP_StateClassificationFlag_ACPI
)
3820 data
->acpi_pcie_gen
= ps
->performance_levels
[0].pcie_gen
;
3822 ps
->uvd_clks
.vclk
= state
->uvd_clocks
.VCLK
;
3823 ps
->uvd_clks
.dclk
= state
->uvd_clocks
.DCLK
;
3828 switch (state
->classification
.ui_label
) {
3829 case PP_StateUILabel_Performance
:
3830 data
->use_pcie_performance_levels
= true;
3832 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3833 if (data
->pcie_gen_performance
.max
<
3834 ps
->performance_levels
[i
].pcie_gen
)
3835 data
->pcie_gen_performance
.max
=
3836 ps
->performance_levels
[i
].pcie_gen
;
3838 if (data
->pcie_gen_performance
.min
>
3839 ps
->performance_levels
[i
].pcie_gen
)
3840 data
->pcie_gen_performance
.min
=
3841 ps
->performance_levels
[i
].pcie_gen
;
3843 if (data
->pcie_lane_performance
.max
<
3844 ps
->performance_levels
[i
].pcie_lane
)
3845 data
->pcie_lane_performance
.max
=
3846 ps
->performance_levels
[i
].pcie_lane
;
3848 if (data
->pcie_lane_performance
.min
>
3849 ps
->performance_levels
[i
].pcie_lane
)
3850 data
->pcie_lane_performance
.min
=
3851 ps
->performance_levels
[i
].pcie_lane
;
3854 case PP_StateUILabel_Battery
:
3855 data
->use_pcie_power_saving_levels
= true;
3857 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3858 if (data
->pcie_gen_power_saving
.max
<
3859 ps
->performance_levels
[i
].pcie_gen
)
3860 data
->pcie_gen_power_saving
.max
=
3861 ps
->performance_levels
[i
].pcie_gen
;
3863 if (data
->pcie_gen_power_saving
.min
>
3864 ps
->performance_levels
[i
].pcie_gen
)
3865 data
->pcie_gen_power_saving
.min
=
3866 ps
->performance_levels
[i
].pcie_gen
;
3868 if (data
->pcie_lane_power_saving
.max
<
3869 ps
->performance_levels
[i
].pcie_lane
)
3870 data
->pcie_lane_power_saving
.max
=
3871 ps
->performance_levels
[i
].pcie_lane
;
3873 if (data
->pcie_lane_power_saving
.min
>
3874 ps
->performance_levels
[i
].pcie_lane
)
3875 data
->pcie_lane_power_saving
.min
=
3876 ps
->performance_levels
[i
].pcie_lane
;
3886 static int fiji_apply_state_adjust_rules(struct pp_hwmgr
*hwmgr
,
3887 struct pp_power_state
*request_ps
,
3888 const struct pp_power_state
*current_ps
)
3890 struct fiji_power_state
*fiji_ps
=
3891 cast_phw_fiji_power_state(&request_ps
->hardware
);
3894 struct PP_Clocks minimum_clocks
= {0};
3895 bool disable_mclk_switching
;
3896 bool disable_mclk_switching_for_frame_lock
;
3897 struct cgs_display_info info
= {0};
3898 const struct phm_clock_and_voltage_limits
*max_limits
;
3900 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
3901 struct phm_ppt_v1_information
*table_info
=
3902 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
3904 int32_t stable_pstate_sclk
= 0, stable_pstate_mclk
= 0;
3906 data
->battery_state
= (PP_StateUILabel_Battery
==
3907 request_ps
->classification
.ui_label
);
3909 PP_ASSERT_WITH_CODE(fiji_ps
->performance_level_count
== 2,
3910 "VI should always have 2 performance levels",);
3912 max_limits
= (PP_PowerSource_AC
== hwmgr
->power_source
) ?
3913 &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
) :
3914 &(hwmgr
->dyn_state
.max_clock_voltage_on_dc
);
3916 /* Cap clock DPM tables at DC MAX if it is in DC. */
3917 if (PP_PowerSource_DC
== hwmgr
->power_source
) {
3918 for (i
= 0; i
< fiji_ps
->performance_level_count
; i
++) {
3919 if (fiji_ps
->performance_levels
[i
].memory_clock
> max_limits
->mclk
)
3920 fiji_ps
->performance_levels
[i
].memory_clock
= max_limits
->mclk
;
3921 if (fiji_ps
->performance_levels
[i
].engine_clock
> max_limits
->sclk
)
3922 fiji_ps
->performance_levels
[i
].engine_clock
= max_limits
->sclk
;
3926 fiji_ps
->vce_clks
.evclk
= hwmgr
->vce_arbiter
.evclk
;
3927 fiji_ps
->vce_clks
.ecclk
= hwmgr
->vce_arbiter
.ecclk
;
3929 fiji_ps
->acp_clk
= hwmgr
->acp_arbiter
.acpclk
;
3931 cgs_get_active_displays_info(hwmgr
->device
, &info
);
3933 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3935 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3937 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
3938 PHM_PlatformCaps_StablePState
)) {
3939 max_limits
= &(hwmgr
->dyn_state
.max_clock_voltage_on_ac
);
3940 stable_pstate_sclk
= (max_limits
->sclk
* 75) / 100;
3942 for (count
= table_info
->vdd_dep_on_sclk
->count
- 1;
3943 count
>= 0; count
--) {
3944 if (stable_pstate_sclk
>=
3945 table_info
->vdd_dep_on_sclk
->entries
[count
].clk
) {
3946 stable_pstate_sclk
=
3947 table_info
->vdd_dep_on_sclk
->entries
[count
].clk
;
3953 stable_pstate_sclk
= table_info
->vdd_dep_on_sclk
->entries
[0].clk
;
3955 stable_pstate_mclk
= max_limits
->mclk
;
3957 minimum_clocks
.engineClock
= stable_pstate_sclk
;
3958 minimum_clocks
.memoryClock
= stable_pstate_mclk
;
3961 if (minimum_clocks
.engineClock
< hwmgr
->gfx_arbiter
.sclk
)
3962 minimum_clocks
.engineClock
= hwmgr
->gfx_arbiter
.sclk
;
3964 if (minimum_clocks
.memoryClock
< hwmgr
->gfx_arbiter
.mclk
)
3965 minimum_clocks
.memoryClock
= hwmgr
->gfx_arbiter
.mclk
;
3967 fiji_ps
->sclk_threshold
= hwmgr
->gfx_arbiter
.sclk_threshold
;
3969 if (0 != hwmgr
->gfx_arbiter
.sclk_over_drive
) {
3970 PP_ASSERT_WITH_CODE((hwmgr
->gfx_arbiter
.sclk_over_drive
<=
3971 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
),
3972 "Overdrive sclk exceeds limit",
3973 hwmgr
->gfx_arbiter
.sclk_over_drive
=
3974 hwmgr
->platform_descriptor
.overdriveLimit
.engineClock
);
3976 if (hwmgr
->gfx_arbiter
.sclk_over_drive
>= hwmgr
->gfx_arbiter
.sclk
)
3977 fiji_ps
->performance_levels
[1].engine_clock
=
3978 hwmgr
->gfx_arbiter
.sclk_over_drive
;
3981 if (0 != hwmgr
->gfx_arbiter
.mclk_over_drive
) {
3982 PP_ASSERT_WITH_CODE((hwmgr
->gfx_arbiter
.mclk_over_drive
<=
3983 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
),
3984 "Overdrive mclk exceeds limit",
3985 hwmgr
->gfx_arbiter
.mclk_over_drive
=
3986 hwmgr
->platform_descriptor
.overdriveLimit
.memoryClock
);
3988 if (hwmgr
->gfx_arbiter
.mclk_over_drive
>= hwmgr
->gfx_arbiter
.mclk
)
3989 fiji_ps
->performance_levels
[1].memory_clock
=
3990 hwmgr
->gfx_arbiter
.mclk_over_drive
;
3993 disable_mclk_switching_for_frame_lock
= phm_cap_enabled(
3994 hwmgr
->platform_descriptor
.platformCaps
,
3995 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock
);
3997 disable_mclk_switching
= (1 < info
.display_count
) ||
3998 disable_mclk_switching_for_frame_lock
;
4000 sclk
= fiji_ps
->performance_levels
[0].engine_clock
;
4001 mclk
= fiji_ps
->performance_levels
[0].memory_clock
;
4003 if (disable_mclk_switching
)
4004 mclk
= fiji_ps
->performance_levels
4005 [fiji_ps
->performance_level_count
- 1].memory_clock
;
4007 if (sclk
< minimum_clocks
.engineClock
)
4008 sclk
= (minimum_clocks
.engineClock
> max_limits
->sclk
) ?
4009 max_limits
->sclk
: minimum_clocks
.engineClock
;
4011 if (mclk
< minimum_clocks
.memoryClock
)
4012 mclk
= (minimum_clocks
.memoryClock
> max_limits
->mclk
) ?
4013 max_limits
->mclk
: minimum_clocks
.memoryClock
;
4015 fiji_ps
->performance_levels
[0].engine_clock
= sclk
;
4016 fiji_ps
->performance_levels
[0].memory_clock
= mclk
;
4018 fiji_ps
->performance_levels
[1].engine_clock
=
4019 (fiji_ps
->performance_levels
[1].engine_clock
>=
4020 fiji_ps
->performance_levels
[0].engine_clock
) ?
4021 fiji_ps
->performance_levels
[1].engine_clock
:
4022 fiji_ps
->performance_levels
[0].engine_clock
;
4024 if (disable_mclk_switching
) {
4025 if (mclk
< fiji_ps
->performance_levels
[1].memory_clock
)
4026 mclk
= fiji_ps
->performance_levels
[1].memory_clock
;
4028 fiji_ps
->performance_levels
[0].memory_clock
= mclk
;
4029 fiji_ps
->performance_levels
[1].memory_clock
= mclk
;
4031 if (fiji_ps
->performance_levels
[1].memory_clock
<
4032 fiji_ps
->performance_levels
[0].memory_clock
)
4033 fiji_ps
->performance_levels
[1].memory_clock
=
4034 fiji_ps
->performance_levels
[0].memory_clock
;
4037 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4038 PHM_PlatformCaps_StablePState
)) {
4039 for (i
= 0; i
< fiji_ps
->performance_level_count
; i
++) {
4040 fiji_ps
->performance_levels
[i
].engine_clock
= stable_pstate_sclk
;
4041 fiji_ps
->performance_levels
[i
].memory_clock
= stable_pstate_mclk
;
4042 fiji_ps
->performance_levels
[i
].pcie_gen
= data
->pcie_gen_performance
.max
;
4043 fiji_ps
->performance_levels
[i
].pcie_lane
= data
->pcie_gen_performance
.max
;
4050 static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr
*hwmgr
, const void *input
)
4052 const struct phm_set_power_state_input
*states
=
4053 (const struct phm_set_power_state_input
*)input
;
4054 const struct fiji_power_state
*fiji_ps
=
4055 cast_const_phw_fiji_power_state(states
->pnew_state
);
4056 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4057 struct fiji_single_dpm_table
*sclk_table
= &(data
->dpm_table
.sclk_table
);
4058 uint32_t sclk
= fiji_ps
->performance_levels
4059 [fiji_ps
->performance_level_count
- 1].engine_clock
;
4060 struct fiji_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mclk_table
);
4061 uint32_t mclk
= fiji_ps
->performance_levels
4062 [fiji_ps
->performance_level_count
- 1].memory_clock
;
4063 struct PP_Clocks min_clocks
= {0};
4065 struct cgs_display_info info
= {0};
4067 data
->need_update_smu7_dpm_table
= 0;
4069 for (i
= 0; i
< sclk_table
->count
; i
++) {
4070 if (sclk
== sclk_table
->dpm_levels
[i
].value
)
4074 if (i
>= sclk_table
->count
)
4075 data
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_SCLK
;
4077 /* TODO: Check SCLK in DAL's minimum clocks
4078 * in case DeepSleep divider update is required.
4080 if(data
->display_timing
.min_clock_in_sr
!= min_clocks
.engineClockInSR
)
4081 data
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_SCLK
;
4084 for (i
= 0; i
< mclk_table
->count
; i
++) {
4085 if (mclk
== mclk_table
->dpm_levels
[i
].value
)
4089 if (i
>= mclk_table
->count
)
4090 data
->need_update_smu7_dpm_table
|= DPMTABLE_OD_UPDATE_MCLK
;
4092 cgs_get_active_displays_info(hwmgr
->device
, &info
);
4094 if (data
->display_timing
.num_existing_displays
!= info
.display_count
)
4095 data
->need_update_smu7_dpm_table
|= DPMTABLE_UPDATE_MCLK
;
4100 static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr
*hwmgr
,
4101 const struct fiji_power_state
*fiji_ps
)
4104 uint32_t sclk
, max_sclk
= 0;
4105 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4106 struct fiji_dpm_table
*dpm_table
= &data
->dpm_table
;
4108 for (i
= 0; i
< fiji_ps
->performance_level_count
; i
++) {
4109 sclk
= fiji_ps
->performance_levels
[i
].engine_clock
;
4110 if (max_sclk
< sclk
)
4114 for (i
= 0; i
< dpm_table
->sclk_table
.count
; i
++) {
4115 if (dpm_table
->sclk_table
.dpm_levels
[i
].value
== max_sclk
)
4116 return (uint16_t) ((i
>= dpm_table
->pcie_speed_table
.count
) ?
4117 dpm_table
->pcie_speed_table
.dpm_levels
4118 [dpm_table
->pcie_speed_table
.count
- 1].value
:
4119 dpm_table
->pcie_speed_table
.dpm_levels
[i
].value
);
4125 static int fiji_request_link_speed_change_before_state_change(
4126 struct pp_hwmgr
*hwmgr
, const void *input
)
4128 const struct phm_set_power_state_input
*states
=
4129 (const struct phm_set_power_state_input
*)input
;
4130 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4131 const struct fiji_power_state
*fiji_nps
=
4132 cast_const_phw_fiji_power_state(states
->pnew_state
);
4133 const struct fiji_power_state
*fiji_cps
=
4134 cast_const_phw_fiji_power_state(states
->pcurrent_state
);
4136 uint16_t target_link_speed
= fiji_get_maximum_link_speed(hwmgr
, fiji_nps
);
4137 uint16_t current_link_speed
;
4139 if (data
->force_pcie_gen
== PP_PCIEGenInvalid
)
4140 current_link_speed
= fiji_get_maximum_link_speed(hwmgr
, fiji_cps
);
4142 current_link_speed
= data
->force_pcie_gen
;
4144 data
->force_pcie_gen
= PP_PCIEGenInvalid
;
4145 data
->pspp_notify_required
= false;
4146 if (target_link_speed
> current_link_speed
) {
4147 switch(target_link_speed
) {
4149 if (0 == acpi_pcie_perf_request(hwmgr
->device
, PCIE_PERF_REQ_GEN3
, false))
4151 data
->force_pcie_gen
= PP_PCIEGen2
;
4152 if (current_link_speed
== PP_PCIEGen2
)
4155 if (0 == acpi_pcie_perf_request(hwmgr
->device
, PCIE_PERF_REQ_GEN2
, false))
4158 data
->force_pcie_gen
= fiji_get_current_pcie_speed(hwmgr
);
4162 if (target_link_speed
< current_link_speed
)
4163 data
->pspp_notify_required
= true;
4169 static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
4171 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4173 if (0 == data
->need_update_smu7_dpm_table
)
4176 if ((0 == data
->sclk_dpm_key_disabled
) &&
4177 (data
->need_update_smu7_dpm_table
&
4178 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
))) {
4179 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr
),
4180 "Trying to freeze SCLK DPM when DPM is disabled",);
4181 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4182 PPSMC_MSG_SCLKDPM_FreezeLevel
),
4183 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4187 if ((0 == data
->mclk_dpm_key_disabled
) &&
4188 (data
->need_update_smu7_dpm_table
&
4189 DPMTABLE_OD_UPDATE_MCLK
)) {
4190 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr
),
4191 "Trying to freeze MCLK DPM when DPM is disabled",);
4192 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4193 PPSMC_MSG_MCLKDPM_FreezeLevel
),
4194 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4201 static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
4202 struct pp_hwmgr
*hwmgr
, const void *input
)
4205 const struct phm_set_power_state_input
*states
=
4206 (const struct phm_set_power_state_input
*)input
;
4207 const struct fiji_power_state
*fiji_ps
=
4208 cast_const_phw_fiji_power_state(states
->pnew_state
);
4209 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4210 uint32_t sclk
= fiji_ps
->performance_levels
4211 [fiji_ps
->performance_level_count
- 1].engine_clock
;
4212 uint32_t mclk
= fiji_ps
->performance_levels
4213 [fiji_ps
->performance_level_count
- 1].memory_clock
;
4214 struct fiji_dpm_table
*dpm_table
= &data
->dpm_table
;
4216 struct fiji_dpm_table
*golden_dpm_table
= &data
->golden_dpm_table
;
4217 uint32_t dpm_count
, clock_percent
;
4220 if (0 == data
->need_update_smu7_dpm_table
)
4223 if (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_SCLK
) {
4224 dpm_table
->sclk_table
.dpm_levels
4225 [dpm_table
->sclk_table
.count
- 1].value
= sclk
;
4227 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4228 PHM_PlatformCaps_OD6PlusinACSupport
) ||
4229 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4230 PHM_PlatformCaps_OD6PlusinDCSupport
)) {
4231 /* Need to do calculation based on the golden DPM table
4232 * as the Heatmap GPU Clock axis is also based on the default values
4234 PP_ASSERT_WITH_CODE(
4235 (golden_dpm_table
->sclk_table
.dpm_levels
4236 [golden_dpm_table
->sclk_table
.count
- 1].value
!= 0),
4239 dpm_count
= dpm_table
->sclk_table
.count
< 2 ?
4240 0 : dpm_table
->sclk_table
.count
- 2;
4241 for (i
= dpm_count
; i
> 1; i
--) {
4242 if (sclk
> golden_dpm_table
->sclk_table
.dpm_levels
4243 [golden_dpm_table
->sclk_table
.count
-1].value
) {
4245 ((sclk
- golden_dpm_table
->sclk_table
.dpm_levels
4246 [golden_dpm_table
->sclk_table
.count
-1].value
) * 100) /
4247 golden_dpm_table
->sclk_table
.dpm_levels
4248 [golden_dpm_table
->sclk_table
.count
-1].value
;
4250 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
4251 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
+
4252 (golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
*
4255 } else if (golden_dpm_table
->sclk_table
.dpm_levels
4256 [dpm_table
->sclk_table
.count
-1].value
> sclk
) {
4258 ((golden_dpm_table
->sclk_table
.dpm_levels
4259 [golden_dpm_table
->sclk_table
.count
- 1].value
- sclk
) *
4261 golden_dpm_table
->sclk_table
.dpm_levels
4262 [golden_dpm_table
->sclk_table
.count
-1].value
;
4264 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
4265 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
-
4266 (golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
*
4267 clock_percent
) / 100;
4269 dpm_table
->sclk_table
.dpm_levels
[i
].value
=
4270 golden_dpm_table
->sclk_table
.dpm_levels
[i
].value
;
4275 if (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
) {
4276 dpm_table
->mclk_table
.dpm_levels
4277 [dpm_table
->mclk_table
.count
- 1].value
= mclk
;
4278 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4279 PHM_PlatformCaps_OD6PlusinACSupport
) ||
4280 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4281 PHM_PlatformCaps_OD6PlusinDCSupport
)) {
4283 PP_ASSERT_WITH_CODE(
4284 (golden_dpm_table
->mclk_table
.dpm_levels
4285 [golden_dpm_table
->mclk_table
.count
-1].value
!= 0),
4288 dpm_count
= dpm_table
->mclk_table
.count
< 2 ?
4289 0 : dpm_table
->mclk_table
.count
- 2;
4290 for (i
= dpm_count
; i
> 1; i
--) {
4291 if (mclk
> golden_dpm_table
->mclk_table
.dpm_levels
4292 [golden_dpm_table
->mclk_table
.count
-1].value
) {
4293 clock_percent
= ((mclk
-
4294 golden_dpm_table
->mclk_table
.dpm_levels
4295 [golden_dpm_table
->mclk_table
.count
-1].value
) * 100) /
4296 golden_dpm_table
->mclk_table
.dpm_levels
4297 [golden_dpm_table
->mclk_table
.count
-1].value
;
4299 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
4300 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
+
4301 (golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
*
4302 clock_percent
) / 100;
4304 } else if (golden_dpm_table
->mclk_table
.dpm_levels
4305 [dpm_table
->mclk_table
.count
-1].value
> mclk
) {
4306 clock_percent
= ((golden_dpm_table
->mclk_table
.dpm_levels
4307 [golden_dpm_table
->mclk_table
.count
-1].value
- mclk
) * 100) /
4308 golden_dpm_table
->mclk_table
.dpm_levels
4309 [golden_dpm_table
->mclk_table
.count
-1].value
;
4311 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
4312 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
-
4313 (golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
*
4314 clock_percent
) / 100;
4316 dpm_table
->mclk_table
.dpm_levels
[i
].value
=
4317 golden_dpm_table
->mclk_table
.dpm_levels
[i
].value
;
4322 if (data
->need_update_smu7_dpm_table
&
4323 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
)) {
4324 result
= fiji_populate_all_memory_levels(hwmgr
);
4325 PP_ASSERT_WITH_CODE((0 == result
),
4326 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4330 if (data
->need_update_smu7_dpm_table
&
4331 (DPMTABLE_OD_UPDATE_MCLK
+ DPMTABLE_UPDATE_MCLK
)) {
4332 /*populate MCLK dpm table to SMU7 */
4333 result
= fiji_populate_all_memory_levels(hwmgr
);
4334 PP_ASSERT_WITH_CODE((0 == result
),
4335 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4342 static int fiji_trim_single_dpm_states(struct pp_hwmgr
*hwmgr
,
4343 struct fiji_single_dpm_table
* dpm_table
,
4344 uint32_t low_limit
, uint32_t high_limit
)
4348 for (i
= 0; i
< dpm_table
->count
; i
++) {
4349 if ((dpm_table
->dpm_levels
[i
].value
< low_limit
) ||
4350 (dpm_table
->dpm_levels
[i
].value
> high_limit
))
4351 dpm_table
->dpm_levels
[i
].enabled
= false;
4353 dpm_table
->dpm_levels
[i
].enabled
= true;
4358 static int fiji_trim_dpm_states(struct pp_hwmgr
*hwmgr
,
4359 const struct fiji_power_state
*fiji_ps
)
4362 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4363 uint32_t high_limit_count
;
4365 PP_ASSERT_WITH_CODE((fiji_ps
->performance_level_count
>= 1),
4366 "power state did not have any performance level",
4369 high_limit_count
= (1 == fiji_ps
->performance_level_count
) ? 0 : 1;
4371 fiji_trim_single_dpm_states(hwmgr
,
4372 &(data
->dpm_table
.sclk_table
),
4373 fiji_ps
->performance_levels
[0].engine_clock
,
4374 fiji_ps
->performance_levels
[high_limit_count
].engine_clock
);
4376 fiji_trim_single_dpm_states(hwmgr
,
4377 &(data
->dpm_table
.mclk_table
),
4378 fiji_ps
->performance_levels
[0].memory_clock
,
4379 fiji_ps
->performance_levels
[high_limit_count
].memory_clock
);
4384 static int fiji_generate_dpm_level_enable_mask(
4385 struct pp_hwmgr
*hwmgr
, const void *input
)
4388 const struct phm_set_power_state_input
*states
=
4389 (const struct phm_set_power_state_input
*)input
;
4390 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4391 const struct fiji_power_state
*fiji_ps
=
4392 cast_const_phw_fiji_power_state(states
->pnew_state
);
4394 result
= fiji_trim_dpm_states(hwmgr
, fiji_ps
);
4398 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
=
4399 fiji_get_dpm_level_enable_mask_value(&data
->dpm_table
.sclk_table
);
4400 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
=
4401 fiji_get_dpm_level_enable_mask_value(&data
->dpm_table
.mclk_table
);
4402 data
->last_mclk_dpm_enable_mask
=
4403 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
;
4405 if (data
->uvd_enabled
) {
4406 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
& 1)
4407 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
&= 0xFFFFFFFE;
4410 data
->dpm_level_enable_mask
.pcie_dpm_enable_mask
=
4411 fiji_get_dpm_level_enable_mask_value(&data
->dpm_table
.pcie_speed_table
);
4416 int fiji_enable_disable_uvd_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4418 return smum_send_msg_to_smc(hwmgr
->smumgr
, enable
?
4419 (PPSMC_Msg
)PPSMC_MSG_UVDDPM_Enable
:
4420 (PPSMC_Msg
)PPSMC_MSG_UVDDPM_Disable
);
4423 int fiji_enable_disable_vce_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4425 return smum_send_msg_to_smc(hwmgr
->smumgr
, enable
?
4426 PPSMC_MSG_VCEDPM_Enable
:
4427 PPSMC_MSG_VCEDPM_Disable
);
4430 int fiji_enable_disable_samu_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4432 return smum_send_msg_to_smc(hwmgr
->smumgr
, enable
?
4433 PPSMC_MSG_SAMUDPM_Enable
:
4434 PPSMC_MSG_SAMUDPM_Disable
);
4437 int fiji_enable_disable_acp_dpm(struct pp_hwmgr
*hwmgr
, bool enable
)
4439 return smum_send_msg_to_smc(hwmgr
->smumgr
, enable
?
4440 PPSMC_MSG_ACPDPM_Enable
:
4441 PPSMC_MSG_ACPDPM_Disable
);
4444 int fiji_update_uvd_dpm(struct pp_hwmgr
*hwmgr
, bool bgate
)
4446 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4447 uint32_t mm_boot_level_offset
, mm_boot_level_value
;
4448 struct phm_ppt_v1_information
*table_info
=
4449 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
4452 data
->smc_state_table
.UvdBootLevel
= 0;
4453 if (table_info
->mm_dep_table
->count
> 0)
4454 data
->smc_state_table
.UvdBootLevel
=
4455 (uint8_t) (table_info
->mm_dep_table
->count
- 1);
4456 mm_boot_level_offset
= data
->dpm_table_start
+
4457 offsetof(SMU73_Discrete_DpmTable
, UvdBootLevel
);
4458 mm_boot_level_offset
/= 4;
4459 mm_boot_level_offset
*= 4;
4460 mm_boot_level_value
= cgs_read_ind_register(hwmgr
->device
,
4461 CGS_IND_REG__SMC
, mm_boot_level_offset
);
4462 mm_boot_level_value
&= 0x00FFFFFF;
4463 mm_boot_level_value
|= data
->smc_state_table
.UvdBootLevel
<< 24;
4464 cgs_write_ind_register(hwmgr
->device
,
4465 CGS_IND_REG__SMC
, mm_boot_level_offset
, mm_boot_level_value
);
4467 if (!phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4468 PHM_PlatformCaps_UVDDPM
) ||
4469 phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4470 PHM_PlatformCaps_StablePState
))
4471 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4472 PPSMC_MSG_UVDDPM_SetEnabledMask
,
4473 (uint32_t)(1 << data
->smc_state_table
.UvdBootLevel
));
4476 return fiji_enable_disable_uvd_dpm(hwmgr
, !bgate
);
4479 int fiji_update_vce_dpm(struct pp_hwmgr
*hwmgr
, const void *input
)
4481 const struct phm_set_power_state_input
*states
=
4482 (const struct phm_set_power_state_input
*)input
;
4483 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4484 const struct fiji_power_state
*fiji_nps
=
4485 cast_const_phw_fiji_power_state(states
->pnew_state
);
4486 const struct fiji_power_state
*fiji_cps
=
4487 cast_const_phw_fiji_power_state(states
->pcurrent_state
);
4489 uint32_t mm_boot_level_offset
, mm_boot_level_value
;
4490 struct phm_ppt_v1_information
*table_info
=
4491 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
4493 if (fiji_nps
->vce_clks
.evclk
>0 &&
4494 (fiji_cps
== NULL
|| fiji_cps
->vce_clks
.evclk
== 0)) {
4495 data
->smc_state_table
.VceBootLevel
=
4496 (uint8_t) (table_info
->mm_dep_table
->count
- 1);
4498 mm_boot_level_offset
= data
->dpm_table_start
+
4499 offsetof(SMU73_Discrete_DpmTable
, VceBootLevel
);
4500 mm_boot_level_offset
/= 4;
4501 mm_boot_level_offset
*= 4;
4502 mm_boot_level_value
= cgs_read_ind_register(hwmgr
->device
,
4503 CGS_IND_REG__SMC
, mm_boot_level_offset
);
4504 mm_boot_level_value
&= 0xFF00FFFF;
4505 mm_boot_level_value
|= data
->smc_state_table
.VceBootLevel
<< 16;
4506 cgs_write_ind_register(hwmgr
->device
,
4507 CGS_IND_REG__SMC
, mm_boot_level_offset
, mm_boot_level_value
);
4509 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4510 PHM_PlatformCaps_StablePState
)) {
4511 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4512 PPSMC_MSG_VCEDPM_SetEnabledMask
,
4513 (uint32_t)1 << data
->smc_state_table
.VceBootLevel
);
4515 fiji_enable_disable_vce_dpm(hwmgr
, true);
4516 } else if (fiji_nps
->vce_clks
.evclk
== 0 &&
4518 fiji_cps
->vce_clks
.evclk
> 0)
4519 fiji_enable_disable_vce_dpm(hwmgr
, false);
4525 int fiji_update_samu_dpm(struct pp_hwmgr
*hwmgr
, bool bgate
)
4527 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4528 uint32_t mm_boot_level_offset
, mm_boot_level_value
;
4529 struct phm_ppt_v1_information
*table_info
=
4530 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
4533 data
->smc_state_table
.SamuBootLevel
=
4534 (uint8_t) (table_info
->mm_dep_table
->count
- 1);
4535 mm_boot_level_offset
= data
->dpm_table_start
+
4536 offsetof(SMU73_Discrete_DpmTable
, SamuBootLevel
);
4537 mm_boot_level_offset
/= 4;
4538 mm_boot_level_offset
*= 4;
4539 mm_boot_level_value
= cgs_read_ind_register(hwmgr
->device
,
4540 CGS_IND_REG__SMC
, mm_boot_level_offset
);
4541 mm_boot_level_value
&= 0xFFFFFF00;
4542 mm_boot_level_value
|= data
->smc_state_table
.SamuBootLevel
<< 0;
4543 cgs_write_ind_register(hwmgr
->device
,
4544 CGS_IND_REG__SMC
, mm_boot_level_offset
, mm_boot_level_value
);
4546 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4547 PHM_PlatformCaps_StablePState
))
4548 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4549 PPSMC_MSG_SAMUDPM_SetEnabledMask
,
4550 (uint32_t)(1 << data
->smc_state_table
.SamuBootLevel
));
4553 return fiji_enable_disable_samu_dpm(hwmgr
, !bgate
);
4556 int fiji_update_acp_dpm(struct pp_hwmgr
*hwmgr
, bool bgate
)
4558 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4559 uint32_t mm_boot_level_offset
, mm_boot_level_value
;
4560 struct phm_ppt_v1_information
*table_info
=
4561 (struct phm_ppt_v1_information
*)(hwmgr
->pptable
);
4564 data
->smc_state_table
.AcpBootLevel
=
4565 (uint8_t) (table_info
->mm_dep_table
->count
- 1);
4566 mm_boot_level_offset
= data
->dpm_table_start
+
4567 offsetof(SMU73_Discrete_DpmTable
, AcpBootLevel
);
4568 mm_boot_level_offset
/= 4;
4569 mm_boot_level_offset
*= 4;
4570 mm_boot_level_value
= cgs_read_ind_register(hwmgr
->device
,
4571 CGS_IND_REG__SMC
, mm_boot_level_offset
);
4572 mm_boot_level_value
&= 0xFFFF00FF;
4573 mm_boot_level_value
|= data
->smc_state_table
.AcpBootLevel
<< 8;
4574 cgs_write_ind_register(hwmgr
->device
,
4575 CGS_IND_REG__SMC
, mm_boot_level_offset
, mm_boot_level_value
);
4577 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4578 PHM_PlatformCaps_StablePState
))
4579 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4580 PPSMC_MSG_ACPDPM_SetEnabledMask
,
4581 (uint32_t)(1 << data
->smc_state_table
.AcpBootLevel
));
4584 return fiji_enable_disable_acp_dpm(hwmgr
, !bgate
);
4587 static int fiji_update_sclk_threshold(struct pp_hwmgr
*hwmgr
)
4589 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4592 uint32_t low_sclk_interrupt_threshold
= 0;
4594 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4595 PHM_PlatformCaps_SclkThrottleLowNotification
)
4596 && (hwmgr
->gfx_arbiter
.sclk_threshold
!=
4597 data
->low_sclk_interrupt_threshold
)) {
4598 data
->low_sclk_interrupt_threshold
=
4599 hwmgr
->gfx_arbiter
.sclk_threshold
;
4600 low_sclk_interrupt_threshold
=
4601 data
->low_sclk_interrupt_threshold
;
4603 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold
);
4605 result
= fiji_copy_bytes_to_smc(
4607 data
->dpm_table_start
+
4608 offsetof(SMU73_Discrete_DpmTable
,
4609 LowSclkInterruptThreshold
),
4610 (uint8_t *)&low_sclk_interrupt_threshold
,
4618 static int fiji_program_mem_timing_parameters(struct pp_hwmgr
*hwmgr
)
4620 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4622 if (data
->need_update_smu7_dpm_table
&
4623 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_OD_UPDATE_MCLK
))
4624 return fiji_program_memory_timing_parameters(hwmgr
);
4629 static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr
*hwmgr
)
4631 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4633 if (0 == data
->need_update_smu7_dpm_table
)
4636 if ((0 == data
->sclk_dpm_key_disabled
) &&
4637 (data
->need_update_smu7_dpm_table
&
4638 (DPMTABLE_OD_UPDATE_SCLK
+ DPMTABLE_UPDATE_SCLK
))) {
4640 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr
),
4641 "Trying to Unfreeze SCLK DPM when DPM is disabled",);
4642 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4643 PPSMC_MSG_SCLKDPM_UnfreezeLevel
),
4644 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4648 if ((0 == data
->mclk_dpm_key_disabled
) &&
4649 (data
->need_update_smu7_dpm_table
& DPMTABLE_OD_UPDATE_MCLK
)) {
4651 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr
),
4652 "Trying to Unfreeze MCLK DPM when DPM is disabled",);
4653 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr
->smumgr
,
4654 PPSMC_MSG_SCLKDPM_UnfreezeLevel
),
4655 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4659 data
->need_update_smu7_dpm_table
= 0;
4664 /* Look up the voltaged based on DAL's requested level.
4665 * and then send the requested VDDC voltage to SMC
4667 static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr
*hwmgr
)
4672 int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr
*hwmgr
)
4675 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4677 /* Apply minimum voltage based on DAL's request level */
4678 fiji_apply_dal_minimum_voltage_request(hwmgr
);
4680 if (0 == data
->sclk_dpm_key_disabled
) {
4681 /* Checking if DPM is running. If we discover hang because of this,
4682 * we should skip this message.
4684 if (!fiji_is_dpm_running(hwmgr
))
4685 printk(KERN_ERR
"[ powerplay ] "
4686 "Trying to set Enable Mask when DPM is disabled \n");
4688 if (data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
) {
4689 result
= smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4690 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
4691 data
->dpm_level_enable_mask
.sclk_dpm_enable_mask
);
4692 PP_ASSERT_WITH_CODE((0 == result
),
4693 "Set Sclk Dpm enable Mask failed", return -1);
4697 if (0 == data
->mclk_dpm_key_disabled
) {
4698 /* Checking if DPM is running. If we discover hang because of this,
4699 * we should skip this message.
4701 if (!fiji_is_dpm_running(hwmgr
))
4702 printk(KERN_ERR
"[ powerplay ]"
4703 " Trying to set Enable Mask when DPM is disabled \n");
4705 if (data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
) {
4706 result
= smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4707 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
4708 data
->dpm_level_enable_mask
.mclk_dpm_enable_mask
);
4709 PP_ASSERT_WITH_CODE((0 == result
),
4710 "Set Mclk Dpm enable Mask failed", return -1);
4717 static int fiji_notify_link_speed_change_after_state_change(
4718 struct pp_hwmgr
*hwmgr
, const void *input
)
4720 const struct phm_set_power_state_input
*states
=
4721 (const struct phm_set_power_state_input
*)input
;
4722 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4723 const struct fiji_power_state
*fiji_ps
=
4724 cast_const_phw_fiji_power_state(states
->pnew_state
);
4725 uint16_t target_link_speed
= fiji_get_maximum_link_speed(hwmgr
, fiji_ps
);
4728 if (data
->pspp_notify_required
) {
4729 if (target_link_speed
== PP_PCIEGen3
)
4730 request
= PCIE_PERF_REQ_GEN3
;
4731 else if (target_link_speed
== PP_PCIEGen2
)
4732 request
= PCIE_PERF_REQ_GEN2
;
4734 request
= PCIE_PERF_REQ_GEN1
;
4736 if(request
== PCIE_PERF_REQ_GEN1
&&
4737 fiji_get_current_pcie_speed(hwmgr
) > 0)
4740 if (acpi_pcie_perf_request(hwmgr
->device
, request
, false)) {
4741 if (PP_PCIEGen2
== target_link_speed
)
4742 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4744 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4751 static int fiji_set_power_state_tasks(struct pp_hwmgr
*hwmgr
,
4754 int tmp_result
, result
= 0;
4756 tmp_result
= fiji_find_dpm_states_clocks_in_dpm_table(hwmgr
, input
);
4757 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4758 "Failed to find DPM states clocks in DPM table!",
4759 result
= tmp_result
);
4761 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4762 PHM_PlatformCaps_PCIEPerformanceRequest
)) {
4764 fiji_request_link_speed_change_before_state_change(hwmgr
, input
);
4765 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4766 "Failed to request link speed change before state change!",
4767 result
= tmp_result
);
4770 tmp_result
= fiji_freeze_sclk_mclk_dpm(hwmgr
);
4771 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4772 "Failed to freeze SCLK MCLK DPM!", result
= tmp_result
);
4774 tmp_result
= fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr
, input
);
4775 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4776 "Failed to populate and upload SCLK MCLK DPM levels!",
4777 result
= tmp_result
);
4779 tmp_result
= fiji_generate_dpm_level_enable_mask(hwmgr
, input
);
4780 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4781 "Failed to generate DPM level enabled mask!",
4782 result
= tmp_result
);
4784 tmp_result
= fiji_update_vce_dpm(hwmgr
, input
);
4785 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4786 "Failed to update VCE DPM!",
4787 result
= tmp_result
);
4789 tmp_result
= fiji_update_sclk_threshold(hwmgr
);
4790 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4791 "Failed to update SCLK threshold!",
4792 result
= tmp_result
);
4794 tmp_result
= fiji_program_mem_timing_parameters(hwmgr
);
4795 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4796 "Failed to program memory timing parameters!",
4797 result
= tmp_result
);
4799 tmp_result
= fiji_unfreeze_sclk_mclk_dpm(hwmgr
);
4800 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4801 "Failed to unfreeze SCLK MCLK DPM!",
4802 result
= tmp_result
);
4804 tmp_result
= fiji_upload_dpm_level_enable_mask(hwmgr
);
4805 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4806 "Failed to upload DPM level enabled mask!",
4807 result
= tmp_result
);
4809 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
4810 PHM_PlatformCaps_PCIEPerformanceRequest
)) {
4812 fiji_notify_link_speed_change_after_state_change(hwmgr
, input
);
4813 PP_ASSERT_WITH_CODE((0 == tmp_result
),
4814 "Failed to notify link speed change after state change!",
4815 result
= tmp_result
);
4821 static int fiji_dpm_get_sclk(struct pp_hwmgr
*hwmgr
, bool low
)
4823 struct pp_power_state
*ps
;
4824 struct fiji_power_state
*fiji_ps
;
4829 ps
= hwmgr
->request_ps
;
4834 fiji_ps
= cast_phw_fiji_power_state(&ps
->hardware
);
4837 return fiji_ps
->performance_levels
[0].engine_clock
;
4839 return fiji_ps
->performance_levels
4840 [fiji_ps
->performance_level_count
-1].engine_clock
;
4843 static int fiji_dpm_get_mclk(struct pp_hwmgr
*hwmgr
, bool low
)
4845 struct pp_power_state
*ps
;
4846 struct fiji_power_state
*fiji_ps
;
4851 ps
= hwmgr
->request_ps
;
4856 fiji_ps
= cast_phw_fiji_power_state(&ps
->hardware
);
4859 return fiji_ps
->performance_levels
[0].memory_clock
;
4861 return fiji_ps
->performance_levels
4862 [fiji_ps
->performance_level_count
-1].memory_clock
;
4865 static void fiji_print_current_perforce_level(
4866 struct pp_hwmgr
*hwmgr
, struct seq_file
*m
)
4868 uint32_t sclk
, mclk
, activity_percent
= 0;
4870 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4872 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetSclkFrequency
);
4874 sclk
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
4876 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetMclkFrequency
);
4878 mclk
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
4879 seq_printf(m
, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
4880 mclk
/ 100, sclk
/ 100);
4882 offset
= data
->soft_regs_start
+ offsetof(SMU73_SoftRegisters
, AverageGraphicsActivity
);
4883 activity_percent
= cgs_read_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
, offset
);
4884 activity_percent
+= 0x80;
4885 activity_percent
>>= 8;
4887 seq_printf(m
, "\n [GPU load]: %u%%\n\n", activity_percent
> 100 ? 100 : activity_percent
);
4889 seq_printf(m
, "uvd %sabled\n", data
->uvd_power_gated
? "dis" : "en");
4891 seq_printf(m
, "vce %sabled\n", data
->vce_power_gated
? "dis" : "en");
4894 static int fiji_program_display_gap(struct pp_hwmgr
*hwmgr
)
4896 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
4897 uint32_t num_active_displays
= 0;
4898 uint32_t display_gap
= cgs_read_ind_register(hwmgr
->device
,
4899 CGS_IND_REG__SMC
, ixCG_DISPLAY_GAP_CNTL
);
4900 uint32_t display_gap2
;
4901 uint32_t pre_vbi_time_in_us
;
4902 uint32_t frame_time_in_us
;
4904 uint32_t refresh_rate
= 0;
4905 struct cgs_display_info info
= {0};
4906 struct cgs_mode_info mode_info
;
4908 info
.mode_info
= &mode_info
;
4910 cgs_get_active_displays_info(hwmgr
->device
, &info
);
4911 num_active_displays
= info
.display_count
;
4913 display_gap
= PHM_SET_FIELD(display_gap
, CG_DISPLAY_GAP_CNTL
,
4914 DISP_GAP
, (num_active_displays
> 0)?
4915 DISPLAY_GAP_VBLANK_OR_WM
: DISPLAY_GAP_IGNORE
);
4916 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
4917 ixCG_DISPLAY_GAP_CNTL
, display_gap
);
4919 ref_clock
= mode_info
.ref_clock
;
4920 refresh_rate
= mode_info
.refresh_rate
;
4922 if (refresh_rate
== 0)
4925 frame_time_in_us
= 1000000 / refresh_rate
;
4927 pre_vbi_time_in_us
= frame_time_in_us
- 200 - mode_info
.vblank_time_us
;
4928 display_gap2
= pre_vbi_time_in_us
* (ref_clock
/ 100);
4930 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
4931 ixCG_DISPLAY_GAP_CNTL2
, display_gap2
);
4933 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
4934 data
->soft_regs_start
+
4935 offsetof(SMU73_SoftRegisters
, PreVBlankGap
), 0x64);
4937 cgs_write_ind_register(hwmgr
->device
, CGS_IND_REG__SMC
,
4938 data
->soft_regs_start
+
4939 offsetof(SMU73_SoftRegisters
, VBlankTimeout
),
4940 (frame_time_in_us
- pre_vbi_time_in_us
));
4942 if (num_active_displays
== 1)
4943 tonga_notify_smc_display_change(hwmgr
, true);
4948 int fiji_display_configuration_changed_task(struct pp_hwmgr
*hwmgr
)
4950 return fiji_program_display_gap(hwmgr
);
4953 static int fiji_set_max_fan_pwm_output(struct pp_hwmgr
*hwmgr
,
4954 uint16_t us_max_fan_pwm
)
4956 hwmgr
->thermal_controller
.
4957 advanceFanControlParameters
.usMaxFanPWM
= us_max_fan_pwm
;
4959 if (phm_is_hw_access_blocked(hwmgr
))
4962 return smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4963 PPSMC_MSG_SetFanPwmMax
, us_max_fan_pwm
);
4966 static int fiji_set_max_fan_rpm_output(struct pp_hwmgr
*hwmgr
,
4967 uint16_t us_max_fan_rpm
)
4969 hwmgr
->thermal_controller
.
4970 advanceFanControlParameters
.usMaxFanRPM
= us_max_fan_rpm
;
4972 if (phm_is_hw_access_blocked(hwmgr
))
4975 return smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
4976 PPSMC_MSG_SetFanRpmMax
, us_max_fan_rpm
);
4979 int fiji_dpm_set_interrupt_state(void *private_data
,
4980 unsigned src_id
, unsigned type
,
4983 uint32_t cg_thermal_int
;
4984 struct pp_hwmgr
*hwmgr
= ((struct pp_eventmgr
*)private_data
)->hwmgr
;
4990 case AMD_THERMAL_IRQ_LOW_TO_HIGH
:
4992 cg_thermal_int
= cgs_read_ind_register(hwmgr
->device
,
4993 CGS_IND_REG__SMC
, ixCG_THERMAL_INT
);
4994 cg_thermal_int
|= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK
;
4995 cgs_write_ind_register(hwmgr
->device
,
4996 CGS_IND_REG__SMC
, ixCG_THERMAL_INT
, cg_thermal_int
);
4998 cg_thermal_int
= cgs_read_ind_register(hwmgr
->device
,
4999 CGS_IND_REG__SMC
, ixCG_THERMAL_INT
);
5000 cg_thermal_int
&= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK
;
5001 cgs_write_ind_register(hwmgr
->device
,
5002 CGS_IND_REG__SMC
, ixCG_THERMAL_INT
, cg_thermal_int
);
5006 case AMD_THERMAL_IRQ_HIGH_TO_LOW
:
5008 cg_thermal_int
= cgs_read_ind_register(hwmgr
->device
,
5009 CGS_IND_REG__SMC
, ixCG_THERMAL_INT
);
5010 cg_thermal_int
|= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK
;
5011 cgs_write_ind_register(hwmgr
->device
,
5012 CGS_IND_REG__SMC
, ixCG_THERMAL_INT
, cg_thermal_int
);
5014 cg_thermal_int
= cgs_read_ind_register(hwmgr
->device
,
5015 CGS_IND_REG__SMC
, ixCG_THERMAL_INT
);
5016 cg_thermal_int
&= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK
;
5017 cgs_write_ind_register(hwmgr
->device
,
5018 CGS_IND_REG__SMC
, ixCG_THERMAL_INT
, cg_thermal_int
);
5027 int fiji_register_internal_thermal_interrupt(struct pp_hwmgr
*hwmgr
,
5028 const void *thermal_interrupt_info
)
5031 const struct pp_interrupt_registration_info
*info
=
5032 (const struct pp_interrupt_registration_info
*)
5033 thermal_interrupt_info
;
5038 result
= cgs_add_irq_source(hwmgr
->device
, 230, AMD_THERMAL_IRQ_LAST
,
5039 fiji_dpm_set_interrupt_state
,
5040 info
->call_back
, info
->context
);
5045 result
= cgs_add_irq_source(hwmgr
->device
, 231, AMD_THERMAL_IRQ_LAST
,
5046 fiji_dpm_set_interrupt_state
,
5047 info
->call_back
, info
->context
);
5055 static int fiji_set_fan_control_mode(struct pp_hwmgr
*hwmgr
, uint32_t mode
)
5058 /* stop auto-manage */
5059 if (phm_cap_enabled(hwmgr
->platform_descriptor
.platformCaps
,
5060 PHM_PlatformCaps_MicrocodeFanControl
))
5061 fiji_fan_ctrl_stop_smc_fan_control(hwmgr
);
5062 fiji_fan_ctrl_set_static_mode(hwmgr
, mode
);
5064 /* restart auto-manage */
5065 fiji_fan_ctrl_reset_fan_speed_to_default(hwmgr
);
5070 static int fiji_get_fan_control_mode(struct pp_hwmgr
*hwmgr
)
5072 if (hwmgr
->fan_ctrl_is_in_default_mode
)
5073 return hwmgr
->fan_ctrl_default_mode
;
5075 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr
->device
, CGS_IND_REG__SMC
,
5076 CG_FDO_CTRL2
, FDO_PWM_MODE
);
5079 static int fiji_get_pp_table(struct pp_hwmgr
*hwmgr
, char **table
)
5081 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
5083 *table
= (char *)&data
->smc_state_table
;
5085 return sizeof(struct SMU73_Discrete_DpmTable
);
5088 static int fiji_set_pp_table(struct pp_hwmgr
*hwmgr
, const char *buf
, size_t size
)
5090 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
5092 void *table
= (void *)&data
->smc_state_table
;
5094 memcpy(table
, buf
, size
);
5099 static int fiji_force_clock_level(struct pp_hwmgr
*hwmgr
,
5100 enum pp_clock_type type
, int level
)
5102 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
5104 if (hwmgr
->dpm_level
!= AMD_DPM_FORCED_LEVEL_MANUAL
)
5109 if (!data
->sclk_dpm_key_disabled
)
5110 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
5111 PPSMC_MSG_SCLKDPM_SetEnabledMask
,
5115 if (!data
->mclk_dpm_key_disabled
)
5116 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
5117 PPSMC_MSG_MCLKDPM_SetEnabledMask
,
5121 if (!data
->pcie_dpm_key_disabled
)
5122 smum_send_msg_to_smc_with_parameter(hwmgr
->smumgr
,
5123 PPSMC_MSG_PCIeDPM_ForceLevel
,
5133 static int fiji_print_clock_levels(struct pp_hwmgr
*hwmgr
,
5134 enum pp_clock_type type
, char *buf
)
5136 struct fiji_hwmgr
*data
= (struct fiji_hwmgr
*)(hwmgr
->backend
);
5137 struct fiji_single_dpm_table
*sclk_table
= &(data
->dpm_table
.sclk_table
);
5138 struct fiji_single_dpm_table
*mclk_table
= &(data
->dpm_table
.mclk_table
);
5139 struct fiji_single_dpm_table
*pcie_table
= &(data
->dpm_table
.pcie_speed_table
);
5140 int i
, now
, size
= 0;
5141 uint32_t clock
, pcie_speed
;
5145 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetSclkFrequency
);
5146 clock
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
5148 for (i
= 0; i
< sclk_table
->count
; i
++) {
5149 if (clock
> sclk_table
->dpm_levels
[i
].value
)
5155 for (i
= 0; i
< sclk_table
->count
; i
++)
5156 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
5157 i
, sclk_table
->dpm_levels
[i
].value
/ 100,
5158 (i
== now
) ? "*" : "");
5161 smum_send_msg_to_smc(hwmgr
->smumgr
, PPSMC_MSG_API_GetMclkFrequency
);
5162 clock
= cgs_read_register(hwmgr
->device
, mmSMC_MSG_ARG_0
);
5164 for (i
= 0; i
< mclk_table
->count
; i
++) {
5165 if (clock
> mclk_table
->dpm_levels
[i
].value
)
5171 for (i
= 0; i
< mclk_table
->count
; i
++)
5172 size
+= sprintf(buf
+ size
, "%d: %uMhz %s\n",
5173 i
, mclk_table
->dpm_levels
[i
].value
/ 100,
5174 (i
== now
) ? "*" : "");
5177 pcie_speed
= fiji_get_current_pcie_speed(hwmgr
);
5178 for (i
= 0; i
< pcie_table
->count
; i
++) {
5179 if (pcie_speed
!= pcie_table
->dpm_levels
[i
].value
)
5185 for (i
= 0; i
< pcie_table
->count
; i
++)
5186 size
+= sprintf(buf
+ size
, "%d: %s %s\n", i
,
5187 (pcie_table
->dpm_levels
[i
].value
== 0) ? "2.5GB, x1" :
5188 (pcie_table
->dpm_levels
[i
].value
== 1) ? "5.0GB, x16" :
5189 (pcie_table
->dpm_levels
[i
].value
== 2) ? "8.0GB, x16" : "",
5190 (i
== now
) ? "*" : "");
5198 static const struct pp_hwmgr_func fiji_hwmgr_funcs
= {
5199 .backend_init
= &fiji_hwmgr_backend_init
,
5200 .backend_fini
= &tonga_hwmgr_backend_fini
,
5201 .asic_setup
= &fiji_setup_asic_task
,
5202 .dynamic_state_management_enable
= &fiji_enable_dpm_tasks
,
5203 .force_dpm_level
= &fiji_dpm_force_dpm_level
,
5204 .get_num_of_pp_table_entries
= &tonga_get_number_of_powerplay_table_entries
,
5205 .get_power_state_size
= &fiji_get_power_state_size
,
5206 .get_pp_table_entry
= &fiji_get_pp_table_entry
,
5207 .patch_boot_state
= &fiji_patch_boot_state
,
5208 .apply_state_adjust_rules
= &fiji_apply_state_adjust_rules
,
5209 .power_state_set
= &fiji_set_power_state_tasks
,
5210 .get_sclk
= &fiji_dpm_get_sclk
,
5211 .get_mclk
= &fiji_dpm_get_mclk
,
5212 .print_current_perforce_level
= &fiji_print_current_perforce_level
,
5213 .powergate_uvd
= &fiji_phm_powergate_uvd
,
5214 .powergate_vce
= &fiji_phm_powergate_vce
,
5215 .disable_clock_power_gating
= &fiji_phm_disable_clock_power_gating
,
5216 .notify_smc_display_config_after_ps_adjustment
=
5217 &tonga_notify_smc_display_config_after_ps_adjustment
,
5218 .display_config_changed
= &fiji_display_configuration_changed_task
,
5219 .set_max_fan_pwm_output
= fiji_set_max_fan_pwm_output
,
5220 .set_max_fan_rpm_output
= fiji_set_max_fan_rpm_output
,
5221 .get_temperature
= fiji_thermal_get_temperature
,
5222 .stop_thermal_controller
= fiji_thermal_stop_thermal_controller
,
5223 .get_fan_speed_info
= fiji_fan_ctrl_get_fan_speed_info
,
5224 .get_fan_speed_percent
= fiji_fan_ctrl_get_fan_speed_percent
,
5225 .set_fan_speed_percent
= fiji_fan_ctrl_set_fan_speed_percent
,
5226 .reset_fan_speed_to_default
= fiji_fan_ctrl_reset_fan_speed_to_default
,
5227 .get_fan_speed_rpm
= fiji_fan_ctrl_get_fan_speed_rpm
,
5228 .set_fan_speed_rpm
= fiji_fan_ctrl_set_fan_speed_rpm
,
5229 .uninitialize_thermal_controller
= fiji_thermal_ctrl_uninitialize_thermal_controller
,
5230 .register_internal_thermal_interrupt
= fiji_register_internal_thermal_interrupt
,
5231 .set_fan_control_mode
= fiji_set_fan_control_mode
,
5232 .get_fan_control_mode
= fiji_get_fan_control_mode
,
5233 .get_pp_table
= fiji_get_pp_table
,
5234 .set_pp_table
= fiji_set_pp_table
,
5235 .force_clock_level
= fiji_force_clock_level
,
5236 .print_clock_levels
= fiji_print_clock_levels
,
5239 int fiji_hwmgr_init(struct pp_hwmgr
*hwmgr
)
5241 struct fiji_hwmgr
*data
;
5244 data
= kzalloc(sizeof(struct fiji_hwmgr
), GFP_KERNEL
);
5248 hwmgr
->backend
= data
;
5249 hwmgr
->hwmgr_func
= &fiji_hwmgr_funcs
;
5250 hwmgr
->pptable_func
= &tonga_pptable_funcs
;
5251 pp_fiji_thermal_initialize(hwmgr
);