drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/errno.h>
  24 #include "hwmgr.h"
  25 #include "hardwaremanager.h"
  26 #include "power_state.h"
  27 #include "pp_acpi.h"
  28 #include "amd_acpi.h"
  29 #include "amd_powerplay.h"
  30
  31 void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
  32 {
  33         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
  34         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
  35         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
  36         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
  37         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
  38         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
  39         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
  40         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
  41         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
  42         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
  43
  44         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
  45         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
  46         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
  47
  48         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
  49
  50         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
  51         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
  52
  53         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
  54
  55         if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
  56                 acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
  57                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
  58 }
  59
  60 bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
  61 {
  62         return hwmgr->block_hw_access;
  63 }
  64
  65 int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
  66 {
  67         hwmgr->block_hw_access = block;
  68         return 0;
  69 }
  70
  71 int phm_setup_asic(struct pp_hwmgr *hwmgr)
  72 {
  73         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
  74                 PHM_PlatformCaps_TablelessHardwareInterface)) {
  75                 if (NULL != hwmgr->hwmgr_func->asic_setup)
  76                         return hwmgr->hwmgr_func->asic_setup(hwmgr);
  77         } else {
  78                 return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
  79                                           NULL, NULL);
  80         }
  81
  82         return 0;
  83 }
  84
  85 int phm_set_power_state(struct pp_hwmgr *hwmgr,
  86                     const struct pp_hw_power_state *pcurrent_state,
  87                     const struct pp_hw_power_state *pnew_power_state)
  88 {
  89         struct phm_set_power_state_input states;
  90
  91         states.pcurrent_state = pcurrent_state;
  92         states.pnew_state = pnew_power_state;
  93
  94         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
  95                 PHM_PlatformCaps_TablelessHardwareInterface)) {
  96                 if (NULL != hwmgr->hwmgr_func->power_state_set)
  97                         return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
  98         } else {
  99                 return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
 100         }
 101
 102         return 0;
 103 }
 104
 105 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 106 {
 107         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 108                 PHM_PlatformCaps_TablelessHardwareInterface)) {
 109                 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
 110                         return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
 111         } else {
 112                 return phm_dispatch_table(hwmgr,
 113                                 &(hwmgr->enable_dynamic_state_management),
 114                                 NULL, NULL);
 115         }
 116         return 0;
 117 }
 118
 119 int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
 120 {
 121         if (hwmgr->hwmgr_func->force_dpm_level != NULL)
 122                 return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
 123
 124         return 0;
 125 }
 126
 127 int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 128                                    struct pp_power_state *adjusted_ps,
 129                              const struct pp_power_state *current_ps)
 130 {
 131         if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
 132                 return hwmgr->hwmgr_func->apply_state_adjust_rules(
 133                                                                         hwmgr,
 134                                                                  adjusted_ps,
 135                                                                  current_ps);
 136         return 0;
 137 }
 138
 139 int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
 140 {
 141         if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
 142                 return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
 143         return 0;
 144 }
 145
 146 int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
 147 {
 148         if (hwmgr->hwmgr_func->powergate_uvd != NULL)
 149                 return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
 150         return 0;
 151 }
 152
 153 int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
 154 {
 155         if (hwmgr->hwmgr_func->powergate_vce != NULL)
 156                 return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
 157         return 0;
 158 }
 159
 160 int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
 161 {
 162         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 163                 PHM_PlatformCaps_TablelessHardwareInterface)) {
 164                 if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
 165                         return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
 166         } else {
 167                 return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
 168         }
 169         return 0;
 170 }
 171
 172 int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
 173 {
 174         if (hwmgr == NULL)
 175                 return -EINVAL;
 176
 177         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 178                                  PHM_PlatformCaps_TablelessHardwareInterface)) {
 179                 if (NULL != hwmgr->hwmgr_func->display_config_changed)
 180                         hwmgr->hwmgr_func->display_config_changed(hwmgr);
 181         } else
 182                 return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
 183         return 0;
 184 }
 185
 186 int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
 187 {
 188         if (hwmgr == NULL)
 189                 return -EINVAL;
 190
 191         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 192                                  PHM_PlatformCaps_TablelessHardwareInterface))
 193                 if (NULL != hwmgr->hwmgr_func->display_config_changed)
 194                         hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
 195
 196         return 0;
 197 }
 198
 199 int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 200 {
 201         if (hwmgr == NULL || hwmgr->hwmgr_func->stop_thermal_controller == NULL)
 202                 return -EINVAL;
 203
 204         return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
 205 }
 206
 207 int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
 208 {
 209         if (hwmgr == NULL || hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
 210                 return -EINVAL;
 211
 212         return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
 213 }
 214
 215 /**
 216 * Initializes the thermal controller subsystem.
 217 *
 218 * @param    pHwMgr  the address of the powerplay hardware manager.
 219 * @param    pTemperatureRange the address of the structure holding the temperature range.
 220 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
 221 */
 222 int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
 223 {
 224
 225         return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
 226 }
 227
 228
 229 bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
 230 {
 231         if (hwmgr == NULL || hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
 232                 return -EINVAL;
 233
 234         return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
 235 }
 236
 237
 238 int phm_check_states_equal(struct pp_hwmgr *hwmgr,
 239                                  const struct pp_hw_power_state *pstate1,
 240                                  const struct pp_hw_power_state *pstate2,
 241                                  bool *equal)
 242 {
 243         if (hwmgr == NULL || hwmgr->hwmgr_func->check_states_equal == NULL)
 244                 return -EINVAL;
 245
 246         return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
 247 }
 248
 249 int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
 250                     const struct amd_pp_display_configuration *display_config)
 251 {
 252         if (hwmgr == NULL || hwmgr->hwmgr_func->store_cc6_data == NULL)
 253                 return -EINVAL;
 254
 255         /* to do pass other display configuration in furture */
 256         return hwmgr->hwmgr_func->store_cc6_data(hwmgr,
 257                                         display_config->cpu_pstate_separation_time,
 258                                         display_config->cpu_cc6_disable,
 259                                         display_config->cpu_pstate_disable,
 260                                         display_config->nb_pstate_switch_disable);
 261
 262 }
 263
 264 int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
 265                 struct pp_dal_clock_info*info)
 266 {
 267         if (hwmgr == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
 268                 return -EINVAL;
 269
 270         return hwmgr->hwmgr_func->get_dal_power_level(hwmgr,info);
 271 }
 272
 273 int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 274 {
 275         if (hwmgr != NULL && hwmgr->hwmgr_func->set_cpu_power_state != NULL)
 276                 return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
 277
 278         return 0;
 279 }
 280