drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "linux/delay.h"
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include "cgs_common.h"
  28 #include "power_state.h"
  29 #include "hwmgr.h"
  30 #include "cz_hwmgr.h"
  31 #include "tonga_hwmgr.h"
  32
  33 int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
  34 {
  35         struct pp_hwmgr *hwmgr;
  36
  37         if ((handle == NULL) || (pp_init == NULL))
  38                 return -EINVAL;
  39
  40         hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
  41         if (hwmgr == NULL)
  42                 return -ENOMEM;
  43
  44         handle->hwmgr = hwmgr;
  45         hwmgr->smumgr = handle->smu_mgr;
  46         hwmgr->device = pp_init->device;
  47         hwmgr->chip_family = pp_init->chip_family;
  48         hwmgr->chip_id = pp_init->chip_id;
  49         hwmgr->hw_revision = pp_init->rev_id;
  50         hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
  51         hwmgr->power_source = PP_PowerSource_AC;
  52
  53         switch (hwmgr->chip_family) {
  54         case AMD_FAMILY_CZ:
  55                 cz_hwmgr_init(hwmgr);
  56                 break;
  57         case AMD_FAMILY_VI:
  58                 switch (hwmgr->chip_id) {
  59                 case CHIP_TONGA:
  60                         tonga_hwmgr_init(hwmgr);
  61                         break;
  62                 default:
  63                         return -EINVAL;
  64                 }
  65                 break;
  66         default:
  67                 return -EINVAL;
  68         }
  69
  70         phm_init_dynamic_caps(hwmgr);
  71
  72         return 0;
  73 }
  74
  75 int hwmgr_fini(struct pp_hwmgr *hwmgr)
  76 {
  77         if (hwmgr == NULL || hwmgr->ps == NULL)
  78                 return -EINVAL;
  79
  80         kfree(hwmgr->ps);
  81         kfree(hwmgr);
  82         return 0;
  83 }
  84
  85 int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
  86 {
  87         int result;
  88         unsigned int i;
  89         unsigned int table_entries;
  90         struct pp_power_state *state;
  91         int size;
  92
  93         if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
  94                 return -EINVAL;
  95
  96         if (hwmgr->hwmgr_func->get_power_state_size == NULL)
  97                 return -EINVAL;
  98
  99         hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
 100
 101         hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
 102                                           sizeof(struct pp_power_state);
 103
 104         hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
 105
 106         state = hwmgr->ps;
 107
 108         for (i = 0; i < table_entries; i++) {
 109                 result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
 110                 if (state->classification.flags & PP_StateClassificationFlag_Boot) {
 111                         hwmgr->boot_ps = state;
 112                         hwmgr->current_ps = hwmgr->request_ps = state;
 113                 }
 114
 115                 state->id = i + 1; /* assigned unique num for every power state id */
 116
 117                 if (state->classification.flags & PP_StateClassificationFlag_Uvd)
 118                         hwmgr->uvd_ps = state;
 119                 state = (struct pp_power_state *)((uint64_t)state + size);
 120         }
 121
 122         return 0;
 123 }
 124
 125
 126 /**
 127  * Returns once the part of the register indicated by the mask has
 128  * reached the given value.
 129  */
 130 int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
 131                          uint32_t value, uint32_t mask)
 132 {
 133         uint32_t i;
 134         uint32_t cur_value;
 135
 136         if (hwmgr == NULL || hwmgr->device == NULL) {
 137                 printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
 138                 return -EINVAL;
 139         }
 140
 141         for (i = 0; i < hwmgr->usec_timeout; i++) {
 142                 cur_value = cgs_read_register(hwmgr->device, index);
 143                 if ((cur_value & mask) == (value & mask))
 144                         break;
 145                 udelay(1);
 146         }
 147
 148         /* timeout means wrong logic*/
 149         if (i == hwmgr->usec_timeout)
 150                 return -1;
 151         return 0;
 152 }
 153
 154 int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
 155                                 uint32_t index, uint32_t value, uint32_t mask)
 156 {
 157         uint32_t i;
 158         uint32_t cur_value;
 159
 160         if (hwmgr == NULL || hwmgr->device == NULL) {
 161                 printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
 162                 return -EINVAL;
 163         }
 164
 165         for (i = 0; i < hwmgr->usec_timeout; i++) {
 166                 cur_value = cgs_read_register(hwmgr->device, index);
 167                 if ((cur_value & mask) != (value & mask))
 168                         break;
 169                 udelay(1);
 170         }
 171
 172         /* timeout means wrong logic*/
 173         if (i == hwmgr->usec_timeout)
 174                 return -1;
 175         return 0;
 176 }
 177
 178
 179 /**
 180  * Returns once the part of the register indicated by the mask has
 181  * reached the given value.The indirect space is described by giving
 182  * the memory-mapped index of the indirect index register.
 183  */
 184 void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
 185                                 uint32_t indirect_port,
 186                                 uint32_t index,
 187                                 uint32_t value,
 188                                 uint32_t mask)
 189 {
 190         if (hwmgr == NULL || hwmgr->device == NULL) {
 191                 printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
 192                 return;
 193         }
 194
 195         cgs_write_register(hwmgr->device, indirect_port, index);
 196         phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
 197 }
 198
 199 void phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
 200                                         uint32_t indirect_port,
 201                                         uint32_t index,
 202                                         uint32_t value,
 203                                         uint32_t mask)
 204 {
 205         if (hwmgr == NULL || hwmgr->device == NULL) {
 206                 printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!");
 207                 return;
 208         }
 209
 210         cgs_write_register(hwmgr->device, indirect_port, index);
 211         phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
 212                                       value, mask);
 213 }
 214
 215 bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
 216 {
 217         return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating);
 218 }
 219
 220 bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
 221 {
 222         return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
 223 }