drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef TONGA_HWMGR_H
  24 #define TONGA_HWMGR_H
  25
  26 #include "hwmgr.h"
  27 #include "smu72_discrete.h"
  28 #include "ppatomctrl.h"
  29 #include "ppinterrupt.h"
  30 #include "tonga_powertune.h"
  31
  32 #define TONGA_MAX_HARDWARE_POWERLEVELS 2
  33 #define TONGA_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15
  34
  35 struct tonga_performance_level {
  36         uint32_t        memory_clock;
  37         uint32_t        engine_clock;
  38         uint16_t    pcie_gen;
  39         uint16_t    pcie_lane;
  40 };
  41
  42 struct _phw_tonga_bacos {
  43         uint32_t                          best_match;
  44         uint32_t                          baco_flags;
  45         struct tonga_performance_level            performance_level;
  46 };
  47 typedef struct _phw_tonga_bacos phw_tonga_bacos;
  48
  49 struct _phw_tonga_uvd_clocks {
  50         uint32_t   VCLK;
  51         uint32_t   DCLK;
  52 };
  53
  54 typedef struct _phw_tonga_uvd_clocks phw_tonga_uvd_clocks;
  55
  56 struct _phw_tonga_vce_clocks {
  57         uint32_t   EVCLK;
  58         uint32_t   ECCLK;
  59 };
  60
  61 typedef struct _phw_tonga_vce_clocks phw_tonga_vce_clocks;
  62
  63 struct tonga_power_state {
  64         uint32_t                    magic;
  65         phw_tonga_uvd_clocks        uvd_clocks;
  66         phw_tonga_vce_clocks        vce_clocks;
  67         uint32_t                    sam_clk;
  68         uint32_t                    acp_clk;
  69         uint16_t                    performance_level_count;
  70         bool                        dc_compatible;
  71         uint32_t                    sclk_threshold;
  72         struct tonga_performance_level performance_levels[TONGA_MAX_HARDWARE_POWERLEVELS];
  73 };
  74
  75 struct _phw_tonga_dpm_level {
  76         bool            enabled;
  77         uint32_t    value;
  78         uint32_t    param1;
  79 };
  80 typedef struct _phw_tonga_dpm_level phw_tonga_dpm_level;
  81
  82 #define TONGA_MAX_DEEPSLEEP_DIVIDER_ID 5
  83 #define MAX_REGULAR_DPM_NUMBER 8
  84 #define TONGA_MINIMUM_ENGINE_CLOCK 2500
  85
  86 struct tonga_single_dpm_table {
  87         uint32_t count;
  88         phw_tonga_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
  89 };
  90
  91 struct tonga_dpm_table {
  92         struct tonga_single_dpm_table  sclk_table;
  93         struct tonga_single_dpm_table  mclk_table;
  94         struct tonga_single_dpm_table  pcie_speed_table;
  95         struct tonga_single_dpm_table  vddc_table;
  96         struct tonga_single_dpm_table  vdd_gfx_table;
  97         struct tonga_single_dpm_table  vdd_ci_table;
  98         struct tonga_single_dpm_table  mvdd_table;
  99 };
 100 typedef struct _phw_tonga_dpm_table phw_tonga_dpm_table;
 101
 102
 103 struct _phw_tonga_clock_regisiters {
 104         uint32_t  vCG_SPLL_FUNC_CNTL;
 105         uint32_t  vCG_SPLL_FUNC_CNTL_2;
 106         uint32_t  vCG_SPLL_FUNC_CNTL_3;
 107         uint32_t  vCG_SPLL_FUNC_CNTL_4;
 108         uint32_t  vCG_SPLL_SPREAD_SPECTRUM;
 109         uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;
 110         uint32_t  vDLL_CNTL;
 111         uint32_t  vMCLK_PWRMGT_CNTL;
 112         uint32_t  vMPLL_AD_FUNC_CNTL;
 113         uint32_t  vMPLL_DQ_FUNC_CNTL;
 114         uint32_t  vMPLL_FUNC_CNTL;
 115         uint32_t  vMPLL_FUNC_CNTL_1;
 116         uint32_t  vMPLL_FUNC_CNTL_2;
 117         uint32_t  vMPLL_SS1;
 118         uint32_t  vMPLL_SS2;
 119 };
 120 typedef struct _phw_tonga_clock_regisiters phw_tonga_clock_registers;
 121
 122 struct _phw_tonga_voltage_smio_registers {
 123         uint32_t vs0_vid_lower_smio_cntl;
 124 };
 125 typedef struct _phw_tonga_voltage_smio_registers phw_tonga_voltage_smio_registers;
 126
 127
 128 struct _phw_tonga_mc_reg_entry {
 129         uint32_t mclk_max;
 130         uint32_t mc_data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
 131 };
 132 typedef struct _phw_tonga_mc_reg_entry phw_tonga_mc_reg_entry;
 133
 134 struct _phw_tonga_mc_reg_table {
 135         uint8_t   last;               /* number of registers*/
 136         uint8_t   num_entries;        /* number of entries in mc_reg_table_entry used*/
 137         uint16_t  validflag;          /* indicate the corresponding register is valid or not. 1: valid, 0: invalid. bit0->address[0], bit1->address[1], etc.*/
 138         phw_tonga_mc_reg_entry    mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
 139         SMU72_Discrete_MCRegisterAddress mc_reg_address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
 140 };
 141 typedef struct _phw_tonga_mc_reg_table phw_tonga_mc_reg_table;
 142
 143 #define DISABLE_MC_LOADMICROCODE   1
 144 #define DISABLE_MC_CFGPROGRAMMING  2
 145
 146 /*Ultra Low Voltage parameter structure */
 147 struct _phw_tonga_ulv_parm{
 148         bool    ulv_supported;
 149         uint32_t   ch_ulv_parameter;
 150         uint32_t   ulv_volt_change_delay;
 151         struct tonga_performance_level   ulv_power_level;
 152 };
 153 typedef struct _phw_tonga_ulv_parm phw_tonga_ulv_parm;
 154
 155 #define TONGA_MAX_LEAKAGE_COUNT  8
 156
 157 struct _phw_tonga_leakage_voltage {
 158         uint16_t  count;
 159         uint16_t  leakage_id[TONGA_MAX_LEAKAGE_COUNT];
 160         uint16_t  actual_voltage[TONGA_MAX_LEAKAGE_COUNT];
 161 };
 162 typedef struct _phw_tonga_leakage_voltage phw_tonga_leakage_voltage;
 163
 164 struct _phw_tonga_display_timing {
 165         uint32_t min_clock_insr;
 166         uint32_t num_existing_displays;
 167 };
 168 typedef struct _phw_tonga_display_timing phw_tonga_display_timing;
 169
 170 struct _phw_tonga_dpmlevel_enable_mask {
 171         uint32_t uvd_dpm_enable_mask;
 172         uint32_t vce_dpm_enable_mask;
 173         uint32_t acp_dpm_enable_mask;
 174         uint32_t samu_dpm_enable_mask;
 175         uint32_t sclk_dpm_enable_mask;
 176         uint32_t mclk_dpm_enable_mask;
 177         uint32_t pcie_dpm_enable_mask;
 178 };
 179 typedef struct _phw_tonga_dpmlevel_enable_mask phw_tonga_dpmlevel_enable_mask;
 180
 181 struct _phw_tonga_pcie_perf_range {
 182         uint16_t max;
 183         uint16_t min;
 184 };
 185 typedef struct _phw_tonga_pcie_perf_range phw_tonga_pcie_perf_range;
 186
 187 struct _phw_tonga_vbios_boot_state {
 188         uint16_t                                        mvdd_bootup_value;
 189         uint16_t                                        vddc_bootup_value;
 190         uint16_t                                        vddci_bootup_value;
 191         uint16_t                                        vddgfx_bootup_value;
 192         uint32_t                                        sclk_bootup_value;
 193         uint32_t                                        mclk_bootup_value;
 194         uint16_t                                        pcie_gen_bootup_value;
 195         uint16_t                                        pcie_lane_bootup_value;
 196 };
 197 typedef struct _phw_tonga_vbios_boot_state phw_tonga_vbios_boot_state;
 198
 199 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
 200 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
 201 #define DPMTABLE_UPDATE_SCLK        0x00000004
 202 #define DPMTABLE_UPDATE_MCLK        0x00000008
 203
 204 /* We need to review which fields are needed. */
 205 /* This is mostly a copy of the RV7xx/Evergreen structure which is close, but not identical to the N.Islands one. */
 206 struct tonga_hwmgr {
 207         struct tonga_dpm_table               dpm_table;
 208         struct tonga_dpm_table               golden_dpm_table;
 209
 210         uint32_t                           voting_rights_clients0;
 211         uint32_t                           voting_rights_clients1;
 212         uint32_t                           voting_rights_clients2;
 213         uint32_t                           voting_rights_clients3;
 214         uint32_t                           voting_rights_clients4;
 215         uint32_t                           voting_rights_clients5;
 216         uint32_t                           voting_rights_clients6;
 217         uint32_t                           voting_rights_clients7;
 218         uint32_t                           static_screen_threshold_unit;
 219         uint32_t                           static_screen_threshold;
 220         uint32_t                           voltage_control;
 221         uint32_t                           vdd_gfx_control;
 222
 223         uint32_t                           vddc_vddci_delta;
 224         uint32_t                           vddc_vddgfx_delta;
 225
 226         struct pp_interrupt_registration_info    internal_high_thermal_interrupt_info;
 227         struct pp_interrupt_registration_info    internal_low_thermal_interrupt_info;
 228         struct pp_interrupt_registration_info    smc_to_host_interrupt_info;
 229         uint32_t                          active_auto_throttle_sources;
 230
 231         struct pp_interrupt_registration_info    external_throttle_interrupt;
 232         irq_handler_func_t             external_throttle_callback;
 233         void                             *external_throttle_context;
 234
 235         struct pp_interrupt_registration_info    ctf_interrupt_info;
 236         irq_handler_func_t             ctf_callback;
 237         void                             *ctf_context;
 238
 239         phw_tonga_clock_registers         clock_registers;
 240         phw_tonga_voltage_smio_registers  voltage_smio_registers;
 241
 242         bool                            is_memory_GDDR5;
 243         uint16_t                          acpi_vddc;
 244         bool                            pspp_notify_required;        /* Flag to indicate if PSPP notification to SBIOS is required */
 245         uint16_t                          force_pcie_gen;            /* The forced PCI-E speed if not 0xffff */
 246         uint16_t                          acpi_pcie_gen;             /* The PCI-E speed at ACPI time */
 247         uint32_t                           pcie_gen_cap;             /* The PCI-E speed capabilities bitmap from CAIL */
 248         uint32_t                           pcie_lane_cap;            /* The PCI-E lane capabilities bitmap from CAIL */
 249         uint32_t                           pcie_spc_cap;             /* Symbol Per Clock Capabilities from registry */
 250         phw_tonga_leakage_voltage               vddc_leakage;            /* The Leakage VDDC supported (based on leakage ID).*/
 251         phw_tonga_leakage_voltage               vddcgfx_leakage;         /* The Leakage VDDC supported (based on leakage ID). */
 252         phw_tonga_leakage_voltage               vddci_leakage;           /* The Leakage VDDCI supported (based on leakage ID). */
 253
 254         uint32_t                           mvdd_control;
 255         uint32_t                           vddc_mask_low;
 256         uint32_t                           mvdd_mask_low;
 257         uint16_t                          max_vddc_in_pp_table;        /* the maximum VDDC value in the powerplay table*/
 258         uint16_t                          min_vddc_in_pp_table;
 259         uint16_t                          max_vddci_in_pp_table;       /* the maximum VDDCI value in the powerplay table */
 260         uint16_t                          min_vddci_in_pp_table;
 261         uint32_t                           mclk_strobe_mode_threshold;
 262         uint32_t                           mclk_stutter_mode_threshold;
 263         uint32_t                           mclk_edc_enable_threshold;
 264         uint32_t                           mclk_edc_wr_enable_threshold;
 265         bool                            is_uvd_enabled;
 266         bool                            is_xdma_enabled;
 267         phw_tonga_vbios_boot_state      vbios_boot_state;
 268
 269         bool                         battery_state;
 270         bool                         is_tlu_enabled;
 271         bool                         pcie_performance_request;
 272
 273         /* -------------- SMC SRAM Address of firmware header tables ----------------*/
 274         uint32_t                           sram_end;                 /* The first address after the SMC SRAM. */
 275         uint32_t                           dpm_table_start;          /* The start of the dpm table in the SMC SRAM. */
 276         uint32_t                           soft_regs_start;          /* The start of the soft registers in the SMC SRAM. */
 277         uint32_t                           mc_reg_table_start;       /* The start of the mc register table in the SMC SRAM. */
 278         uint32_t                           fan_table_start;          /* The start of the fan table in the SMC SRAM. */
 279         uint32_t                           arb_table_start;          /* The start of the ARB setting table in the SMC SRAM. */
 280         SMU72_Discrete_DpmTable         smc_state_table;             /* The carbon copy of the SMC state table. */
 281         SMU72_Discrete_MCRegisters      mc_reg_table;
 282         SMU72_Discrete_Ulv              ulv_setting;                 /* The carbon copy of ULV setting. */
 283         /* -------------- Stuff originally coming from Evergreen --------------------*/
 284         phw_tonga_mc_reg_table                  tonga_mc_reg_table;
 285         uint32_t                         vdd_ci_control;
 286         pp_atomctrl_voltage_table        vddc_voltage_table;
 287         pp_atomctrl_voltage_table        vddci_voltage_table;
 288         pp_atomctrl_voltage_table        vddgfx_voltage_table;
 289         pp_atomctrl_voltage_table        mvdd_voltage_table;
 290
 291         uint32_t                           mgcg_cgtt_local2;
 292         uint32_t                           mgcg_cgtt_local3;
 293         uint32_t                           gpio_debug;
 294         uint32_t                                                        mc_micro_code_feature;
 295         uint32_t                                                        highest_mclk;
 296         uint16_t                          acpi_vdd_ci;
 297         uint8_t                           mvdd_high_index;
 298         uint8_t                           mvdd_low_index;
 299         bool                         dll_defaule_on;
 300         bool                         performance_request_registered;
 301
 302         /* ----------------- Low Power Features ---------------------*/
 303         phw_tonga_bacos                                 bacos;
 304         phw_tonga_ulv_parm              ulv;
 305         /* ----------------- CAC Stuff ---------------------*/
 306         uint32_t                                        cac_table_start;
 307         bool                         cac_configuration_required;    /* TRUE if PP_CACConfigurationRequired == 1 */
 308         bool                         driver_calculate_cac_leakage;  /* TRUE if PP_DriverCalculateCACLeakage == 1 */
 309         bool                         cac_enabled;
 310         /* ----------------- DPM2 Parameters ---------------------*/
 311         uint32_t                                        power_containment_features;
 312         bool                         enable_bapm_feature;
 313         bool                         enable_tdc_limit_feature;
 314         bool                         enable_pkg_pwr_tracking_feature;
 315         bool                         disable_uvd_power_tune_feature;
 316         phw_tonga_pt_defaults           *power_tune_defaults;
 317         SMU72_Discrete_PmFuses           power_tune_table;
 318         uint32_t                           ul_dte_tj_offset;             /* Fudge factor in DPM table to correct HW DTE errors */
 319         uint32_t                           fast_watemark_threshold;      /* use fast watermark if clock is equal or above this. In percentage of the target high sclk. */
 320
 321         /* ----------------- Phase Shedding ---------------------*/
 322         bool                         vddc_phase_shed_control;
 323         /* --------------------- DI/DT --------------------------*/
 324         phw_tonga_display_timing       display_timing;
 325         /* --------- ReadRegistry data for memory and engine clock margins ---- */
 326         uint32_t                           engine_clock_data;
 327         uint32_t                           memory_clock_data;
 328         /* -------- Thermal Temperature Setting --------------*/
 329         phw_tonga_dpmlevel_enable_mask     dpm_level_enable_mask;
 330         uint32_t                           need_update_smu7_dpm_table;
 331         uint32_t                           sclk_dpm_key_disabled;
 332         uint32_t                           mclk_dpm_key_disabled;
 333         uint32_t                           pcie_dpm_key_disabled;
 334         uint32_t                           min_engine_clocks; /* used to store the previous dal min sclock */
 335         phw_tonga_pcie_perf_range       pcie_gen_performance;
 336         phw_tonga_pcie_perf_range       pcie_lane_performance;
 337         phw_tonga_pcie_perf_range       pcie_gen_power_saving;
 338         phw_tonga_pcie_perf_range       pcie_lane_power_saving;
 339         bool                            use_pcie_performance_levels;
 340         bool                            use_pcie_power_saving_levels;
 341         uint32_t                           activity_target[SMU72_MAX_LEVELS_GRAPHICS]; /* percentage value from 0-100, default 50 */
 342         uint32_t                           mclk_activity_target;
 343         uint32_t                           low_sclk_interrupt_threshold;
 344         uint32_t                           last_mclk_dpm_enable_mask;
 345         bool                                                            uvd_enabled;
 346         uint32_t                           pcc_monitor_enabled;
 347
 348         /* --------- Power Gating States ------------*/
 349         bool                           uvd_power_gated;  /* 1: gated, 0:not gated */
 350         bool                           vce_power_gated;  /* 1: gated, 0:not gated */
 351         bool                           samu_power_gated; /* 1: gated, 0:not gated */
 352         bool                           acp_power_gated;  /* 1: gated, 0:not gated */
 353         bool                           pg_acp_init;
 354
 355 };
 356
 357 typedef struct tonga_hwmgr tonga_hwmgr;
 358
 359 #define TONGA_DPM2_NEAR_TDP_DEC          10
 360 #define TONGA_DPM2_ABOVE_SAFE_INC        5
 361 #define TONGA_DPM2_BELOW_SAFE_INC        20
 362
 363 #define TONGA_DPM2_LTA_WINDOW_SIZE       7  /* Log2 of the LTA window size (l2numWin_TDP). Eg. If LTA windows size is 128, then this value should be Log2(128) = 7. */
 364
 365 #define TONGA_DPM2_LTS_TRUNCATE          0
 366
 367 #define TONGA_DPM2_TDP_SAFE_LIMIT_PERCENT            80  /* Maximum 100 */
 368
 369 #define TONGA_DPM2_MAXPS_PERCENT_H                   90  /* Maximum 0xFF */
 370 #define TONGA_DPM2_MAXPS_PERCENT_M                   90  /* Maximum 0xFF */
 371
 372 #define TONGA_DPM2_PWREFFICIENCYRATIO_MARGIN         50
 373
 374 #define TONGA_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
 375 #define TONGA_DPM2_SQ_RAMP_MIN_POWER                 0x12
 376 #define TONGA_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
 377 #define TONGA_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
 378 #define TONGA_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
 379
 380 #define TONGA_VOLTAGE_CONTROL_NONE                   0x0
 381 #define TONGA_VOLTAGE_CONTROL_BY_GPIO                0x1
 382 #define TONGA_VOLTAGE_CONTROL_BY_SVID2               0x2
 383 #define TONGA_VOLTAGE_CONTROL_MERGED                 0x3
 384
 385 #define TONGA_Q88_FORMAT_CONVERSION_UNIT             256 /*To convert to Q8.8 format for firmware */
 386
 387 #define TONGA_UNUSED_GPIO_PIN                        0x7F
 388
 389 #define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
 390 #define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X)
 391
 392 #define PP_HOST_TO_SMC_US(X) cpu_to_be16(X)
 393 #define PP_SMC_TO_HOST_US(X) be16_to_cpu(X)
 394
 395 #define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X))
 396 #define CONVERT_FROM_SMC_TO_HOST_UL(X) ((X) = PP_SMC_TO_HOST_UL(X))
 397
 398 #define CONVERT_FROM_HOST_TO_SMC_US(X) ((X) = PP_HOST_TO_SMC_US(X))
 399
 400 int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
 401 int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
 402 int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
 403 int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable);
 404 int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
 405 uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr);
 406
 407 #endif
 408