drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _HWMGR_H_
  24 #define _HWMGR_H_
  25
  26 #include <linux/seq_file.h>
  27 #include "amd_powerplay.h"
  28 #include "pp_instance.h"
  29 #include "hardwaremanager.h"
  30 #include "pp_power_source.h"
  31
  32 struct pp_instance;
  33 struct pp_hwmgr;
  34 struct pp_hw_power_state;
  35 struct pp_power_state;
  36 struct PP_VCEState;
  37
  38 enum PP_Result {
  39         PP_Result_TableImmediateExit = 0x13,
  40 };
  41
  42 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
  43 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
  44 #define PCIE_PERF_REQ_GEN1         2
  45 #define PCIE_PERF_REQ_GEN2         3
  46 #define PCIE_PERF_REQ_GEN3         4
  47
  48 enum PHM_BackEnd_Magic {
  49         PHM_Dummy_Magic       = 0xAA5555AA,
  50         PHM_RV770_Magic       = 0xDCBAABCD,
  51         PHM_Kong_Magic        = 0x239478DF,
  52         PHM_NIslands_Magic    = 0x736C494E,
  53         PHM_Sumo_Magic        = 0x8339FA11,
  54         PHM_SIslands_Magic    = 0x369431AC,
  55         PHM_Trinity_Magic     = 0x96751873,
  56         PHM_CIslands_Magic    = 0x38AC78B0,
  57         PHM_Kv_Magic          = 0xDCBBABC0,
  58         PHM_VIslands_Magic    = 0x20130307,
  59         PHM_Cz_Magic          = 0x67DCBA25
  60 };
  61
  62 enum PP_DAL_POWERLEVEL {
  63         PP_DAL_POWERLEVEL_INVALID = 0,
  64         PP_DAL_POWERLEVEL_ULTRALOW,
  65         PP_DAL_POWERLEVEL_LOW,
  66         PP_DAL_POWERLEVEL_NOMINAL,
  67         PP_DAL_POWERLEVEL_PERFORMANCE,
  68
  69         PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
  70         PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
  71         PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
  72         PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
  73         PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
  74         PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
  75         PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
  76         PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
  77 };
  78
  79 #define PHM_PCIE_POWERGATING_TARGET_GFX            0
  80 #define PHM_PCIE_POWERGATING_TARGET_DDI            1
  81 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
  82 #define PHM_PCIE_POWERGATING_TARGET_PHY            3
  83
  84 typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
  85                                   void *output, void *storage, int result);
  86
  87 typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
  88
  89 struct phm_set_power_state_input {
  90         const struct pp_hw_power_state *pcurrent_state;
  91         const struct pp_hw_power_state *pnew_state;
  92 };
  93
  94 struct phm_acp_arbiter {
  95         uint32_t acpclk;
  96 };
  97
  98 struct phm_uvd_arbiter {
  99         uint32_t vclk;
 100         uint32_t dclk;
 101         uint32_t vclk_ceiling;
 102         uint32_t dclk_ceiling;
 103 };
 104
 105 struct phm_vce_arbiter {
 106         uint32_t   evclk;
 107         uint32_t   ecclk;
 108 };
 109
 110 struct phm_gfx_arbiter {
 111         uint32_t sclk;
 112         uint32_t mclk;
 113         uint32_t sclk_over_drive;
 114         uint32_t mclk_over_drive;
 115         uint32_t sclk_threshold;
 116         uint32_t num_cus;
 117 };
 118
 119 /* Entries in the master tables */
 120 struct phm_master_table_item {
 121         phm_check_function isFunctionNeededInRuntimeTable;
 122         phm_table_function tableFunction;
 123 };
 124
 125 enum phm_master_table_flag {
 126         PHM_MasterTableFlag_None         = 0,
 127         PHM_MasterTableFlag_ExitOnError  = 1,
 128 };
 129
 130 /* The header of the master tables */
 131 struct phm_master_table_header {
 132         uint32_t storage_size;
 133         uint32_t flags;
 134         struct phm_master_table_item *master_list;
 135 };
 136
 137 struct phm_runtime_table_header {
 138         uint32_t storage_size;
 139         bool exit_error;
 140         phm_table_function *function_list;
 141 };
 142
 143 struct phm_clock_array {
 144         uint32_t count;
 145         uint32_t values[1];
 146 };
 147
 148 struct phm_clock_voltage_dependency_record {
 149         uint32_t clk;
 150         uint32_t v;
 151 };
 152
 153 struct phm_vceclock_voltage_dependency_record {
 154         uint32_t ecclk;
 155         uint32_t evclk;
 156         uint32_t v;
 157 };
 158
 159 struct phm_uvdclock_voltage_dependency_record {
 160         uint32_t vclk;
 161         uint32_t dclk;
 162         uint32_t v;
 163 };
 164
 165 struct phm_samuclock_voltage_dependency_record {
 166         uint32_t samclk;
 167         uint32_t v;
 168 };
 169
 170 struct phm_acpclock_voltage_dependency_record {
 171         uint32_t acpclk;
 172         uint32_t v;
 173 };
 174
 175 struct phm_clock_voltage_dependency_table {
 176         uint32_t count;                                                                         /* Number of entries. */
 177         struct phm_clock_voltage_dependency_record entries[1];          /* Dynamically allocate count entries. */
 178 };
 179
 180 struct phm_phase_shedding_limits_record {
 181         uint32_t  Voltage;
 182         uint32_t    Sclk;
 183         uint32_t    Mclk;
 184 };
 185
 186
 187 extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
 188                               struct phm_runtime_table_header *rt_table,
 189                               void *input, void *output);
 190
 191 extern int phm_construct_table(struct pp_hwmgr *hwmgr,
 192                                struct phm_master_table_header *master_table,
 193                                struct phm_runtime_table_header *rt_table);
 194
 195 extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
 196                              struct phm_runtime_table_header *rt_table);
 197
 198
 199 struct phm_uvd_clock_voltage_dependency_record {
 200         uint32_t vclk;
 201         uint32_t dclk;
 202         uint32_t v;
 203 };
 204
 205 struct phm_uvd_clock_voltage_dependency_table {
 206         uint8_t count;
 207         struct phm_uvd_clock_voltage_dependency_record entries[1];
 208 };
 209
 210 struct phm_acp_clock_voltage_dependency_record {
 211         uint32_t acpclk;
 212         uint32_t v;
 213 };
 214
 215 struct phm_acp_clock_voltage_dependency_table {
 216         uint32_t count;
 217         struct phm_acp_clock_voltage_dependency_record entries[1];
 218 };
 219
 220 struct phm_vce_clock_voltage_dependency_record {
 221         uint32_t ecclk;
 222         uint32_t evclk;
 223         uint32_t v;
 224 };
 225
 226 struct phm_phase_shedding_limits_table {
 227         uint32_t                           count;
 228         struct phm_phase_shedding_limits_record  entries[1];
 229 };
 230
 231 struct phm_vceclock_voltage_dependency_table {
 232         uint8_t count;                                    /* Number of entries. */
 233         struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 234 };
 235
 236 struct phm_uvdclock_voltage_dependency_table {
 237         uint8_t count;                                    /* Number of entries. */
 238         struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 239 };
 240
 241 struct phm_samuclock_voltage_dependency_table {
 242         uint8_t count;                                    /* Number of entries. */
 243         struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 244 };
 245
 246 struct phm_acpclock_voltage_dependency_table {
 247         uint32_t count;                                    /* Number of entries. */
 248         struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 249 };
 250
 251 struct phm_vce_clock_voltage_dependency_table {
 252         uint8_t count;
 253         struct phm_vce_clock_voltage_dependency_record entries[1];
 254 };
 255
 256 struct pp_hwmgr_func {
 257         int (*backend_init)(struct pp_hwmgr *hw_mgr);
 258         int (*backend_fini)(struct pp_hwmgr *hw_mgr);
 259         int (*asic_setup)(struct pp_hwmgr *hw_mgr);
 260         int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
 261
 262         int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
 263                                 struct pp_power_state  *prequest_ps,
 264                         const struct pp_power_state *pcurrent_ps);
 265
 266         int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
 267                                         enum amd_dpm_forced_level level);
 268
 269         int (*dynamic_state_management_enable)(
 270                                                 struct pp_hwmgr *hw_mgr);
 271
 272         int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
 273                                      struct pp_hw_power_state *hw_ps);
 274
 275         int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
 276                             unsigned long, struct pp_power_state *);
 277
 278         int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
 279         int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
 280         int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
 281         int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
 282         int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
 283         int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
 284         int (*power_state_set)(struct pp_hwmgr *hwmgr,
 285                                                 const void *state);
 286         void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr,
 287                                                         struct seq_file *m);
 288         int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 289 };
 290
 291 struct pp_table_func {
 292         int (*pptable_init)(struct pp_hwmgr *hw_mgr);
 293         int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
 294         int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
 295         int (*pptable_get_vce_state_table_entry)(
 296                                                 struct pp_hwmgr *hwmgr,
 297                                                 unsigned long i,
 298                                                 struct PP_VCEState *vce_state,
 299                                                 void **clock_info,
 300                                                 unsigned long *flag);
 301 };
 302
 303 union phm_cac_leakage_record {
 304         struct {
 305                 uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
 306                 uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
 307         };
 308         struct {
 309                 uint16_t Vddc1;
 310                 uint16_t Vddc2;
 311                 uint16_t Vddc3;
 312         };
 313 };
 314
 315 struct phm_cac_leakage_table {
 316         uint32_t count;
 317         union phm_cac_leakage_record entries[1];
 318 };
 319
 320 struct phm_samu_clock_voltage_dependency_record {
 321         uint32_t samclk;
 322         uint32_t v;
 323 };
 324
 325
 326 struct phm_samu_clock_voltage_dependency_table {
 327         uint8_t count;
 328         struct phm_samu_clock_voltage_dependency_record entries[1];
 329 };
 330
 331 struct phm_cac_tdp_table {
 332         uint16_t usTDP;
 333         uint16_t usConfigurableTDP;
 334         uint16_t usTDC;
 335         uint16_t usBatteryPowerLimit;
 336         uint16_t usSmallPowerLimit;
 337         uint16_t usLowCACLeakage;
 338         uint16_t usHighCACLeakage;
 339         uint16_t usMaximumPowerDeliveryLimit;
 340         uint16_t usOperatingTempMinLimit;
 341         uint16_t usOperatingTempMaxLimit;
 342         uint16_t usOperatingTempStep;
 343         uint16_t usOperatingTempHyst;
 344         uint16_t usDefaultTargetOperatingTemp;
 345         uint16_t usTargetOperatingTemp;
 346         uint16_t usPowerTuneDataSetID;
 347         uint16_t usSoftwareShutdownTemp;
 348         uint16_t usClockStretchAmount;
 349         uint16_t usTemperatureLimitHotspot;
 350         uint16_t usTemperatureLimitLiquid1;
 351         uint16_t usTemperatureLimitLiquid2;
 352         uint16_t usTemperatureLimitVrVddc;
 353         uint16_t usTemperatureLimitVrMvdd;
 354         uint16_t usTemperatureLimitPlx;
 355         uint8_t  ucLiquid1_I2C_address;
 356         uint8_t  ucLiquid2_I2C_address;
 357         uint8_t  ucLiquid_I2C_Line;
 358         uint8_t  ucVr_I2C_address;
 359         uint8_t  ucVr_I2C_Line;
 360         uint8_t  ucPlx_I2C_address;
 361         uint8_t  ucPlx_I2C_Line;
 362 };
 363
 364 struct phm_ppm_table {
 365         uint8_t   ppm_design;
 366         uint16_t  cpu_core_number;
 367         uint32_t  platform_tdp;
 368         uint32_t  small_ac_platform_tdp;
 369         uint32_t  platform_tdc;
 370         uint32_t  small_ac_platform_tdc;
 371         uint32_t  apu_tdp;
 372         uint32_t  dgpu_tdp;
 373         uint32_t  dgpu_ulv_power;
 374         uint32_t  tj_max;
 375 };
 376
 377 struct phm_vq_budgeting_record {
 378         uint32_t ulCUs;
 379         uint32_t ulSustainableSOCPowerLimitLow;
 380         uint32_t ulSustainableSOCPowerLimitHigh;
 381         uint32_t ulMinSclkLow;
 382         uint32_t ulMinSclkHigh;
 383         uint8_t  ucDispConfig;
 384         uint32_t ulDClk;
 385         uint32_t ulEClk;
 386         uint32_t ulSustainableSclk;
 387         uint32_t ulSustainableCUs;
 388 };
 389
 390 struct phm_vq_budgeting_table {
 391         uint8_t numEntries;
 392         struct phm_vq_budgeting_record entries[1];
 393 };
 394
 395 struct phm_clock_and_voltage_limits {
 396         uint32_t sclk;
 397         uint32_t mclk;
 398         uint16_t vddc;
 399         uint16_t vddci;
 400         uint16_t vddgfx;
 401 };
 402
 403
 404
 405 struct phm_dynamic_state_info {
 406         struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
 407         struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
 408         struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
 409         struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
 410         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 411         struct phm_clock_array                    *valid_sclk_values;
 412         struct phm_clock_array                    *valid_mclk_values;
 413         struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
 414         struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
 415         uint32_t                                  mclk_sclk_ratio;
 416         uint32_t                                  sclk_mclk_delta;
 417         uint32_t                                  vddc_vddci_delta;
 418         uint32_t                                  min_vddc_for_pcie_gen2;
 419         struct phm_cac_leakage_table              *cac_leakage_table;
 420         struct phm_phase_shedding_limits_table    *vddc_phase_shed_limits_table;
 421
 422         struct phm_vce_clock_voltage_dependency_table
 423                                             *vce_clocl_voltage_dependency_table;
 424         struct phm_uvd_clock_voltage_dependency_table
 425                                             *uvd_clocl_voltage_dependency_table;
 426         struct phm_acp_clock_voltage_dependency_table
 427                                             *acp_clock_voltage_dependency_table;
 428         struct phm_samu_clock_voltage_dependency_table
 429                                            *samu_clock_voltage_dependency_table;
 430
 431         struct phm_ppm_table                          *ppm_parameter_table;
 432         struct phm_cac_tdp_table                      *cac_dtp_table;
 433         struct phm_clock_voltage_dependency_table         *vdd_gfx_dependency_on_sclk;
 434         struct phm_vq_budgeting_table                             *vq_budgeting_table;
 435 };
 436
 437 struct pp_hwmgr {
 438         uint32_t chip_family;
 439         uint32_t chip_id;
 440         uint32_t hw_revision;
 441         uint32_t sub_sys_id;
 442         uint32_t sub_vendor_id;
 443
 444         void *device;
 445         struct pp_smumgr *smumgr;
 446         const void *soft_pp_table;
 447         enum amd_dpm_forced_level dpm_level;
 448         bool block_hw_access;
 449         struct phm_gfx_arbiter gfx_arbiter;
 450         struct phm_acp_arbiter acp_arbiter;
 451         struct phm_uvd_arbiter uvd_arbiter;
 452         struct phm_vce_arbiter vce_arbiter;
 453         uint32_t usec_timeout;
 454         void *pptable;
 455         struct phm_platform_descriptor platform_descriptor;
 456         void *backend;
 457         enum PP_DAL_POWERLEVEL  dal_power_level;
 458         struct phm_dynamic_state_info dyn_state;
 459         struct phm_runtime_table_header setup_asic;
 460         struct phm_runtime_table_header disable_dynamic_state_management;
 461         struct phm_runtime_table_header enable_dynamic_state_management;
 462         struct phm_runtime_table_header set_power_state;
 463         struct phm_runtime_table_header enable_clock_power_gatings;
 464         const struct pp_hwmgr_func *hwmgr_func;
 465         const struct pp_table_func *pptable_func;
 466         struct pp_power_state    *ps;
 467         enum pp_power_source  power_source;
 468         uint32_t num_ps;
 469         uint32_t ps_size;
 470         struct pp_power_state    *current_ps;
 471         struct pp_power_state    *request_ps;
 472         struct pp_power_state    *boot_ps;
 473         struct pp_power_state    *uvd_ps;
 474 };
 475
 476
 477 extern int hwmgr_init(struct amd_pp_init *pp_init,
 478                       struct pp_instance *handle);
 479
 480 extern int hwmgr_fini(struct pp_hwmgr *hwmgr);
 481
 482 extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr);
 483
 484 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
 485                                 uint32_t value, uint32_t mask);
 486
 487 extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
 488                                 uint32_t index, uint32_t value, uint32_t mask);
 489
 490
 491
 492 extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
 493                                 uint32_t indirect_port,
 494                                 uint32_t index,
 495                                 uint32_t value,
 496                                 uint32_t mask);
 497
 498 extern void phm_wait_for_indirect_register_unequal(
 499                                 struct pp_hwmgr *hwmgr,
 500                                 uint32_t indirect_port,
 501                                 uint32_t index,
 502                                 uint32_t value,
 503                                 uint32_t mask);
 504
 505 bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
 506 bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
 507
 508 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
 509
 510 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
 511 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
 512
 513 #define PHM_SET_FIELD(origval, reg, field, fieldval)    \
 514         (((origval) & ~PHM_FIELD_MASK(reg, field)) |    \
 515          (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
 516
 517 #define PHM_GET_FIELD(value, reg, field)        \
 518         (((value) & PHM_FIELD_MASK(reg, field)) >>      \
 519          PHM_FIELD_SHIFT(reg, field))
 520
 521
 522 #define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask)        \
 523         phm_wait_on_register(hwmgr, index, value, mask)
 524
 525 #define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask)        \
 526         phm_wait_for_register_unequal(hwmgr, index, value, mask)
 527
 528 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
 529         phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
 530
 531 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
 532         phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask)
 533
 534 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)    \
 535         phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask)
 536
 537 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask)    \
 538         phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask)
 539
 540 /* Operations on named registers. */
 541
 542 #define PHM_WAIT_REGISTER(hwmgr, reg, value, mask)      \
 543         PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
 544
 545 #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask)      \
 546         PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
 547
 548 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)       \
 549         PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 550
 551 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)       \
 552         PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 553
 554 #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)  \
 555         PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 556
 557 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)  \
 558         PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 559
 560 /* Operations on named fields. */
 561
 562 #define PHM_READ_FIELD(device, reg, field)      \
 563         PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
 564
 565 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field)       \
 566         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 567                         reg, field)
 568
 569 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)  \
 570         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 571                         reg, field)
 572
 573 #define PHM_WRITE_FIELD(device, reg, field, fieldval)   \
 574         cgs_write_register(device, mm##reg, PHM_SET_FIELD(      \
 575                                 cgs_read_register(device, mm##reg), reg, field, fieldval))
 576
 577 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
 578         cgs_write_ind_register(device, port, ix##reg,   \
 579                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 580                                 reg, field, fieldval))
 581
 582 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)       \
 583         cgs_write_ind_register(device, port, ix##reg,   \
 584                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 585                                 reg, field, fieldval))
 586
 587 #define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval)     \
 588         PHM_WAIT_REGISTER(hwmgr, reg, (fieldval)        \
 589                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 590
 591 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)      \
 592         PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
 593                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 594
 595 #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
 596         PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval)    \
 597                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 598
 599 #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval)     \
 600         PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval)        \
 601                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 602
 603 #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)      \
 604         PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
 605                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 606
 607 #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
 608         PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval)    \
 609                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 610
 611 /* Operations on arrays of registers & fields. */
 612
 613 #define PHM_READ_ARRAY_REGISTER(device, reg, offset)    \
 614         cgs_read_register(device, mm##reg + (offset))
 615
 616 #define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value)    \
 617         cgs_write_register(device, mm##reg + (offset), value)
 618
 619 #define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask)        \
 620         PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
 621
 622 #define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask)        \
 623         PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
 624
 625 #define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \
 626         PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field)
 627
 628 #define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue)    \
 629         PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset,    \
 630                         PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset),      \
 631                                 reg, field, fieldvalue))
 632
 633 #define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue)     \
 634         PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset),        \
 635                         (fieldvalue) << PHM_FIELD_SHIFT(reg, field),    \
 636                         PHM_FIELD_MASK(reg, field))
 637
 638 #define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue)     \
 639         PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset),        \
 640                         (fieldvalue) << PHM_FIELD_SHIFT(reg, field),    \
 641                         PHM_FIELD_MASK(reg, field))
 642
 643 #endif /* _HWMGR_H_ */