drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _HWMGR_H_
  24 #define _HWMGR_H_
  25
  26 #include <linux/seq_file.h>
  27 #include "amd_powerplay.h"
  28 #include "pp_instance.h"
  29 #include "hardwaremanager.h"
  30 #include "pp_power_source.h"
  31 #include "hwmgr_ppt.h"
  32
  33 struct pp_instance;
  34 struct pp_hwmgr;
  35 struct pp_hw_power_state;
  36 struct pp_power_state;
  37 struct PP_VCEState;
  38
  39 enum PP_Result {
  40         PP_Result_TableImmediateExit = 0x13,
  41 };
  42
  43 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
  44 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
  45 #define PCIE_PERF_REQ_GEN1         2
  46 #define PCIE_PERF_REQ_GEN2         3
  47 #define PCIE_PERF_REQ_GEN3         4
  48
  49 enum PHM_BackEnd_Magic {
  50         PHM_Dummy_Magic       = 0xAA5555AA,
  51         PHM_RV770_Magic       = 0xDCBAABCD,
  52         PHM_Kong_Magic        = 0x239478DF,
  53         PHM_NIslands_Magic    = 0x736C494E,
  54         PHM_Sumo_Magic        = 0x8339FA11,
  55         PHM_SIslands_Magic    = 0x369431AC,
  56         PHM_Trinity_Magic     = 0x96751873,
  57         PHM_CIslands_Magic    = 0x38AC78B0,
  58         PHM_Kv_Magic          = 0xDCBBABC0,
  59         PHM_VIslands_Magic    = 0x20130307,
  60         PHM_Cz_Magic          = 0x67DCBA25
  61 };
  62
  63 enum PP_DAL_POWERLEVEL {
  64         PP_DAL_POWERLEVEL_INVALID = 0,
  65         PP_DAL_POWERLEVEL_ULTRALOW,
  66         PP_DAL_POWERLEVEL_LOW,
  67         PP_DAL_POWERLEVEL_NOMINAL,
  68         PP_DAL_POWERLEVEL_PERFORMANCE,
  69
  70         PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
  71         PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
  72         PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
  73         PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
  74         PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
  75         PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
  76         PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
  77         PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
  78 };
  79
  80 #define PHM_PCIE_POWERGATING_TARGET_GFX            0
  81 #define PHM_PCIE_POWERGATING_TARGET_DDI            1
  82 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
  83 #define PHM_PCIE_POWERGATING_TARGET_PHY            3
  84
  85 typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
  86                                   void *output, void *storage, int result);
  87
  88 typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
  89
  90 struct phm_set_power_state_input {
  91         const struct pp_hw_power_state *pcurrent_state;
  92         const struct pp_hw_power_state *pnew_state;
  93 };
  94
  95 struct phm_acp_arbiter {
  96         uint32_t acpclk;
  97 };
  98
  99 struct phm_uvd_arbiter {
 100         uint32_t vclk;
 101         uint32_t dclk;
 102         uint32_t vclk_ceiling;
 103         uint32_t dclk_ceiling;
 104 };
 105
 106 struct phm_vce_arbiter {
 107         uint32_t   evclk;
 108         uint32_t   ecclk;
 109 };
 110
 111 struct phm_gfx_arbiter {
 112         uint32_t sclk;
 113         uint32_t mclk;
 114         uint32_t sclk_over_drive;
 115         uint32_t mclk_over_drive;
 116         uint32_t sclk_threshold;
 117         uint32_t num_cus;
 118 };
 119
 120 /* Entries in the master tables */
 121 struct phm_master_table_item {
 122         phm_check_function isFunctionNeededInRuntimeTable;
 123         phm_table_function tableFunction;
 124 };
 125
 126 enum phm_master_table_flag {
 127         PHM_MasterTableFlag_None         = 0,
 128         PHM_MasterTableFlag_ExitOnError  = 1,
 129 };
 130
 131 /* The header of the master tables */
 132 struct phm_master_table_header {
 133         uint32_t storage_size;
 134         uint32_t flags;
 135         struct phm_master_table_item *master_list;
 136 };
 137
 138 struct phm_runtime_table_header {
 139         uint32_t storage_size;
 140         bool exit_error;
 141         phm_table_function *function_list;
 142 };
 143
 144 struct phm_clock_array {
 145         uint32_t count;
 146         uint32_t values[1];
 147 };
 148
 149 struct phm_clock_voltage_dependency_record {
 150         uint32_t clk;
 151         uint32_t v;
 152 };
 153
 154 struct phm_vceclock_voltage_dependency_record {
 155         uint32_t ecclk;
 156         uint32_t evclk;
 157         uint32_t v;
 158 };
 159
 160 struct phm_uvdclock_voltage_dependency_record {
 161         uint32_t vclk;
 162         uint32_t dclk;
 163         uint32_t v;
 164 };
 165
 166 struct phm_samuclock_voltage_dependency_record {
 167         uint32_t samclk;
 168         uint32_t v;
 169 };
 170
 171 struct phm_acpclock_voltage_dependency_record {
 172         uint32_t acpclk;
 173         uint32_t v;
 174 };
 175
 176 struct phm_clock_voltage_dependency_table {
 177         uint32_t count;                                                                         /* Number of entries. */
 178         struct phm_clock_voltage_dependency_record entries[1];          /* Dynamically allocate count entries. */
 179 };
 180
 181 struct phm_phase_shedding_limits_record {
 182         uint32_t  Voltage;
 183         uint32_t    Sclk;
 184         uint32_t    Mclk;
 185 };
 186
 187
 188 extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
 189                               struct phm_runtime_table_header *rt_table,
 190                               void *input, void *output);
 191
 192 extern int phm_construct_table(struct pp_hwmgr *hwmgr,
 193                                struct phm_master_table_header *master_table,
 194                                struct phm_runtime_table_header *rt_table);
 195
 196 extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
 197                              struct phm_runtime_table_header *rt_table);
 198
 199
 200 struct phm_uvd_clock_voltage_dependency_record {
 201         uint32_t vclk;
 202         uint32_t dclk;
 203         uint32_t v;
 204 };
 205
 206 struct phm_uvd_clock_voltage_dependency_table {
 207         uint8_t count;
 208         struct phm_uvd_clock_voltage_dependency_record entries[1];
 209 };
 210
 211 struct phm_acp_clock_voltage_dependency_record {
 212         uint32_t acpclk;
 213         uint32_t v;
 214 };
 215
 216 struct phm_acp_clock_voltage_dependency_table {
 217         uint32_t count;
 218         struct phm_acp_clock_voltage_dependency_record entries[1];
 219 };
 220
 221 struct phm_vce_clock_voltage_dependency_record {
 222         uint32_t ecclk;
 223         uint32_t evclk;
 224         uint32_t v;
 225 };
 226
 227 struct phm_phase_shedding_limits_table {
 228         uint32_t                           count;
 229         struct phm_phase_shedding_limits_record  entries[1];
 230 };
 231
 232 struct phm_vceclock_voltage_dependency_table {
 233         uint8_t count;                                    /* Number of entries. */
 234         struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 235 };
 236
 237 struct phm_uvdclock_voltage_dependency_table {
 238         uint8_t count;                                    /* Number of entries. */
 239         struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 240 };
 241
 242 struct phm_samuclock_voltage_dependency_table {
 243         uint8_t count;                                    /* Number of entries. */
 244         struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 245 };
 246
 247 struct phm_acpclock_voltage_dependency_table {
 248         uint32_t count;                                    /* Number of entries. */
 249         struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 250 };
 251
 252 struct phm_vce_clock_voltage_dependency_table {
 253         uint8_t count;
 254         struct phm_vce_clock_voltage_dependency_record entries[1];
 255 };
 256
 257 struct pp_hwmgr_func {
 258         int (*backend_init)(struct pp_hwmgr *hw_mgr);
 259         int (*backend_fini)(struct pp_hwmgr *hw_mgr);
 260         int (*asic_setup)(struct pp_hwmgr *hw_mgr);
 261         int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
 262
 263         int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
 264                                 struct pp_power_state  *prequest_ps,
 265                         const struct pp_power_state *pcurrent_ps);
 266
 267         int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
 268                                         enum amd_dpm_forced_level level);
 269
 270         int (*dynamic_state_management_enable)(
 271                                                 struct pp_hwmgr *hw_mgr);
 272
 273         int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
 274                                      struct pp_hw_power_state *hw_ps);
 275
 276         int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
 277                             unsigned long, struct pp_power_state *);
 278
 279         int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
 280         int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
 281         int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
 282         int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
 283         int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
 284         int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
 285         int (*power_state_set)(struct pp_hwmgr *hwmgr,
 286                                                 const void *state);
 287         void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr,
 288                                                         struct seq_file *m);
 289         int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 290 };
 291
 292 struct pp_table_func {
 293         int (*pptable_init)(struct pp_hwmgr *hw_mgr);
 294         int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
 295         int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
 296         int (*pptable_get_vce_state_table_entry)(
 297                                                 struct pp_hwmgr *hwmgr,
 298                                                 unsigned long i,
 299                                                 struct PP_VCEState *vce_state,
 300                                                 void **clock_info,
 301                                                 unsigned long *flag);
 302 };
 303
 304 union phm_cac_leakage_record {
 305         struct {
 306                 uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
 307                 uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
 308         };
 309         struct {
 310                 uint16_t Vddc1;
 311                 uint16_t Vddc2;
 312                 uint16_t Vddc3;
 313         };
 314 };
 315
 316 struct phm_cac_leakage_table {
 317         uint32_t count;
 318         union phm_cac_leakage_record entries[1];
 319 };
 320
 321 struct phm_samu_clock_voltage_dependency_record {
 322         uint32_t samclk;
 323         uint32_t v;
 324 };
 325
 326
 327 struct phm_samu_clock_voltage_dependency_table {
 328         uint8_t count;
 329         struct phm_samu_clock_voltage_dependency_record entries[1];
 330 };
 331
 332 struct phm_cac_tdp_table {
 333         uint16_t usTDP;
 334         uint16_t usConfigurableTDP;
 335         uint16_t usTDC;
 336         uint16_t usBatteryPowerLimit;
 337         uint16_t usSmallPowerLimit;
 338         uint16_t usLowCACLeakage;
 339         uint16_t usHighCACLeakage;
 340         uint16_t usMaximumPowerDeliveryLimit;
 341         uint16_t usOperatingTempMinLimit;
 342         uint16_t usOperatingTempMaxLimit;
 343         uint16_t usOperatingTempStep;
 344         uint16_t usOperatingTempHyst;
 345         uint16_t usDefaultTargetOperatingTemp;
 346         uint16_t usTargetOperatingTemp;
 347         uint16_t usPowerTuneDataSetID;
 348         uint16_t usSoftwareShutdownTemp;
 349         uint16_t usClockStretchAmount;
 350         uint16_t usTemperatureLimitHotspot;
 351         uint16_t usTemperatureLimitLiquid1;
 352         uint16_t usTemperatureLimitLiquid2;
 353         uint16_t usTemperatureLimitVrVddc;
 354         uint16_t usTemperatureLimitVrMvdd;
 355         uint16_t usTemperatureLimitPlx;
 356         uint8_t  ucLiquid1_I2C_address;
 357         uint8_t  ucLiquid2_I2C_address;
 358         uint8_t  ucLiquid_I2C_Line;
 359         uint8_t  ucVr_I2C_address;
 360         uint8_t  ucVr_I2C_Line;
 361         uint8_t  ucPlx_I2C_address;
 362         uint8_t  ucPlx_I2C_Line;
 363 };
 364
 365 struct phm_ppm_table {
 366         uint8_t   ppm_design;
 367         uint16_t  cpu_core_number;
 368         uint32_t  platform_tdp;
 369         uint32_t  small_ac_platform_tdp;
 370         uint32_t  platform_tdc;
 371         uint32_t  small_ac_platform_tdc;
 372         uint32_t  apu_tdp;
 373         uint32_t  dgpu_tdp;
 374         uint32_t  dgpu_ulv_power;
 375         uint32_t  tj_max;
 376 };
 377
 378 struct phm_vq_budgeting_record {
 379         uint32_t ulCUs;
 380         uint32_t ulSustainableSOCPowerLimitLow;
 381         uint32_t ulSustainableSOCPowerLimitHigh;
 382         uint32_t ulMinSclkLow;
 383         uint32_t ulMinSclkHigh;
 384         uint8_t  ucDispConfig;
 385         uint32_t ulDClk;
 386         uint32_t ulEClk;
 387         uint32_t ulSustainableSclk;
 388         uint32_t ulSustainableCUs;
 389 };
 390
 391 struct phm_vq_budgeting_table {
 392         uint8_t numEntries;
 393         struct phm_vq_budgeting_record entries[1];
 394 };
 395
 396 struct phm_clock_and_voltage_limits {
 397         uint32_t sclk;
 398         uint32_t mclk;
 399         uint16_t vddc;
 400         uint16_t vddci;
 401         uint16_t vddgfx;
 402 };
 403
 404 /* Structure to hold PPTable information */
 405
 406 struct phm_ppt_v1_information {
 407         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
 408         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
 409         struct phm_clock_array *valid_sclk_values;
 410         struct phm_clock_array *valid_mclk_values;
 411         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
 412         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
 413         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 414         struct phm_ppm_table *ppm_parameter_table;
 415         struct phm_cac_tdp_table *cac_dtp_table;
 416         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
 417         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 418         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
 419         struct phm_ppt_v1_pcie_table *pcie_table;
 420         uint16_t us_ulv_voltage_offset;
 421 };
 422
 423 struct phm_dynamic_state_info {
 424         struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
 425         struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
 426         struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
 427         struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
 428         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 429         struct phm_clock_array                    *valid_sclk_values;
 430         struct phm_clock_array                    *valid_mclk_values;
 431         struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
 432         struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
 433         uint32_t                                  mclk_sclk_ratio;
 434         uint32_t                                  sclk_mclk_delta;
 435         uint32_t                                  vddc_vddci_delta;
 436         uint32_t                                  min_vddc_for_pcie_gen2;
 437         struct phm_cac_leakage_table              *cac_leakage_table;
 438         struct phm_phase_shedding_limits_table    *vddc_phase_shed_limits_table;
 439
 440         struct phm_vce_clock_voltage_dependency_table
 441                                             *vce_clocl_voltage_dependency_table;
 442         struct phm_uvd_clock_voltage_dependency_table
 443                                             *uvd_clocl_voltage_dependency_table;
 444         struct phm_acp_clock_voltage_dependency_table
 445                                             *acp_clock_voltage_dependency_table;
 446         struct phm_samu_clock_voltage_dependency_table
 447                                            *samu_clock_voltage_dependency_table;
 448
 449         struct phm_ppm_table                          *ppm_parameter_table;
 450         struct phm_cac_tdp_table                      *cac_dtp_table;
 451         struct phm_clock_voltage_dependency_table         *vdd_gfx_dependency_on_sclk;
 452         struct phm_vq_budgeting_table                             *vq_budgeting_table;
 453 };
 454
 455 struct pp_fan_info {
 456         bool bNoFan;
 457         uint8_t   ucTachometerPulsesPerRevolution;
 458         uint32_t   ulMinRPM;
 459         uint32_t   ulMaxRPM;
 460 };
 461
 462 struct pp_advance_fan_control_parameters {
 463         uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
 464         uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
 465         uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
 466         uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
 467         uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
 468         uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
 469         uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
 470         uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
 471         uint16_t  usTMax;                          /* The max temperature */
 472         uint8_t   ucFanControlMode;
 473         uint16_t  usFanPWMMinLimit;
 474         uint16_t  usFanPWMMaxLimit;
 475         uint16_t  usFanPWMStep;
 476         uint16_t  usDefaultMaxFanPWM;
 477         uint16_t  usFanOutputSensitivity;
 478         uint16_t  usDefaultFanOutputSensitivity;
 479         uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
 480         uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
 481         uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
 482         uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
 483         uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
 484         uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
 485         uint16_t  usFanCurrentLow;                 /* Low current */
 486         uint16_t  usFanCurrentHigh;                /* High current */
 487         uint16_t  usFanRPMLow;                     /* Low RPM */
 488         uint16_t  usFanRPMHigh;                    /* High RPM */
 489         uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
 490         uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
 491         uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
 492         uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
 493         uint16_t  usFanGainHotspot;
 494         uint16_t  usFanGainLiquid;
 495         uint16_t  usFanGainVrVddc;
 496         uint16_t  usFanGainVrMvdd;
 497         uint16_t  usFanGainPlx;
 498         uint16_t  usFanGainHbm;
 499 };
 500
 501 struct pp_thermal_controller_info {
 502         uint8_t ucType;
 503         uint8_t ucI2cLine;
 504         uint8_t ucI2cAddress;
 505         struct pp_fan_info fanInfo;
 506         struct pp_advance_fan_control_parameters advanceFanControlParameters;
 507 };
 508
 509 struct phm_microcode_version_info {
 510         uint32_t SMC;
 511         uint32_t DMCU;
 512         uint32_t MC;
 513         uint32_t NB;
 514 };
 515
 516 /**
 517  * The main hardware manager structure.
 518  */
 519 struct pp_hwmgr {
 520         uint32_t chip_family;
 521         uint32_t chip_id;
 522         uint32_t hw_revision;
 523         uint32_t sub_sys_id;
 524         uint32_t sub_vendor_id;
 525
 526         void *device;
 527         struct pp_smumgr *smumgr;
 528         const void *soft_pp_table;
 529         enum amd_dpm_forced_level dpm_level;
 530         bool block_hw_access;
 531         struct phm_gfx_arbiter gfx_arbiter;
 532         struct phm_acp_arbiter acp_arbiter;
 533         struct phm_uvd_arbiter uvd_arbiter;
 534         struct phm_vce_arbiter vce_arbiter;
 535         uint32_t usec_timeout;
 536         void *pptable;
 537         struct phm_platform_descriptor platform_descriptor;
 538         void *backend;
 539         enum PP_DAL_POWERLEVEL  dal_power_level;
 540         struct phm_dynamic_state_info dyn_state;
 541         struct phm_runtime_table_header setup_asic;
 542         struct phm_runtime_table_header disable_dynamic_state_management;
 543         struct phm_runtime_table_header enable_dynamic_state_management;
 544         struct phm_runtime_table_header set_power_state;
 545         struct phm_runtime_table_header enable_clock_power_gatings;
 546         const struct pp_hwmgr_func *hwmgr_func;
 547         const struct pp_table_func *pptable_func;
 548         struct pp_power_state    *ps;
 549         enum pp_power_source  power_source;
 550         uint32_t num_ps;
 551         struct pp_thermal_controller_info thermal_controller;
 552         struct phm_microcode_version_info microcode_version_info;
 553         uint32_t ps_size;
 554         struct pp_power_state    *current_ps;
 555         struct pp_power_state    *request_ps;
 556         struct pp_power_state    *boot_ps;
 557         struct pp_power_state    *uvd_ps;
 558 };
 559
 560
 561 extern int hwmgr_init(struct amd_pp_init *pp_init,
 562                       struct pp_instance *handle);
 563
 564 extern int hwmgr_fini(struct pp_hwmgr *hwmgr);
 565
 566 extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr);
 567
 568 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
 569                                 uint32_t value, uint32_t mask);
 570
 571 extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
 572                                 uint32_t index, uint32_t value, uint32_t mask);
 573
 574 extern uint32_t phm_read_indirect_register(struct pp_hwmgr *hwmgr,
 575                 uint32_t indirect_port, uint32_t index);
 576
 577 extern void phm_write_indirect_register(struct pp_hwmgr *hwmgr,
 578                 uint32_t indirect_port,
 579                 uint32_t index,
 580                 uint32_t value);
 581
 582 extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
 583                                 uint32_t indirect_port,
 584                                 uint32_t index,
 585                                 uint32_t value,
 586                                 uint32_t mask);
 587
 588 extern void phm_wait_for_indirect_register_unequal(
 589                                 struct pp_hwmgr *hwmgr,
 590                                 uint32_t indirect_port,
 591                                 uint32_t index,
 592                                 uint32_t value,
 593                                 uint32_t mask);
 594
 595 bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
 596 bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
 597
 598 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
 599
 600 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
 601 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
 602
 603 #define PHM_SET_FIELD(origval, reg, field, fieldval)    \
 604         (((origval) & ~PHM_FIELD_MASK(reg, field)) |    \
 605          (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
 606
 607 #define PHM_GET_FIELD(value, reg, field)        \
 608         (((value) & PHM_FIELD_MASK(reg, field)) >>      \
 609          PHM_FIELD_SHIFT(reg, field))
 610
 611
 612 #define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask)        \
 613         phm_wait_on_register(hwmgr, index, value, mask)
 614
 615 #define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask)        \
 616         phm_wait_for_register_unequal(hwmgr, index, value, mask)
 617
 618 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
 619         phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
 620
 621 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
 622         phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask)
 623
 624 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)    \
 625         phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask)
 626
 627 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask)    \
 628         phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask)
 629
 630 /* Operations on named registers. */
 631
 632 #define PHM_WAIT_REGISTER(hwmgr, reg, value, mask)      \
 633         PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
 634
 635 #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask)      \
 636         PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
 637
 638 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)       \
 639         PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 640
 641 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)       \
 642         PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 643
 644 #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)  \
 645         PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 646
 647 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)  \
 648         PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 649
 650 /* Operations on named fields. */
 651
 652 #define PHM_READ_FIELD(device, reg, field)      \
 653         PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
 654
 655 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field)       \
 656         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 657                         reg, field)
 658
 659 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)  \
 660         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 661                         reg, field)
 662
 663 #define PHM_WRITE_FIELD(device, reg, field, fieldval)   \
 664         cgs_write_register(device, mm##reg, PHM_SET_FIELD(      \
 665                                 cgs_read_register(device, mm##reg), reg, field, fieldval))
 666
 667 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
 668         cgs_write_ind_register(device, port, ix##reg,   \
 669                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 670                                 reg, field, fieldval))
 671
 672 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)       \
 673         cgs_write_ind_register(device, port, ix##reg,   \
 674                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 675                                 reg, field, fieldval))
 676
 677 #define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval)     \
 678         PHM_WAIT_REGISTER(hwmgr, reg, (fieldval)        \
 679                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 680
 681 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)      \
 682         PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
 683                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 684
 685 #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
 686         PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval)    \
 687                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 688
 689 #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval)     \
 690         PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval)        \
 691                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 692
 693 #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)      \
 694         PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
 695                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 696
 697 #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
 698         PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval)    \
 699                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 700
 701 /* Operations on arrays of registers & fields. */
 702
 703 #define PHM_READ_ARRAY_REGISTER(device, reg, offset)    \
 704         cgs_read_register(device, mm##reg + (offset))
 705
 706 #define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value)    \
 707         cgs_write_register(device, mm##reg + (offset), value)
 708
 709 #define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask)        \
 710         PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
 711
 712 #define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask)        \
 713         PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
 714
 715 #define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \
 716         PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field)
 717
 718 #define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue)    \
 719         PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset,    \
 720                         PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset),      \
 721                                 reg, field, fieldvalue))
 722
 723 #define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue)     \
 724         PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset),        \
 725                         (fieldvalue) << PHM_FIELD_SHIFT(reg, field),    \
 726                         PHM_FIELD_MASK(reg, field))
 727
 728 #define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue)     \
 729         PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset),        \
 730                         (fieldvalue) << PHM_FIELD_SHIFT(reg, field),    \
 731                         PHM_FIELD_MASK(reg, field))
 732
 733 #endif /* _HWMGR_H_ */