drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include "pp_instance.h"
  27 #include "smumgr.h"
  28 #include "cgs_common.h"
  29 #include "linux/delay.h"
  30 #include "cz_smumgr.h"
  31
  32 int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
  33 {
  34         struct pp_smumgr *smumgr;
  35
  36         if ((handle == NULL) || (pp_init == NULL))
  37                 return -EINVAL;
  38
  39         smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
  40         if (smumgr == NULL)
  41                 return -ENOMEM;
  42
  43         smumgr->device = pp_init->device;
  44         smumgr->chip_family = pp_init->chip_family;
  45         smumgr->chip_id = pp_init->chip_id;
  46         smumgr->hw_revision = pp_init->rev_id;
  47         smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
  48         smumgr->reload_fw = 1;
  49         handle->smu_mgr = smumgr;
  50
  51         switch (smumgr->chip_family) {
  52         case AMD_FAMILY_CZ:
  53                 cz_smum_init(smumgr);
  54                 break;
  55         case AMD_FAMILY_VI:
  56                 /* TODO */
  57                 break;
  58         default:
  59                 kfree(smumgr);
  60                 return -EINVAL;
  61         }
  62
  63         return 0;
  64 }
  65
  66 int smum_fini(struct pp_smumgr *smumgr)
  67 {
  68         kfree(smumgr);
  69         return 0;
  70 }
  71
  72 int smum_get_argument(struct pp_smumgr *smumgr)
  73 {
  74         if (NULL != smumgr->smumgr_funcs->get_argument)
  75                 return smumgr->smumgr_funcs->get_argument(smumgr);
  76
  77         return 0;
  78 }
  79
  80 int smum_download_powerplay_table(struct pp_smumgr *smumgr,
  81                                                                 void **table)
  82 {
  83         if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
  84                 return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
  85                                                                         table);
  86
  87         return 0;
  88 }
  89
  90 int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
  91 {
  92         if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
  93                 return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
  94
  95         return 0;
  96 }
  97
  98 int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
  99 {
 100         if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
 101                 return -EINVAL;
 102
 103         return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
 104 }
 105
 106 int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
 107                                         uint16_t msg, uint32_t parameter)
 108 {
 109         if (smumgr == NULL ||
 110                 smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
 111                 return -EINVAL;
 112         return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
 113                                                 smumgr, msg, parameter);
 114 }
 115
 116 /*
 117  * Returns once the part of the register indicated by the mask has
 118  * reached the given value.
 119  */
 120 int smum_wait_on_register(struct pp_smumgr *smumgr,
 121                                 uint32_t index,
 122                                 uint32_t value, uint32_t mask)
 123 {
 124         uint32_t i;
 125         uint32_t cur_value;
 126
 127         if (smumgr == NULL || smumgr->device == NULL)
 128                 return -EINVAL;
 129
 130         for (i = 0; i < smumgr->usec_timeout; i++) {
 131                 cur_value = cgs_read_register(smumgr->device, index);
 132                 if ((cur_value & mask) == (value & mask))
 133                         break;
 134                 udelay(1);
 135         }
 136
 137         /* timeout means wrong logic*/
 138         if (i == smumgr->usec_timeout)
 139                 return -1;
 140
 141         return 0;
 142 }
 143
 144 int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
 145                                         uint32_t index,
 146                                         uint32_t value, uint32_t mask)
 147 {
 148         uint32_t i;
 149         uint32_t cur_value;
 150
 151         if (smumgr == NULL)
 152                 return -EINVAL;
 153
 154         for (i = 0; i < smumgr->usec_timeout; i++) {
 155                 cur_value = cgs_read_register(smumgr->device,
 156                                                                         index);
 157                 if ((cur_value & mask) != (value & mask))
 158                         break;
 159                 udelay(1);
 160         }
 161
 162         /* timeout means wrong logic */
 163         if (i == smumgr->usec_timeout)
 164                 return -1;
 165
 166         return 0;
 167 }
 168
 169
 170 /*
 171  * Returns once the part of the register indicated by the mask
 172  * has reached the given value.The indirect space is described by
 173  * giving the memory-mapped index of the indirect index register.
 174  */
 175 int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
 176                                         uint32_t indirect_port,
 177                                         uint32_t index,
 178                                         uint32_t value,
 179                                         uint32_t mask)
 180 {
 181         if (smumgr == NULL || smumgr->device == NULL)
 182                 return -EINVAL;
 183
 184         cgs_write_register(smumgr->device, indirect_port, index);
 185         return smum_wait_on_register(smumgr, indirect_port + 1,
 186                                                 mask, value);
 187 }
 188
 189 void smum_wait_for_indirect_register_unequal(
 190                                                 struct pp_smumgr *smumgr,
 191                                                 uint32_t indirect_port,
 192                                                 uint32_t index,
 193                                                 uint32_t value,
 194                                                 uint32_t mask)
 195 {
 196         if (smumgr == NULL || smumgr->device == NULL)
 197                 return;
 198         cgs_write_register(smumgr->device, indirect_port, index);
 199         smum_wait_for_register_unequal(smumgr, indirect_port + 1,
 200                                                 value, mask);
 201 }
 202
 203 int smu_allocate_memory(void *device, uint32_t size,
 204                          enum cgs_gpu_mem_type type,
 205                          uint32_t byte_align, uint64_t *mc_addr,
 206                          void **kptr, void *handle)
 207 {
 208         int ret = 0;
 209         cgs_handle_t cgs_handle;
 210
 211         if (device == NULL || handle == NULL ||
 212             mc_addr == NULL || kptr == NULL)
 213                 return -EINVAL;
 214
 215         ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
 216                                 0, 0, (cgs_handle_t *)handle);
 217         if (ret)
 218                 return -ENOMEM;
 219
 220         cgs_handle = *(cgs_handle_t *)handle;
 221
 222         ret = cgs_gmap_gpu_mem(device, cgs_handle, mc_addr);
 223         if (ret)
 224                 goto error_gmap;
 225
 226         ret = cgs_kmap_gpu_mem(device, cgs_handle, kptr);
 227         if (ret)
 228                 goto error_kmap;
 229
 230         return 0;
 231
 232 error_kmap:
 233         cgs_gunmap_gpu_mem(device, cgs_handle);
 234
 235 error_gmap:
 236         cgs_free_gpu_mem(device, cgs_handle);
 237         return ret;
 238 }
 239
 240 int smu_free_memory(void *device, void *handle)
 241 {
 242         cgs_handle_t cgs_handle = (cgs_handle_t)handle;
 243
 244         if (device == NULL || handle == NULL)
 245                 return -EINVAL;
 246
 247         cgs_kunmap_gpu_mem(device, cgs_handle);
 248         cgs_gunmap_gpu_mem(device, cgs_handle);
 249         cgs_free_gpu_mem(device, cgs_handle);
 250
 251         return 0;
 252 }