2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
9 * Implementation of a CRTC class for the HDLCD driver.
13 #include <drm/drm_atomic_helper.h>
14 #include <drm/drm_crtc.h>
15 #include <drm/drm_crtc_helper.h>
16 #include <drm/drm_fb_helper.h>
17 #include <drm/drm_fb_cma_helper.h>
18 #include <drm/drm_gem_cma_helper.h>
19 #include <drm/drm_of.h>
20 #include <drm/drm_plane_helper.h>
21 #include <linux/clk.h>
22 #include <linux/of_graph.h>
23 #include <linux/platform_data/simplefb.h>
24 #include <video/videomode.h>
26 #include "hdlcd_drv.h"
27 #include "hdlcd_regs.h"
30 * The HDLCD controller is a dumb RGB streamer that gets connected to
31 * a single HDMI transmitter or in the case of the ARM Models it gets
32 * emulated by the software that does the actual rendering.
36 static void hdlcd_crtc_cleanup(struct drm_crtc
*crtc
)
38 struct hdlcd_drm_private
*hdlcd
= crtc_to_hdlcd_priv(crtc
);
40 /* stop the controller on cleanup */
41 hdlcd_write(hdlcd
, HDLCD_REG_COMMAND
, 0);
42 drm_crtc_cleanup(crtc
);
45 static const struct drm_crtc_funcs hdlcd_crtc_funcs
= {
46 .destroy
= hdlcd_crtc_cleanup
,
47 .set_config
= drm_atomic_helper_set_config
,
48 .page_flip
= drm_atomic_helper_page_flip
,
49 .reset
= drm_atomic_helper_crtc_reset
,
50 .atomic_duplicate_state
= drm_atomic_helper_crtc_duplicate_state
,
51 .atomic_destroy_state
= drm_atomic_helper_crtc_destroy_state
,
54 static struct simplefb_format supported_formats
[] = SIMPLEFB_FORMATS
;
57 * Setup the HDLCD registers for decoding the pixels out of the framebuffer
59 static int hdlcd_set_pxl_fmt(struct drm_crtc
*crtc
)
62 struct hdlcd_drm_private
*hdlcd
= crtc_to_hdlcd_priv(crtc
);
63 uint32_t pixel_format
;
64 struct simplefb_format
*format
= NULL
;
67 pixel_format
= crtc
->primary
->state
->fb
->pixel_format
;
69 for (i
= 0; i
< ARRAY_SIZE(supported_formats
); i
++) {
70 if (supported_formats
[i
].fourcc
== pixel_format
)
71 format
= &supported_formats
[i
];
77 /* HDLCD uses 'bytes per pixel', zero means 1 byte */
78 btpp
= (format
->bits_per_pixel
+ 7) / 8;
79 hdlcd_write(hdlcd
, HDLCD_REG_PIXEL_FORMAT
, (btpp
- 1) << 3);
82 * The format of the HDLCD_REG_<color>_SELECT register is:
83 * - bits[23:16] - default value for that color component
84 * - bits[11:8] - number of bits to extract for each color component
85 * - bits[4:0] - index of the lowest bit to extract
87 * The default color value is used when bits[11:8] are zero, when the
88 * pixel is outside the visible frame area or when there is a
91 hdlcd_write(hdlcd
, HDLCD_REG_RED_SELECT
, format
->red
.offset
|
92 #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN
93 0x00ff0000 | /* show underruns in red */
95 ((format
->red
.length
& 0xf) << 8));
96 hdlcd_write(hdlcd
, HDLCD_REG_GREEN_SELECT
, format
->green
.offset
|
97 ((format
->green
.length
& 0xf) << 8));
98 hdlcd_write(hdlcd
, HDLCD_REG_BLUE_SELECT
, format
->blue
.offset
|
99 ((format
->blue
.length
& 0xf) << 8));
104 static void hdlcd_crtc_mode_set_nofb(struct drm_crtc
*crtc
)
106 struct hdlcd_drm_private
*hdlcd
= crtc_to_hdlcd_priv(crtc
);
107 struct drm_display_mode
*m
= &crtc
->state
->adjusted_mode
;
109 unsigned int polarities
, err
;
111 vm
.vfront_porch
= m
->crtc_vsync_start
- m
->crtc_vdisplay
;
112 vm
.vback_porch
= m
->crtc_vtotal
- m
->crtc_vsync_end
;
113 vm
.vsync_len
= m
->crtc_vsync_end
- m
->crtc_vsync_start
;
114 vm
.hfront_porch
= m
->crtc_hsync_start
- m
->crtc_hdisplay
;
115 vm
.hback_porch
= m
->crtc_htotal
- m
->crtc_hsync_end
;
116 vm
.hsync_len
= m
->crtc_hsync_end
- m
->crtc_hsync_start
;
118 polarities
= HDLCD_POLARITY_DATAEN
| HDLCD_POLARITY_DATA
;
120 if (m
->flags
& DRM_MODE_FLAG_PHSYNC
)
121 polarities
|= HDLCD_POLARITY_HSYNC
;
122 if (m
->flags
& DRM_MODE_FLAG_PVSYNC
)
123 polarities
|= HDLCD_POLARITY_VSYNC
;
125 /* Allow max number of outstanding requests and largest burst size */
126 hdlcd_write(hdlcd
, HDLCD_REG_BUS_OPTIONS
,
127 HDLCD_BUS_MAX_OUTSTAND
| HDLCD_BUS_BURST_16
);
129 hdlcd_write(hdlcd
, HDLCD_REG_V_DATA
, m
->crtc_vdisplay
- 1);
130 hdlcd_write(hdlcd
, HDLCD_REG_V_BACK_PORCH
, vm
.vback_porch
- 1);
131 hdlcd_write(hdlcd
, HDLCD_REG_V_FRONT_PORCH
, vm
.vfront_porch
- 1);
132 hdlcd_write(hdlcd
, HDLCD_REG_V_SYNC
, vm
.vsync_len
- 1);
133 hdlcd_write(hdlcd
, HDLCD_REG_H_DATA
, m
->crtc_hdisplay
- 1);
134 hdlcd_write(hdlcd
, HDLCD_REG_H_BACK_PORCH
, vm
.hback_porch
- 1);
135 hdlcd_write(hdlcd
, HDLCD_REG_H_FRONT_PORCH
, vm
.hfront_porch
- 1);
136 hdlcd_write(hdlcd
, HDLCD_REG_H_SYNC
, vm
.hsync_len
- 1);
137 hdlcd_write(hdlcd
, HDLCD_REG_POLARITIES
, polarities
);
139 err
= hdlcd_set_pxl_fmt(crtc
);
143 clk_set_rate(hdlcd
->clk
, m
->crtc_clock
* 1000);
146 static void hdlcd_crtc_enable(struct drm_crtc
*crtc
)
148 struct hdlcd_drm_private
*hdlcd
= crtc_to_hdlcd_priv(crtc
);
150 clk_prepare_enable(hdlcd
->clk
);
151 hdlcd_crtc_mode_set_nofb(crtc
);
152 hdlcd_write(hdlcd
, HDLCD_REG_COMMAND
, 1);
155 static void hdlcd_crtc_disable(struct drm_crtc
*crtc
)
157 struct hdlcd_drm_private
*hdlcd
= crtc_to_hdlcd_priv(crtc
);
159 if (!crtc
->state
->active
)
162 hdlcd_write(hdlcd
, HDLCD_REG_COMMAND
, 0);
163 clk_disable_unprepare(hdlcd
->clk
);
166 static int hdlcd_crtc_atomic_check(struct drm_crtc
*crtc
,
167 struct drm_crtc_state
*state
)
169 struct hdlcd_drm_private
*hdlcd
= crtc_to_hdlcd_priv(crtc
);
170 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
171 long rate
, clk_rate
= mode
->clock
* 1000;
173 rate
= clk_round_rate(hdlcd
->clk
, clk_rate
);
174 if (rate
!= clk_rate
) {
175 /* clock required by mode not supported by hardware */
182 static void hdlcd_crtc_atomic_begin(struct drm_crtc
*crtc
,
183 struct drm_crtc_state
*state
)
185 struct drm_pending_vblank_event
*event
= crtc
->state
->event
;
188 crtc
->state
->event
= NULL
;
190 spin_lock_irq(&crtc
->dev
->event_lock
);
191 if (drm_crtc_vblank_get(crtc
) == 0)
192 drm_crtc_arm_vblank_event(crtc
, event
);
194 drm_crtc_send_vblank_event(crtc
, event
);
195 spin_unlock_irq(&crtc
->dev
->event_lock
);
199 static void hdlcd_crtc_atomic_flush(struct drm_crtc
*crtc
,
200 struct drm_crtc_state
*state
)
204 static bool hdlcd_crtc_mode_fixup(struct drm_crtc
*crtc
,
205 const struct drm_display_mode
*mode
,
206 struct drm_display_mode
*adjusted_mode
)
211 static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs
= {
212 .mode_fixup
= hdlcd_crtc_mode_fixup
,
213 .mode_set
= drm_helper_crtc_mode_set
,
214 .mode_set_base
= drm_helper_crtc_mode_set_base
,
215 .mode_set_nofb
= hdlcd_crtc_mode_set_nofb
,
216 .enable
= hdlcd_crtc_enable
,
217 .disable
= hdlcd_crtc_disable
,
218 .prepare
= hdlcd_crtc_disable
,
219 .commit
= hdlcd_crtc_enable
,
220 .atomic_check
= hdlcd_crtc_atomic_check
,
221 .atomic_begin
= hdlcd_crtc_atomic_begin
,
222 .atomic_flush
= hdlcd_crtc_atomic_flush
,
225 static int hdlcd_plane_atomic_check(struct drm_plane
*plane
,
226 struct drm_plane_state
*state
)
230 src_w
= state
->src_w
>> 16;
231 src_h
= state
->src_h
>> 16;
233 /* we can't do any scaling of the plane source */
234 if ((src_w
!= state
->crtc_w
) || (src_h
!= state
->crtc_h
))
240 static void hdlcd_plane_atomic_update(struct drm_plane
*plane
,
241 struct drm_plane_state
*state
)
243 struct hdlcd_drm_private
*hdlcd
;
244 struct drm_gem_cma_object
*gem
;
245 unsigned int depth
, bpp
;
246 u32 src_w
, src_h
, dest_w
, dest_h
;
247 dma_addr_t scanout_start
;
249 if (!plane
->state
->fb
)
252 drm_fb_get_bpp_depth(plane
->state
->fb
->pixel_format
, &depth
, &bpp
);
253 src_w
= plane
->state
->src_w
>> 16;
254 src_h
= plane
->state
->src_h
>> 16;
255 dest_w
= plane
->state
->crtc_w
;
256 dest_h
= plane
->state
->crtc_h
;
257 gem
= drm_fb_cma_get_gem_obj(plane
->state
->fb
, 0);
258 scanout_start
= gem
->paddr
+ plane
->state
->fb
->offsets
[0] +
259 plane
->state
->crtc_y
* plane
->state
->fb
->pitches
[0] +
260 plane
->state
->crtc_x
* bpp
/ 8;
262 hdlcd
= plane
->dev
->dev_private
;
263 hdlcd_write(hdlcd
, HDLCD_REG_FB_LINE_LENGTH
, plane
->state
->fb
->pitches
[0]);
264 hdlcd_write(hdlcd
, HDLCD_REG_FB_LINE_PITCH
, plane
->state
->fb
->pitches
[0]);
265 hdlcd_write(hdlcd
, HDLCD_REG_FB_LINE_COUNT
, dest_h
- 1);
266 hdlcd_write(hdlcd
, HDLCD_REG_FB_BASE
, scanout_start
);
269 static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs
= {
270 .atomic_check
= hdlcd_plane_atomic_check
,
271 .atomic_update
= hdlcd_plane_atomic_update
,
274 static void hdlcd_plane_destroy(struct drm_plane
*plane
)
276 drm_plane_helper_disable(plane
);
277 drm_plane_cleanup(plane
);
280 static const struct drm_plane_funcs hdlcd_plane_funcs
= {
281 .update_plane
= drm_atomic_helper_update_plane
,
282 .disable_plane
= drm_atomic_helper_disable_plane
,
283 .destroy
= hdlcd_plane_destroy
,
284 .reset
= drm_atomic_helper_plane_reset
,
285 .atomic_duplicate_state
= drm_atomic_helper_plane_duplicate_state
,
286 .atomic_destroy_state
= drm_atomic_helper_plane_destroy_state
,
289 static struct drm_plane
*hdlcd_plane_init(struct drm_device
*drm
)
291 struct hdlcd_drm_private
*hdlcd
= drm
->dev_private
;
292 struct drm_plane
*plane
= NULL
;
293 u32 formats
[ARRAY_SIZE(supported_formats
)], i
;
296 plane
= devm_kzalloc(drm
->dev
, sizeof(*plane
), GFP_KERNEL
);
298 return ERR_PTR(-ENOMEM
);
300 for (i
= 0; i
< ARRAY_SIZE(supported_formats
); i
++)
301 formats
[i
] = supported_formats
[i
].fourcc
;
303 ret
= drm_universal_plane_init(drm
, plane
, 0xff, &hdlcd_plane_funcs
,
304 formats
, ARRAY_SIZE(formats
),
305 DRM_PLANE_TYPE_PRIMARY
, NULL
);
307 devm_kfree(drm
->dev
, plane
);
311 drm_plane_helper_add(plane
, &hdlcd_plane_helper_funcs
);
312 hdlcd
->plane
= plane
;
317 int hdlcd_setup_crtc(struct drm_device
*drm
)
319 struct hdlcd_drm_private
*hdlcd
= drm
->dev_private
;
320 struct drm_plane
*primary
;
323 primary
= hdlcd_plane_init(drm
);
325 return PTR_ERR(primary
);
327 ret
= drm_crtc_init_with_planes(drm
, &hdlcd
->crtc
, primary
, NULL
,
328 &hdlcd_crtc_funcs
, NULL
);
330 hdlcd_plane_destroy(primary
);
331 devm_kfree(drm
->dev
, primary
);
335 drm_crtc_helper_add(&hdlcd
->crtc
, &hdlcd_crtc_helper_funcs
);