3 * (C) COPYRIGHT 2013-2016 ARM Limited. All rights reserved.
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
10 * ARM Mali DP hardware manipulation routines.
13 #ifndef __MALIDP_HW_H__
14 #define __MALIDP_HW_H__
16 #include <linux/bitops.h>
17 #include "malidp_regs.h"
22 /* Mali DP IP blocks */
29 /* Mali DP layer IDs */
32 DE_GRAPHICS1
= BIT(1),
33 DE_GRAPHICS2
= BIT(2), /* used only in DP500 */
38 struct malidp_input_format
{
39 u32 format
; /* DRM fourcc */
40 u8 layer
; /* bitmask of layers supporting it */
41 u8 id
; /* used internally */
44 #define MALIDP_INVALID_FORMAT_ID 0xff
47 * hide the differences between register maps
48 * by using a common structure to hold the
49 * base register offsets
52 struct malidp_irq_map
{
53 u32 irq_mask
; /* mask of IRQs that can be enabled in the block */
54 u32 vsync_irq
; /* IRQ bit used for signaling during VSYNC */
58 u16 id
; /* layer ID */
59 u16 base
; /* address offset for the register bank */
60 u16 ptr
; /* address offset for the pointer register */
64 #define MALIDP_REGMAP_HAS_CLEARIRQ (1 << 0)
66 struct malidp_hw_regmap
{
67 /* address offset of the DE register bank */
68 /* is always 0x0000 */
69 /* address offset of the SE registers bank */
71 /* address offset of the DC registers bank */
74 /* address offset for the output depth register */
75 const u16 out_depth_base
;
77 /* bitmap with register map features */
80 /* list of supported layers */
82 const struct malidp_layer
*layers
;
84 const struct malidp_irq_map de_irq_map
;
85 const struct malidp_irq_map se_irq_map
;
86 const struct malidp_irq_map dc_irq_map
;
88 /* list of supported input formats for each layer */
89 const struct malidp_input_format
*input_formats
;
90 const u8 n_input_formats
;
93 struct malidp_hw_device
{
94 const struct malidp_hw_regmap map
;
101 /* main clock for display core */
103 /* pixel clock for display core */
107 * Validate the driver instance against the hardware bits
109 int (*query_hw
)(struct malidp_hw_device
*hwdev
);
112 * Set the hardware into config mode, ready to accept mode changes
114 void (*enter_config_mode
)(struct malidp_hw_device
*hwdev
);
117 * Tell hardware to exit configuration mode
119 void (*leave_config_mode
)(struct malidp_hw_device
*hwdev
);
122 * Query if hardware is in configuration mode
124 bool (*in_config_mode
)(struct malidp_hw_device
*hwdev
);
127 * Set configuration valid flag for hardware parameters that can
128 * be changed outside the configuration mode. Hardware will use
129 * the new settings when config valid is set after the end of the
130 * current buffer scanout
132 void (*set_config_valid
)(struct malidp_hw_device
*hwdev
);
135 * Set a new mode in hardware. Requires the hardware to be in
136 * configuration mode before this function is called.
138 void (*modeset
)(struct malidp_hw_device
*hwdev
, struct videomode
*m
);
141 * Calculate the required rotation memory given the active area
142 * and the buffer format.
144 int (*rotmem_required
)(struct malidp_hw_device
*hwdev
, u16 w
, u16 h
, u32 fmt
);
151 /* size of memory used for rotating layers, up to two banks available */
152 u32 rotation_memory
[2];
155 /* Supported variants of the hardware */
160 /* keep the next entry last */
164 extern const struct malidp_hw_device malidp_device
[MALIDP_MAX_DEVICES
];
166 static inline u32
malidp_hw_read(struct malidp_hw_device
*hwdev
, u32 reg
)
168 return readl(hwdev
->regs
+ reg
);
171 static inline void malidp_hw_write(struct malidp_hw_device
*hwdev
,
174 writel(value
, hwdev
->regs
+ reg
);
177 static inline void malidp_hw_setbits(struct malidp_hw_device
*hwdev
,
180 u32 data
= malidp_hw_read(hwdev
, reg
);
183 malidp_hw_write(hwdev
, data
, reg
);
186 static inline void malidp_hw_clearbits(struct malidp_hw_device
*hwdev
,
189 u32 data
= malidp_hw_read(hwdev
, reg
);
192 malidp_hw_write(hwdev
, data
, reg
);
195 static inline u32
malidp_get_block_base(struct malidp_hw_device
*hwdev
,
199 case MALIDP_SE_BLOCK
:
200 return hwdev
->map
.se_base
;
201 case MALIDP_DC_BLOCK
:
202 return hwdev
->map
.dc_base
;
208 static inline void malidp_hw_disable_irq(struct malidp_hw_device
*hwdev
,
211 u32 base
= malidp_get_block_base(hwdev
, block
);
213 malidp_hw_clearbits(hwdev
, irq
, base
+ MALIDP_REG_MASKIRQ
);
216 static inline void malidp_hw_enable_irq(struct malidp_hw_device
*hwdev
,
219 u32 base
= malidp_get_block_base(hwdev
, block
);
221 malidp_hw_setbits(hwdev
, irq
, base
+ MALIDP_REG_MASKIRQ
);
224 int malidp_de_irq_init(struct drm_device
*drm
, int irq
);
225 void malidp_de_irq_fini(struct drm_device
*drm
);
226 int malidp_se_irq_init(struct drm_device
*drm
, int irq
);
227 void malidp_se_irq_fini(struct drm_device
*drm
);
229 u8
malidp_hw_get_format_id(const struct malidp_hw_regmap
*map
,
230 u8 layer_id
, u32 format
);
233 * background color components are defined as 12bits values,
234 * they will be shifted right when stored on hardware that
235 * supports only 8bits per channel
237 #define MALIDP_BGND_COLOR_R 0x000
238 #define MALIDP_BGND_COLOR_G 0x000
239 #define MALIDP_BGND_COLOR_B 0x000
241 #endif /* __MALIDP_HW_H__ */