2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/component.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_plane_helper.h>
16 #include "armada_crtc.h"
17 #include "armada_drm.h"
18 #include "armada_fb.h"
19 #include "armada_gem.h"
20 #include "armada_hw.h"
22 struct armada_frame_work
{
23 struct drm_pending_vblank_event
*event
;
24 struct armada_regs regs
[4];
25 struct drm_framebuffer
*old_fb
;
37 * A note about interlacing. Let's consider HDMI 1920x1080i.
38 * The timing parameters we have from X are:
39 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
40 * 1920 2448 2492 2640 1080 1084 1094 1125
41 * Which get translated to:
42 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
43 * 1920 2448 2492 2640 540 542 547 562
45 * This is how it is defined by CEA-861-D - line and pixel numbers are
46 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
47 * line: 2640. The odd frame, the first active line is at line 21, and
48 * the even frame, the first active line is 584.
50 * LN: 560 561 562 563 567 568 569
51 * DE: ~~~|____________________________//__________________________
52 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
53 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
54 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
56 * LN: 1123 1124 1125 1 5 6 7
57 * DE: ~~~|____________________________//__________________________
58 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
59 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
62 * The Armada LCD Controller line and pixel numbers are, like X timings,
63 * referenced to the top left of the active frame.
65 * So, translating these to our LCD controller:
66 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
67 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
68 * Note: Vsync front porch remains constant!
71 * vtotal = mode->crtc_vtotal + 1;
72 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
73 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
75 * vtotal = mode->crtc_vtotal;
76 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
77 * vhorizpos = mode->crtc_hsync_start;
79 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
81 * So, we need to reprogram these registers on each vsync event:
82 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
84 * Note: we do not use the frame done interrupts because these appear
85 * to happen too early, and lead to jitter on the display (presumably
86 * they occur at the end of the last active line, before the vsync back
87 * porch, which we're reprogramming.)
91 armada_drm_crtc_update_regs(struct armada_crtc
*dcrtc
, struct armada_regs
*regs
)
93 while (regs
->offset
!= ~0) {
94 void __iomem
*reg
= dcrtc
->base
+ regs
->offset
;
99 val
&= readl_relaxed(reg
);
100 writel_relaxed(val
| regs
->val
, reg
);
105 #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
107 static void armada_drm_crtc_update(struct armada_crtc
*dcrtc
)
111 dumb_ctrl
= dcrtc
->cfg_dumb_ctrl
;
113 if (!dpms_blanked(dcrtc
->dpms
))
114 dumb_ctrl
|= CFG_DUMB_ENA
;
117 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
118 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
119 * force LCD_D[23:0] to output blank color, overriding the GPIO or
120 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
122 if (dpms_blanked(dcrtc
->dpms
) &&
123 (dumb_ctrl
& DUMB_MASK
) == DUMB24_RGB888_0
) {
124 dumb_ctrl
&= ~DUMB_MASK
;
125 dumb_ctrl
|= DUMB_BLANK
;
129 * The documentation doesn't indicate what the normal state of
130 * the sync signals are. Sebastian Hesselbart kindly probed
131 * these signals on his board to determine their state.
133 * The non-inverted state of the sync signals is active high.
134 * Setting these bits makes the appropriate signal active low.
136 if (dcrtc
->crtc
.mode
.flags
& DRM_MODE_FLAG_NCSYNC
)
137 dumb_ctrl
|= CFG_INV_CSYNC
;
138 if (dcrtc
->crtc
.mode
.flags
& DRM_MODE_FLAG_NHSYNC
)
139 dumb_ctrl
|= CFG_INV_HSYNC
;
140 if (dcrtc
->crtc
.mode
.flags
& DRM_MODE_FLAG_NVSYNC
)
141 dumb_ctrl
|= CFG_INV_VSYNC
;
143 if (dcrtc
->dumb_ctrl
!= dumb_ctrl
) {
144 dcrtc
->dumb_ctrl
= dumb_ctrl
;
145 writel_relaxed(dumb_ctrl
, dcrtc
->base
+ LCD_SPU_DUMB_CTRL
);
149 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer
*fb
,
150 int x
, int y
, struct armada_regs
*regs
, bool interlaced
)
152 struct armada_gem_object
*obj
= drm_fb_obj(fb
);
153 unsigned pitch
= fb
->pitches
[0];
154 unsigned offset
= y
* pitch
+ x
* fb
->bits_per_pixel
/ 8;
155 uint32_t addr_odd
, addr_even
;
158 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
159 pitch
, x
, y
, fb
->bits_per_pixel
);
161 addr_odd
= addr_even
= obj
->dev_addr
+ offset
;
168 /* write offset, base, and pitch */
169 armada_reg_queue_set(regs
, i
, addr_odd
, LCD_CFG_GRA_START_ADDR0
);
170 armada_reg_queue_set(regs
, i
, addr_even
, LCD_CFG_GRA_START_ADDR1
);
171 armada_reg_queue_mod(regs
, i
, pitch
, 0xffff, LCD_CFG_GRA_PITCH
);
176 void armada_drm_vbl_event_add(struct armada_crtc
*dcrtc
,
177 struct armada_vbl_event
*evt
)
182 WARN_ON(drm_vblank_get(dcrtc
->crtc
.dev
, dcrtc
->num
));
184 spin_lock_irqsave(&dcrtc
->irq_lock
, flags
);
185 not_on_list
= list_empty(&evt
->node
);
187 list_add_tail(&evt
->node
, &dcrtc
->vbl_list
);
188 spin_unlock_irqrestore(&dcrtc
->irq_lock
, flags
);
191 drm_vblank_put(dcrtc
->crtc
.dev
, dcrtc
->num
);
194 void armada_drm_vbl_event_remove(struct armada_crtc
*dcrtc
,
195 struct armada_vbl_event
*evt
)
197 if (!list_empty(&evt
->node
)) {
198 list_del_init(&evt
->node
);
199 drm_vblank_put(dcrtc
->crtc
.dev
, dcrtc
->num
);
203 static void armada_drm_vbl_event_run(struct armada_crtc
*dcrtc
)
205 struct armada_vbl_event
*e
, *n
;
207 list_for_each_entry_safe(e
, n
, &dcrtc
->vbl_list
, node
) {
208 list_del_init(&e
->node
);
209 drm_vblank_put(dcrtc
->crtc
.dev
, dcrtc
->num
);
210 e
->fn(dcrtc
, e
->data
);
214 static int armada_drm_crtc_queue_frame_work(struct armada_crtc
*dcrtc
,
215 struct armada_frame_work
*work
)
217 struct drm_device
*dev
= dcrtc
->crtc
.dev
;
221 ret
= drm_vblank_get(dev
, dcrtc
->num
);
223 DRM_ERROR("failed to acquire vblank counter\n");
227 spin_lock_irqsave(&dev
->event_lock
, flags
);
228 if (!dcrtc
->frame_work
)
229 dcrtc
->frame_work
= work
;
232 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
235 drm_vblank_put(dev
, dcrtc
->num
);
240 static void armada_drm_crtc_complete_frame_work(struct armada_crtc
*dcrtc
)
242 struct drm_device
*dev
= dcrtc
->crtc
.dev
;
243 struct armada_frame_work
*work
= dcrtc
->frame_work
;
245 dcrtc
->frame_work
= NULL
;
247 armada_drm_crtc_update_regs(dcrtc
, work
->regs
);
250 drm_send_vblank_event(dev
, dcrtc
->num
, work
->event
);
252 drm_vblank_put(dev
, dcrtc
->num
);
254 /* Finally, queue the process-half of the cleanup. */
255 __armada_drm_queue_unref_work(dcrtc
->crtc
.dev
, work
->old_fb
);
259 static void armada_drm_crtc_finish_fb(struct armada_crtc
*dcrtc
,
260 struct drm_framebuffer
*fb
, bool force
)
262 struct armada_frame_work
*work
;
268 /* Display is disabled, so just drop the old fb */
269 drm_framebuffer_unreference(fb
);
273 work
= kmalloc(sizeof(*work
), GFP_KERNEL
);
278 armada_reg_queue_end(work
->regs
, i
);
280 if (armada_drm_crtc_queue_frame_work(dcrtc
, work
) == 0)
287 * Oops - just drop the reference immediately and hope for
288 * the best. The worst that will happen is the buffer gets
289 * reused before it has finished being displayed.
291 drm_framebuffer_unreference(fb
);
294 static void armada_drm_vblank_off(struct armada_crtc
*dcrtc
)
296 struct drm_device
*dev
= dcrtc
->crtc
.dev
;
299 * Tell the DRM core that vblank IRQs aren't going to happen for
300 * a while. This cleans up any pending vblank events for us.
302 drm_crtc_vblank_off(&dcrtc
->crtc
);
304 /* Handle any pending flip event. */
305 spin_lock_irq(&dev
->event_lock
);
306 if (dcrtc
->frame_work
)
307 armada_drm_crtc_complete_frame_work(dcrtc
);
308 spin_unlock_irq(&dev
->event_lock
);
311 void armada_drm_crtc_gamma_set(struct drm_crtc
*crtc
, u16 r
, u16 g
, u16 b
,
316 void armada_drm_crtc_gamma_get(struct drm_crtc
*crtc
, u16
*r
, u16
*g
, u16
*b
,
321 /* The mode_config.mutex will be held for this call */
322 static void armada_drm_crtc_dpms(struct drm_crtc
*crtc
, int dpms
)
324 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
326 if (dcrtc
->dpms
!= dpms
) {
328 armada_drm_crtc_update(dcrtc
);
329 if (dpms_blanked(dpms
))
330 armada_drm_vblank_off(dcrtc
);
332 drm_crtc_vblank_on(&dcrtc
->crtc
);
337 * Prepare for a mode set. Turn off overlay to ensure that we don't end
338 * up with the overlay size being bigger than the active screen size.
339 * We rely upon X refreshing this state after the mode set has completed.
341 * The mode_config.mutex will be held for this call
343 static void armada_drm_crtc_prepare(struct drm_crtc
*crtc
)
345 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
346 struct drm_plane
*plane
;
349 * If we have an overlay plane associated with this CRTC, disable
350 * it before the modeset to avoid its coordinates being outside
351 * the new mode parameters. DRM doesn't provide help with this.
353 plane
= dcrtc
->plane
;
355 struct drm_framebuffer
*fb
= plane
->fb
;
357 plane
->funcs
->disable_plane(plane
);
360 drm_framebuffer_unreference(fb
);
364 /* The mode_config.mutex will be held for this call */
365 static void armada_drm_crtc_commit(struct drm_crtc
*crtc
)
367 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
369 if (dcrtc
->dpms
!= DRM_MODE_DPMS_ON
) {
370 dcrtc
->dpms
= DRM_MODE_DPMS_ON
;
371 armada_drm_crtc_update(dcrtc
);
375 /* The mode_config.mutex will be held for this call */
376 static bool armada_drm_crtc_mode_fixup(struct drm_crtc
*crtc
,
377 const struct drm_display_mode
*mode
, struct drm_display_mode
*adj
)
379 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
382 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
383 if (!dcrtc
->variant
->has_spu_adv_reg
&&
384 adj
->flags
& DRM_MODE_FLAG_INTERLACE
)
387 /* Check whether the display mode is possible */
388 ret
= dcrtc
->variant
->compute_clock(dcrtc
, adj
, NULL
);
395 static void armada_drm_crtc_irq(struct armada_crtc
*dcrtc
, u32 stat
)
397 void __iomem
*base
= dcrtc
->base
;
399 if (stat
& DMA_FF_UNDERFLOW
)
400 DRM_ERROR("video underflow on crtc %u\n", dcrtc
->num
);
401 if (stat
& GRA_FF_UNDERFLOW
)
402 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc
->num
);
404 if (stat
& VSYNC_IRQ
)
405 drm_handle_vblank(dcrtc
->crtc
.dev
, dcrtc
->num
);
407 spin_lock(&dcrtc
->irq_lock
);
408 armada_drm_vbl_event_run(dcrtc
);
410 if (stat
& GRA_FRAME_IRQ
&& dcrtc
->interlaced
) {
411 int i
= stat
& GRA_FRAME_IRQ0
? 0 : 1;
414 writel_relaxed(dcrtc
->v
[i
].spu_v_porch
, base
+ LCD_SPU_V_PORCH
);
415 writel_relaxed(dcrtc
->v
[i
].spu_v_h_total
,
416 base
+ LCD_SPUT_V_H_TOTAL
);
418 val
= readl_relaxed(base
+ LCD_SPU_ADV_REG
);
419 val
&= ~(ADV_VSYNC_L_OFF
| ADV_VSYNC_H_OFF
| ADV_VSYNCOFFEN
);
420 val
|= dcrtc
->v
[i
].spu_adv_reg
;
421 writel_relaxed(val
, base
+ LCD_SPU_ADV_REG
);
424 if (stat
& DUMB_FRAMEDONE
&& dcrtc
->cursor_update
) {
425 writel_relaxed(dcrtc
->cursor_hw_pos
,
426 base
+ LCD_SPU_HWC_OVSA_HPXL_VLN
);
427 writel_relaxed(dcrtc
->cursor_hw_sz
,
428 base
+ LCD_SPU_HWC_HPXL_VLN
);
429 armada_updatel(CFG_HWC_ENA
,
430 CFG_HWC_ENA
| CFG_HWC_1BITMOD
| CFG_HWC_1BITENA
,
431 base
+ LCD_SPU_DMA_CTRL0
);
432 dcrtc
->cursor_update
= false;
433 armada_drm_crtc_disable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
436 spin_unlock(&dcrtc
->irq_lock
);
438 if (stat
& GRA_FRAME_IRQ
) {
439 struct drm_device
*dev
= dcrtc
->crtc
.dev
;
441 spin_lock(&dev
->event_lock
);
442 if (dcrtc
->frame_work
)
443 armada_drm_crtc_complete_frame_work(dcrtc
);
444 spin_unlock(&dev
->event_lock
);
446 wake_up(&dcrtc
->frame_wait
);
450 static irqreturn_t
armada_drm_irq(int irq
, void *arg
)
452 struct armada_crtc
*dcrtc
= arg
;
453 u32 v
, stat
= readl_relaxed(dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
456 * This is rediculous - rather than writing bits to clear, we
457 * have to set the actual status register value. This is racy.
459 writel_relaxed(0, dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
461 /* Mask out those interrupts we haven't enabled */
462 v
= stat
& dcrtc
->irq_ena
;
464 if (v
& (VSYNC_IRQ
|GRA_FRAME_IRQ
|DUMB_FRAMEDONE
)) {
465 armada_drm_crtc_irq(dcrtc
, stat
);
471 /* These are locked by dev->vbl_lock */
472 void armada_drm_crtc_disable_irq(struct armada_crtc
*dcrtc
, u32 mask
)
474 if (dcrtc
->irq_ena
& mask
) {
475 dcrtc
->irq_ena
&= ~mask
;
476 writel(dcrtc
->irq_ena
, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
480 void armada_drm_crtc_enable_irq(struct armada_crtc
*dcrtc
, u32 mask
)
482 if ((dcrtc
->irq_ena
& mask
) != mask
) {
483 dcrtc
->irq_ena
|= mask
;
484 writel(dcrtc
->irq_ena
, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
485 if (readl_relaxed(dcrtc
->base
+ LCD_SPU_IRQ_ISR
) & mask
)
486 writel(0, dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
490 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc
*dcrtc
)
492 struct drm_display_mode
*adj
= &dcrtc
->crtc
.mode
;
495 if (dcrtc
->csc_yuv_mode
== CSC_YUV_CCIR709
)
496 val
|= CFG_CSC_YUV_CCIR709
;
497 if (dcrtc
->csc_rgb_mode
== CSC_RGB_STUDIO
)
498 val
|= CFG_CSC_RGB_STUDIO
;
501 * In auto mode, set the colorimetry, based upon the HDMI spec.
502 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
503 * ITU601. It may be more appropriate to set this depending on
504 * the source - but what if the graphic frame is YUV and the
505 * video frame is RGB?
507 if ((adj
->hdisplay
== 1280 && adj
->vdisplay
== 720 &&
508 !(adj
->flags
& DRM_MODE_FLAG_INTERLACE
)) ||
509 (adj
->hdisplay
== 1920 && adj
->vdisplay
== 1080)) {
510 if (dcrtc
->csc_yuv_mode
== CSC_AUTO
)
511 val
|= CFG_CSC_YUV_CCIR709
;
515 * We assume we're connected to a TV-like device, so the YUV->RGB
516 * conversion should produce a limited range. We should set this
517 * depending on the connectors attached to this CRTC, and what
518 * kind of device they report being connected.
520 if (dcrtc
->csc_rgb_mode
== CSC_AUTO
)
521 val
|= CFG_CSC_RGB_STUDIO
;
526 /* The mode_config.mutex will be held for this call */
527 static int armada_drm_crtc_mode_set(struct drm_crtc
*crtc
,
528 struct drm_display_mode
*mode
, struct drm_display_mode
*adj
,
529 int x
, int y
, struct drm_framebuffer
*old_fb
)
531 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
532 struct armada_regs regs
[17];
533 uint32_t lm
, rm
, tm
, bm
, val
, sclk
;
538 drm_framebuffer_reference(crtc
->primary
->fb
);
540 interlaced
= !!(adj
->flags
& DRM_MODE_FLAG_INTERLACE
);
542 i
= armada_drm_crtc_calc_fb(dcrtc
->crtc
.primary
->fb
,
543 x
, y
, regs
, interlaced
);
545 rm
= adj
->crtc_hsync_start
- adj
->crtc_hdisplay
;
546 lm
= adj
->crtc_htotal
- adj
->crtc_hsync_end
;
547 bm
= adj
->crtc_vsync_start
- adj
->crtc_vdisplay
;
548 tm
= adj
->crtc_vtotal
- adj
->crtc_vsync_end
;
550 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
552 adj
->crtc_hsync_start
,
554 adj
->crtc_htotal
, lm
, rm
);
555 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
557 adj
->crtc_vsync_start
,
559 adj
->crtc_vtotal
, tm
, bm
);
561 /* Wait for pending flips to complete */
562 wait_event(dcrtc
->frame_wait
, !dcrtc
->frame_work
);
564 drm_crtc_vblank_off(crtc
);
566 val
= dcrtc
->dumb_ctrl
& ~CFG_DUMB_ENA
;
567 if (val
!= dcrtc
->dumb_ctrl
) {
568 dcrtc
->dumb_ctrl
= val
;
569 writel_relaxed(val
, dcrtc
->base
+ LCD_SPU_DUMB_CTRL
);
572 /* Now compute the divider for real */
573 dcrtc
->variant
->compute_clock(dcrtc
, adj
, &sclk
);
575 /* Ensure graphic fifo is enabled */
576 armada_reg_queue_mod(regs
, i
, 0, CFG_PDWN64x66
, LCD_SPU_SRAM_PARA1
);
577 armada_reg_queue_set(regs
, i
, sclk
, LCD_CFG_SCLK_DIV
);
579 if (interlaced
^ dcrtc
->interlaced
) {
580 if (adj
->flags
& DRM_MODE_FLAG_INTERLACE
)
581 drm_vblank_get(dcrtc
->crtc
.dev
, dcrtc
->num
);
583 drm_vblank_put(dcrtc
->crtc
.dev
, dcrtc
->num
);
584 dcrtc
->interlaced
= interlaced
;
587 spin_lock_irqsave(&dcrtc
->irq_lock
, flags
);
589 /* Even interlaced/progressive frame */
590 dcrtc
->v
[1].spu_v_h_total
= adj
->crtc_vtotal
<< 16 |
592 dcrtc
->v
[1].spu_v_porch
= tm
<< 16 | bm
;
593 val
= adj
->crtc_hsync_start
;
594 dcrtc
->v
[1].spu_adv_reg
= val
<< 20 | val
| ADV_VSYNCOFFEN
|
595 dcrtc
->variant
->spu_adv_reg
;
598 /* Odd interlaced frame */
599 dcrtc
->v
[0].spu_v_h_total
= dcrtc
->v
[1].spu_v_h_total
+
601 dcrtc
->v
[0].spu_v_porch
= dcrtc
->v
[1].spu_v_porch
+ 1;
602 val
= adj
->crtc_hsync_start
- adj
->crtc_htotal
/ 2;
603 dcrtc
->v
[0].spu_adv_reg
= val
<< 20 | val
| ADV_VSYNCOFFEN
|
604 dcrtc
->variant
->spu_adv_reg
;
606 dcrtc
->v
[0] = dcrtc
->v
[1];
609 val
= adj
->crtc_vdisplay
<< 16 | adj
->crtc_hdisplay
;
611 armada_reg_queue_set(regs
, i
, val
, LCD_SPU_V_H_ACTIVE
);
612 armada_reg_queue_set(regs
, i
, val
, LCD_SPU_GRA_HPXL_VLN
);
613 armada_reg_queue_set(regs
, i
, val
, LCD_SPU_GZM_HPXL_VLN
);
614 armada_reg_queue_set(regs
, i
, (lm
<< 16) | rm
, LCD_SPU_H_PORCH
);
615 armada_reg_queue_set(regs
, i
, dcrtc
->v
[0].spu_v_porch
, LCD_SPU_V_PORCH
);
616 armada_reg_queue_set(regs
, i
, dcrtc
->v
[0].spu_v_h_total
,
619 if (dcrtc
->variant
->has_spu_adv_reg
) {
620 armada_reg_queue_mod(regs
, i
, dcrtc
->v
[0].spu_adv_reg
,
621 ADV_VSYNC_L_OFF
| ADV_VSYNC_H_OFF
|
622 ADV_VSYNCOFFEN
, LCD_SPU_ADV_REG
);
625 val
= CFG_GRA_ENA
| CFG_GRA_HSMOOTH
;
626 val
|= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc
->crtc
.primary
->fb
)->fmt
);
627 val
|= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc
->crtc
.primary
->fb
)->mod
);
629 if (drm_fb_to_armada_fb(dcrtc
->crtc
.primary
->fb
)->fmt
> CFG_420
)
630 val
|= CFG_PALETTE_ENA
;
633 val
|= CFG_GRA_FTOGGLE
;
635 armada_reg_queue_mod(regs
, i
, val
, CFG_GRAFORMAT
|
636 CFG_GRA_MOD(CFG_SWAPRB
| CFG_SWAPUV
|
637 CFG_SWAPYU
| CFG_YUV2RGB
) |
638 CFG_PALETTE_ENA
| CFG_GRA_FTOGGLE
,
641 val
= adj
->flags
& DRM_MODE_FLAG_NVSYNC
? CFG_VSYNC_INV
: 0;
642 armada_reg_queue_mod(regs
, i
, val
, CFG_VSYNC_INV
, LCD_SPU_DMA_CTRL1
);
644 val
= dcrtc
->spu_iopad_ctrl
| armada_drm_crtc_calculate_csc(dcrtc
);
645 armada_reg_queue_set(regs
, i
, val
, LCD_SPU_IOPAD_CONTROL
);
646 armada_reg_queue_end(regs
, i
);
648 armada_drm_crtc_update_regs(dcrtc
, regs
);
649 spin_unlock_irqrestore(&dcrtc
->irq_lock
, flags
);
651 armada_drm_crtc_update(dcrtc
);
653 drm_crtc_vblank_on(crtc
);
654 armada_drm_crtc_finish_fb(dcrtc
, old_fb
, dpms_blanked(dcrtc
->dpms
));
659 /* The mode_config.mutex will be held for this call */
660 static int armada_drm_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
661 struct drm_framebuffer
*old_fb
)
663 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
664 struct armada_regs regs
[4];
667 i
= armada_drm_crtc_calc_fb(crtc
->primary
->fb
, crtc
->x
, crtc
->y
, regs
,
669 armada_reg_queue_end(regs
, i
);
671 /* Wait for pending flips to complete */
672 wait_event(dcrtc
->frame_wait
, !dcrtc
->frame_work
);
674 /* Take a reference to the new fb as we're using it */
675 drm_framebuffer_reference(crtc
->primary
->fb
);
677 /* Update the base in the CRTC */
678 armada_drm_crtc_update_regs(dcrtc
, regs
);
680 /* Drop our previously held reference */
681 armada_drm_crtc_finish_fb(dcrtc
, old_fb
, dpms_blanked(dcrtc
->dpms
));
686 /* The mode_config.mutex will be held for this call */
687 static void armada_drm_crtc_disable(struct drm_crtc
*crtc
)
689 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
691 armada_drm_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
692 armada_drm_crtc_finish_fb(dcrtc
, crtc
->primary
->fb
, true);
694 /* Power down most RAMs and FIFOs */
695 writel_relaxed(CFG_PDWN256x32
| CFG_PDWN256x24
| CFG_PDWN256x8
|
696 CFG_PDWN32x32
| CFG_PDWN16x66
| CFG_PDWN32x66
|
697 CFG_PDWN64x66
, dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
700 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs
= {
701 .dpms
= armada_drm_crtc_dpms
,
702 .prepare
= armada_drm_crtc_prepare
,
703 .commit
= armada_drm_crtc_commit
,
704 .mode_fixup
= armada_drm_crtc_mode_fixup
,
705 .mode_set
= armada_drm_crtc_mode_set
,
706 .mode_set_base
= armada_drm_crtc_mode_set_base
,
707 .disable
= armada_drm_crtc_disable
,
710 static void armada_load_cursor_argb(void __iomem
*base
, uint32_t *pix
,
711 unsigned stride
, unsigned width
, unsigned height
)
716 addr
= SRAM_HWC32_RAM1
;
717 for (y
= 0; y
< height
; y
++) {
718 uint32_t *p
= &pix
[y
* stride
];
721 for (x
= 0; x
< width
; x
++, p
++) {
724 val
= (val
& 0xff00ff00) |
725 (val
& 0x000000ff) << 16 |
726 (val
& 0x00ff0000) >> 16;
729 base
+ LCD_SPU_SRAM_WRDAT
);
730 writel_relaxed(addr
| SRAM_WRITE
,
731 base
+ LCD_SPU_SRAM_CTRL
);
732 readl_relaxed(base
+ LCD_SPU_HWC_OVSA_HPXL_VLN
);
734 if ((addr
& 0x00ff) == 0)
736 if ((addr
& 0x30ff) == 0)
737 addr
= SRAM_HWC32_RAM2
;
742 static void armada_drm_crtc_cursor_tran(void __iomem
*base
)
746 for (addr
= 0; addr
< 256; addr
++) {
747 /* write the default value */
748 writel_relaxed(0x55555555, base
+ LCD_SPU_SRAM_WRDAT
);
749 writel_relaxed(addr
| SRAM_WRITE
| SRAM_HWC32_TRAN
,
750 base
+ LCD_SPU_SRAM_CTRL
);
754 static int armada_drm_crtc_cursor_update(struct armada_crtc
*dcrtc
, bool reload
)
756 uint32_t xoff
, xscr
, w
= dcrtc
->cursor_w
, s
;
757 uint32_t yoff
, yscr
, h
= dcrtc
->cursor_h
;
761 * Calculate the visible width and height of the cursor,
762 * screen position, and the position in the cursor bitmap.
764 if (dcrtc
->cursor_x
< 0) {
765 xoff
= -dcrtc
->cursor_x
;
768 } else if (dcrtc
->cursor_x
+ w
> dcrtc
->crtc
.mode
.hdisplay
) {
770 xscr
= dcrtc
->cursor_x
;
771 w
= max_t(int, dcrtc
->crtc
.mode
.hdisplay
- dcrtc
->cursor_x
, 0);
774 xscr
= dcrtc
->cursor_x
;
777 if (dcrtc
->cursor_y
< 0) {
778 yoff
= -dcrtc
->cursor_y
;
781 } else if (dcrtc
->cursor_y
+ h
> dcrtc
->crtc
.mode
.vdisplay
) {
783 yscr
= dcrtc
->cursor_y
;
784 h
= max_t(int, dcrtc
->crtc
.mode
.vdisplay
- dcrtc
->cursor_y
, 0);
787 yscr
= dcrtc
->cursor_y
;
790 /* On interlaced modes, the vertical cursor size must be halved */
792 if (dcrtc
->interlaced
) {
798 if (!dcrtc
->cursor_obj
|| !h
|| !w
) {
799 spin_lock_irq(&dcrtc
->irq_lock
);
800 armada_drm_crtc_disable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
801 dcrtc
->cursor_update
= false;
802 armada_updatel(0, CFG_HWC_ENA
, dcrtc
->base
+ LCD_SPU_DMA_CTRL0
);
803 spin_unlock_irq(&dcrtc
->irq_lock
);
807 para1
= readl_relaxed(dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
808 armada_updatel(CFG_CSB_256x32
, CFG_CSB_256x32
| CFG_PDWN256x32
,
809 dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
812 * Initialize the transparency if the SRAM was powered down.
813 * We must also reload the cursor data as well.
815 if (!(para1
& CFG_CSB_256x32
)) {
816 armada_drm_crtc_cursor_tran(dcrtc
->base
);
820 if (dcrtc
->cursor_hw_sz
!= (h
<< 16 | w
)) {
821 spin_lock_irq(&dcrtc
->irq_lock
);
822 armada_drm_crtc_disable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
823 dcrtc
->cursor_update
= false;
824 armada_updatel(0, CFG_HWC_ENA
, dcrtc
->base
+ LCD_SPU_DMA_CTRL0
);
825 spin_unlock_irq(&dcrtc
->irq_lock
);
829 struct armada_gem_object
*obj
= dcrtc
->cursor_obj
;
831 /* Set the top-left corner of the cursor image */
833 pix
+= yoff
* s
+ xoff
;
834 armada_load_cursor_argb(dcrtc
->base
, pix
, s
, w
, h
);
837 /* Reload the cursor position, size and enable in the IRQ handler */
838 spin_lock_irq(&dcrtc
->irq_lock
);
839 dcrtc
->cursor_hw_pos
= yscr
<< 16 | xscr
;
840 dcrtc
->cursor_hw_sz
= h
<< 16 | w
;
841 dcrtc
->cursor_update
= true;
842 armada_drm_crtc_enable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
843 spin_unlock_irq(&dcrtc
->irq_lock
);
848 static void cursor_update(void *data
)
850 armada_drm_crtc_cursor_update(data
, true);
853 static int armada_drm_crtc_cursor_set(struct drm_crtc
*crtc
,
854 struct drm_file
*file
, uint32_t handle
, uint32_t w
, uint32_t h
)
856 struct drm_device
*dev
= crtc
->dev
;
857 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
858 struct armada_gem_object
*obj
= NULL
;
861 /* If no cursor support, replicate drm's return value */
862 if (!dcrtc
->variant
->has_spu_adv_reg
)
865 if (handle
&& w
> 0 && h
> 0) {
866 /* maximum size is 64x32 or 32x64 */
867 if (w
> 64 || h
> 64 || (w
> 32 && h
> 32))
870 obj
= armada_gem_object_lookup(dev
, file
, handle
);
874 /* Must be a kernel-mapped object */
876 drm_gem_object_unreference_unlocked(&obj
->obj
);
880 if (obj
->obj
.size
< w
* h
* 4) {
881 DRM_ERROR("buffer is too small\n");
882 drm_gem_object_unreference_unlocked(&obj
->obj
);
887 mutex_lock(&dev
->struct_mutex
);
888 if (dcrtc
->cursor_obj
) {
889 dcrtc
->cursor_obj
->update
= NULL
;
890 dcrtc
->cursor_obj
->update_data
= NULL
;
891 drm_gem_object_unreference(&dcrtc
->cursor_obj
->obj
);
893 dcrtc
->cursor_obj
= obj
;
896 ret
= armada_drm_crtc_cursor_update(dcrtc
, true);
898 obj
->update_data
= dcrtc
;
899 obj
->update
= cursor_update
;
901 mutex_unlock(&dev
->struct_mutex
);
906 static int armada_drm_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
908 struct drm_device
*dev
= crtc
->dev
;
909 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
912 /* If no cursor support, replicate drm's return value */
913 if (!dcrtc
->variant
->has_spu_adv_reg
)
916 mutex_lock(&dev
->struct_mutex
);
919 ret
= armada_drm_crtc_cursor_update(dcrtc
, false);
920 mutex_unlock(&dev
->struct_mutex
);
925 static void armada_drm_crtc_destroy(struct drm_crtc
*crtc
)
927 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
928 struct armada_private
*priv
= crtc
->dev
->dev_private
;
930 if (dcrtc
->cursor_obj
)
931 drm_gem_object_unreference(&dcrtc
->cursor_obj
->obj
);
933 priv
->dcrtc
[dcrtc
->num
] = NULL
;
934 drm_crtc_cleanup(&dcrtc
->crtc
);
936 if (!IS_ERR(dcrtc
->clk
))
937 clk_disable_unprepare(dcrtc
->clk
);
939 writel_relaxed(0, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
941 of_node_put(dcrtc
->crtc
.port
);
947 * The mode_config lock is held here, to prevent races between this
950 static int armada_drm_crtc_page_flip(struct drm_crtc
*crtc
,
951 struct drm_framebuffer
*fb
, struct drm_pending_vblank_event
*event
, uint32_t page_flip_flags
)
953 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
954 struct armada_frame_work
*work
;
955 struct drm_device
*dev
= crtc
->dev
;
960 /* We don't support changing the pixel format */
961 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
964 work
= kmalloc(sizeof(*work
), GFP_KERNEL
);
969 work
->old_fb
= dcrtc
->crtc
.primary
->fb
;
971 i
= armada_drm_crtc_calc_fb(fb
, crtc
->x
, crtc
->y
, work
->regs
,
973 armada_reg_queue_end(work
->regs
, i
);
976 * Ensure that we hold a reference on the new framebuffer.
977 * This has to match the behaviour in mode_set.
979 drm_framebuffer_reference(fb
);
981 ret
= armada_drm_crtc_queue_frame_work(dcrtc
, work
);
983 /* Undo our reference above */
984 drm_framebuffer_unreference(fb
);
990 * Don't take a reference on the new framebuffer;
991 * drm_mode_page_flip_ioctl() has already grabbed a reference and
992 * will _not_ drop that reference on successful return from this
993 * function. Simply mark this new framebuffer as the current one.
995 dcrtc
->crtc
.primary
->fb
= fb
;
998 * Finally, if the display is blanked, we won't receive an
999 * interrupt, so complete it now.
1001 if (dpms_blanked(dcrtc
->dpms
)) {
1002 spin_lock_irqsave(&dev
->event_lock
, flags
);
1003 if (dcrtc
->frame_work
)
1004 armada_drm_crtc_complete_frame_work(dcrtc
);
1005 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
1012 armada_drm_crtc_set_property(struct drm_crtc
*crtc
,
1013 struct drm_property
*property
, uint64_t val
)
1015 struct armada_private
*priv
= crtc
->dev
->dev_private
;
1016 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
1017 bool update_csc
= false;
1019 if (property
== priv
->csc_yuv_prop
) {
1020 dcrtc
->csc_yuv_mode
= val
;
1022 } else if (property
== priv
->csc_rgb_prop
) {
1023 dcrtc
->csc_rgb_mode
= val
;
1030 val
= dcrtc
->spu_iopad_ctrl
|
1031 armada_drm_crtc_calculate_csc(dcrtc
);
1032 writel_relaxed(val
, dcrtc
->base
+ LCD_SPU_IOPAD_CONTROL
);
1038 static struct drm_crtc_funcs armada_crtc_funcs
= {
1039 .cursor_set
= armada_drm_crtc_cursor_set
,
1040 .cursor_move
= armada_drm_crtc_cursor_move
,
1041 .destroy
= armada_drm_crtc_destroy
,
1042 .set_config
= drm_crtc_helper_set_config
,
1043 .page_flip
= armada_drm_crtc_page_flip
,
1044 .set_property
= armada_drm_crtc_set_property
,
1047 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list
[] = {
1048 { CSC_AUTO
, "Auto" },
1049 { CSC_YUV_CCIR601
, "CCIR601" },
1050 { CSC_YUV_CCIR709
, "CCIR709" },
1053 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list
[] = {
1054 { CSC_AUTO
, "Auto" },
1055 { CSC_RGB_COMPUTER
, "Computer system" },
1056 { CSC_RGB_STUDIO
, "Studio" },
1059 static int armada_drm_crtc_create_properties(struct drm_device
*dev
)
1061 struct armada_private
*priv
= dev
->dev_private
;
1063 if (priv
->csc_yuv_prop
)
1066 priv
->csc_yuv_prop
= drm_property_create_enum(dev
, 0,
1067 "CSC_YUV", armada_drm_csc_yuv_enum_list
,
1068 ARRAY_SIZE(armada_drm_csc_yuv_enum_list
));
1069 priv
->csc_rgb_prop
= drm_property_create_enum(dev
, 0,
1070 "CSC_RGB", armada_drm_csc_rgb_enum_list
,
1071 ARRAY_SIZE(armada_drm_csc_rgb_enum_list
));
1073 if (!priv
->csc_yuv_prop
|| !priv
->csc_rgb_prop
)
1079 static int armada_drm_crtc_create(struct drm_device
*drm
, struct device
*dev
,
1080 struct resource
*res
, int irq
, const struct armada_variant
*variant
,
1081 struct device_node
*port
)
1083 struct armada_private
*priv
= drm
->dev_private
;
1084 struct armada_crtc
*dcrtc
;
1088 ret
= armada_drm_crtc_create_properties(drm
);
1092 base
= devm_ioremap_resource(dev
, res
);
1094 return PTR_ERR(base
);
1096 dcrtc
= kzalloc(sizeof(*dcrtc
), GFP_KERNEL
);
1098 DRM_ERROR("failed to allocate Armada crtc\n");
1102 if (dev
!= drm
->dev
)
1103 dev_set_drvdata(dev
, dcrtc
);
1105 dcrtc
->variant
= variant
;
1107 dcrtc
->num
= drm
->mode_config
.num_crtc
;
1108 dcrtc
->clk
= ERR_PTR(-EINVAL
);
1109 dcrtc
->csc_yuv_mode
= CSC_AUTO
;
1110 dcrtc
->csc_rgb_mode
= CSC_AUTO
;
1111 dcrtc
->cfg_dumb_ctrl
= DUMB24_RGB888_0
;
1112 dcrtc
->spu_iopad_ctrl
= CFG_VSCALE_LN_EN
| CFG_IOPAD_DUMB24
;
1113 spin_lock_init(&dcrtc
->irq_lock
);
1114 dcrtc
->irq_ena
= CLEAN_SPU_IRQ_ISR
;
1115 INIT_LIST_HEAD(&dcrtc
->vbl_list
);
1116 init_waitqueue_head(&dcrtc
->frame_wait
);
1118 /* Initialize some registers which we don't otherwise set */
1119 writel_relaxed(0x00000001, dcrtc
->base
+ LCD_CFG_SCLK_DIV
);
1120 writel_relaxed(0x00000000, dcrtc
->base
+ LCD_SPU_BLANKCOLOR
);
1121 writel_relaxed(dcrtc
->spu_iopad_ctrl
,
1122 dcrtc
->base
+ LCD_SPU_IOPAD_CONTROL
);
1123 writel_relaxed(0x00000000, dcrtc
->base
+ LCD_SPU_SRAM_PARA0
);
1124 writel_relaxed(CFG_PDWN256x32
| CFG_PDWN256x24
| CFG_PDWN256x8
|
1125 CFG_PDWN32x32
| CFG_PDWN16x66
| CFG_PDWN32x66
|
1126 CFG_PDWN64x66
, dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
1127 writel_relaxed(0x2032ff81, dcrtc
->base
+ LCD_SPU_DMA_CTRL1
);
1128 writel_relaxed(0x00000000, dcrtc
->base
+ LCD_SPU_GRA_OVSA_HPXL_VLN
);
1129 writel_relaxed(dcrtc
->irq_ena
, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
1130 writel_relaxed(0, dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
1132 ret
= devm_request_irq(dev
, irq
, armada_drm_irq
, 0, "armada_drm_crtc",
1139 if (dcrtc
->variant
->init
) {
1140 ret
= dcrtc
->variant
->init(dcrtc
, dev
);
1147 /* Ensure AXI pipeline is enabled */
1148 armada_updatel(CFG_ARBFAST_ENA
, 0, dcrtc
->base
+ LCD_SPU_DMA_CTRL0
);
1150 priv
->dcrtc
[dcrtc
->num
] = dcrtc
;
1152 dcrtc
->crtc
.port
= port
;
1153 drm_crtc_init(drm
, &dcrtc
->crtc
, &armada_crtc_funcs
);
1154 drm_crtc_helper_add(&dcrtc
->crtc
, &armada_crtc_helper_funcs
);
1156 drm_object_attach_property(&dcrtc
->crtc
.base
, priv
->csc_yuv_prop
,
1157 dcrtc
->csc_yuv_mode
);
1158 drm_object_attach_property(&dcrtc
->crtc
.base
, priv
->csc_rgb_prop
,
1159 dcrtc
->csc_rgb_mode
);
1161 return armada_overlay_plane_create(drm
, 1 << dcrtc
->num
);
1165 armada_lcd_bind(struct device
*dev
, struct device
*master
, void *data
)
1167 struct platform_device
*pdev
= to_platform_device(dev
);
1168 struct drm_device
*drm
= data
;
1169 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1170 int irq
= platform_get_irq(pdev
, 0);
1171 const struct armada_variant
*variant
;
1172 struct device_node
*port
= NULL
;
1177 if (!dev
->of_node
) {
1178 const struct platform_device_id
*id
;
1180 id
= platform_get_device_id(pdev
);
1184 variant
= (const struct armada_variant
*)id
->driver_data
;
1186 const struct of_device_id
*match
;
1187 struct device_node
*np
, *parent
= dev
->of_node
;
1189 match
= of_match_device(dev
->driver
->of_match_table
, dev
);
1193 np
= of_get_child_by_name(parent
, "ports");
1196 port
= of_get_child_by_name(parent
, "port");
1199 dev_err(dev
, "no port node found in %s\n",
1204 variant
= match
->data
;
1207 return armada_drm_crtc_create(drm
, dev
, res
, irq
, variant
, port
);
1211 armada_lcd_unbind(struct device
*dev
, struct device
*master
, void *data
)
1213 struct armada_crtc
*dcrtc
= dev_get_drvdata(dev
);
1215 armada_drm_crtc_destroy(&dcrtc
->crtc
);
1218 static const struct component_ops armada_lcd_ops
= {
1219 .bind
= armada_lcd_bind
,
1220 .unbind
= armada_lcd_unbind
,
1223 static int armada_lcd_probe(struct platform_device
*pdev
)
1225 return component_add(&pdev
->dev
, &armada_lcd_ops
);
1228 static int armada_lcd_remove(struct platform_device
*pdev
)
1230 component_del(&pdev
->dev
, &armada_lcd_ops
);
1234 static struct of_device_id armada_lcd_of_match
[] = {
1236 .compatible
= "marvell,dove-lcd",
1237 .data
= &armada510_ops
,
1241 MODULE_DEVICE_TABLE(of
, armada_lcd_of_match
);
1243 static const struct platform_device_id armada_lcd_platform_ids
[] = {
1245 .name
= "armada-lcd",
1246 .driver_data
= (unsigned long)&armada510_ops
,
1248 .name
= "armada-510-lcd",
1249 .driver_data
= (unsigned long)&armada510_ops
,
1253 MODULE_DEVICE_TABLE(platform
, armada_lcd_platform_ids
);
1255 struct platform_driver armada_lcd_platform_driver
= {
1256 .probe
= armada_lcd_probe
,
1257 .remove
= armada_lcd_remove
,
1259 .name
= "armada-lcd",
1260 .owner
= THIS_MODULE
,
1261 .of_match_table
= armada_lcd_of_match
,
1263 .id_table
= armada_lcd_platform_ids
,