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drm: imx: imx-hdmi: move imx-hdmi to bridge/dw_hdmi
[deliverable/linux.git] / drivers / gpu / drm / bridge / dw_hdmi.c
1 /*
2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * Designware High-Definition Multimedia Interface (HDMI) driver
10 *
11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
12 */
13 #include <linux/module.h>
14 #include <linux/irq.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/hdmi.h>
19 #include <linux/of_device.h>
20
21 #include <drm/drm_of.h>
22 #include <drm/drmP.h>
23 #include <drm/drm_crtc_helper.h>
24 #include <drm/drm_edid.h>
25 #include <drm/drm_encoder_slave.h>
26 #include <drm/bridge/dw_hdmi.h>
27
28 #include "dw_hdmi.h"
29
30 #define HDMI_EDID_LEN 512
31
32 #define RGB 0
33 #define YCBCR444 1
34 #define YCBCR422_16BITS 2
35 #define YCBCR422_8BITS 3
36 #define XVYCC444 4
37
38 enum hdmi_datamap {
39 RGB444_8B = 0x01,
40 RGB444_10B = 0x03,
41 RGB444_12B = 0x05,
42 RGB444_16B = 0x07,
43 YCbCr444_8B = 0x09,
44 YCbCr444_10B = 0x0B,
45 YCbCr444_12B = 0x0D,
46 YCbCr444_16B = 0x0F,
47 YCbCr422_8B = 0x16,
48 YCbCr422_10B = 0x14,
49 YCbCr422_12B = 0x12,
50 };
51
52 static const u16 csc_coeff_default[3][4] = {
53 { 0x2000, 0x0000, 0x0000, 0x0000 },
54 { 0x0000, 0x2000, 0x0000, 0x0000 },
55 { 0x0000, 0x0000, 0x2000, 0x0000 }
56 };
57
58 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
59 { 0x2000, 0x6926, 0x74fd, 0x010e },
60 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
61 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
62 };
63
64 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
65 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
66 { 0x2000, 0x3264, 0x0000, 0x7e6d },
67 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
68 };
69
70 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
71 { 0x2591, 0x1322, 0x074b, 0x0000 },
72 { 0x6535, 0x2000, 0x7acc, 0x0200 },
73 { 0x6acd, 0x7534, 0x2000, 0x0200 }
74 };
75
76 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
77 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
78 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
79 { 0x6756, 0x78ab, 0x2000, 0x0200 }
80 };
81
82 struct hdmi_vmode {
83 bool mdvi;
84 bool mhsyncpolarity;
85 bool mvsyncpolarity;
86 bool minterlaced;
87 bool mdataenablepolarity;
88
89 unsigned int mpixelclock;
90 unsigned int mpixelrepetitioninput;
91 unsigned int mpixelrepetitionoutput;
92 };
93
94 struct hdmi_data_info {
95 unsigned int enc_in_format;
96 unsigned int enc_out_format;
97 unsigned int enc_color_depth;
98 unsigned int colorimetry;
99 unsigned int pix_repet_factor;
100 unsigned int hdcp_enable;
101 struct hdmi_vmode video_mode;
102 };
103
104 struct dw_hdmi {
105 struct drm_connector connector;
106 struct drm_encoder *encoder;
107 struct drm_bridge *bridge;
108
109 enum dw_hdmi_devtype dev_type;
110 struct device *dev;
111 struct clk *isfr_clk;
112 struct clk *iahb_clk;
113
114 struct hdmi_data_info hdmi_data;
115 const struct dw_hdmi_plat_data *plat_data;
116
117 int vic;
118
119 u8 edid[HDMI_EDID_LEN];
120 bool cable_plugin;
121
122 bool phy_enabled;
123 struct drm_display_mode previous_mode;
124
125 struct regmap *regmap;
126 struct i2c_adapter *ddc;
127 void __iomem *regs;
128
129 unsigned int sample_rate;
130 int ratio;
131 };
132
133 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
134 {
135 writeb(val, hdmi->regs + offset);
136 }
137
138 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
139 {
140 return readb(hdmi->regs + offset);
141 }
142
143 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
144 {
145 u8 val = hdmi_readb(hdmi, reg) & ~mask;
146
147 val |= data & mask;
148 hdmi_writeb(hdmi, val, reg);
149 }
150
151 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
152 u8 shift, u8 mask)
153 {
154 hdmi_modb(hdmi, data << shift, mask, reg);
155 }
156
157 static void hdmi_set_clock_regenerator_n(struct dw_hdmi *hdmi,
158 unsigned int value)
159 {
160 hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1);
161 hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2);
162 hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3);
163
164 /* nshift factor = 0 */
165 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
166 }
167
168 static void hdmi_regenerate_cts(struct dw_hdmi *hdmi, unsigned int cts)
169 {
170 /* Must be set/cleared first */
171 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
172
173 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
174 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
175 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
176 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
177 }
178
179 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
180 unsigned int ratio)
181 {
182 unsigned int n = (128 * freq) / 1000;
183
184 switch (freq) {
185 case 32000:
186 if (pixel_clk == 25170000)
187 n = (ratio == 150) ? 9152 : 4576;
188 else if (pixel_clk == 27020000)
189 n = (ratio == 150) ? 8192 : 4096;
190 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
191 n = 11648;
192 else
193 n = 4096;
194 break;
195
196 case 44100:
197 if (pixel_clk == 25170000)
198 n = 7007;
199 else if (pixel_clk == 74170000)
200 n = 17836;
201 else if (pixel_clk == 148350000)
202 n = (ratio == 150) ? 17836 : 8918;
203 else
204 n = 6272;
205 break;
206
207 case 48000:
208 if (pixel_clk == 25170000)
209 n = (ratio == 150) ? 9152 : 6864;
210 else if (pixel_clk == 27020000)
211 n = (ratio == 150) ? 8192 : 6144;
212 else if (pixel_clk == 74170000)
213 n = 11648;
214 else if (pixel_clk == 148350000)
215 n = (ratio == 150) ? 11648 : 5824;
216 else
217 n = 6144;
218 break;
219
220 case 88200:
221 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
222 break;
223
224 case 96000:
225 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
226 break;
227
228 case 176400:
229 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
230 break;
231
232 case 192000:
233 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
234 break;
235
236 default:
237 break;
238 }
239
240 return n;
241 }
242
243 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
244 unsigned int ratio)
245 {
246 unsigned int cts = 0;
247
248 pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
249 pixel_clk, ratio);
250
251 switch (freq) {
252 case 32000:
253 if (pixel_clk == 297000000) {
254 cts = 222750;
255 break;
256 }
257 case 48000:
258 case 96000:
259 case 192000:
260 switch (pixel_clk) {
261 case 25200000:
262 case 27000000:
263 case 54000000:
264 case 74250000:
265 case 148500000:
266 cts = pixel_clk / 1000;
267 break;
268 case 297000000:
269 cts = 247500;
270 break;
271 /*
272 * All other TMDS clocks are not supported by
273 * DWC_hdmi_tx. The TMDS clocks divided or
274 * multiplied by 1,001 coefficients are not
275 * supported.
276 */
277 default:
278 break;
279 }
280 break;
281 case 44100:
282 case 88200:
283 case 176400:
284 switch (pixel_clk) {
285 case 25200000:
286 cts = 28000;
287 break;
288 case 27000000:
289 cts = 30000;
290 break;
291 case 54000000:
292 cts = 60000;
293 break;
294 case 74250000:
295 cts = 82500;
296 break;
297 case 148500000:
298 cts = 165000;
299 break;
300 case 297000000:
301 cts = 247500;
302 break;
303 default:
304 break;
305 }
306 break;
307 default:
308 break;
309 }
310 if (ratio == 100)
311 return cts;
312 return (cts * ratio) / 100;
313 }
314
315 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
316 unsigned long pixel_clk)
317 {
318 unsigned int clk_n, clk_cts;
319
320 clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
321 hdmi->ratio);
322 clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
323 hdmi->ratio);
324
325 if (!clk_cts) {
326 dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
327 __func__, pixel_clk);
328 return;
329 }
330
331 dev_dbg(hdmi->dev, "%s: samplerate=%d ratio=%d pixelclk=%lu N=%d cts=%d\n",
332 __func__, hdmi->sample_rate, hdmi->ratio,
333 pixel_clk, clk_n, clk_cts);
334
335 hdmi_set_clock_regenerator_n(hdmi, clk_n);
336 hdmi_regenerate_cts(hdmi, clk_cts);
337 }
338
339 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
340 {
341 hdmi_set_clk_regenerator(hdmi, 74250000);
342 }
343
344 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
345 {
346 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
347 }
348
349 /*
350 * this submodule is responsible for the video data synchronization.
351 * for example, for RGB 4:4:4 input, the data map is defined as
352 * pin{47~40} <==> R[7:0]
353 * pin{31~24} <==> G[7:0]
354 * pin{15~8} <==> B[7:0]
355 */
356 static void hdmi_video_sample(struct dw_hdmi *hdmi)
357 {
358 int color_format = 0;
359 u8 val;
360
361 if (hdmi->hdmi_data.enc_in_format == RGB) {
362 if (hdmi->hdmi_data.enc_color_depth == 8)
363 color_format = 0x01;
364 else if (hdmi->hdmi_data.enc_color_depth == 10)
365 color_format = 0x03;
366 else if (hdmi->hdmi_data.enc_color_depth == 12)
367 color_format = 0x05;
368 else if (hdmi->hdmi_data.enc_color_depth == 16)
369 color_format = 0x07;
370 else
371 return;
372 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
373 if (hdmi->hdmi_data.enc_color_depth == 8)
374 color_format = 0x09;
375 else if (hdmi->hdmi_data.enc_color_depth == 10)
376 color_format = 0x0B;
377 else if (hdmi->hdmi_data.enc_color_depth == 12)
378 color_format = 0x0D;
379 else if (hdmi->hdmi_data.enc_color_depth == 16)
380 color_format = 0x0F;
381 else
382 return;
383 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
384 if (hdmi->hdmi_data.enc_color_depth == 8)
385 color_format = 0x16;
386 else if (hdmi->hdmi_data.enc_color_depth == 10)
387 color_format = 0x14;
388 else if (hdmi->hdmi_data.enc_color_depth == 12)
389 color_format = 0x12;
390 else
391 return;
392 }
393
394 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
395 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
396 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
397 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
398
399 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
400 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
401 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
402 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
403 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
404 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
405 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
406 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
407 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
408 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
409 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
410 }
411
412 static int is_color_space_conversion(struct dw_hdmi *hdmi)
413 {
414 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
415 }
416
417 static int is_color_space_decimation(struct dw_hdmi *hdmi)
418 {
419 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
420 return 0;
421 if (hdmi->hdmi_data.enc_in_format == RGB ||
422 hdmi->hdmi_data.enc_in_format == YCBCR444)
423 return 1;
424 return 0;
425 }
426
427 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
428 {
429 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
430 return 0;
431 if (hdmi->hdmi_data.enc_out_format == RGB ||
432 hdmi->hdmi_data.enc_out_format == YCBCR444)
433 return 1;
434 return 0;
435 }
436
437 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
438 {
439 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
440 unsigned i;
441 u32 csc_scale = 1;
442
443 if (is_color_space_conversion(hdmi)) {
444 if (hdmi->hdmi_data.enc_out_format == RGB) {
445 if (hdmi->hdmi_data.colorimetry ==
446 HDMI_COLORIMETRY_ITU_601)
447 csc_coeff = &csc_coeff_rgb_out_eitu601;
448 else
449 csc_coeff = &csc_coeff_rgb_out_eitu709;
450 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
451 if (hdmi->hdmi_data.colorimetry ==
452 HDMI_COLORIMETRY_ITU_601)
453 csc_coeff = &csc_coeff_rgb_in_eitu601;
454 else
455 csc_coeff = &csc_coeff_rgb_in_eitu709;
456 csc_scale = 0;
457 }
458 }
459
460 /* The CSC registers are sequential, alternating MSB then LSB */
461 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
462 u16 coeff_a = (*csc_coeff)[0][i];
463 u16 coeff_b = (*csc_coeff)[1][i];
464 u16 coeff_c = (*csc_coeff)[2][i];
465
466 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
467 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
468 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
469 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
470 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
471 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
472 }
473
474 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
475 HDMI_CSC_SCALE);
476 }
477
478 static void hdmi_video_csc(struct dw_hdmi *hdmi)
479 {
480 int color_depth = 0;
481 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
482 int decimation = 0;
483
484 /* YCC422 interpolation to 444 mode */
485 if (is_color_space_interpolation(hdmi))
486 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
487 else if (is_color_space_decimation(hdmi))
488 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
489
490 if (hdmi->hdmi_data.enc_color_depth == 8)
491 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
492 else if (hdmi->hdmi_data.enc_color_depth == 10)
493 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
494 else if (hdmi->hdmi_data.enc_color_depth == 12)
495 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
496 else if (hdmi->hdmi_data.enc_color_depth == 16)
497 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
498 else
499 return;
500
501 /* Configure the CSC registers */
502 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
503 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
504 HDMI_CSC_SCALE);
505
506 dw_hdmi_update_csc_coeffs(hdmi);
507 }
508
509 /*
510 * HDMI video packetizer is used to packetize the data.
511 * for example, if input is YCC422 mode or repeater is used,
512 * data should be repacked this module can be bypassed.
513 */
514 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
515 {
516 unsigned int color_depth = 0;
517 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
518 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
519 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
520 u8 val, vp_conf;
521
522 if (hdmi_data->enc_out_format == RGB ||
523 hdmi_data->enc_out_format == YCBCR444) {
524 if (!hdmi_data->enc_color_depth) {
525 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
526 } else if (hdmi_data->enc_color_depth == 8) {
527 color_depth = 4;
528 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
529 } else if (hdmi_data->enc_color_depth == 10) {
530 color_depth = 5;
531 } else if (hdmi_data->enc_color_depth == 12) {
532 color_depth = 6;
533 } else if (hdmi_data->enc_color_depth == 16) {
534 color_depth = 7;
535 } else {
536 return;
537 }
538 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
539 if (!hdmi_data->enc_color_depth ||
540 hdmi_data->enc_color_depth == 8)
541 remap_size = HDMI_VP_REMAP_YCC422_16bit;
542 else if (hdmi_data->enc_color_depth == 10)
543 remap_size = HDMI_VP_REMAP_YCC422_20bit;
544 else if (hdmi_data->enc_color_depth == 12)
545 remap_size = HDMI_VP_REMAP_YCC422_24bit;
546 else
547 return;
548 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
549 } else {
550 return;
551 }
552
553 /* set the packetizer registers */
554 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
555 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
556 ((hdmi_data->pix_repet_factor <<
557 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
558 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
559 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
560
561 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
562 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
563
564 /* Data from pixel repeater block */
565 if (hdmi_data->pix_repet_factor > 1) {
566 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
567 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
568 } else { /* data from packetizer block */
569 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
570 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
571 }
572
573 hdmi_modb(hdmi, vp_conf,
574 HDMI_VP_CONF_PR_EN_MASK |
575 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
576
577 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
578 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
579
580 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
581
582 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
583 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
584 HDMI_VP_CONF_PP_EN_ENABLE |
585 HDMI_VP_CONF_YCC422_EN_DISABLE;
586 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
587 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
588 HDMI_VP_CONF_PP_EN_DISABLE |
589 HDMI_VP_CONF_YCC422_EN_ENABLE;
590 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
591 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
592 HDMI_VP_CONF_PP_EN_DISABLE |
593 HDMI_VP_CONF_YCC422_EN_DISABLE;
594 } else {
595 return;
596 }
597
598 hdmi_modb(hdmi, vp_conf,
599 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
600 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
601
602 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
603 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
604 HDMI_VP_STUFF_PP_STUFFING_MASK |
605 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
606
607 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
608 HDMI_VP_CONF);
609 }
610
611 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
612 unsigned char bit)
613 {
614 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
615 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
616 }
617
618 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
619 unsigned char bit)
620 {
621 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
622 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
623 }
624
625 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
626 unsigned char bit)
627 {
628 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
629 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
630 }
631
632 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
633 unsigned char bit)
634 {
635 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
636 }
637
638 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
639 unsigned char bit)
640 {
641 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
642 }
643
644 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
645 {
646 while ((hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
647 if (msec-- == 0)
648 return false;
649 udelay(1000);
650 }
651 return true;
652 }
653
654 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
655 unsigned char addr)
656 {
657 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
658 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
659 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
660 HDMI_PHY_I2CM_DATAO_1_ADDR);
661 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
662 HDMI_PHY_I2CM_DATAO_0_ADDR);
663 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
664 HDMI_PHY_I2CM_OPERATION_ADDR);
665 hdmi_phy_wait_i2c_done(hdmi, 1000);
666 }
667
668 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
669 unsigned char addr)
670 {
671 __hdmi_phy_i2c_write(hdmi, data, addr);
672 return 0;
673 }
674
675 static void dw_hdmi_phy_enable_power(struct dw_hdmi *hdmi, u8 enable)
676 {
677 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
678 HDMI_PHY_CONF0_PDZ_OFFSET,
679 HDMI_PHY_CONF0_PDZ_MASK);
680 }
681
682 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
683 {
684 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
685 HDMI_PHY_CONF0_ENTMDS_OFFSET,
686 HDMI_PHY_CONF0_ENTMDS_MASK);
687 }
688
689 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
690 {
691 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
692 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
693 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
694 }
695
696 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
697 {
698 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
699 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
700 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
701 }
702
703 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
704 {
705 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
706 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
707 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
708 }
709
710 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
711 {
712 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
713 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
714 HDMI_PHY_CONF0_SELDIPIF_MASK);
715 }
716
717 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
718 unsigned char res, int cscon)
719 {
720 unsigned res_idx, i;
721 u8 val, msec;
722 const struct dw_hdmi_mpll_config *mpll_config =
723 hdmi->plat_data->mpll_cfg;
724 const struct dw_hdmi_curr_ctrl *curr_ctrl = hdmi->plat_data->cur_ctr;
725 const struct dw_hdmi_sym_term *sym_term = hdmi->plat_data->sym_term;
726
727 if (prep)
728 return -EINVAL;
729
730 switch (res) {
731 case 0: /* color resolution 0 is 8 bit colour depth */
732 case 8:
733 res_idx = DW_HDMI_RES_8;
734 break;
735 case 10:
736 res_idx = DW_HDMI_RES_10;
737 break;
738 case 12:
739 res_idx = DW_HDMI_RES_12;
740 break;
741 default:
742 return -EINVAL;
743 }
744
745 /* Enable csc path */
746 if (cscon)
747 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
748 else
749 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
750
751 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
752
753 /* gen2 tx power off */
754 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
755
756 /* gen2 pddq */
757 dw_hdmi_phy_gen2_pddq(hdmi, 1);
758
759 /* PHY reset */
760 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
761 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
762
763 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
764
765 hdmi_phy_test_clear(hdmi, 1);
766 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
767 HDMI_PHY_I2CM_SLAVE_ADDR);
768 hdmi_phy_test_clear(hdmi, 0);
769
770 /* PLL/MPLL Cfg - always match on final entry */
771 for (i = 0; mpll_config[i].mpixelclock != (~0UL); i++)
772 if (hdmi->hdmi_data.video_mode.mpixelclock <=
773 mpll_config[i].mpixelclock)
774 break;
775
776 hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
777 hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
778
779 for (i = 0; curr_ctrl[i].mpixelclock != (~0UL); i++)
780 if (hdmi->hdmi_data.video_mode.mpixelclock <=
781 curr_ctrl[i].mpixelclock)
782 break;
783
784 if (curr_ctrl[i].mpixelclock == (~0UL)) {
785 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
786 hdmi->hdmi_data.video_mode.mpixelclock);
787 return -EINVAL;
788 }
789
790 /* CURRCTRL */
791 hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
792
793 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
794 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
795
796 for (i = 0; sym_term[i].mpixelclock != (~0UL); i++)
797 if (hdmi->hdmi_data.video_mode.mpixelclock <=
798 sym_term[i].mpixelclock)
799 break;
800
801 /* RESISTANCE TERM 133Ohm Cfg */
802 hdmi_phy_i2c_write(hdmi, sym_term[i].term, 0x19); /* TXTERM */
803 /* PREEMP Cgf 0.00 */
804 hdmi_phy_i2c_write(hdmi, sym_term[i].sym_ctr, 0x09); /* CKSYMTXCTRL */
805
806 /* TX/CK LVL 10 */
807 hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
808 /* REMOVE CLK TERM */
809 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
810
811 dw_hdmi_phy_enable_power(hdmi, 1);
812
813 /* toggle TMDS enable */
814 dw_hdmi_phy_enable_tmds(hdmi, 0);
815 dw_hdmi_phy_enable_tmds(hdmi, 1);
816
817 /* gen2 tx power on */
818 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
819 dw_hdmi_phy_gen2_pddq(hdmi, 0);
820
821 /*Wait for PHY PLL lock */
822 msec = 5;
823 do {
824 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
825 if (!val)
826 break;
827
828 if (msec == 0) {
829 dev_err(hdmi->dev, "PHY PLL not locked\n");
830 return -ETIMEDOUT;
831 }
832
833 udelay(1000);
834 msec--;
835 } while (1);
836
837 return 0;
838 }
839
840 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
841 {
842 int i, ret;
843 bool cscon = false;
844
845 /*check csc whether needed activated in HDMI mode */
846 cscon = (is_color_space_conversion(hdmi) &&
847 !hdmi->hdmi_data.video_mode.mdvi);
848
849 /* HDMI Phy spec says to do the phy initialization sequence twice */
850 for (i = 0; i < 2; i++) {
851 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
852 dw_hdmi_phy_sel_interface_control(hdmi, 0);
853 dw_hdmi_phy_enable_tmds(hdmi, 0);
854 dw_hdmi_phy_enable_power(hdmi, 0);
855
856 /* Enable CSC */
857 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
858 if (ret)
859 return ret;
860 }
861
862 hdmi->phy_enabled = true;
863 return 0;
864 }
865
866 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
867 {
868 u8 de;
869
870 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
871 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
872 else
873 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
874
875 /* disable rx detect */
876 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
877 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
878
879 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
880
881 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
882 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
883 }
884
885 static void hdmi_config_AVI(struct dw_hdmi *hdmi)
886 {
887 u8 val, pix_fmt, under_scan;
888 u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
889 bool aspect_16_9;
890
891 aspect_16_9 = false; /* FIXME */
892
893 /* AVI Data Byte 1 */
894 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
895 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
896 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
897 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
898 else
899 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
900
901 under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
902
903 /*
904 * Active format identification data is present in the AVI InfoFrame.
905 * Under scan info, no bar data
906 */
907 val = pix_fmt | under_scan |
908 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
909 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
910
911 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
912
913 /* AVI Data Byte 2 -Set the Aspect Ratio */
914 if (aspect_16_9) {
915 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
916 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
917 } else {
918 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
919 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
920 }
921
922 /* Set up colorimetry */
923 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
924 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
925 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
926 ext_colorimetry =
927 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
928 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
929 ext_colorimetry =
930 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
931 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
932 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
933 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
934 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
935 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
936 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
937 } else { /* Carries no data */
938 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
939 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
940 }
941
942 val = colorimetry | coded_ratio | act_ratio;
943 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
944
945 /* AVI Data Byte 3 */
946 val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
947 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
948 HDMI_FC_AVICONF2_SCALING_NONE;
949 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
950
951 /* AVI Data Byte 4 */
952 hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
953
954 /* AVI Data Byte 5- set up input and output pixel repetition */
955 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
956 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
957 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
958 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
959 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
960 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
961 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
962
963 /* IT Content and quantization range = don't care */
964 val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
965 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
966 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
967
968 /* AVI Data Bytes 6-13 */
969 hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
970 hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
971 hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
972 hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
973 hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
974 hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
975 hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
976 hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
977 }
978
979 static void hdmi_av_composer(struct dw_hdmi *hdmi,
980 const struct drm_display_mode *mode)
981 {
982 u8 inv_val;
983 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
984 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
985
986 vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
987 vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
988 vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
989 vmode->mpixelclock = mode->clock * 1000;
990
991 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
992
993 /* Set up HDMI_FC_INVIDCONF */
994 inv_val = (hdmi->hdmi_data.hdcp_enable ?
995 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
996 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
997
998 inv_val |= (vmode->mvsyncpolarity ?
999 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1000 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1001
1002 inv_val |= (vmode->mhsyncpolarity ?
1003 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1004 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1005
1006 inv_val |= (vmode->mdataenablepolarity ?
1007 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1008 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1009
1010 if (hdmi->vic == 39)
1011 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1012 else
1013 inv_val |= (vmode->minterlaced ?
1014 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1015 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1016
1017 inv_val |= (vmode->minterlaced ?
1018 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1019 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1020
1021 inv_val |= (vmode->mdvi ?
1022 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1023 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1024
1025 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1026
1027 /* Set up horizontal active pixel width */
1028 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1029 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1030
1031 /* Set up vertical active lines */
1032 hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1033 hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1034
1035 /* Set up horizontal blanking pixel region width */
1036 hblank = mode->htotal - mode->hdisplay;
1037 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1038 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1039
1040 /* Set up vertical blanking pixel region width */
1041 vblank = mode->vtotal - mode->vdisplay;
1042 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1043
1044 /* Set up HSYNC active edge delay width (in pixel clks) */
1045 h_de_hs = mode->hsync_start - mode->hdisplay;
1046 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1047 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1048
1049 /* Set up VSYNC active edge delay (in lines) */
1050 v_de_vs = mode->vsync_start - mode->vdisplay;
1051 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1052
1053 /* Set up HSYNC active pulse width (in pixel clks) */
1054 hsync_len = mode->hsync_end - mode->hsync_start;
1055 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1056 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1057
1058 /* Set up VSYNC active edge delay (in lines) */
1059 vsync_len = mode->vsync_end - mode->vsync_start;
1060 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1061 }
1062
1063 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1064 {
1065 if (!hdmi->phy_enabled)
1066 return;
1067
1068 dw_hdmi_phy_enable_tmds(hdmi, 0);
1069 dw_hdmi_phy_enable_power(hdmi, 0);
1070
1071 hdmi->phy_enabled = false;
1072 }
1073
1074 /* HDMI Initialization Step B.4 */
1075 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1076 {
1077 u8 clkdis;
1078
1079 /* control period minimum duration */
1080 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1081 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1082 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1083
1084 /* Set to fill TMDS data channels */
1085 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1086 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1087 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1088
1089 /* Enable pixel clock and tmds data path */
1090 clkdis = 0x7F;
1091 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1092 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1093
1094 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1095 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1096
1097 /* Enable csc path */
1098 if (is_color_space_conversion(hdmi)) {
1099 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1100 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1101 }
1102 }
1103
1104 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1105 {
1106 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1107 }
1108
1109 /* Workaround to clear the overflow condition */
1110 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1111 {
1112 int count;
1113 u8 val;
1114
1115 /* TMDS software reset */
1116 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1117
1118 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1119 if (hdmi->dev_type == IMX6DL_HDMI) {
1120 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1121 return;
1122 }
1123
1124 for (count = 0; count < 4; count++)
1125 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1126 }
1127
1128 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1129 {
1130 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1131 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1132 }
1133
1134 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1135 {
1136 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1137 HDMI_IH_MUTE_FC_STAT2);
1138 }
1139
1140 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1141 {
1142 int ret;
1143
1144 hdmi_disable_overflow_interrupts(hdmi);
1145
1146 hdmi->vic = drm_match_cea_mode(mode);
1147
1148 if (!hdmi->vic) {
1149 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1150 hdmi->hdmi_data.video_mode.mdvi = true;
1151 } else {
1152 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1153 hdmi->hdmi_data.video_mode.mdvi = false;
1154 }
1155
1156 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1157 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1158 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1159 (hdmi->vic == 17) || (hdmi->vic == 18))
1160 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1161 else
1162 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1163
1164 if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
1165 (hdmi->vic == 12) || (hdmi->vic == 13) ||
1166 (hdmi->vic == 14) || (hdmi->vic == 15) ||
1167 (hdmi->vic == 25) || (hdmi->vic == 26) ||
1168 (hdmi->vic == 27) || (hdmi->vic == 28) ||
1169 (hdmi->vic == 29) || (hdmi->vic == 30) ||
1170 (hdmi->vic == 35) || (hdmi->vic == 36) ||
1171 (hdmi->vic == 37) || (hdmi->vic == 38))
1172 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1173 else
1174 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1175
1176 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1177
1178 /* TODO: Get input format from IPU (via FB driver interface) */
1179 hdmi->hdmi_data.enc_in_format = RGB;
1180
1181 hdmi->hdmi_data.enc_out_format = RGB;
1182
1183 hdmi->hdmi_data.enc_color_depth = 8;
1184 hdmi->hdmi_data.pix_repet_factor = 0;
1185 hdmi->hdmi_data.hdcp_enable = 0;
1186 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1187
1188 /* HDMI Initialization Step B.1 */
1189 hdmi_av_composer(hdmi, mode);
1190
1191 /* HDMI Initializateion Step B.2 */
1192 ret = dw_hdmi_phy_init(hdmi);
1193 if (ret)
1194 return ret;
1195
1196 /* HDMI Initialization Step B.3 */
1197 dw_hdmi_enable_video_path(hdmi);
1198
1199 /* not for DVI mode */
1200 if (hdmi->hdmi_data.video_mode.mdvi) {
1201 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1202 } else {
1203 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1204
1205 /* HDMI Initialization Step E - Configure audio */
1206 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1207 hdmi_enable_audio_clk(hdmi);
1208
1209 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1210 hdmi_config_AVI(hdmi);
1211 }
1212
1213 hdmi_video_packetize(hdmi);
1214 hdmi_video_csc(hdmi);
1215 hdmi_video_sample(hdmi);
1216 hdmi_tx_hdcp_config(hdmi);
1217
1218 dw_hdmi_clear_overflow(hdmi);
1219 if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1220 hdmi_enable_overflow_interrupts(hdmi);
1221
1222 return 0;
1223 }
1224
1225 /* Wait until we are registered to enable interrupts */
1226 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1227 {
1228 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1229 HDMI_PHY_I2CM_INT_ADDR);
1230
1231 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1232 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1233 HDMI_PHY_I2CM_CTLINT_ADDR);
1234
1235 /* enable cable hot plug irq */
1236 hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1237
1238 /* Clear Hotplug interrupts */
1239 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1240
1241 return 0;
1242 }
1243
1244 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1245 {
1246 u8 ih_mute;
1247
1248 /*
1249 * Boot up defaults are:
1250 * HDMI_IH_MUTE = 0x03 (disabled)
1251 * HDMI_IH_MUTE_* = 0x00 (enabled)
1252 *
1253 * Disable top level interrupt bits in HDMI block
1254 */
1255 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1256 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1257 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1258
1259 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1260
1261 /* by default mask all interrupts */
1262 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1263 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1264 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1265 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1266 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1267 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1268 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1269 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1270 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1271 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1272 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1273 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1274 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1275 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1276 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1277
1278 /* Disable interrupts in the IH_MUTE_* registers */
1279 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1280 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1281 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1282 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1283 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1284 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1285 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1286 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1287 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1288 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1289
1290 /* Enable top level interrupt bits in HDMI block */
1291 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1292 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1293 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1294 }
1295
1296 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1297 {
1298 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1299 }
1300
1301 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1302 {
1303 dw_hdmi_phy_disable(hdmi);
1304 }
1305
1306 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1307 struct drm_display_mode *mode,
1308 struct drm_display_mode *adjusted_mode)
1309 {
1310 struct dw_hdmi *hdmi = bridge->driver_private;
1311
1312 dw_hdmi_setup(hdmi, mode);
1313
1314 /* Store the display mode for plugin/DKMS poweron events */
1315 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1316 }
1317
1318 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1319 const struct drm_display_mode *mode,
1320 struct drm_display_mode *adjusted_mode)
1321 {
1322 return true;
1323 }
1324
1325 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1326 {
1327 struct dw_hdmi *hdmi = bridge->driver_private;
1328
1329 dw_hdmi_poweroff(hdmi);
1330 }
1331
1332 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1333 {
1334 struct dw_hdmi *hdmi = bridge->driver_private;
1335
1336 dw_hdmi_poweron(hdmi);
1337 }
1338
1339 static void dw_hdmi_bridge_destroy(struct drm_bridge *bridge)
1340 {
1341 drm_bridge_cleanup(bridge);
1342 kfree(bridge);
1343 }
1344
1345 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1346 {
1347 /* do nothing */
1348 }
1349
1350 static enum drm_connector_status
1351 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1352 {
1353 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1354 connector);
1355
1356 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1357 connector_status_connected : connector_status_disconnected;
1358 }
1359
1360 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1361 {
1362 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1363 connector);
1364 struct edid *edid;
1365 int ret;
1366
1367 if (!hdmi->ddc)
1368 return 0;
1369
1370 edid = drm_get_edid(connector, hdmi->ddc);
1371 if (edid) {
1372 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1373 edid->width_cm, edid->height_cm);
1374
1375 drm_mode_connector_update_edid_property(connector, edid);
1376 ret = drm_add_edid_modes(connector, edid);
1377 kfree(edid);
1378 } else {
1379 dev_dbg(hdmi->dev, "failed to get edid\n");
1380 }
1381
1382 return 0;
1383 }
1384
1385 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1386 *connector)
1387 {
1388 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1389 connector);
1390
1391 return hdmi->encoder;
1392 }
1393
1394 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1395 {
1396 drm_connector_unregister(connector);
1397 drm_connector_cleanup(connector);
1398 }
1399
1400 static struct drm_connector_funcs dw_hdmi_connector_funcs = {
1401 .dpms = drm_helper_connector_dpms,
1402 .fill_modes = drm_helper_probe_single_connector_modes,
1403 .detect = dw_hdmi_connector_detect,
1404 .destroy = dw_hdmi_connector_destroy,
1405 };
1406
1407 static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1408 .get_modes = dw_hdmi_connector_get_modes,
1409 .best_encoder = dw_hdmi_connector_best_encoder,
1410 };
1411
1412 struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1413 .enable = dw_hdmi_bridge_enable,
1414 .disable = dw_hdmi_bridge_disable,
1415 .pre_enable = dw_hdmi_bridge_nop,
1416 .post_disable = dw_hdmi_bridge_nop,
1417 .mode_set = dw_hdmi_bridge_mode_set,
1418 .mode_fixup = dw_hdmi_bridge_mode_fixup,
1419 .destroy = dw_hdmi_bridge_destroy,
1420 };
1421
1422 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1423 {
1424 struct dw_hdmi *hdmi = dev_id;
1425 u8 intr_stat;
1426
1427 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1428 if (intr_stat)
1429 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1430
1431 return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1432 }
1433
1434 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1435 {
1436 struct dw_hdmi *hdmi = dev_id;
1437 u8 intr_stat;
1438 u8 phy_int_pol;
1439
1440 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1441
1442 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1443
1444 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1445 if (phy_int_pol & HDMI_PHY_HPD) {
1446 dev_dbg(hdmi->dev, "EVENT=plugin\n");
1447
1448 hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1449
1450 dw_hdmi_poweron(hdmi);
1451 } else {
1452 dev_dbg(hdmi->dev, "EVENT=plugout\n");
1453
1454 hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1455 HDMI_PHY_POL0);
1456
1457 dw_hdmi_poweroff(hdmi);
1458 }
1459 drm_helper_hpd_irq_event(hdmi->connector.dev);
1460 }
1461
1462 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1463 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1464
1465 return IRQ_HANDLED;
1466 }
1467
1468 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1469 {
1470 struct drm_encoder *encoder = hdmi->encoder;
1471 struct drm_bridge *bridge;
1472 int ret;
1473
1474 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1475 if (!bridge) {
1476 DRM_ERROR("Failed to allocate drm bridge\n");
1477 return -ENOMEM;
1478 }
1479
1480 hdmi->bridge = bridge;
1481 bridge->driver_private = hdmi;
1482
1483 ret = drm_bridge_init(drm, bridge, &dw_hdmi_bridge_funcs);
1484 if (ret) {
1485 DRM_ERROR("Failed to initialize bridge with drm\n");
1486 return -EINVAL;
1487 }
1488
1489 encoder->bridge = bridge;
1490 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1491
1492 drm_connector_helper_add(&hdmi->connector,
1493 &dw_hdmi_connector_helper_funcs);
1494 drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1495 DRM_MODE_CONNECTOR_HDMIA);
1496
1497 hdmi->connector.encoder = encoder;
1498
1499 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1500
1501 return 0;
1502 }
1503
1504 int dw_hdmi_bind(struct device *dev, struct device *master,
1505 void *data, struct drm_encoder *encoder,
1506 struct resource *iores, int irq,
1507 const struct dw_hdmi_plat_data *plat_data)
1508 {
1509 struct drm_device *drm = data;
1510 struct device_node *np = dev->of_node;
1511 struct device_node *ddc_node;
1512 struct dw_hdmi *hdmi;
1513 int ret;
1514
1515 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1516 if (!hdmi)
1517 return -ENOMEM;
1518
1519 hdmi->plat_data = plat_data;
1520 hdmi->dev = dev;
1521 hdmi->dev_type = plat_data->dev_type;
1522 hdmi->sample_rate = 48000;
1523 hdmi->ratio = 100;
1524 hdmi->encoder = encoder;
1525
1526 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1527 if (ddc_node) {
1528 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1529 of_node_put(ddc_node);
1530 if (!hdmi->ddc) {
1531 dev_dbg(hdmi->dev, "failed to read ddc node\n");
1532 return -EPROBE_DEFER;
1533 }
1534
1535 } else {
1536 dev_dbg(hdmi->dev, "no ddc property found\n");
1537 }
1538
1539 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1540 dw_hdmi_irq, IRQF_SHARED,
1541 dev_name(dev), hdmi);
1542 if (ret)
1543 return ret;
1544
1545 hdmi->regs = devm_ioremap_resource(dev, iores);
1546 if (IS_ERR(hdmi->regs))
1547 return PTR_ERR(hdmi->regs);
1548
1549 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1550 if (IS_ERR(hdmi->isfr_clk)) {
1551 ret = PTR_ERR(hdmi->isfr_clk);
1552 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1553 return ret;
1554 }
1555
1556 ret = clk_prepare_enable(hdmi->isfr_clk);
1557 if (ret) {
1558 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1559 return ret;
1560 }
1561
1562 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1563 if (IS_ERR(hdmi->iahb_clk)) {
1564 ret = PTR_ERR(hdmi->iahb_clk);
1565 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1566 goto err_isfr;
1567 }
1568
1569 ret = clk_prepare_enable(hdmi->iahb_clk);
1570 if (ret) {
1571 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1572 goto err_isfr;
1573 }
1574
1575 /* Product and revision IDs */
1576 dev_info(dev,
1577 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1578 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1579 hdmi_readb(hdmi, HDMI_REVISION_ID),
1580 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1581 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1582
1583 initialize_hdmi_ih_mutes(hdmi);
1584
1585 /*
1586 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1587 * N and cts values before enabling phy
1588 */
1589 hdmi_init_clk_regenerator(hdmi);
1590
1591 /*
1592 * Configure registers related to HDMI interrupt
1593 * generation before registering IRQ.
1594 */
1595 hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1596
1597 /* Clear Hotplug interrupts */
1598 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1599
1600 ret = dw_hdmi_fb_registered(hdmi);
1601 if (ret)
1602 goto err_iahb;
1603
1604 ret = dw_hdmi_register(drm, hdmi);
1605 if (ret)
1606 goto err_iahb;
1607
1608 /* Unmute interrupts */
1609 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1610
1611 dev_set_drvdata(dev, hdmi);
1612
1613 return 0;
1614
1615 err_iahb:
1616 clk_disable_unprepare(hdmi->iahb_clk);
1617 err_isfr:
1618 clk_disable_unprepare(hdmi->isfr_clk);
1619
1620 return ret;
1621 }
1622 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1623
1624 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1625 {
1626 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1627
1628 /* Disable all interrupts */
1629 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1630
1631 hdmi->connector.funcs->destroy(&hdmi->connector);
1632 hdmi->encoder->funcs->destroy(hdmi->encoder);
1633
1634 clk_disable_unprepare(hdmi->iahb_clk);
1635 clk_disable_unprepare(hdmi->isfr_clk);
1636 i2c_put_adapter(hdmi->ddc);
1637 }
1638 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1639
1640 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1641 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1642 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1643 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1644 MODULE_LICENSE("GPL");
1645 MODULE_ALIAS("platform:dw-hdmi");
Linux kernel - Deliverables
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