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drm/exynos: introduce exynos_drm_plane_state structure
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos7_drm_decon.c
1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c
2 *
3 * Copyright (C) 2014 Samsung Electronics Co.Ltd
4 * Authors:
5 * Akshu Agarwal <akshua@gmail.com>
6 * Ajay Kumar <ajaykumar.rs@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15 #include <drm/exynos_drm.h>
16
17 #include <linux/clk.h>
18 #include <linux/component.h>
19 #include <linux/kernel.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/exynos7_decon.h>
29
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_plane.h"
32 #include "exynos_drm_drv.h"
33 #include "exynos_drm_fb.h"
34 #include "exynos_drm_fbdev.h"
35 #include "exynos_drm_iommu.h"
36
37 /*
38 * DECON stands for Display and Enhancement controller.
39 */
40
41 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
42
43 #define WINDOWS_NR 2
44 #define CURSOR_WIN 1
45
46 struct decon_context {
47 struct device *dev;
48 struct drm_device *drm_dev;
49 struct exynos_drm_crtc *crtc;
50 struct exynos_drm_plane planes[WINDOWS_NR];
51 struct clk *pclk;
52 struct clk *aclk;
53 struct clk *eclk;
54 struct clk *vclk;
55 void __iomem *regs;
56 unsigned long irq_flags;
57 bool i80_if;
58 bool suspended;
59 int pipe;
60 wait_queue_head_t wait_vsync_queue;
61 atomic_t wait_vsync_event;
62
63 struct exynos_drm_panel_info panel;
64 struct drm_encoder *encoder;
65 };
66
67 static const struct of_device_id decon_driver_dt_match[] = {
68 {.compatible = "samsung,exynos7-decon"},
69 {},
70 };
71 MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
72
73 static const uint32_t decon_formats[] = {
74 DRM_FORMAT_RGB565,
75 DRM_FORMAT_XRGB8888,
76 DRM_FORMAT_XBGR8888,
77 DRM_FORMAT_RGBX8888,
78 DRM_FORMAT_BGRX8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_RGBA8888,
82 DRM_FORMAT_BGRA8888,
83 };
84
85 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
86 {
87 struct decon_context *ctx = crtc->ctx;
88
89 if (ctx->suspended)
90 return;
91
92 atomic_set(&ctx->wait_vsync_event, 1);
93
94 /*
95 * wait for DECON to signal VSYNC interrupt or return after
96 * timeout which is set to 50ms (refresh rate of 20).
97 */
98 if (!wait_event_timeout(ctx->wait_vsync_queue,
99 !atomic_read(&ctx->wait_vsync_event),
100 HZ/20))
101 DRM_DEBUG_KMS("vblank wait timed out.\n");
102 }
103
104 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
105 {
106 struct decon_context *ctx = crtc->ctx;
107 unsigned int win, ch_enabled = 0;
108
109 DRM_DEBUG_KMS("%s\n", __FILE__);
110
111 /* Check if any channel is enabled. */
112 for (win = 0; win < WINDOWS_NR; win++) {
113 u32 val = readl(ctx->regs + WINCON(win));
114
115 if (val & WINCONx_ENWIN) {
116 val &= ~WINCONx_ENWIN;
117 writel(val, ctx->regs + WINCON(win));
118 ch_enabled = 1;
119 }
120 }
121
122 /* Wait for vsync, as disable channel takes effect at next vsync */
123 if (ch_enabled)
124 decon_wait_for_vblank(ctx->crtc);
125 }
126
127 static int decon_ctx_initialize(struct decon_context *ctx,
128 struct drm_device *drm_dev)
129 {
130 struct exynos_drm_private *priv = drm_dev->dev_private;
131 int ret;
132
133 ctx->drm_dev = drm_dev;
134 ctx->pipe = priv->pipe++;
135
136 decon_clear_channels(ctx->crtc);
137
138 ret = drm_iommu_attach_device(drm_dev, ctx->dev);
139 if (ret)
140 priv->pipe--;
141
142 return ret;
143 }
144
145 static void decon_ctx_remove(struct decon_context *ctx)
146 {
147 /* detach this sub driver from iommu mapping if supported. */
148 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
149 }
150
151 static u32 decon_calc_clkdiv(struct decon_context *ctx,
152 const struct drm_display_mode *mode)
153 {
154 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
155 u32 clkdiv;
156
157 /* Find the clock divider value that gets us closest to ideal_clk */
158 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
159
160 return (clkdiv < 0x100) ? clkdiv : 0xff;
161 }
162
163 static void decon_commit(struct exynos_drm_crtc *crtc)
164 {
165 struct decon_context *ctx = crtc->ctx;
166 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
167 u32 val, clkdiv;
168
169 if (ctx->suspended)
170 return;
171
172 /* nothing to do if we haven't set the mode yet */
173 if (mode->htotal == 0 || mode->vtotal == 0)
174 return;
175
176 if (!ctx->i80_if) {
177 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
178 /* setup vertical timing values. */
179 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
180 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
181 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
182
183 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
184 writel(val, ctx->regs + VIDTCON0);
185
186 val = VIDTCON1_VSPW(vsync_len - 1);
187 writel(val, ctx->regs + VIDTCON1);
188
189 /* setup horizontal timing values. */
190 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
191 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
192 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
193
194 /* setup horizontal timing values. */
195 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
196 writel(val, ctx->regs + VIDTCON2);
197
198 val = VIDTCON3_HSPW(hsync_len - 1);
199 writel(val, ctx->regs + VIDTCON3);
200 }
201
202 /* setup horizontal and vertical display size. */
203 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
204 VIDTCON4_HOZVAL(mode->hdisplay - 1);
205 writel(val, ctx->regs + VIDTCON4);
206
207 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
208
209 /*
210 * fields of register with prefix '_F' would be updated
211 * at vsync(same as dma start)
212 */
213 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
214 writel(val, ctx->regs + VIDCON0);
215
216 clkdiv = decon_calc_clkdiv(ctx, mode);
217 if (clkdiv > 1) {
218 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
219 writel(val, ctx->regs + VCLKCON1);
220 writel(val, ctx->regs + VCLKCON2);
221 }
222
223 val = readl(ctx->regs + DECON_UPDATE);
224 val |= DECON_UPDATE_STANDALONE_F;
225 writel(val, ctx->regs + DECON_UPDATE);
226 }
227
228 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
229 {
230 struct decon_context *ctx = crtc->ctx;
231 u32 val;
232
233 if (ctx->suspended)
234 return -EPERM;
235
236 if (!test_and_set_bit(0, &ctx->irq_flags)) {
237 val = readl(ctx->regs + VIDINTCON0);
238
239 val |= VIDINTCON0_INT_ENABLE;
240
241 if (!ctx->i80_if) {
242 val |= VIDINTCON0_INT_FRAME;
243 val &= ~VIDINTCON0_FRAMESEL0_MASK;
244 val |= VIDINTCON0_FRAMESEL0_VSYNC;
245 }
246
247 writel(val, ctx->regs + VIDINTCON0);
248 }
249
250 return 0;
251 }
252
253 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
254 {
255 struct decon_context *ctx = crtc->ctx;
256 u32 val;
257
258 if (ctx->suspended)
259 return;
260
261 if (test_and_clear_bit(0, &ctx->irq_flags)) {
262 val = readl(ctx->regs + VIDINTCON0);
263
264 val &= ~VIDINTCON0_INT_ENABLE;
265 if (!ctx->i80_if)
266 val &= ~VIDINTCON0_INT_FRAME;
267
268 writel(val, ctx->regs + VIDINTCON0);
269 }
270 }
271
272 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
273 struct drm_framebuffer *fb)
274 {
275 unsigned long val;
276 int padding;
277
278 val = readl(ctx->regs + WINCON(win));
279 val &= ~WINCONx_BPPMODE_MASK;
280
281 switch (fb->pixel_format) {
282 case DRM_FORMAT_RGB565:
283 val |= WINCONx_BPPMODE_16BPP_565;
284 val |= WINCONx_BURSTLEN_16WORD;
285 break;
286 case DRM_FORMAT_XRGB8888:
287 val |= WINCONx_BPPMODE_24BPP_xRGB;
288 val |= WINCONx_BURSTLEN_16WORD;
289 break;
290 case DRM_FORMAT_XBGR8888:
291 val |= WINCONx_BPPMODE_24BPP_xBGR;
292 val |= WINCONx_BURSTLEN_16WORD;
293 break;
294 case DRM_FORMAT_RGBX8888:
295 val |= WINCONx_BPPMODE_24BPP_RGBx;
296 val |= WINCONx_BURSTLEN_16WORD;
297 break;
298 case DRM_FORMAT_BGRX8888:
299 val |= WINCONx_BPPMODE_24BPP_BGRx;
300 val |= WINCONx_BURSTLEN_16WORD;
301 break;
302 case DRM_FORMAT_ARGB8888:
303 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
304 WINCONx_ALPHA_SEL;
305 val |= WINCONx_BURSTLEN_16WORD;
306 break;
307 case DRM_FORMAT_ABGR8888:
308 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
309 WINCONx_ALPHA_SEL;
310 val |= WINCONx_BURSTLEN_16WORD;
311 break;
312 case DRM_FORMAT_RGBA8888:
313 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
314 WINCONx_ALPHA_SEL;
315 val |= WINCONx_BURSTLEN_16WORD;
316 break;
317 case DRM_FORMAT_BGRA8888:
318 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
319 WINCONx_ALPHA_SEL;
320 val |= WINCONx_BURSTLEN_16WORD;
321 break;
322 default:
323 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
324
325 val |= WINCONx_BPPMODE_24BPP_xRGB;
326 val |= WINCONx_BURSTLEN_16WORD;
327 break;
328 }
329
330 DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel);
331
332 /*
333 * In case of exynos, setting dma-burst to 16Word causes permanent
334 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
335 * switching which is based on plane size is not recommended as
336 * plane size varies a lot towards the end of the screen and rapid
337 * movement causes unstable DMA which results into iommu crash/tear.
338 */
339
340 padding = (fb->pitches[0] / (fb->bits_per_pixel >> 3)) - fb->width;
341 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
342 val &= ~WINCONx_BURSTLEN_MASK;
343 val |= WINCONx_BURSTLEN_8WORD;
344 }
345
346 writel(val, ctx->regs + WINCON(win));
347 }
348
349 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
350 {
351 unsigned int keycon0 = 0, keycon1 = 0;
352
353 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
354 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
355
356 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
357
358 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
359 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
360 }
361
362 /**
363 * shadow_protect_win() - disable updating values from shadow registers at vsync
364 *
365 * @win: window to protect registers for
366 * @protect: 1 to protect (disable updates)
367 */
368 static void decon_shadow_protect_win(struct decon_context *ctx,
369 unsigned int win, bool protect)
370 {
371 u32 bits, val;
372
373 bits = SHADOWCON_WINx_PROTECT(win);
374
375 val = readl(ctx->regs + SHADOWCON);
376 if (protect)
377 val |= bits;
378 else
379 val &= ~bits;
380 writel(val, ctx->regs + SHADOWCON);
381 }
382
383 static void decon_atomic_begin(struct exynos_drm_crtc *crtc,
384 struct exynos_drm_plane *plane)
385 {
386 struct decon_context *ctx = crtc->ctx;
387
388 if (ctx->suspended)
389 return;
390
391 decon_shadow_protect_win(ctx, plane->zpos, true);
392 }
393
394 static void decon_update_plane(struct exynos_drm_crtc *crtc,
395 struct exynos_drm_plane *plane)
396 {
397 struct exynos_drm_plane_state *state =
398 to_exynos_plane_state(plane->base.state);
399 struct decon_context *ctx = crtc->ctx;
400 struct drm_framebuffer *fb = state->base.fb;
401 int padding;
402 unsigned long val, alpha;
403 unsigned int last_x;
404 unsigned int last_y;
405 unsigned int win = plane->zpos;
406 unsigned int bpp = fb->bits_per_pixel >> 3;
407 unsigned int pitch = fb->pitches[0];
408
409 if (ctx->suspended)
410 return;
411
412 /*
413 * SHADOWCON/PRTCON register is used for enabling timing.
414 *
415 * for example, once only width value of a register is set,
416 * if the dma is started then decon hardware could malfunction so
417 * with protect window setting, the register fields with prefix '_F'
418 * wouldn't be updated at vsync also but updated once unprotect window
419 * is set.
420 */
421
422 /* buffer start address */
423 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
424 writel(val, ctx->regs + VIDW_BUF_START(win));
425
426 padding = (pitch / bpp) - fb->width;
427
428 /* buffer size */
429 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
430 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
431
432 /* offset from the start of the buffer to read */
433 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
434 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
435
436 DRM_DEBUG_KMS("start addr = 0x%lx\n",
437 (unsigned long)val);
438 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
439 state->crtc.w, state->crtc.h);
440
441 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
442 VIDOSDxA_TOPLEFT_Y(state->crtc.y);
443 writel(val, ctx->regs + VIDOSD_A(win));
444
445 last_x = state->crtc.x + state->crtc.w;
446 if (last_x)
447 last_x--;
448 last_y = state->crtc.y + state->crtc.h;
449 if (last_y)
450 last_y--;
451
452 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
453
454 writel(val, ctx->regs + VIDOSD_B(win));
455
456 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
457 state->crtc.x, state->crtc.y, last_x, last_y);
458
459 /* OSD alpha */
460 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
461 VIDOSDxC_ALPHA0_G_F(0x0) |
462 VIDOSDxC_ALPHA0_B_F(0x0);
463
464 writel(alpha, ctx->regs + VIDOSD_C(win));
465
466 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
467 VIDOSDxD_ALPHA1_G_F(0xff) |
468 VIDOSDxD_ALPHA1_B_F(0xff);
469
470 writel(alpha, ctx->regs + VIDOSD_D(win));
471
472 decon_win_set_pixfmt(ctx, win, fb);
473
474 /* hardware window 0 doesn't support color key. */
475 if (win != 0)
476 decon_win_set_colkey(ctx, win);
477
478 /* wincon */
479 val = readl(ctx->regs + WINCON(win));
480 val |= WINCONx_TRIPLE_BUF_MODE;
481 val |= WINCONx_ENWIN;
482 writel(val, ctx->regs + WINCON(win));
483
484 /* Enable DMA channel and unprotect windows */
485 decon_shadow_protect_win(ctx, win, false);
486
487 val = readl(ctx->regs + DECON_UPDATE);
488 val |= DECON_UPDATE_STANDALONE_F;
489 writel(val, ctx->regs + DECON_UPDATE);
490 }
491
492 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
493 struct exynos_drm_plane *plane)
494 {
495 struct decon_context *ctx = crtc->ctx;
496 unsigned int win = plane->zpos;
497 u32 val;
498
499 if (ctx->suspended)
500 return;
501
502 /* protect windows */
503 decon_shadow_protect_win(ctx, win, true);
504
505 /* wincon */
506 val = readl(ctx->regs + WINCON(win));
507 val &= ~WINCONx_ENWIN;
508 writel(val, ctx->regs + WINCON(win));
509
510 val = readl(ctx->regs + DECON_UPDATE);
511 val |= DECON_UPDATE_STANDALONE_F;
512 writel(val, ctx->regs + DECON_UPDATE);
513 }
514
515 static void decon_atomic_flush(struct exynos_drm_crtc *crtc,
516 struct exynos_drm_plane *plane)
517 {
518 struct decon_context *ctx = crtc->ctx;
519
520 if (ctx->suspended)
521 return;
522
523 decon_shadow_protect_win(ctx, plane->zpos, false);
524 }
525
526 static void decon_init(struct decon_context *ctx)
527 {
528 u32 val;
529
530 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
531
532 val = VIDOUTCON0_DISP_IF_0_ON;
533 if (!ctx->i80_if)
534 val |= VIDOUTCON0_RGBIF;
535 writel(val, ctx->regs + VIDOUTCON0);
536
537 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
538
539 if (!ctx->i80_if)
540 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
541 }
542
543 static void decon_enable(struct exynos_drm_crtc *crtc)
544 {
545 struct decon_context *ctx = crtc->ctx;
546
547 if (!ctx->suspended)
548 return;
549
550 pm_runtime_get_sync(ctx->dev);
551
552 decon_init(ctx);
553
554 /* if vblank was enabled status, enable it again. */
555 if (test_and_clear_bit(0, &ctx->irq_flags))
556 decon_enable_vblank(ctx->crtc);
557
558 decon_commit(ctx->crtc);
559
560 ctx->suspended = false;
561 }
562
563 static void decon_disable(struct exynos_drm_crtc *crtc)
564 {
565 struct decon_context *ctx = crtc->ctx;
566 int i;
567
568 if (ctx->suspended)
569 return;
570
571 /*
572 * We need to make sure that all windows are disabled before we
573 * suspend that connector. Otherwise we might try to scan from
574 * a destroyed buffer later.
575 */
576 for (i = 0; i < WINDOWS_NR; i++)
577 decon_disable_plane(crtc, &ctx->planes[i]);
578
579 pm_runtime_put_sync(ctx->dev);
580
581 ctx->suspended = true;
582 }
583
584 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
585 .enable = decon_enable,
586 .disable = decon_disable,
587 .commit = decon_commit,
588 .enable_vblank = decon_enable_vblank,
589 .disable_vblank = decon_disable_vblank,
590 .wait_for_vblank = decon_wait_for_vblank,
591 .atomic_begin = decon_atomic_begin,
592 .update_plane = decon_update_plane,
593 .disable_plane = decon_disable_plane,
594 .atomic_flush = decon_atomic_flush,
595 };
596
597
598 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
599 {
600 struct decon_context *ctx = (struct decon_context *)dev_id;
601 u32 val, clear_bit;
602 int win;
603
604 val = readl(ctx->regs + VIDINTCON1);
605
606 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
607 if (val & clear_bit)
608 writel(clear_bit, ctx->regs + VIDINTCON1);
609
610 /* check the crtc is detached already from encoder */
611 if (ctx->pipe < 0 || !ctx->drm_dev)
612 goto out;
613
614 if (!ctx->i80_if) {
615 drm_crtc_handle_vblank(&ctx->crtc->base);
616 for (win = 0 ; win < WINDOWS_NR ; win++) {
617 struct exynos_drm_plane *plane = &ctx->planes[win];
618
619 if (!plane->pending_fb)
620 continue;
621
622 exynos_drm_crtc_finish_update(ctx->crtc, plane);
623 }
624
625 /* set wait vsync event to zero and wake up queue. */
626 if (atomic_read(&ctx->wait_vsync_event)) {
627 atomic_set(&ctx->wait_vsync_event, 0);
628 wake_up(&ctx->wait_vsync_queue);
629 }
630 }
631 out:
632 return IRQ_HANDLED;
633 }
634
635 static int decon_bind(struct device *dev, struct device *master, void *data)
636 {
637 struct decon_context *ctx = dev_get_drvdata(dev);
638 struct drm_device *drm_dev = data;
639 struct exynos_drm_plane *exynos_plane;
640 enum drm_plane_type type;
641 unsigned int zpos;
642 int ret;
643
644 ret = decon_ctx_initialize(ctx, drm_dev);
645 if (ret) {
646 DRM_ERROR("decon_ctx_initialize failed.\n");
647 return ret;
648 }
649
650 for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
651 type = exynos_plane_get_type(zpos, CURSOR_WIN);
652 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
653 1 << ctx->pipe, type, decon_formats,
654 ARRAY_SIZE(decon_formats), zpos);
655 if (ret)
656 return ret;
657 }
658
659 exynos_plane = &ctx->planes[DEFAULT_WIN];
660 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
661 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
662 &decon_crtc_ops, ctx);
663 if (IS_ERR(ctx->crtc)) {
664 decon_ctx_remove(ctx);
665 return PTR_ERR(ctx->crtc);
666 }
667
668 if (ctx->encoder)
669 exynos_dpi_bind(drm_dev, ctx->encoder);
670
671 return 0;
672
673 }
674
675 static void decon_unbind(struct device *dev, struct device *master,
676 void *data)
677 {
678 struct decon_context *ctx = dev_get_drvdata(dev);
679
680 decon_disable(ctx->crtc);
681
682 if (ctx->encoder)
683 exynos_dpi_remove(ctx->encoder);
684
685 decon_ctx_remove(ctx);
686 }
687
688 static const struct component_ops decon_component_ops = {
689 .bind = decon_bind,
690 .unbind = decon_unbind,
691 };
692
693 static int decon_probe(struct platform_device *pdev)
694 {
695 struct device *dev = &pdev->dev;
696 struct decon_context *ctx;
697 struct device_node *i80_if_timings;
698 struct resource *res;
699 int ret;
700
701 if (!dev->of_node)
702 return -ENODEV;
703
704 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
705 if (!ctx)
706 return -ENOMEM;
707
708 ctx->dev = dev;
709 ctx->suspended = true;
710
711 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
712 if (i80_if_timings)
713 ctx->i80_if = true;
714 of_node_put(i80_if_timings);
715
716 ctx->regs = of_iomap(dev->of_node, 0);
717 if (!ctx->regs)
718 return -ENOMEM;
719
720 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
721 if (IS_ERR(ctx->pclk)) {
722 dev_err(dev, "failed to get bus clock pclk\n");
723 ret = PTR_ERR(ctx->pclk);
724 goto err_iounmap;
725 }
726
727 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
728 if (IS_ERR(ctx->aclk)) {
729 dev_err(dev, "failed to get bus clock aclk\n");
730 ret = PTR_ERR(ctx->aclk);
731 goto err_iounmap;
732 }
733
734 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
735 if (IS_ERR(ctx->eclk)) {
736 dev_err(dev, "failed to get eclock\n");
737 ret = PTR_ERR(ctx->eclk);
738 goto err_iounmap;
739 }
740
741 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
742 if (IS_ERR(ctx->vclk)) {
743 dev_err(dev, "failed to get vclock\n");
744 ret = PTR_ERR(ctx->vclk);
745 goto err_iounmap;
746 }
747
748 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
749 ctx->i80_if ? "lcd_sys" : "vsync");
750 if (!res) {
751 dev_err(dev, "irq request failed.\n");
752 ret = -ENXIO;
753 goto err_iounmap;
754 }
755
756 ret = devm_request_irq(dev, res->start, decon_irq_handler,
757 0, "drm_decon", ctx);
758 if (ret) {
759 dev_err(dev, "irq request failed.\n");
760 goto err_iounmap;
761 }
762
763 init_waitqueue_head(&ctx->wait_vsync_queue);
764 atomic_set(&ctx->wait_vsync_event, 0);
765
766 platform_set_drvdata(pdev, ctx);
767
768 ctx->encoder = exynos_dpi_probe(dev);
769 if (IS_ERR(ctx->encoder)) {
770 ret = PTR_ERR(ctx->encoder);
771 goto err_iounmap;
772 }
773
774 pm_runtime_enable(dev);
775
776 ret = component_add(dev, &decon_component_ops);
777 if (ret)
778 goto err_disable_pm_runtime;
779
780 return ret;
781
782 err_disable_pm_runtime:
783 pm_runtime_disable(dev);
784
785 err_iounmap:
786 iounmap(ctx->regs);
787
788 return ret;
789 }
790
791 static int decon_remove(struct platform_device *pdev)
792 {
793 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
794
795 pm_runtime_disable(&pdev->dev);
796
797 iounmap(ctx->regs);
798
799 component_del(&pdev->dev, &decon_component_ops);
800
801 return 0;
802 }
803
804 #ifdef CONFIG_PM
805 static int exynos7_decon_suspend(struct device *dev)
806 {
807 struct decon_context *ctx = dev_get_drvdata(dev);
808
809 clk_disable_unprepare(ctx->vclk);
810 clk_disable_unprepare(ctx->eclk);
811 clk_disable_unprepare(ctx->aclk);
812 clk_disable_unprepare(ctx->pclk);
813
814 return 0;
815 }
816
817 static int exynos7_decon_resume(struct device *dev)
818 {
819 struct decon_context *ctx = dev_get_drvdata(dev);
820 int ret;
821
822 ret = clk_prepare_enable(ctx->pclk);
823 if (ret < 0) {
824 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
825 return ret;
826 }
827
828 ret = clk_prepare_enable(ctx->aclk);
829 if (ret < 0) {
830 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
831 return ret;
832 }
833
834 ret = clk_prepare_enable(ctx->eclk);
835 if (ret < 0) {
836 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
837 return ret;
838 }
839
840 ret = clk_prepare_enable(ctx->vclk);
841 if (ret < 0) {
842 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
843 return ret;
844 }
845
846 return 0;
847 }
848 #endif
849
850 static const struct dev_pm_ops exynos7_decon_pm_ops = {
851 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
852 NULL)
853 };
854
855 struct platform_driver decon_driver = {
856 .probe = decon_probe,
857 .remove = decon_remove,
858 .driver = {
859 .name = "exynos-decon",
860 .pm = &exynos7_decon_pm_ops,
861 .of_match_table = decon_driver_dt_match,
862 },
863 };
Linux kernel - Deliverables
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