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15b0865ecf97fe939f832df9ecb547358c8dc416
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_dp_core.c
1 /*
2 * Samsung SoC DP (Display Port) interface driver.
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/io.h>
18 #include <linux/interrupt.h>
19 #include <linux/of.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_graph.h>
22 #include <linux/gpio.h>
23 #include <linux/component.h>
24 #include <linux/phy/phy.h>
25 #include <video/of_display_timing.h>
26 #include <video/of_videomode.h>
27
28 #include <drm/drmP.h>
29 #include <drm/drm_crtc.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/drm_panel.h>
32
33 #include "exynos_dp_core.h"
34
35 #define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \
36 connector)
37
38 static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
39 {
40 return to_exynos_crtc(dp->encoder->crtc);
41 }
42
43 static inline struct exynos_dp_device *
44 display_to_dp(struct exynos_drm_display *d)
45 {
46 return container_of(d, struct exynos_dp_device, display);
47 }
48
49 struct bridge_init {
50 struct i2c_client *client;
51 struct device_node *node;
52 };
53
54 static void exynos_dp_init_dp(struct exynos_dp_device *dp)
55 {
56 exynos_dp_reset(dp);
57
58 exynos_dp_swreset(dp);
59
60 exynos_dp_init_analog_param(dp);
61 exynos_dp_init_interrupt(dp);
62
63 /* SW defined function Normal operation */
64 exynos_dp_enable_sw_function(dp);
65
66 exynos_dp_config_interrupt(dp);
67 exynos_dp_init_analog_func(dp);
68
69 exynos_dp_init_hpd(dp);
70 exynos_dp_init_aux(dp);
71 }
72
73 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
74 {
75 int timeout_loop = 0;
76
77 while (exynos_dp_get_plug_in_status(dp) != 0) {
78 timeout_loop++;
79 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
80 dev_err(dp->dev, "failed to get hpd plug status\n");
81 return -ETIMEDOUT;
82 }
83 usleep_range(10, 11);
84 }
85
86 return 0;
87 }
88
89 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
90 {
91 int i;
92 unsigned char sum = 0;
93
94 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
95 sum = sum + edid_data[i];
96
97 return sum;
98 }
99
100 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
101 {
102 unsigned char edid[EDID_BLOCK_LENGTH * 2];
103 unsigned int extend_block = 0;
104 unsigned char sum;
105 unsigned char test_vector;
106 int retval;
107
108 /*
109 * EDID device address is 0x50.
110 * However, if necessary, you must have set upper address
111 * into E-EDID in I2C device, 0x30.
112 */
113
114 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
115 retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
116 EDID_EXTENSION_FLAG,
117 &extend_block);
118 if (retval)
119 return retval;
120
121 if (extend_block > 0) {
122 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
123
124 /* Read EDID data */
125 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
126 EDID_HEADER_PATTERN,
127 EDID_BLOCK_LENGTH,
128 &edid[EDID_HEADER_PATTERN]);
129 if (retval != 0) {
130 dev_err(dp->dev, "EDID Read failed!\n");
131 return -EIO;
132 }
133 sum = exynos_dp_calc_edid_check_sum(edid);
134 if (sum != 0) {
135 dev_err(dp->dev, "EDID bad checksum!\n");
136 return -EIO;
137 }
138
139 /* Read additional EDID data */
140 retval = exynos_dp_read_bytes_from_i2c(dp,
141 I2C_EDID_DEVICE_ADDR,
142 EDID_BLOCK_LENGTH,
143 EDID_BLOCK_LENGTH,
144 &edid[EDID_BLOCK_LENGTH]);
145 if (retval != 0) {
146 dev_err(dp->dev, "EDID Read failed!\n");
147 return -EIO;
148 }
149 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
150 if (sum != 0) {
151 dev_err(dp->dev, "EDID bad checksum!\n");
152 return -EIO;
153 }
154
155 exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
156 &test_vector);
157 if (test_vector & DP_TEST_LINK_EDID_READ) {
158 exynos_dp_write_byte_to_dpcd(dp,
159 DP_TEST_EDID_CHECKSUM,
160 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
161 exynos_dp_write_byte_to_dpcd(dp,
162 DP_TEST_RESPONSE,
163 DP_TEST_EDID_CHECKSUM_WRITE);
164 }
165 } else {
166 dev_info(dp->dev, "EDID data does not include any extensions.\n");
167
168 /* Read EDID data */
169 retval = exynos_dp_read_bytes_from_i2c(dp,
170 I2C_EDID_DEVICE_ADDR,
171 EDID_HEADER_PATTERN,
172 EDID_BLOCK_LENGTH,
173 &edid[EDID_HEADER_PATTERN]);
174 if (retval != 0) {
175 dev_err(dp->dev, "EDID Read failed!\n");
176 return -EIO;
177 }
178 sum = exynos_dp_calc_edid_check_sum(edid);
179 if (sum != 0) {
180 dev_err(dp->dev, "EDID bad checksum!\n");
181 return -EIO;
182 }
183
184 exynos_dp_read_byte_from_dpcd(dp,
185 DP_TEST_REQUEST,
186 &test_vector);
187 if (test_vector & DP_TEST_LINK_EDID_READ) {
188 exynos_dp_write_byte_to_dpcd(dp,
189 DP_TEST_EDID_CHECKSUM,
190 edid[EDID_CHECKSUM]);
191 exynos_dp_write_byte_to_dpcd(dp,
192 DP_TEST_RESPONSE,
193 DP_TEST_EDID_CHECKSUM_WRITE);
194 }
195 }
196
197 dev_dbg(dp->dev, "EDID Read success!\n");
198 return 0;
199 }
200
201 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
202 {
203 u8 buf[12];
204 int i;
205 int retval;
206
207 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
208 retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
209 12, buf);
210 if (retval)
211 return retval;
212
213 /* Read EDID */
214 for (i = 0; i < 3; i++) {
215 retval = exynos_dp_read_edid(dp);
216 if (!retval)
217 break;
218 }
219
220 return retval;
221 }
222
223 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
224 bool enable)
225 {
226 u8 data;
227
228 exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
229
230 if (enable)
231 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
232 DP_LANE_COUNT_ENHANCED_FRAME_EN |
233 DPCD_LANE_COUNT_SET(data));
234 else
235 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
236 DPCD_LANE_COUNT_SET(data));
237 }
238
239 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
240 {
241 u8 data;
242 int retval;
243
244 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
245 retval = DPCD_ENHANCED_FRAME_CAP(data);
246
247 return retval;
248 }
249
250 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
251 {
252 u8 data;
253
254 data = exynos_dp_is_enhanced_mode_available(dp);
255 exynos_dp_enable_rx_to_enhanced_mode(dp, data);
256 exynos_dp_enable_enhanced_mode(dp, data);
257 }
258
259 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
260 {
261 exynos_dp_set_training_pattern(dp, DP_NONE);
262
263 exynos_dp_write_byte_to_dpcd(dp,
264 DP_TRAINING_PATTERN_SET,
265 DP_TRAINING_PATTERN_DISABLE);
266 }
267
268 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
269 int pre_emphasis, int lane)
270 {
271 switch (lane) {
272 case 0:
273 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
274 break;
275 case 1:
276 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
277 break;
278
279 case 2:
280 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
281 break;
282
283 case 3:
284 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
285 break;
286 }
287 }
288
289 static int exynos_dp_link_start(struct exynos_dp_device *dp)
290 {
291 u8 buf[4];
292 int lane, lane_count, pll_tries, retval;
293
294 lane_count = dp->link_train.lane_count;
295
296 dp->link_train.lt_state = CLOCK_RECOVERY;
297 dp->link_train.eq_loop = 0;
298
299 for (lane = 0; lane < lane_count; lane++)
300 dp->link_train.cr_loop[lane] = 0;
301
302 /* Set link rate and count as you want to establish*/
303 exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
304 exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
305
306 /* Setup RX configuration */
307 buf[0] = dp->link_train.link_rate;
308 buf[1] = dp->link_train.lane_count;
309 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
310 2, buf);
311 if (retval)
312 return retval;
313
314 /* Set TX pre-emphasis to minimum */
315 for (lane = 0; lane < lane_count; lane++)
316 exynos_dp_set_lane_lane_pre_emphasis(dp,
317 PRE_EMPHASIS_LEVEL_0, lane);
318
319 /* Wait for PLL lock */
320 pll_tries = 0;
321 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
322 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
323 dev_err(dp->dev, "Wait for PLL lock timed out\n");
324 return -ETIMEDOUT;
325 }
326
327 pll_tries++;
328 usleep_range(90, 120);
329 }
330
331 /* Set training pattern 1 */
332 exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
333
334 /* Set RX training pattern */
335 retval = exynos_dp_write_byte_to_dpcd(dp,
336 DP_TRAINING_PATTERN_SET,
337 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
338 if (retval)
339 return retval;
340
341 for (lane = 0; lane < lane_count; lane++)
342 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
343 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
344
345 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
346 lane_count, buf);
347
348 return retval;
349 }
350
351 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
352 {
353 int shift = (lane & 1) * 4;
354 u8 link_value = link_status[lane>>1];
355
356 return (link_value >> shift) & 0xf;
357 }
358
359 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
360 {
361 int lane;
362 u8 lane_status;
363
364 for (lane = 0; lane < lane_count; lane++) {
365 lane_status = exynos_dp_get_lane_status(link_status, lane);
366 if ((lane_status & DP_LANE_CR_DONE) == 0)
367 return -EINVAL;
368 }
369 return 0;
370 }
371
372 static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
373 int lane_count)
374 {
375 int lane;
376 u8 lane_status;
377
378 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
379 return -EINVAL;
380
381 for (lane = 0; lane < lane_count; lane++) {
382 lane_status = exynos_dp_get_lane_status(link_status, lane);
383 lane_status &= DP_CHANNEL_EQ_BITS;
384 if (lane_status != DP_CHANNEL_EQ_BITS)
385 return -EINVAL;
386 }
387
388 return 0;
389 }
390
391 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
392 int lane)
393 {
394 int shift = (lane & 1) * 4;
395 u8 link_value = adjust_request[lane>>1];
396
397 return (link_value >> shift) & 0x3;
398 }
399
400 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
401 u8 adjust_request[2],
402 int lane)
403 {
404 int shift = (lane & 1) * 4;
405 u8 link_value = adjust_request[lane>>1];
406
407 return ((link_value >> shift) & 0xc) >> 2;
408 }
409
410 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
411 u8 training_lane_set, int lane)
412 {
413 switch (lane) {
414 case 0:
415 exynos_dp_set_lane0_link_training(dp, training_lane_set);
416 break;
417 case 1:
418 exynos_dp_set_lane1_link_training(dp, training_lane_set);
419 break;
420
421 case 2:
422 exynos_dp_set_lane2_link_training(dp, training_lane_set);
423 break;
424
425 case 3:
426 exynos_dp_set_lane3_link_training(dp, training_lane_set);
427 break;
428 }
429 }
430
431 static unsigned int exynos_dp_get_lane_link_training(
432 struct exynos_dp_device *dp,
433 int lane)
434 {
435 u32 reg;
436
437 switch (lane) {
438 case 0:
439 reg = exynos_dp_get_lane0_link_training(dp);
440 break;
441 case 1:
442 reg = exynos_dp_get_lane1_link_training(dp);
443 break;
444 case 2:
445 reg = exynos_dp_get_lane2_link_training(dp);
446 break;
447 case 3:
448 reg = exynos_dp_get_lane3_link_training(dp);
449 break;
450 default:
451 WARN_ON(1);
452 return 0;
453 }
454
455 return reg;
456 }
457
458 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
459 {
460 exynos_dp_training_pattern_dis(dp);
461 exynos_dp_set_enhanced_mode(dp);
462
463 dp->link_train.lt_state = FAILED;
464 }
465
466 static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
467 u8 adjust_request[2])
468 {
469 int lane, lane_count;
470 u8 voltage_swing, pre_emphasis, training_lane;
471
472 lane_count = dp->link_train.lane_count;
473 for (lane = 0; lane < lane_count; lane++) {
474 voltage_swing = exynos_dp_get_adjust_request_voltage(
475 adjust_request, lane);
476 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
477 adjust_request, lane);
478 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
479 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
480
481 if (voltage_swing == VOLTAGE_LEVEL_3)
482 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
483 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
484 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
485
486 dp->link_train.training_lane[lane] = training_lane;
487 }
488 }
489
490 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
491 {
492 int lane, lane_count, retval;
493 u8 voltage_swing, pre_emphasis, training_lane;
494 u8 link_status[2], adjust_request[2];
495
496 usleep_range(100, 101);
497
498 lane_count = dp->link_train.lane_count;
499
500 retval = exynos_dp_read_bytes_from_dpcd(dp,
501 DP_LANE0_1_STATUS, 2, link_status);
502 if (retval)
503 return retval;
504
505 retval = exynos_dp_read_bytes_from_dpcd(dp,
506 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
507 if (retval)
508 return retval;
509
510 if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
511 /* set training pattern 2 for EQ */
512 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
513
514 retval = exynos_dp_write_byte_to_dpcd(dp,
515 DP_TRAINING_PATTERN_SET,
516 DP_LINK_SCRAMBLING_DISABLE |
517 DP_TRAINING_PATTERN_2);
518 if (retval)
519 return retval;
520
521 dev_info(dp->dev, "Link Training Clock Recovery success\n");
522 dp->link_train.lt_state = EQUALIZER_TRAINING;
523 } else {
524 for (lane = 0; lane < lane_count; lane++) {
525 training_lane = exynos_dp_get_lane_link_training(
526 dp, lane);
527 voltage_swing = exynos_dp_get_adjust_request_voltage(
528 adjust_request, lane);
529 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
530 adjust_request, lane);
531
532 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
533 voltage_swing &&
534 DPCD_PRE_EMPHASIS_GET(training_lane) ==
535 pre_emphasis)
536 dp->link_train.cr_loop[lane]++;
537
538 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
539 voltage_swing == VOLTAGE_LEVEL_3 ||
540 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
541 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
542 dp->link_train.cr_loop[lane],
543 voltage_swing, pre_emphasis);
544 exynos_dp_reduce_link_rate(dp);
545 return -EIO;
546 }
547 }
548 }
549
550 exynos_dp_get_adjust_training_lane(dp, adjust_request);
551
552 for (lane = 0; lane < lane_count; lane++)
553 exynos_dp_set_lane_link_training(dp,
554 dp->link_train.training_lane[lane], lane);
555
556 retval = exynos_dp_write_bytes_to_dpcd(dp,
557 DP_TRAINING_LANE0_SET, lane_count,
558 dp->link_train.training_lane);
559 if (retval)
560 return retval;
561
562 return retval;
563 }
564
565 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
566 {
567 int lane, lane_count, retval;
568 u32 reg;
569 u8 link_align, link_status[2], adjust_request[2];
570
571 usleep_range(400, 401);
572
573 lane_count = dp->link_train.lane_count;
574
575 retval = exynos_dp_read_bytes_from_dpcd(dp,
576 DP_LANE0_1_STATUS, 2, link_status);
577 if (retval)
578 return retval;
579
580 if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
581 exynos_dp_reduce_link_rate(dp);
582 return -EIO;
583 }
584
585 retval = exynos_dp_read_bytes_from_dpcd(dp,
586 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
587 if (retval)
588 return retval;
589
590 retval = exynos_dp_read_byte_from_dpcd(dp,
591 DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
592 if (retval)
593 return retval;
594
595 exynos_dp_get_adjust_training_lane(dp, adjust_request);
596
597 if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
598 /* traing pattern Set to Normal */
599 exynos_dp_training_pattern_dis(dp);
600
601 dev_info(dp->dev, "Link Training success!\n");
602
603 exynos_dp_get_link_bandwidth(dp, &reg);
604 dp->link_train.link_rate = reg;
605 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
606 dp->link_train.link_rate);
607
608 exynos_dp_get_lane_count(dp, &reg);
609 dp->link_train.lane_count = reg;
610 dev_dbg(dp->dev, "final lane count = %.2x\n",
611 dp->link_train.lane_count);
612
613 /* set enhanced mode if available */
614 exynos_dp_set_enhanced_mode(dp);
615 dp->link_train.lt_state = FINISHED;
616
617 return 0;
618 }
619
620 /* not all locked */
621 dp->link_train.eq_loop++;
622
623 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
624 dev_err(dp->dev, "EQ Max loop\n");
625 exynos_dp_reduce_link_rate(dp);
626 return -EIO;
627 }
628
629 for (lane = 0; lane < lane_count; lane++)
630 exynos_dp_set_lane_link_training(dp,
631 dp->link_train.training_lane[lane], lane);
632
633 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
634 lane_count, dp->link_train.training_lane);
635
636 return retval;
637 }
638
639 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
640 u8 *bandwidth)
641 {
642 u8 data;
643
644 /*
645 * For DP rev.1.1, Maximum link rate of Main Link lanes
646 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
647 */
648 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
649 *bandwidth = data;
650 }
651
652 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
653 u8 *lane_count)
654 {
655 u8 data;
656
657 /*
658 * For DP rev.1.1, Maximum number of Main Link lanes
659 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
660 */
661 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
662 *lane_count = DPCD_MAX_LANE_COUNT(data);
663 }
664
665 static void exynos_dp_init_training(struct exynos_dp_device *dp,
666 enum link_lane_count_type max_lane,
667 enum link_rate_type max_rate)
668 {
669 /*
670 * MACRO_RST must be applied after the PLL_LOCK to avoid
671 * the DP inter pair skew issue for at least 10 us
672 */
673 exynos_dp_reset_macro(dp);
674
675 /* Initialize by reading RX's DPCD */
676 exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
677 exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
678
679 if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
680 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
681 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
682 dp->link_train.link_rate);
683 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
684 }
685
686 if (dp->link_train.lane_count == 0) {
687 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
688 dp->link_train.lane_count);
689 dp->link_train.lane_count = (u8)LANE_COUNT1;
690 }
691
692 /* Setup TX lane count & rate */
693 if (dp->link_train.lane_count > max_lane)
694 dp->link_train.lane_count = max_lane;
695 if (dp->link_train.link_rate > max_rate)
696 dp->link_train.link_rate = max_rate;
697
698 /* All DP analog module power up */
699 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
700 }
701
702 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
703 {
704 int retval = 0, training_finished = 0;
705
706 dp->link_train.lt_state = START;
707
708 /* Process here */
709 while (!retval && !training_finished) {
710 switch (dp->link_train.lt_state) {
711 case START:
712 retval = exynos_dp_link_start(dp);
713 if (retval)
714 dev_err(dp->dev, "LT link start failed!\n");
715 break;
716 case CLOCK_RECOVERY:
717 retval = exynos_dp_process_clock_recovery(dp);
718 if (retval)
719 dev_err(dp->dev, "LT CR failed!\n");
720 break;
721 case EQUALIZER_TRAINING:
722 retval = exynos_dp_process_equalizer_training(dp);
723 if (retval)
724 dev_err(dp->dev, "LT EQ failed!\n");
725 break;
726 case FINISHED:
727 training_finished = 1;
728 break;
729 case FAILED:
730 return -EREMOTEIO;
731 }
732 }
733 if (retval)
734 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
735
736 return retval;
737 }
738
739 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
740 u32 count,
741 u32 bwtype)
742 {
743 int i;
744 int retval;
745
746 for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
747 exynos_dp_init_training(dp, count, bwtype);
748 retval = exynos_dp_sw_link_training(dp);
749 if (retval == 0)
750 break;
751
752 usleep_range(100, 110);
753 }
754
755 return retval;
756 }
757
758 static int exynos_dp_config_video(struct exynos_dp_device *dp)
759 {
760 int retval = 0;
761 int timeout_loop = 0;
762 int done_count = 0;
763
764 exynos_dp_config_video_slave_mode(dp);
765
766 exynos_dp_set_video_color_format(dp);
767
768 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
769 dev_err(dp->dev, "PLL is not locked yet.\n");
770 return -EINVAL;
771 }
772
773 for (;;) {
774 timeout_loop++;
775 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
776 break;
777 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
778 dev_err(dp->dev, "Timeout of video streamclk ok\n");
779 return -ETIMEDOUT;
780 }
781
782 usleep_range(1, 2);
783 }
784
785 /* Set to use the register calculated M/N video */
786 exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
787
788 /* For video bist, Video timing must be generated by register */
789 exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
790
791 /* Disable video mute */
792 exynos_dp_enable_video_mute(dp, 0);
793
794 /* Configure video slave mode */
795 exynos_dp_enable_video_master(dp, 0);
796
797 /* Enable video */
798 exynos_dp_start_video(dp);
799
800 timeout_loop = 0;
801
802 for (;;) {
803 timeout_loop++;
804 if (exynos_dp_is_video_stream_on(dp) == 0) {
805 done_count++;
806 if (done_count > 10)
807 break;
808 } else if (done_count) {
809 done_count = 0;
810 }
811 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
812 dev_err(dp->dev, "Timeout of video streamclk ok\n");
813 return -ETIMEDOUT;
814 }
815
816 usleep_range(1000, 1001);
817 }
818
819 if (retval != 0)
820 dev_err(dp->dev, "Video stream is not detected!\n");
821
822 return retval;
823 }
824
825 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
826 {
827 u8 data;
828
829 if (enable) {
830 exynos_dp_enable_scrambling(dp);
831
832 exynos_dp_read_byte_from_dpcd(dp,
833 DP_TRAINING_PATTERN_SET,
834 &data);
835 exynos_dp_write_byte_to_dpcd(dp,
836 DP_TRAINING_PATTERN_SET,
837 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
838 } else {
839 exynos_dp_disable_scrambling(dp);
840
841 exynos_dp_read_byte_from_dpcd(dp,
842 DP_TRAINING_PATTERN_SET,
843 &data);
844 exynos_dp_write_byte_to_dpcd(dp,
845 DP_TRAINING_PATTERN_SET,
846 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
847 }
848 }
849
850 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
851 {
852 struct exynos_dp_device *dp = arg;
853
854 enum dp_irq_type irq_type;
855
856 irq_type = exynos_dp_get_irq_type(dp);
857 switch (irq_type) {
858 case DP_IRQ_TYPE_HP_CABLE_IN:
859 dev_dbg(dp->dev, "Received irq - cable in\n");
860 schedule_work(&dp->hotplug_work);
861 exynos_dp_clear_hotplug_interrupts(dp);
862 break;
863 case DP_IRQ_TYPE_HP_CABLE_OUT:
864 dev_dbg(dp->dev, "Received irq - cable out\n");
865 exynos_dp_clear_hotplug_interrupts(dp);
866 break;
867 case DP_IRQ_TYPE_HP_CHANGE:
868 /*
869 * We get these change notifications once in a while, but there
870 * is nothing we can do with them. Just ignore it for now and
871 * only handle cable changes.
872 */
873 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
874 exynos_dp_clear_hotplug_interrupts(dp);
875 break;
876 default:
877 dev_err(dp->dev, "Received irq - unknown type!\n");
878 break;
879 }
880 return IRQ_HANDLED;
881 }
882
883 static void exynos_dp_hotplug(struct work_struct *work)
884 {
885 struct exynos_dp_device *dp;
886
887 dp = container_of(work, struct exynos_dp_device, hotplug_work);
888
889 if (dp->drm_dev)
890 drm_helper_hpd_irq_event(dp->drm_dev);
891 }
892
893 static void exynos_dp_commit(struct exynos_drm_display *display)
894 {
895 struct exynos_dp_device *dp = display_to_dp(display);
896 int ret;
897
898 /* Keep the panel disabled while we configure video */
899 if (dp->panel) {
900 if (drm_panel_disable(dp->panel))
901 DRM_ERROR("failed to disable the panel\n");
902 }
903
904 ret = exynos_dp_detect_hpd(dp);
905 if (ret) {
906 /* Cable has been disconnected, we're done */
907 return;
908 }
909
910 ret = exynos_dp_handle_edid(dp);
911 if (ret) {
912 dev_err(dp->dev, "unable to handle edid\n");
913 return;
914 }
915
916 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
917 dp->video_info->link_rate);
918 if (ret) {
919 dev_err(dp->dev, "unable to do link train\n");
920 return;
921 }
922
923 exynos_dp_enable_scramble(dp, 1);
924 exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
925 exynos_dp_enable_enhanced_mode(dp, 1);
926
927 exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
928 exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
929
930 exynos_dp_init_video(dp);
931 ret = exynos_dp_config_video(dp);
932 if (ret)
933 dev_err(dp->dev, "unable to config video\n");
934
935 /* Safe to enable the panel now */
936 if (dp->panel) {
937 if (drm_panel_enable(dp->panel))
938 DRM_ERROR("failed to enable the panel\n");
939 }
940 }
941
942 static enum drm_connector_status exynos_dp_detect(
943 struct drm_connector *connector, bool force)
944 {
945 return connector_status_connected;
946 }
947
948 static void exynos_dp_connector_destroy(struct drm_connector *connector)
949 {
950 drm_connector_unregister(connector);
951 drm_connector_cleanup(connector);
952 }
953
954 static struct drm_connector_funcs exynos_dp_connector_funcs = {
955 .dpms = drm_helper_connector_dpms,
956 .fill_modes = drm_helper_probe_single_connector_modes,
957 .detect = exynos_dp_detect,
958 .destroy = exynos_dp_connector_destroy,
959 };
960
961 static int exynos_dp_get_modes(struct drm_connector *connector)
962 {
963 struct exynos_dp_device *dp = ctx_from_connector(connector);
964 struct drm_display_mode *mode;
965
966 if (dp->panel)
967 return drm_panel_get_modes(dp->panel);
968
969 mode = drm_mode_create(connector->dev);
970 if (!mode) {
971 DRM_ERROR("failed to create a new display mode.\n");
972 return 0;
973 }
974
975 drm_display_mode_from_videomode(&dp->priv.vm, mode);
976 mode->width_mm = dp->priv.width_mm;
977 mode->height_mm = dp->priv.height_mm;
978 connector->display_info.width_mm = mode->width_mm;
979 connector->display_info.height_mm = mode->height_mm;
980
981 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
982 drm_mode_set_name(mode);
983 drm_mode_probed_add(connector, mode);
984
985 return 1;
986 }
987
988 static struct drm_encoder *exynos_dp_best_encoder(
989 struct drm_connector *connector)
990 {
991 struct exynos_dp_device *dp = ctx_from_connector(connector);
992
993 return dp->encoder;
994 }
995
996 static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
997 .get_modes = exynos_dp_get_modes,
998 .best_encoder = exynos_dp_best_encoder,
999 };
1000
1001 /* returns the number of bridges attached */
1002 static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
1003 struct drm_encoder *encoder)
1004 {
1005 int ret;
1006
1007 encoder->bridge = dp->bridge;
1008 dp->bridge->encoder = encoder;
1009 ret = drm_bridge_attach(encoder->dev, dp->bridge);
1010 if (ret) {
1011 DRM_ERROR("Failed to attach bridge to drm\n");
1012 return ret;
1013 }
1014
1015 return 0;
1016 }
1017
1018 static int exynos_dp_create_connector(struct exynos_drm_display *display,
1019 struct drm_encoder *encoder)
1020 {
1021 struct exynos_dp_device *dp = display_to_dp(display);
1022 struct drm_connector *connector = &dp->connector;
1023 int ret;
1024
1025 dp->encoder = encoder;
1026
1027 /* Pre-empt DP connector creation if there's a bridge */
1028 if (dp->bridge) {
1029 ret = exynos_drm_attach_lcd_bridge(dp, encoder);
1030 if (!ret)
1031 return 0;
1032 }
1033
1034 connector->polled = DRM_CONNECTOR_POLL_HPD;
1035
1036 ret = drm_connector_init(dp->drm_dev, connector,
1037 &exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
1038 if (ret) {
1039 DRM_ERROR("Failed to initialize connector with drm\n");
1040 return ret;
1041 }
1042
1043 drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
1044 drm_connector_register(connector);
1045 drm_mode_connector_attach_encoder(connector, encoder);
1046
1047 if (dp->panel)
1048 ret = drm_panel_attach(dp->panel, &dp->connector);
1049
1050 return ret;
1051 }
1052
1053 static void exynos_dp_phy_init(struct exynos_dp_device *dp)
1054 {
1055 if (dp->phy)
1056 phy_power_on(dp->phy);
1057 }
1058
1059 static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
1060 {
1061 if (dp->phy)
1062 phy_power_off(dp->phy);
1063 }
1064
1065 static void exynos_dp_poweron(struct exynos_dp_device *dp)
1066 {
1067 struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
1068
1069 if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1070 return;
1071
1072 if (dp->panel) {
1073 if (drm_panel_prepare(dp->panel)) {
1074 DRM_ERROR("failed to setup the panel\n");
1075 return;
1076 }
1077 }
1078
1079 if (crtc->ops->clock_enable)
1080 crtc->ops->clock_enable(dp_to_crtc(dp), true);
1081
1082 clk_prepare_enable(dp->clock);
1083 exynos_dp_phy_init(dp);
1084 exynos_dp_init_dp(dp);
1085 enable_irq(dp->irq);
1086 exynos_dp_commit(&dp->display);
1087 }
1088
1089 static void exynos_dp_poweroff(struct exynos_dp_device *dp)
1090 {
1091 struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
1092
1093 if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1094 return;
1095
1096 if (dp->panel) {
1097 if (drm_panel_disable(dp->panel)) {
1098 DRM_ERROR("failed to disable the panel\n");
1099 return;
1100 }
1101 }
1102
1103 disable_irq(dp->irq);
1104 flush_work(&dp->hotplug_work);
1105 exynos_dp_phy_exit(dp);
1106 clk_disable_unprepare(dp->clock);
1107
1108 if (crtc->ops->clock_enable)
1109 crtc->ops->clock_enable(dp_to_crtc(dp), false);
1110
1111 if (dp->panel) {
1112 if (drm_panel_unprepare(dp->panel))
1113 DRM_ERROR("failed to turnoff the panel\n");
1114 }
1115 }
1116
1117 static void exynos_dp_dpms(struct exynos_drm_display *display, int mode)
1118 {
1119 struct exynos_dp_device *dp = display_to_dp(display);
1120
1121 switch (mode) {
1122 case DRM_MODE_DPMS_ON:
1123 exynos_dp_poweron(dp);
1124 break;
1125 case DRM_MODE_DPMS_STANDBY:
1126 case DRM_MODE_DPMS_SUSPEND:
1127 case DRM_MODE_DPMS_OFF:
1128 exynos_dp_poweroff(dp);
1129 break;
1130 default:
1131 break;
1132 }
1133 dp->dpms_mode = mode;
1134 }
1135
1136 static struct exynos_drm_display_ops exynos_dp_display_ops = {
1137 .create_connector = exynos_dp_create_connector,
1138 .dpms = exynos_dp_dpms,
1139 .commit = exynos_dp_commit,
1140 };
1141
1142 static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
1143 {
1144 struct device_node *dp_node = dev->of_node;
1145 struct video_info *dp_video_config;
1146
1147 dp_video_config = devm_kzalloc(dev,
1148 sizeof(*dp_video_config), GFP_KERNEL);
1149 if (!dp_video_config)
1150 return ERR_PTR(-ENOMEM);
1151
1152 dp_video_config->h_sync_polarity =
1153 of_property_read_bool(dp_node, "hsync-active-high");
1154
1155 dp_video_config->v_sync_polarity =
1156 of_property_read_bool(dp_node, "vsync-active-high");
1157
1158 dp_video_config->interlaced =
1159 of_property_read_bool(dp_node, "interlaced");
1160
1161 if (of_property_read_u32(dp_node, "samsung,color-space",
1162 &dp_video_config->color_space)) {
1163 dev_err(dev, "failed to get color-space\n");
1164 return ERR_PTR(-EINVAL);
1165 }
1166
1167 if (of_property_read_u32(dp_node, "samsung,dynamic-range",
1168 &dp_video_config->dynamic_range)) {
1169 dev_err(dev, "failed to get dynamic-range\n");
1170 return ERR_PTR(-EINVAL);
1171 }
1172
1173 if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1174 &dp_video_config->ycbcr_coeff)) {
1175 dev_err(dev, "failed to get ycbcr-coeff\n");
1176 return ERR_PTR(-EINVAL);
1177 }
1178
1179 if (of_property_read_u32(dp_node, "samsung,color-depth",
1180 &dp_video_config->color_depth)) {
1181 dev_err(dev, "failed to get color-depth\n");
1182 return ERR_PTR(-EINVAL);
1183 }
1184
1185 if (of_property_read_u32(dp_node, "samsung,link-rate",
1186 &dp_video_config->link_rate)) {
1187 dev_err(dev, "failed to get link-rate\n");
1188 return ERR_PTR(-EINVAL);
1189 }
1190
1191 if (of_property_read_u32(dp_node, "samsung,lane-count",
1192 &dp_video_config->lane_count)) {
1193 dev_err(dev, "failed to get lane-count\n");
1194 return ERR_PTR(-EINVAL);
1195 }
1196
1197 return dp_video_config;
1198 }
1199
1200 static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
1201 {
1202 int ret;
1203
1204 ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
1205 OF_USE_NATIVE_MODE);
1206 if (ret) {
1207 DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
1208 return ret;
1209 }
1210 return 0;
1211 }
1212
1213 static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
1214 {
1215 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1216 struct platform_device *pdev = to_platform_device(dev);
1217 struct drm_device *drm_dev = data;
1218 struct resource *res;
1219 unsigned int irq_flags;
1220 int ret = 0;
1221
1222 dp->dev = &pdev->dev;
1223 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1224
1225 dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
1226 if (IS_ERR(dp->video_info))
1227 return PTR_ERR(dp->video_info);
1228
1229 dp->phy = devm_phy_get(dp->dev, "dp");
1230 if (IS_ERR(dp->phy)) {
1231 dev_err(dp->dev, "no DP phy configured\n");
1232 ret = PTR_ERR(dp->phy);
1233 if (ret) {
1234 /*
1235 * phy itself is not enabled, so we can move forward
1236 * assigning NULL to phy pointer.
1237 */
1238 if (ret == -ENOSYS || ret == -ENODEV)
1239 dp->phy = NULL;
1240 else
1241 return ret;
1242 }
1243 }
1244
1245 if (!dp->panel && !dp->bridge) {
1246 ret = exynos_dp_dt_parse_panel(dp);
1247 if (ret)
1248 return ret;
1249 }
1250
1251 dp->clock = devm_clk_get(&pdev->dev, "dp");
1252 if (IS_ERR(dp->clock)) {
1253 dev_err(&pdev->dev, "failed to get clock\n");
1254 return PTR_ERR(dp->clock);
1255 }
1256
1257 clk_prepare_enable(dp->clock);
1258
1259 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1260
1261 dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1262 if (IS_ERR(dp->reg_base))
1263 return PTR_ERR(dp->reg_base);
1264
1265 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
1266
1267 if (gpio_is_valid(dp->hpd_gpio)) {
1268 /*
1269 * Set up the hotplug GPIO from the device tree as an interrupt.
1270 * Simply specifying a different interrupt in the device tree
1271 * doesn't work since we handle hotplug rather differently when
1272 * using a GPIO. We also need the actual GPIO specifier so
1273 * that we can get the current state of the GPIO.
1274 */
1275 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1276 "hpd_gpio");
1277 if (ret) {
1278 dev_err(&pdev->dev, "failed to get hpd gpio\n");
1279 return ret;
1280 }
1281 dp->irq = gpio_to_irq(dp->hpd_gpio);
1282 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1283 } else {
1284 dp->hpd_gpio = -ENODEV;
1285 dp->irq = platform_get_irq(pdev, 0);
1286 irq_flags = 0;
1287 }
1288
1289 if (dp->irq == -ENXIO) {
1290 dev_err(&pdev->dev, "failed to get irq\n");
1291 return -ENODEV;
1292 }
1293
1294 INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1295
1296 exynos_dp_phy_init(dp);
1297
1298 exynos_dp_init_dp(dp);
1299
1300 ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
1301 irq_flags, "exynos-dp", dp);
1302 if (ret) {
1303 dev_err(&pdev->dev, "failed to request irq\n");
1304 return ret;
1305 }
1306 disable_irq(dp->irq);
1307
1308 dp->drm_dev = drm_dev;
1309
1310 return exynos_drm_create_enc_conn(drm_dev, &dp->display);
1311 }
1312
1313 static void exynos_dp_unbind(struct device *dev, struct device *master,
1314 void *data)
1315 {
1316 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1317
1318 exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_OFF);
1319 }
1320
1321 static const struct component_ops exynos_dp_ops = {
1322 .bind = exynos_dp_bind,
1323 .unbind = exynos_dp_unbind,
1324 };
1325
1326 static int exynos_dp_probe(struct platform_device *pdev)
1327 {
1328 struct device *dev = &pdev->dev;
1329 struct device_node *panel_node, *bridge_node, *endpoint;
1330 struct exynos_dp_device *dp;
1331 int ret;
1332
1333 dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
1334 GFP_KERNEL);
1335 if (!dp)
1336 return -ENOMEM;
1337
1338 dp->display.type = EXYNOS_DISPLAY_TYPE_LCD;
1339 dp->display.ops = &exynos_dp_display_ops;
1340 platform_set_drvdata(pdev, dp);
1341
1342 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1343 dp->display.type);
1344 if (ret)
1345 return ret;
1346
1347 panel_node = of_parse_phandle(dev->of_node, "panel", 0);
1348 if (panel_node) {
1349 dp->panel = of_drm_find_panel(panel_node);
1350 of_node_put(panel_node);
1351 if (!dp->panel)
1352 return -EPROBE_DEFER;
1353 }
1354
1355 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1356 if (endpoint) {
1357 bridge_node = of_graph_get_remote_port_parent(endpoint);
1358 if (bridge_node) {
1359 dp->bridge = of_drm_find_bridge(bridge_node);
1360 of_node_put(bridge_node);
1361 if (!dp->bridge)
1362 return -EPROBE_DEFER;
1363 } else
1364 return -EPROBE_DEFER;
1365 }
1366
1367 ret = component_add(&pdev->dev, &exynos_dp_ops);
1368 if (ret)
1369 exynos_drm_component_del(&pdev->dev,
1370 EXYNOS_DEVICE_TYPE_CONNECTOR);
1371
1372 return ret;
1373 }
1374
1375 static int exynos_dp_remove(struct platform_device *pdev)
1376 {
1377 component_del(&pdev->dev, &exynos_dp_ops);
1378 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1379
1380 return 0;
1381 }
1382
1383 #ifdef CONFIG_PM_SLEEP
1384 static int exynos_dp_suspend(struct device *dev)
1385 {
1386 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1387
1388 exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_OFF);
1389 return 0;
1390 }
1391
1392 static int exynos_dp_resume(struct device *dev)
1393 {
1394 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1395
1396 exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_ON);
1397 return 0;
1398 }
1399 #endif
1400
1401 static const struct dev_pm_ops exynos_dp_pm_ops = {
1402 SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1403 };
1404
1405 static const struct of_device_id exynos_dp_match[] = {
1406 { .compatible = "samsung,exynos5-dp" },
1407 {},
1408 };
1409 MODULE_DEVICE_TABLE(of, exynos_dp_match);
1410
1411 struct platform_driver dp_driver = {
1412 .probe = exynos_dp_probe,
1413 .remove = exynos_dp_remove,
1414 .driver = {
1415 .name = "exynos-dp",
1416 .owner = THIS_MODULE,
1417 .pm = &exynos_dp_pm_ops,
1418 .of_match_table = exynos_dp_match,
1419 },
1420 };
1421
1422 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1423 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1424 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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