2 * Samsung SoC DP (Display Port) interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
21 #include <linux/phy/phy.h>
22 #include <video/of_display_timing.h>
23 #include <video/of_videomode.h>
26 #include <drm/drm_crtc.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/bridge/ptn3460.h>
30 #include "exynos_drm_drv.h"
31 #include "exynos_dp_core.h"
33 #define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \
37 struct i2c_client
*client
;
38 struct device_node
*node
;
41 static int exynos_dp_init_dp(struct exynos_dp_device
*dp
)
45 exynos_dp_swreset(dp
);
47 exynos_dp_init_analog_param(dp
);
48 exynos_dp_init_interrupt(dp
);
50 /* SW defined function Normal operation */
51 exynos_dp_enable_sw_function(dp
);
53 exynos_dp_config_interrupt(dp
);
54 exynos_dp_init_analog_func(dp
);
56 exynos_dp_init_hpd(dp
);
57 exynos_dp_init_aux(dp
);
62 static int exynos_dp_detect_hpd(struct exynos_dp_device
*dp
)
66 while (exynos_dp_get_plug_in_status(dp
) != 0) {
68 if (DP_TIMEOUT_LOOP_COUNT
< timeout_loop
) {
69 dev_err(dp
->dev
, "failed to get hpd plug status\n");
78 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data
)
81 unsigned char sum
= 0;
83 for (i
= 0; i
< EDID_BLOCK_LENGTH
; i
++)
84 sum
= sum
+ edid_data
[i
];
89 static int exynos_dp_read_edid(struct exynos_dp_device
*dp
)
91 unsigned char edid
[EDID_BLOCK_LENGTH
* 2];
92 unsigned int extend_block
= 0;
94 unsigned char test_vector
;
98 * EDID device address is 0x50.
99 * However, if necessary, you must have set upper address
100 * into E-EDID in I2C device, 0x30.
103 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
104 retval
= exynos_dp_read_byte_from_i2c(dp
, I2C_EDID_DEVICE_ADDR
,
110 if (extend_block
> 0) {
111 dev_dbg(dp
->dev
, "EDID data includes a single extension!\n");
114 retval
= exynos_dp_read_bytes_from_i2c(dp
, I2C_EDID_DEVICE_ADDR
,
117 &edid
[EDID_HEADER_PATTERN
]);
119 dev_err(dp
->dev
, "EDID Read failed!\n");
122 sum
= exynos_dp_calc_edid_check_sum(edid
);
124 dev_err(dp
->dev
, "EDID bad checksum!\n");
128 /* Read additional EDID data */
129 retval
= exynos_dp_read_bytes_from_i2c(dp
,
130 I2C_EDID_DEVICE_ADDR
,
133 &edid
[EDID_BLOCK_LENGTH
]);
135 dev_err(dp
->dev
, "EDID Read failed!\n");
138 sum
= exynos_dp_calc_edid_check_sum(&edid
[EDID_BLOCK_LENGTH
]);
140 dev_err(dp
->dev
, "EDID bad checksum!\n");
144 exynos_dp_read_byte_from_dpcd(dp
, DPCD_ADDR_TEST_REQUEST
,
146 if (test_vector
& DPCD_TEST_EDID_READ
) {
147 exynos_dp_write_byte_to_dpcd(dp
,
148 DPCD_ADDR_TEST_EDID_CHECKSUM
,
149 edid
[EDID_BLOCK_LENGTH
+ EDID_CHECKSUM
]);
150 exynos_dp_write_byte_to_dpcd(dp
,
151 DPCD_ADDR_TEST_RESPONSE
,
152 DPCD_TEST_EDID_CHECKSUM_WRITE
);
155 dev_info(dp
->dev
, "EDID data does not include any extensions.\n");
158 retval
= exynos_dp_read_bytes_from_i2c(dp
,
159 I2C_EDID_DEVICE_ADDR
,
162 &edid
[EDID_HEADER_PATTERN
]);
164 dev_err(dp
->dev
, "EDID Read failed!\n");
167 sum
= exynos_dp_calc_edid_check_sum(edid
);
169 dev_err(dp
->dev
, "EDID bad checksum!\n");
173 exynos_dp_read_byte_from_dpcd(dp
,
174 DPCD_ADDR_TEST_REQUEST
,
176 if (test_vector
& DPCD_TEST_EDID_READ
) {
177 exynos_dp_write_byte_to_dpcd(dp
,
178 DPCD_ADDR_TEST_EDID_CHECKSUM
,
179 edid
[EDID_CHECKSUM
]);
180 exynos_dp_write_byte_to_dpcd(dp
,
181 DPCD_ADDR_TEST_RESPONSE
,
182 DPCD_TEST_EDID_CHECKSUM_WRITE
);
186 dev_err(dp
->dev
, "EDID Read success!\n");
190 static int exynos_dp_handle_edid(struct exynos_dp_device
*dp
)
196 /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
197 retval
= exynos_dp_read_bytes_from_dpcd(dp
, DPCD_ADDR_DPCD_REV
,
203 for (i
= 0; i
< 3; i
++) {
204 retval
= exynos_dp_read_edid(dp
);
212 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device
*dp
,
217 exynos_dp_read_byte_from_dpcd(dp
, DPCD_ADDR_LANE_COUNT_SET
, &data
);
220 exynos_dp_write_byte_to_dpcd(dp
, DPCD_ADDR_LANE_COUNT_SET
,
221 DPCD_ENHANCED_FRAME_EN
|
222 DPCD_LANE_COUNT_SET(data
));
224 exynos_dp_write_byte_to_dpcd(dp
, DPCD_ADDR_LANE_COUNT_SET
,
225 DPCD_LANE_COUNT_SET(data
));
228 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device
*dp
)
233 exynos_dp_read_byte_from_dpcd(dp
, DPCD_ADDR_MAX_LANE_COUNT
, &data
);
234 retval
= DPCD_ENHANCED_FRAME_CAP(data
);
239 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device
*dp
)
243 data
= exynos_dp_is_enhanced_mode_available(dp
);
244 exynos_dp_enable_rx_to_enhanced_mode(dp
, data
);
245 exynos_dp_enable_enhanced_mode(dp
, data
);
248 static void exynos_dp_training_pattern_dis(struct exynos_dp_device
*dp
)
250 exynos_dp_set_training_pattern(dp
, DP_NONE
);
252 exynos_dp_write_byte_to_dpcd(dp
,
253 DPCD_ADDR_TRAINING_PATTERN_SET
,
254 DPCD_TRAINING_PATTERN_DISABLED
);
257 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device
*dp
,
258 int pre_emphasis
, int lane
)
262 exynos_dp_set_lane0_pre_emphasis(dp
, pre_emphasis
);
265 exynos_dp_set_lane1_pre_emphasis(dp
, pre_emphasis
);
269 exynos_dp_set_lane2_pre_emphasis(dp
, pre_emphasis
);
273 exynos_dp_set_lane3_pre_emphasis(dp
, pre_emphasis
);
278 static int exynos_dp_link_start(struct exynos_dp_device
*dp
)
281 int lane
, lane_count
, pll_tries
, retval
;
283 lane_count
= dp
->link_train
.lane_count
;
285 dp
->link_train
.lt_state
= CLOCK_RECOVERY
;
286 dp
->link_train
.eq_loop
= 0;
288 for (lane
= 0; lane
< lane_count
; lane
++)
289 dp
->link_train
.cr_loop
[lane
] = 0;
291 /* Set link rate and count as you want to establish*/
292 exynos_dp_set_link_bandwidth(dp
, dp
->link_train
.link_rate
);
293 exynos_dp_set_lane_count(dp
, dp
->link_train
.lane_count
);
295 /* Setup RX configuration */
296 buf
[0] = dp
->link_train
.link_rate
;
297 buf
[1] = dp
->link_train
.lane_count
;
298 retval
= exynos_dp_write_bytes_to_dpcd(dp
, DPCD_ADDR_LINK_BW_SET
,
303 /* Set TX pre-emphasis to minimum */
304 for (lane
= 0; lane
< lane_count
; lane
++)
305 exynos_dp_set_lane_lane_pre_emphasis(dp
,
306 PRE_EMPHASIS_LEVEL_0
, lane
);
308 /* Wait for PLL lock */
310 while (exynos_dp_get_pll_lock_status(dp
) == PLL_UNLOCKED
) {
311 if (pll_tries
== DP_TIMEOUT_LOOP_COUNT
) {
312 dev_err(dp
->dev
, "Wait for PLL lock timed out\n");
317 usleep_range(90, 120);
320 /* Set training pattern 1 */
321 exynos_dp_set_training_pattern(dp
, TRAINING_PTN1
);
323 /* Set RX training pattern */
324 retval
= exynos_dp_write_byte_to_dpcd(dp
,
325 DPCD_ADDR_TRAINING_PATTERN_SET
,
326 DPCD_SCRAMBLING_DISABLED
| DPCD_TRAINING_PATTERN_1
);
330 for (lane
= 0; lane
< lane_count
; lane
++)
331 buf
[lane
] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0
|
332 DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0
;
334 retval
= exynos_dp_write_bytes_to_dpcd(dp
, DPCD_ADDR_TRAINING_LANE0_SET
,
340 static unsigned char exynos_dp_get_lane_status(u8 link_status
[2], int lane
)
342 int shift
= (lane
& 1) * 4;
343 u8 link_value
= link_status
[lane
>>1];
345 return (link_value
>> shift
) & 0xf;
348 static int exynos_dp_clock_recovery_ok(u8 link_status
[2], int lane_count
)
353 for (lane
= 0; lane
< lane_count
; lane
++) {
354 lane_status
= exynos_dp_get_lane_status(link_status
, lane
);
355 if ((lane_status
& DPCD_LANE_CR_DONE
) == 0)
361 static int exynos_dp_channel_eq_ok(u8 link_status
[2], u8 link_align
,
367 if ((link_align
& DPCD_INTERLANE_ALIGN_DONE
) == 0)
370 for (lane
= 0; lane
< lane_count
; lane
++) {
371 lane_status
= exynos_dp_get_lane_status(link_status
, lane
);
372 lane_status
&= DPCD_CHANNEL_EQ_BITS
;
373 if (lane_status
!= DPCD_CHANNEL_EQ_BITS
)
380 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request
[2],
383 int shift
= (lane
& 1) * 4;
384 u8 link_value
= adjust_request
[lane
>>1];
386 return (link_value
>> shift
) & 0x3;
389 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
390 u8 adjust_request
[2],
393 int shift
= (lane
& 1) * 4;
394 u8 link_value
= adjust_request
[lane
>>1];
396 return ((link_value
>> shift
) & 0xc) >> 2;
399 static void exynos_dp_set_lane_link_training(struct exynos_dp_device
*dp
,
400 u8 training_lane_set
, int lane
)
404 exynos_dp_set_lane0_link_training(dp
, training_lane_set
);
407 exynos_dp_set_lane1_link_training(dp
, training_lane_set
);
411 exynos_dp_set_lane2_link_training(dp
, training_lane_set
);
415 exynos_dp_set_lane3_link_training(dp
, training_lane_set
);
420 static unsigned int exynos_dp_get_lane_link_training(
421 struct exynos_dp_device
*dp
,
428 reg
= exynos_dp_get_lane0_link_training(dp
);
431 reg
= exynos_dp_get_lane1_link_training(dp
);
434 reg
= exynos_dp_get_lane2_link_training(dp
);
437 reg
= exynos_dp_get_lane3_link_training(dp
);
447 static void exynos_dp_reduce_link_rate(struct exynos_dp_device
*dp
)
449 exynos_dp_training_pattern_dis(dp
);
450 exynos_dp_set_enhanced_mode(dp
);
452 dp
->link_train
.lt_state
= FAILED
;
455 static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device
*dp
,
456 u8 adjust_request
[2])
458 int lane
, lane_count
;
459 u8 voltage_swing
, pre_emphasis
, training_lane
;
461 lane_count
= dp
->link_train
.lane_count
;
462 for (lane
= 0; lane
< lane_count
; lane
++) {
463 voltage_swing
= exynos_dp_get_adjust_request_voltage(
464 adjust_request
, lane
);
465 pre_emphasis
= exynos_dp_get_adjust_request_pre_emphasis(
466 adjust_request
, lane
);
467 training_lane
= DPCD_VOLTAGE_SWING_SET(voltage_swing
) |
468 DPCD_PRE_EMPHASIS_SET(pre_emphasis
);
470 if (voltage_swing
== VOLTAGE_LEVEL_3
)
471 training_lane
|= DPCD_MAX_SWING_REACHED
;
472 if (pre_emphasis
== PRE_EMPHASIS_LEVEL_3
)
473 training_lane
|= DPCD_MAX_PRE_EMPHASIS_REACHED
;
475 dp
->link_train
.training_lane
[lane
] = training_lane
;
479 static int exynos_dp_process_clock_recovery(struct exynos_dp_device
*dp
)
481 int lane
, lane_count
, retval
;
482 u8 voltage_swing
, pre_emphasis
, training_lane
;
483 u8 link_status
[2], adjust_request
[2];
485 usleep_range(100, 101);
487 lane_count
= dp
->link_train
.lane_count
;
489 retval
= exynos_dp_read_bytes_from_dpcd(dp
,
490 DPCD_ADDR_LANE0_1_STATUS
, 2, link_status
);
494 retval
= exynos_dp_read_bytes_from_dpcd(dp
,
495 DPCD_ADDR_ADJUST_REQUEST_LANE0_1
, 2, adjust_request
);
499 if (exynos_dp_clock_recovery_ok(link_status
, lane_count
) == 0) {
500 /* set training pattern 2 for EQ */
501 exynos_dp_set_training_pattern(dp
, TRAINING_PTN2
);
503 retval
= exynos_dp_write_byte_to_dpcd(dp
,
504 DPCD_ADDR_TRAINING_PATTERN_SET
,
505 DPCD_SCRAMBLING_DISABLED
|
506 DPCD_TRAINING_PATTERN_2
);
510 dev_info(dp
->dev
, "Link Training Clock Recovery success\n");
511 dp
->link_train
.lt_state
= EQUALIZER_TRAINING
;
513 for (lane
= 0; lane
< lane_count
; lane
++) {
514 training_lane
= exynos_dp_get_lane_link_training(
516 voltage_swing
= exynos_dp_get_adjust_request_voltage(
517 adjust_request
, lane
);
518 pre_emphasis
= exynos_dp_get_adjust_request_pre_emphasis(
519 adjust_request
, lane
);
521 if (DPCD_VOLTAGE_SWING_GET(training_lane
) ==
523 DPCD_PRE_EMPHASIS_GET(training_lane
) ==
525 dp
->link_train
.cr_loop
[lane
]++;
527 if (dp
->link_train
.cr_loop
[lane
] == MAX_CR_LOOP
||
528 voltage_swing
== VOLTAGE_LEVEL_3
||
529 pre_emphasis
== PRE_EMPHASIS_LEVEL_3
) {
530 dev_err(dp
->dev
, "CR Max reached (%d,%d,%d)\n",
531 dp
->link_train
.cr_loop
[lane
],
532 voltage_swing
, pre_emphasis
);
533 exynos_dp_reduce_link_rate(dp
);
539 exynos_dp_get_adjust_training_lane(dp
, adjust_request
);
541 for (lane
= 0; lane
< lane_count
; lane
++)
542 exynos_dp_set_lane_link_training(dp
,
543 dp
->link_train
.training_lane
[lane
], lane
);
545 retval
= exynos_dp_write_bytes_to_dpcd(dp
,
546 DPCD_ADDR_TRAINING_LANE0_SET
, lane_count
,
547 dp
->link_train
.training_lane
);
554 static int exynos_dp_process_equalizer_training(struct exynos_dp_device
*dp
)
556 int lane
, lane_count
, retval
;
558 u8 link_align
, link_status
[2], adjust_request
[2];
560 usleep_range(400, 401);
562 lane_count
= dp
->link_train
.lane_count
;
564 retval
= exynos_dp_read_bytes_from_dpcd(dp
,
565 DPCD_ADDR_LANE0_1_STATUS
, 2, link_status
);
569 if (exynos_dp_clock_recovery_ok(link_status
, lane_count
)) {
570 exynos_dp_reduce_link_rate(dp
);
574 retval
= exynos_dp_read_bytes_from_dpcd(dp
,
575 DPCD_ADDR_ADJUST_REQUEST_LANE0_1
, 2, adjust_request
);
579 retval
= exynos_dp_read_byte_from_dpcd(dp
,
580 DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED
, &link_align
);
584 exynos_dp_get_adjust_training_lane(dp
, adjust_request
);
586 if (!exynos_dp_channel_eq_ok(link_status
, link_align
, lane_count
)) {
587 /* traing pattern Set to Normal */
588 exynos_dp_training_pattern_dis(dp
);
590 dev_info(dp
->dev
, "Link Training success!\n");
592 exynos_dp_get_link_bandwidth(dp
, ®
);
593 dp
->link_train
.link_rate
= reg
;
594 dev_dbg(dp
->dev
, "final bandwidth = %.2x\n",
595 dp
->link_train
.link_rate
);
597 exynos_dp_get_lane_count(dp
, ®
);
598 dp
->link_train
.lane_count
= reg
;
599 dev_dbg(dp
->dev
, "final lane count = %.2x\n",
600 dp
->link_train
.lane_count
);
602 /* set enhanced mode if available */
603 exynos_dp_set_enhanced_mode(dp
);
604 dp
->link_train
.lt_state
= FINISHED
;
610 dp
->link_train
.eq_loop
++;
612 if (dp
->link_train
.eq_loop
> MAX_EQ_LOOP
) {
613 dev_err(dp
->dev
, "EQ Max loop\n");
614 exynos_dp_reduce_link_rate(dp
);
618 for (lane
= 0; lane
< lane_count
; lane
++)
619 exynos_dp_set_lane_link_training(dp
,
620 dp
->link_train
.training_lane
[lane
], lane
);
622 retval
= exynos_dp_write_bytes_to_dpcd(dp
, DPCD_ADDR_TRAINING_LANE0_SET
,
623 lane_count
, dp
->link_train
.training_lane
);
628 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device
*dp
,
634 * For DP rev.1.1, Maximum link rate of Main Link lanes
635 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
637 exynos_dp_read_byte_from_dpcd(dp
, DPCD_ADDR_MAX_LINK_RATE
, &data
);
641 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device
*dp
,
647 * For DP rev.1.1, Maximum number of Main Link lanes
648 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
650 exynos_dp_read_byte_from_dpcd(dp
, DPCD_ADDR_MAX_LANE_COUNT
, &data
);
651 *lane_count
= DPCD_MAX_LANE_COUNT(data
);
654 static void exynos_dp_init_training(struct exynos_dp_device
*dp
,
655 enum link_lane_count_type max_lane
,
656 enum link_rate_type max_rate
)
659 * MACRO_RST must be applied after the PLL_LOCK to avoid
660 * the DP inter pair skew issue for at least 10 us
662 exynos_dp_reset_macro(dp
);
664 /* Initialize by reading RX's DPCD */
665 exynos_dp_get_max_rx_bandwidth(dp
, &dp
->link_train
.link_rate
);
666 exynos_dp_get_max_rx_lane_count(dp
, &dp
->link_train
.lane_count
);
668 if ((dp
->link_train
.link_rate
!= LINK_RATE_1_62GBPS
) &&
669 (dp
->link_train
.link_rate
!= LINK_RATE_2_70GBPS
)) {
670 dev_err(dp
->dev
, "Rx Max Link Rate is abnormal :%x !\n",
671 dp
->link_train
.link_rate
);
672 dp
->link_train
.link_rate
= LINK_RATE_1_62GBPS
;
675 if (dp
->link_train
.lane_count
== 0) {
676 dev_err(dp
->dev
, "Rx Max Lane count is abnormal :%x !\n",
677 dp
->link_train
.lane_count
);
678 dp
->link_train
.lane_count
= (u8
)LANE_COUNT1
;
681 /* Setup TX lane count & rate */
682 if (dp
->link_train
.lane_count
> max_lane
)
683 dp
->link_train
.lane_count
= max_lane
;
684 if (dp
->link_train
.link_rate
> max_rate
)
685 dp
->link_train
.link_rate
= max_rate
;
687 /* All DP analog module power up */
688 exynos_dp_set_analog_power_down(dp
, POWER_ALL
, 0);
691 static int exynos_dp_sw_link_training(struct exynos_dp_device
*dp
)
693 int retval
= 0, training_finished
= 0;
695 dp
->link_train
.lt_state
= START
;
698 while (!retval
&& !training_finished
) {
699 switch (dp
->link_train
.lt_state
) {
701 retval
= exynos_dp_link_start(dp
);
703 dev_err(dp
->dev
, "LT link start failed!\n");
706 retval
= exynos_dp_process_clock_recovery(dp
);
708 dev_err(dp
->dev
, "LT CR failed!\n");
710 case EQUALIZER_TRAINING
:
711 retval
= exynos_dp_process_equalizer_training(dp
);
713 dev_err(dp
->dev
, "LT EQ failed!\n");
716 training_finished
= 1;
723 dev_err(dp
->dev
, "eDP link training failed (%d)\n", retval
);
728 static int exynos_dp_set_link_train(struct exynos_dp_device
*dp
,
735 for (i
= 0; i
< DP_TIMEOUT_LOOP_COUNT
; i
++) {
736 exynos_dp_init_training(dp
, count
, bwtype
);
737 retval
= exynos_dp_sw_link_training(dp
);
741 usleep_range(100, 110);
747 static int exynos_dp_config_video(struct exynos_dp_device
*dp
)
750 int timeout_loop
= 0;
753 exynos_dp_config_video_slave_mode(dp
);
755 exynos_dp_set_video_color_format(dp
);
757 if (exynos_dp_get_pll_lock_status(dp
) == PLL_UNLOCKED
) {
758 dev_err(dp
->dev
, "PLL is not locked yet.\n");
764 if (exynos_dp_is_slave_video_stream_clock_on(dp
) == 0)
766 if (DP_TIMEOUT_LOOP_COUNT
< timeout_loop
) {
767 dev_err(dp
->dev
, "Timeout of video streamclk ok\n");
774 /* Set to use the register calculated M/N video */
775 exynos_dp_set_video_cr_mn(dp
, CALCULATED_M
, 0, 0);
777 /* For video bist, Video timing must be generated by register */
778 exynos_dp_set_video_timing_mode(dp
, VIDEO_TIMING_FROM_CAPTURE
);
780 /* Disable video mute */
781 exynos_dp_enable_video_mute(dp
, 0);
783 /* Configure video slave mode */
784 exynos_dp_enable_video_master(dp
, 0);
787 exynos_dp_start_video(dp
);
793 if (exynos_dp_is_video_stream_on(dp
) == 0) {
797 } else if (done_count
) {
800 if (DP_TIMEOUT_LOOP_COUNT
< timeout_loop
) {
801 dev_err(dp
->dev
, "Timeout of video streamclk ok\n");
805 usleep_range(1000, 1001);
809 dev_err(dp
->dev
, "Video stream is not detected!\n");
814 static void exynos_dp_enable_scramble(struct exynos_dp_device
*dp
, bool enable
)
819 exynos_dp_enable_scrambling(dp
);
821 exynos_dp_read_byte_from_dpcd(dp
,
822 DPCD_ADDR_TRAINING_PATTERN_SET
,
824 exynos_dp_write_byte_to_dpcd(dp
,
825 DPCD_ADDR_TRAINING_PATTERN_SET
,
826 (u8
)(data
& ~DPCD_SCRAMBLING_DISABLED
));
828 exynos_dp_disable_scrambling(dp
);
830 exynos_dp_read_byte_from_dpcd(dp
,
831 DPCD_ADDR_TRAINING_PATTERN_SET
,
833 exynos_dp_write_byte_to_dpcd(dp
,
834 DPCD_ADDR_TRAINING_PATTERN_SET
,
835 (u8
)(data
| DPCD_SCRAMBLING_DISABLED
));
839 static irqreturn_t
exynos_dp_irq_handler(int irq
, void *arg
)
841 struct exynos_dp_device
*dp
= arg
;
843 enum dp_irq_type irq_type
;
845 irq_type
= exynos_dp_get_irq_type(dp
);
847 case DP_IRQ_TYPE_HP_CABLE_IN
:
848 dev_dbg(dp
->dev
, "Received irq - cable in\n");
849 schedule_work(&dp
->hotplug_work
);
850 exynos_dp_clear_hotplug_interrupts(dp
);
852 case DP_IRQ_TYPE_HP_CABLE_OUT
:
853 dev_dbg(dp
->dev
, "Received irq - cable out\n");
854 exynos_dp_clear_hotplug_interrupts(dp
);
856 case DP_IRQ_TYPE_HP_CHANGE
:
858 * We get these change notifications once in a while, but there
859 * is nothing we can do with them. Just ignore it for now and
860 * only handle cable changes.
862 dev_dbg(dp
->dev
, "Received irq - hotplug change; ignoring.\n");
863 exynos_dp_clear_hotplug_interrupts(dp
);
866 dev_err(dp
->dev
, "Received irq - unknown type!\n");
872 static void exynos_dp_hotplug(struct work_struct
*work
)
874 struct exynos_dp_device
*dp
;
877 dp
= container_of(work
, struct exynos_dp_device
, hotplug_work
);
879 ret
= exynos_dp_detect_hpd(dp
);
881 /* Cable has been disconnected, we're done */
885 ret
= exynos_dp_handle_edid(dp
);
887 dev_err(dp
->dev
, "unable to handle edid\n");
891 ret
= exynos_dp_set_link_train(dp
, dp
->video_info
->lane_count
,
892 dp
->video_info
->link_rate
);
894 dev_err(dp
->dev
, "unable to do link train\n");
898 exynos_dp_enable_scramble(dp
, 1);
899 exynos_dp_enable_rx_to_enhanced_mode(dp
, 1);
900 exynos_dp_enable_enhanced_mode(dp
, 1);
902 exynos_dp_set_lane_count(dp
, dp
->video_info
->lane_count
);
903 exynos_dp_set_link_bandwidth(dp
, dp
->video_info
->link_rate
);
905 exynos_dp_init_video(dp
);
906 ret
= exynos_dp_config_video(dp
);
908 dev_err(dp
->dev
, "unable to config video\n");
911 static enum drm_connector_status
exynos_dp_detect(
912 struct drm_connector
*connector
, bool force
)
914 return connector_status_connected
;
917 static void exynos_dp_connector_destroy(struct drm_connector
*connector
)
921 static struct drm_connector_funcs exynos_dp_connector_funcs
= {
922 .dpms
= drm_helper_connector_dpms
,
923 .fill_modes
= drm_helper_probe_single_connector_modes
,
924 .detect
= exynos_dp_detect
,
925 .destroy
= exynos_dp_connector_destroy
,
928 static int exynos_dp_get_modes(struct drm_connector
*connector
)
930 struct exynos_dp_device
*dp
= ctx_from_connector(connector
);
931 struct drm_display_mode
*mode
;
933 mode
= drm_mode_create(connector
->dev
);
935 DRM_ERROR("failed to create a new display mode.\n");
939 drm_display_mode_from_videomode(&dp
->panel
.vm
, mode
);
940 mode
->width_mm
= dp
->panel
.width_mm
;
941 mode
->height_mm
= dp
->panel
.height_mm
;
942 connector
->display_info
.width_mm
= mode
->width_mm
;
943 connector
->display_info
.height_mm
= mode
->height_mm
;
945 mode
->type
= DRM_MODE_TYPE_DRIVER
| DRM_MODE_TYPE_PREFERRED
;
946 drm_mode_set_name(mode
);
947 drm_mode_probed_add(connector
, mode
);
952 static struct drm_encoder
*exynos_dp_best_encoder(
953 struct drm_connector
*connector
)
955 struct exynos_dp_device
*dp
= ctx_from_connector(connector
);
960 static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs
= {
961 .get_modes
= exynos_dp_get_modes
,
962 .best_encoder
= exynos_dp_best_encoder
,
965 static int exynos_dp_initialize(struct exynos_drm_display
*display
,
966 struct drm_device
*drm_dev
)
968 struct exynos_dp_device
*dp
= display
->ctx
;
970 dp
->drm_dev
= drm_dev
;
975 static bool find_bridge(const char *compat
, struct bridge_init
*bridge
)
977 bridge
->client
= NULL
;
978 bridge
->node
= of_find_compatible_node(NULL
, NULL
, compat
);
982 bridge
->client
= of_find_i2c_device_by_node(bridge
->node
);
989 /* returns the number of bridges attached */
990 static int exynos_drm_attach_lcd_bridge(struct drm_device
*dev
,
991 struct drm_encoder
*encoder
)
993 struct bridge_init bridge
;
996 if (find_bridge("nxp,ptn3460", &bridge
)) {
997 ret
= ptn3460_init(dev
, encoder
, bridge
.client
, bridge
.node
);
1004 static int exynos_dp_create_connector(struct exynos_drm_display
*display
,
1005 struct drm_encoder
*encoder
)
1007 struct exynos_dp_device
*dp
= display
->ctx
;
1008 struct drm_connector
*connector
= &dp
->connector
;
1011 dp
->encoder
= encoder
;
1013 /* Pre-empt DP connector creation if there's a bridge */
1014 ret
= exynos_drm_attach_lcd_bridge(dp
->drm_dev
, encoder
);
1018 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1020 ret
= drm_connector_init(dp
->drm_dev
, connector
,
1021 &exynos_dp_connector_funcs
, DRM_MODE_CONNECTOR_eDP
);
1023 DRM_ERROR("Failed to initialize connector with drm\n");
1027 drm_connector_helper_add(connector
, &exynos_dp_connector_helper_funcs
);
1028 drm_sysfs_connector_add(connector
);
1029 drm_mode_connector_attach_encoder(connector
, encoder
);
1034 static void exynos_dp_phy_init(struct exynos_dp_device
*dp
)
1037 phy_power_on(dp
->phy
);
1038 } else if (dp
->phy_addr
) {
1041 reg
= __raw_readl(dp
->phy_addr
);
1042 reg
|= dp
->enable_mask
;
1043 __raw_writel(reg
, dp
->phy_addr
);
1047 static void exynos_dp_phy_exit(struct exynos_dp_device
*dp
)
1050 phy_power_off(dp
->phy
);
1051 } else if (dp
->phy_addr
) {
1054 reg
= __raw_readl(dp
->phy_addr
);
1055 reg
&= ~(dp
->enable_mask
);
1056 __raw_writel(reg
, dp
->phy_addr
);
1060 static void exynos_dp_poweron(struct exynos_dp_device
*dp
)
1062 if (dp
->dpms_mode
== DRM_MODE_DPMS_ON
)
1065 clk_prepare_enable(dp
->clock
);
1066 exynos_dp_phy_init(dp
);
1067 exynos_dp_init_dp(dp
);
1068 enable_irq(dp
->irq
);
1071 static void exynos_dp_poweroff(struct exynos_dp_device
*dp
)
1073 if (dp
->dpms_mode
!= DRM_MODE_DPMS_ON
)
1076 disable_irq(dp
->irq
);
1077 flush_work(&dp
->hotplug_work
);
1078 exynos_dp_phy_exit(dp
);
1079 clk_disable_unprepare(dp
->clock
);
1082 static void exynos_dp_dpms(struct exynos_drm_display
*display
, int mode
)
1084 struct exynos_dp_device
*dp
= display
->ctx
;
1087 case DRM_MODE_DPMS_ON
:
1088 exynos_dp_poweron(dp
);
1090 case DRM_MODE_DPMS_STANDBY
:
1091 case DRM_MODE_DPMS_SUSPEND
:
1092 case DRM_MODE_DPMS_OFF
:
1093 exynos_dp_poweroff(dp
);
1098 dp
->dpms_mode
= mode
;
1101 static struct exynos_drm_display_ops exynos_dp_display_ops
= {
1102 .initialize
= exynos_dp_initialize
,
1103 .create_connector
= exynos_dp_create_connector
,
1104 .dpms
= exynos_dp_dpms
,
1107 static struct exynos_drm_display exynos_dp_display
= {
1108 .type
= EXYNOS_DISPLAY_TYPE_LCD
,
1109 .ops
= &exynos_dp_display_ops
,
1112 static struct video_info
*exynos_dp_dt_parse_pdata(struct device
*dev
)
1114 struct device_node
*dp_node
= dev
->of_node
;
1115 struct video_info
*dp_video_config
;
1117 dp_video_config
= devm_kzalloc(dev
,
1118 sizeof(*dp_video_config
), GFP_KERNEL
);
1119 if (!dp_video_config
)
1120 return ERR_PTR(-ENOMEM
);
1122 dp_video_config
->h_sync_polarity
=
1123 of_property_read_bool(dp_node
, "hsync-active-high");
1125 dp_video_config
->v_sync_polarity
=
1126 of_property_read_bool(dp_node
, "vsync-active-high");
1128 dp_video_config
->interlaced
=
1129 of_property_read_bool(dp_node
, "interlaced");
1131 if (of_property_read_u32(dp_node
, "samsung,color-space",
1132 &dp_video_config
->color_space
)) {
1133 dev_err(dev
, "failed to get color-space\n");
1134 return ERR_PTR(-EINVAL
);
1137 if (of_property_read_u32(dp_node
, "samsung,dynamic-range",
1138 &dp_video_config
->dynamic_range
)) {
1139 dev_err(dev
, "failed to get dynamic-range\n");
1140 return ERR_PTR(-EINVAL
);
1143 if (of_property_read_u32(dp_node
, "samsung,ycbcr-coeff",
1144 &dp_video_config
->ycbcr_coeff
)) {
1145 dev_err(dev
, "failed to get ycbcr-coeff\n");
1146 return ERR_PTR(-EINVAL
);
1149 if (of_property_read_u32(dp_node
, "samsung,color-depth",
1150 &dp_video_config
->color_depth
)) {
1151 dev_err(dev
, "failed to get color-depth\n");
1152 return ERR_PTR(-EINVAL
);
1155 if (of_property_read_u32(dp_node
, "samsung,link-rate",
1156 &dp_video_config
->link_rate
)) {
1157 dev_err(dev
, "failed to get link-rate\n");
1158 return ERR_PTR(-EINVAL
);
1161 if (of_property_read_u32(dp_node
, "samsung,lane-count",
1162 &dp_video_config
->lane_count
)) {
1163 dev_err(dev
, "failed to get lane-count\n");
1164 return ERR_PTR(-EINVAL
);
1167 return dp_video_config
;
1170 static int exynos_dp_dt_parse_phydata(struct exynos_dp_device
*dp
)
1172 struct device_node
*dp_phy_node
= of_node_get(dp
->dev
->of_node
);
1176 dp_phy_node
= of_find_node_by_name(dp_phy_node
, "dptx-phy");
1178 dp
->phy
= devm_phy_get(dp
->dev
, "dp");
1179 if (IS_ERR(dp
->phy
))
1180 return PTR_ERR(dp
->phy
);
1185 if (of_property_read_u32(dp_phy_node
, "reg", &phy_base
)) {
1186 dev_err(dp
->dev
, "failed to get reg for dptx-phy\n");
1191 if (of_property_read_u32(dp_phy_node
, "samsung,enable-mask",
1192 &dp
->enable_mask
)) {
1193 dev_err(dp
->dev
, "failed to get enable-mask for dptx-phy\n");
1198 dp
->phy_addr
= ioremap(phy_base
, SZ_4
);
1199 if (!dp
->phy_addr
) {
1200 dev_err(dp
->dev
, "failed to ioremap dp-phy\n");
1206 of_node_put(dp_phy_node
);
1211 static int exynos_dp_dt_parse_panel(struct exynos_dp_device
*dp
)
1215 ret
= of_get_videomode(dp
->dev
->of_node
, &dp
->panel
.vm
,
1216 OF_USE_NATIVE_MODE
);
1218 DRM_ERROR("failed: of_get_videomode() : %d\n", ret
);
1224 static int exynos_dp_probe(struct platform_device
*pdev
)
1226 struct resource
*res
;
1227 struct exynos_dp_device
*dp
;
1231 dp
= devm_kzalloc(&pdev
->dev
, sizeof(struct exynos_dp_device
),
1236 dp
->dev
= &pdev
->dev
;
1237 dp
->dpms_mode
= DRM_MODE_DPMS_OFF
;
1239 dp
->video_info
= exynos_dp_dt_parse_pdata(&pdev
->dev
);
1240 if (IS_ERR(dp
->video_info
))
1241 return PTR_ERR(dp
->video_info
);
1243 ret
= exynos_dp_dt_parse_phydata(dp
);
1247 ret
= exynos_dp_dt_parse_panel(dp
);
1251 dp
->clock
= devm_clk_get(&pdev
->dev
, "dp");
1252 if (IS_ERR(dp
->clock
)) {
1253 dev_err(&pdev
->dev
, "failed to get clock\n");
1254 return PTR_ERR(dp
->clock
);
1257 clk_prepare_enable(dp
->clock
);
1259 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1261 dp
->reg_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1262 if (IS_ERR(dp
->reg_base
))
1263 return PTR_ERR(dp
->reg_base
);
1265 dp
->irq
= platform_get_irq(pdev
, 0);
1266 if (dp
->irq
== -ENXIO
) {
1267 dev_err(&pdev
->dev
, "failed to get irq\n");
1271 INIT_WORK(&dp
->hotplug_work
, exynos_dp_hotplug
);
1273 exynos_dp_phy_init(dp
);
1275 exynos_dp_init_dp(dp
);
1277 ret
= devm_request_irq(&pdev
->dev
, dp
->irq
, exynos_dp_irq_handler
, 0,
1280 dev_err(&pdev
->dev
, "failed to request irq\n");
1283 disable_irq(dp
->irq
);
1285 exynos_dp_display
.ctx
= dp
;
1287 platform_set_drvdata(pdev
, &exynos_dp_display
);
1288 exynos_drm_display_register(&exynos_dp_display
);
1293 static int exynos_dp_remove(struct platform_device
*pdev
)
1295 struct exynos_drm_display
*display
= platform_get_drvdata(pdev
);
1297 exynos_dp_dpms(display
, DRM_MODE_DPMS_OFF
);
1298 exynos_drm_display_unregister(&exynos_dp_display
);
1303 #ifdef CONFIG_PM_SLEEP
1304 static int exynos_dp_suspend(struct device
*dev
)
1306 struct platform_device
*pdev
= to_platform_device(dev
);
1307 struct exynos_drm_display
*display
= platform_get_drvdata(pdev
);
1309 exynos_dp_dpms(display
, DRM_MODE_DPMS_OFF
);
1313 static int exynos_dp_resume(struct device
*dev
)
1315 struct platform_device
*pdev
= to_platform_device(dev
);
1316 struct exynos_drm_display
*display
= platform_get_drvdata(pdev
);
1318 exynos_dp_dpms(display
, DRM_MODE_DPMS_ON
);
1323 static const struct dev_pm_ops exynos_dp_pm_ops
= {
1324 SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend
, exynos_dp_resume
)
1327 static const struct of_device_id exynos_dp_match
[] = {
1328 { .compatible
= "samsung,exynos5-dp" },
1332 struct platform_driver dp_driver
= {
1333 .probe
= exynos_dp_probe
,
1334 .remove
= exynos_dp_remove
,
1336 .name
= "exynos-dp",
1337 .owner
= THIS_MODULE
,
1338 .pm
= &exynos_dp_pm_ops
,
1339 .of_match_table
= exynos_dp_match
,
1343 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1344 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1345 MODULE_LICENSE("GPL");