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drm/exynos: dsi: make use of driver data for static values
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_dsi.c
1 /*
2 * Samsung SoC MIPI DSI Master driver.
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
5 *
6 * Contacts: Tomasz Figa <t.figa@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <drm/drmP.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_mipi_dsi.h>
16 #include <drm/drm_panel.h>
17 #include <drm/drm_atomic_helper.h>
18
19 #include <linux/clk.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/irq.h>
22 #include <linux/of_device.h>
23 #include <linux/of_gpio.h>
24 #include <linux/phy/phy.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/component.h>
27
28 #include <video/mipi_display.h>
29 #include <video/videomode.h>
30
31 #include "exynos_drm_crtc.h"
32 #include "exynos_drm_drv.h"
33
34 /* returns true iff both arguments logically differs */
35 #define NEQV(a, b) (!(a) ^ !(b))
36
37 /* DSIM_STATUS */
38 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
39 #define DSIM_STOP_STATE_CLK (1 << 8)
40 #define DSIM_TX_READY_HS_CLK (1 << 10)
41 #define DSIM_PLL_STABLE (1 << 31)
42
43 /* DSIM_SWRST */
44 #define DSIM_FUNCRST (1 << 16)
45 #define DSIM_SWRST (1 << 0)
46
47 /* DSIM_TIMEOUT */
48 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
49 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
50
51 /* DSIM_CLKCTRL */
52 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
53 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
54 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
55 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
56 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
57 #define DSIM_BYTE_CLKEN (1 << 24)
58 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
59 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
60 #define DSIM_PLL_BYPASS (1 << 27)
61 #define DSIM_ESC_CLKEN (1 << 28)
62 #define DSIM_TX_REQUEST_HSCLK (1 << 31)
63
64 /* DSIM_CONFIG */
65 #define DSIM_LANE_EN_CLK (1 << 0)
66 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
67 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
68 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
69 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
70 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
71 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
72 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
73 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
74 #define DSIM_SUB_VC (((x) & 0x3) << 16)
75 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
76 #define DSIM_HSA_MODE (1 << 20)
77 #define DSIM_HBP_MODE (1 << 21)
78 #define DSIM_HFP_MODE (1 << 22)
79 #define DSIM_HSE_MODE (1 << 23)
80 #define DSIM_AUTO_MODE (1 << 24)
81 #define DSIM_VIDEO_MODE (1 << 25)
82 #define DSIM_BURST_MODE (1 << 26)
83 #define DSIM_SYNC_INFORM (1 << 27)
84 #define DSIM_EOT_DISABLE (1 << 28)
85 #define DSIM_MFLUSH_VS (1 << 29)
86 /* This flag is valid only for exynos3250/3472/4415/5260/5430 */
87 #define DSIM_CLKLANE_STOP (1 << 30)
88
89 /* DSIM_ESCMODE */
90 #define DSIM_TX_TRIGGER_RST (1 << 4)
91 #define DSIM_TX_LPDT_LP (1 << 6)
92 #define DSIM_CMD_LPDT_LP (1 << 7)
93 #define DSIM_FORCE_BTA (1 << 16)
94 #define DSIM_FORCE_STOP_STATE (1 << 20)
95 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
96 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
97
98 /* DSIM_MDRESOL */
99 #define DSIM_MAIN_STAND_BY (1 << 31)
100 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
101 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
102
103 /* DSIM_MVPORCH */
104 #define DSIM_CMD_ALLOW(x) ((x) << 28)
105 #define DSIM_STABLE_VFP(x) ((x) << 16)
106 #define DSIM_MAIN_VBP(x) ((x) << 0)
107 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
108 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
109 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
110
111 /* DSIM_MHPORCH */
112 #define DSIM_MAIN_HFP(x) ((x) << 16)
113 #define DSIM_MAIN_HBP(x) ((x) << 0)
114 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
115 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
116
117 /* DSIM_MSYNC */
118 #define DSIM_MAIN_VSA(x) ((x) << 22)
119 #define DSIM_MAIN_HSA(x) ((x) << 0)
120 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
121 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
122
123 /* DSIM_SDRESOL */
124 #define DSIM_SUB_STANDY(x) ((x) << 31)
125 #define DSIM_SUB_VRESOL(x) ((x) << 16)
126 #define DSIM_SUB_HRESOL(x) ((x) << 0)
127 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
128 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
129 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
130
131 /* DSIM_INTSRC */
132 #define DSIM_INT_PLL_STABLE (1 << 31)
133 #define DSIM_INT_SW_RST_RELEASE (1 << 30)
134 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
135 #define DSIM_INT_BTA (1 << 25)
136 #define DSIM_INT_FRAME_DONE (1 << 24)
137 #define DSIM_INT_RX_TIMEOUT (1 << 21)
138 #define DSIM_INT_BTA_TIMEOUT (1 << 20)
139 #define DSIM_INT_RX_DONE (1 << 18)
140 #define DSIM_INT_RX_TE (1 << 17)
141 #define DSIM_INT_RX_ACK (1 << 16)
142 #define DSIM_INT_RX_ECC_ERR (1 << 15)
143 #define DSIM_INT_RX_CRC_ERR (1 << 14)
144
145 /* DSIM_FIFOCTRL */
146 #define DSIM_RX_DATA_FULL (1 << 25)
147 #define DSIM_RX_DATA_EMPTY (1 << 24)
148 #define DSIM_SFR_HEADER_FULL (1 << 23)
149 #define DSIM_SFR_HEADER_EMPTY (1 << 22)
150 #define DSIM_SFR_PAYLOAD_FULL (1 << 21)
151 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
152 #define DSIM_I80_HEADER_FULL (1 << 19)
153 #define DSIM_I80_HEADER_EMPTY (1 << 18)
154 #define DSIM_I80_PAYLOAD_FULL (1 << 17)
155 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
156 #define DSIM_SD_HEADER_FULL (1 << 15)
157 #define DSIM_SD_HEADER_EMPTY (1 << 14)
158 #define DSIM_SD_PAYLOAD_FULL (1 << 13)
159 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
160 #define DSIM_MD_HEADER_FULL (1 << 11)
161 #define DSIM_MD_HEADER_EMPTY (1 << 10)
162 #define DSIM_MD_PAYLOAD_FULL (1 << 9)
163 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
164 #define DSIM_RX_FIFO (1 << 4)
165 #define DSIM_SFR_FIFO (1 << 3)
166 #define DSIM_I80_FIFO (1 << 2)
167 #define DSIM_SD_FIFO (1 << 1)
168 #define DSIM_MD_FIFO (1 << 0)
169
170 /* DSIM_PHYACCHR */
171 #define DSIM_AFC_EN (1 << 14)
172 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
173
174 /* DSIM_PLLCTRL */
175 #define DSIM_FREQ_BAND(x) ((x) << 24)
176 #define DSIM_PLL_EN (1 << 23)
177 #define DSIM_PLL_P(x) ((x) << 13)
178 #define DSIM_PLL_M(x) ((x) << 4)
179 #define DSIM_PLL_S(x) ((x) << 1)
180
181 /* DSIM_PHYCTRL */
182 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
183
184 /* DSIM_PHYTIMING */
185 #define DSIM_PHYTIMING_LPX(x) ((x) << 8)
186 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
187
188 /* DSIM_PHYTIMING1 */
189 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
190 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
191 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
192 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
193
194 /* DSIM_PHYTIMING2 */
195 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
196 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
197 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
198
199 #define DSI_MAX_BUS_WIDTH 4
200 #define DSI_NUM_VIRTUAL_CHANNELS 4
201 #define DSI_TX_FIFO_SIZE 2048
202 #define DSI_RX_FIFO_SIZE 256
203 #define DSI_XFER_TIMEOUT_MS 100
204 #define DSI_RX_FIFO_EMPTY 0x30800002
205
206 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
207
208 #define REG_ADDR(dsi, reg_idx) ((dsi)->reg_base + \
209 dsi->driver_data->reg_ofs[(reg_idx)])
210 #define DSI_WRITE(dsi, reg_idx, val) writel((val), \
211 REG_ADDR((dsi), (reg_idx)))
212 #define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx)))
213
214 enum exynos_dsi_transfer_type {
215 EXYNOS_DSI_TX,
216 EXYNOS_DSI_RX,
217 };
218
219 struct exynos_dsi_transfer {
220 struct list_head list;
221 struct completion completed;
222 int result;
223 u8 data_id;
224 u8 data[2];
225 u16 flags;
226
227 const u8 *tx_payload;
228 u16 tx_len;
229 u16 tx_done;
230
231 u8 *rx_payload;
232 u16 rx_len;
233 u16 rx_done;
234 };
235
236 #define DSIM_STATE_ENABLED BIT(0)
237 #define DSIM_STATE_INITIALIZED BIT(1)
238 #define DSIM_STATE_CMD_LPM BIT(2)
239 #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
240
241 struct exynos_dsi_driver_data {
242 unsigned int *reg_ofs;
243 unsigned int plltmr_reg;
244 unsigned int has_freqband:1;
245 unsigned int has_clklane_stop:1;
246 unsigned int num_clks;
247 unsigned int max_freq;
248 unsigned int wait_for_reset;
249 unsigned int num_bits_resol;
250 unsigned int *reg_values;
251 };
252
253 struct exynos_dsi {
254 struct exynos_drm_display display;
255 struct mipi_dsi_host dsi_host;
256 struct drm_connector connector;
257 struct device_node *panel_node;
258 struct drm_panel *panel;
259 struct device *dev;
260
261 void __iomem *reg_base;
262 struct phy *phy;
263 struct clk *sclk_clk;
264 struct clk *bus_clk;
265 struct regulator_bulk_data supplies[2];
266 int irq;
267 int te_gpio;
268
269 u32 pll_clk_rate;
270 u32 burst_clk_rate;
271 u32 esc_clk_rate;
272 u32 lanes;
273 u32 mode_flags;
274 u32 format;
275 struct videomode vm;
276
277 int state;
278 struct drm_property *brightness;
279 struct completion completed;
280
281 spinlock_t transfer_lock; /* protects transfer_list */
282 struct list_head transfer_list;
283
284 struct exynos_dsi_driver_data *driver_data;
285 };
286
287 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
288 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
289
290 static inline struct exynos_dsi *display_to_dsi(struct exynos_drm_display *d)
291 {
292 return container_of(d, struct exynos_dsi, display);
293 }
294
295 enum reg_idx {
296 DSIM_STATUS_REG, /* Status register */
297 DSIM_SWRST_REG, /* Software reset register */
298 DSIM_CLKCTRL_REG, /* Clock control register */
299 DSIM_TIMEOUT_REG, /* Time out register */
300 DSIM_CONFIG_REG, /* Configuration register */
301 DSIM_ESCMODE_REG, /* Escape mode register */
302 DSIM_MDRESOL_REG,
303 DSIM_MVPORCH_REG, /* Main display Vporch register */
304 DSIM_MHPORCH_REG, /* Main display Hporch register */
305 DSIM_MSYNC_REG, /* Main display sync area register */
306 DSIM_INTSRC_REG, /* Interrupt source register */
307 DSIM_INTMSK_REG, /* Interrupt mask register */
308 DSIM_PKTHDR_REG, /* Packet Header FIFO register */
309 DSIM_PAYLOAD_REG, /* Payload FIFO register */
310 DSIM_RXFIFO_REG, /* Read FIFO register */
311 DSIM_FIFOCTRL_REG, /* FIFO status and control register */
312 DSIM_PLLCTRL_REG, /* PLL control register */
313 DSIM_PHYCTRL_REG,
314 DSIM_PHYTIMING_REG,
315 DSIM_PHYTIMING1_REG,
316 DSIM_PHYTIMING2_REG,
317 NUM_REGS
318 };
319 static unsigned int exynos_reg_ofs[] = {
320 [DSIM_STATUS_REG] = 0x00,
321 [DSIM_SWRST_REG] = 0x04,
322 [DSIM_CLKCTRL_REG] = 0x08,
323 [DSIM_TIMEOUT_REG] = 0x0c,
324 [DSIM_CONFIG_REG] = 0x10,
325 [DSIM_ESCMODE_REG] = 0x14,
326 [DSIM_MDRESOL_REG] = 0x18,
327 [DSIM_MVPORCH_REG] = 0x1c,
328 [DSIM_MHPORCH_REG] = 0x20,
329 [DSIM_MSYNC_REG] = 0x24,
330 [DSIM_INTSRC_REG] = 0x2c,
331 [DSIM_INTMSK_REG] = 0x30,
332 [DSIM_PKTHDR_REG] = 0x34,
333 [DSIM_PAYLOAD_REG] = 0x38,
334 [DSIM_RXFIFO_REG] = 0x3c,
335 [DSIM_FIFOCTRL_REG] = 0x44,
336 [DSIM_PLLCTRL_REG] = 0x4c,
337 [DSIM_PHYCTRL_REG] = 0x5c,
338 [DSIM_PHYTIMING_REG] = 0x64,
339 [DSIM_PHYTIMING1_REG] = 0x68,
340 [DSIM_PHYTIMING2_REG] = 0x6c,
341 };
342
343 enum reg_value_idx {
344 RESET_TYPE,
345 PLL_TIMER,
346 STOP_STATE_CNT,
347 PHYCTRL_ULPS_EXIT,
348 PHYCTRL_VREG_LP,
349 PHYCTRL_SLEW_UP,
350 PHYTIMING_LPX,
351 PHYTIMING_HS_EXIT,
352 PHYTIMING_CLK_PREPARE,
353 PHYTIMING_CLK_ZERO,
354 PHYTIMING_CLK_POST,
355 PHYTIMING_CLK_TRAIL,
356 PHYTIMING_HS_PREPARE,
357 PHYTIMING_HS_ZERO,
358 PHYTIMING_HS_TRAIL
359 };
360
361 static unsigned int reg_values[] = {
362 [RESET_TYPE] = DSIM_SWRST,
363 [PLL_TIMER] = 500,
364 [STOP_STATE_CNT] = 0xf,
365 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
366 [PHYCTRL_VREG_LP] = 0,
367 [PHYCTRL_SLEW_UP] = 0,
368 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
369 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
370 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
371 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
372 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
373 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
374 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
375 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
376 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
377 };
378
379 static struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
380 .reg_ofs = exynos_reg_ofs,
381 .plltmr_reg = 0x50,
382 .has_freqband = 1,
383 .has_clklane_stop = 1,
384 .num_clks = 2,
385 .max_freq = 1000,
386 .wait_for_reset = 1,
387 .num_bits_resol = 11,
388 .reg_values = reg_values,
389 };
390
391 static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
392 .reg_ofs = exynos_reg_ofs,
393 .plltmr_reg = 0x50,
394 .has_freqband = 1,
395 .has_clklane_stop = 1,
396 .num_clks = 2,
397 .max_freq = 1000,
398 .wait_for_reset = 1,
399 .num_bits_resol = 11,
400 .reg_values = reg_values,
401 };
402
403 static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
404 .reg_ofs = exynos_reg_ofs,
405 .plltmr_reg = 0x58,
406 .has_clklane_stop = 1,
407 .num_clks = 2,
408 .max_freq = 1000,
409 .wait_for_reset = 1,
410 .num_bits_resol = 11,
411 .reg_values = reg_values,
412 };
413
414 static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
415 .reg_ofs = exynos_reg_ofs,
416 .plltmr_reg = 0x58,
417 .num_clks = 2,
418 .max_freq = 1000,
419 .wait_for_reset = 1,
420 .num_bits_resol = 11,
421 .reg_values = reg_values,
422 };
423
424 static struct of_device_id exynos_dsi_of_match[] = {
425 { .compatible = "samsung,exynos3250-mipi-dsi",
426 .data = &exynos3_dsi_driver_data },
427 { .compatible = "samsung,exynos4210-mipi-dsi",
428 .data = &exynos4_dsi_driver_data },
429 { .compatible = "samsung,exynos4415-mipi-dsi",
430 .data = &exynos4415_dsi_driver_data },
431 { .compatible = "samsung,exynos5410-mipi-dsi",
432 .data = &exynos5_dsi_driver_data },
433 { }
434 };
435
436 static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
437 struct platform_device *pdev)
438 {
439 const struct of_device_id *of_id =
440 of_match_device(exynos_dsi_of_match, &pdev->dev);
441
442 return (struct exynos_dsi_driver_data *)of_id->data;
443 }
444
445 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
446 {
447 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
448 return;
449
450 dev_err(dsi->dev, "timeout waiting for reset\n");
451 }
452
453 static void exynos_dsi_reset(struct exynos_dsi *dsi)
454 {
455 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
456
457 reinit_completion(&dsi->completed);
458 DSI_WRITE(dsi, DSIM_SWRST_REG, driver_data->reg_values[RESET_TYPE]);
459 }
460
461 #ifndef MHZ
462 #define MHZ (1000*1000)
463 #endif
464
465 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
466 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
467 {
468 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
469 unsigned long best_freq = 0;
470 u32 min_delta = 0xffffffff;
471 u8 p_min, p_max;
472 u8 _p, uninitialized_var(best_p);
473 u16 _m, uninitialized_var(best_m);
474 u8 _s, uninitialized_var(best_s);
475
476 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
477 p_max = fin / (6 * MHZ);
478
479 for (_p = p_min; _p <= p_max; ++_p) {
480 for (_s = 0; _s <= 5; ++_s) {
481 u64 tmp;
482 u32 delta;
483
484 tmp = (u64)fout * (_p << _s);
485 do_div(tmp, fin);
486 _m = tmp;
487 if (_m < 41 || _m > 125)
488 continue;
489
490 tmp = (u64)_m * fin;
491 do_div(tmp, _p);
492 if (tmp < 500 * MHZ ||
493 tmp > driver_data->max_freq * MHZ)
494 continue;
495
496 tmp = (u64)_m * fin;
497 do_div(tmp, _p << _s);
498
499 delta = abs(fout - tmp);
500 if (delta < min_delta) {
501 best_p = _p;
502 best_m = _m;
503 best_s = _s;
504 min_delta = delta;
505 best_freq = tmp;
506 }
507 }
508 }
509
510 if (best_freq) {
511 *p = best_p;
512 *m = best_m;
513 *s = best_s;
514 }
515
516 return best_freq;
517 }
518
519 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
520 unsigned long freq)
521 {
522 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
523 unsigned long fin, fout;
524 int timeout;
525 u8 p, s;
526 u16 m;
527 u32 reg;
528
529 fin = dsi->pll_clk_rate;
530 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
531 if (!fout) {
532 dev_err(dsi->dev,
533 "failed to find PLL PMS for requested frequency\n");
534 return 0;
535 }
536 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
537
538 writel(driver_data->reg_values[PLL_TIMER],
539 dsi->reg_base + driver_data->plltmr_reg);
540
541 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
542
543 if (driver_data->has_freqband) {
544 static const unsigned long freq_bands[] = {
545 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
546 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
547 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
548 770 * MHZ, 870 * MHZ, 950 * MHZ,
549 };
550 int band;
551
552 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
553 if (fout < freq_bands[band])
554 break;
555
556 dev_dbg(dsi->dev, "band %d\n", band);
557
558 reg |= DSIM_FREQ_BAND(band);
559 }
560
561 DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg);
562
563 timeout = 1000;
564 do {
565 if (timeout-- == 0) {
566 dev_err(dsi->dev, "PLL failed to stabilize\n");
567 return 0;
568 }
569 reg = DSI_READ(dsi, DSIM_STATUS_REG);
570 } while ((reg & DSIM_PLL_STABLE) == 0);
571
572 return fout;
573 }
574
575 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
576 {
577 unsigned long hs_clk, byte_clk, esc_clk;
578 unsigned long esc_div;
579 u32 reg;
580
581 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
582 if (!hs_clk) {
583 dev_err(dsi->dev, "failed to configure DSI PLL\n");
584 return -EFAULT;
585 }
586
587 byte_clk = hs_clk / 8;
588 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
589 esc_clk = byte_clk / esc_div;
590
591 if (esc_clk > 20 * MHZ) {
592 ++esc_div;
593 esc_clk = byte_clk / esc_div;
594 }
595
596 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
597 hs_clk, byte_clk, esc_clk);
598
599 reg = DSI_READ(dsi, DSIM_CLKCTRL_REG);
600 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
601 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
602 | DSIM_BYTE_CLK_SRC_MASK);
603 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
604 | DSIM_ESC_PRESCALER(esc_div)
605 | DSIM_LANE_ESC_CLK_EN_CLK
606 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
607 | DSIM_BYTE_CLK_SRC(0)
608 | DSIM_TX_REQUEST_HSCLK;
609 DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg);
610
611 return 0;
612 }
613
614 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
615 {
616 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
617 unsigned int *reg_values = driver_data->reg_values;
618 u32 reg;
619
620 if (driver_data->has_freqband)
621 return;
622
623 /* B D-PHY: D-PHY Master & Slave Analog Block control */
624 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
625 reg_values[PHYCTRL_SLEW_UP];
626 DSI_WRITE(dsi, DSIM_PHYCTRL_REG, reg);
627
628 /*
629 * T LPX: Transmitted length of any Low-Power state period
630 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
631 * burst
632 */
633 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
634 DSI_WRITE(dsi, DSIM_PHYTIMING_REG, reg);
635
636 /*
637 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
638 * Line state immediately before the HS-0 Line state starting the
639 * HS transmission
640 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
641 * transmitting the Clock.
642 * T CLK_POST: Time that the transmitter continues to send HS clock
643 * after the last associated Data Lane has transitioned to LP Mode
644 * Interval is defined as the period from the end of T HS-TRAIL to
645 * the beginning of T CLK-TRAIL
646 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
647 * the last payload clock bit of a HS transmission burst
648 */
649 reg = reg_values[PHYTIMING_CLK_PREPARE] |
650 reg_values[PHYTIMING_CLK_ZERO] |
651 reg_values[PHYTIMING_CLK_POST] |
652 reg_values[PHYTIMING_CLK_TRAIL];
653
654 DSI_WRITE(dsi, DSIM_PHYTIMING1_REG, reg);
655
656 /*
657 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
658 * Line state immediately before the HS-0 Line state starting the
659 * HS transmission
660 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
661 * transmitting the Sync sequence.
662 * T HS-TRAIL: Time that the transmitter drives the flipped differential
663 * state after last payload data bit of a HS transmission burst
664 */
665 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
666 reg_values[PHYTIMING_HS_TRAIL];
667 DSI_WRITE(dsi, DSIM_PHYTIMING2_REG, reg);
668 }
669
670 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
671 {
672 u32 reg;
673
674 reg = DSI_READ(dsi, DSIM_CLKCTRL_REG);
675 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
676 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
677 DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg);
678
679 reg = DSI_READ(dsi, DSIM_PLLCTRL_REG);
680 reg &= ~DSIM_PLL_EN;
681 DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg);
682 }
683
684 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
685 {
686 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
687 int timeout;
688 u32 reg;
689 u32 lanes_mask;
690
691 /* Initialize FIFO pointers */
692 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG);
693 reg &= ~0x1f;
694 DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg);
695
696 usleep_range(9000, 11000);
697
698 reg |= 0x1f;
699 DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg);
700 usleep_range(9000, 11000);
701
702 /* DSI configuration */
703 reg = 0;
704
705 /*
706 * The first bit of mode_flags specifies display configuration.
707 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
708 * mode, otherwise it will support command mode.
709 */
710 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
711 reg |= DSIM_VIDEO_MODE;
712
713 /*
714 * The user manual describes that following bits are ignored in
715 * command mode.
716 */
717 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
718 reg |= DSIM_MFLUSH_VS;
719 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
720 reg |= DSIM_SYNC_INFORM;
721 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
722 reg |= DSIM_BURST_MODE;
723 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
724 reg |= DSIM_AUTO_MODE;
725 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
726 reg |= DSIM_HSE_MODE;
727 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
728 reg |= DSIM_HFP_MODE;
729 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
730 reg |= DSIM_HBP_MODE;
731 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
732 reg |= DSIM_HSA_MODE;
733 }
734
735 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
736 reg |= DSIM_EOT_DISABLE;
737
738 switch (dsi->format) {
739 case MIPI_DSI_FMT_RGB888:
740 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
741 break;
742 case MIPI_DSI_FMT_RGB666:
743 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
744 break;
745 case MIPI_DSI_FMT_RGB666_PACKED:
746 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
747 break;
748 case MIPI_DSI_FMT_RGB565:
749 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
750 break;
751 default:
752 dev_err(dsi->dev, "invalid pixel format\n");
753 return -EINVAL;
754 }
755
756 reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1);
757
758 DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
759
760 reg |= DSIM_LANE_EN_CLK;
761 DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
762
763 lanes_mask = BIT(dsi->lanes) - 1;
764 reg |= DSIM_LANE_EN(lanes_mask);
765 DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
766
767 /*
768 * Use non-continuous clock mode if the periparal wants and
769 * host controller supports
770 *
771 * In non-continous clock mode, host controller will turn off
772 * the HS clock between high-speed transmissions to reduce
773 * power consumption.
774 */
775 if (driver_data->has_clklane_stop &&
776 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
777 reg |= DSIM_CLKLANE_STOP;
778 DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
779 }
780
781 /* Check clock and data lane state are stop state */
782 timeout = 100;
783 do {
784 if (timeout-- == 0) {
785 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
786 return -EFAULT;
787 }
788
789 reg = DSI_READ(dsi, DSIM_STATUS_REG);
790 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
791 != DSIM_STOP_STATE_DAT(lanes_mask))
792 continue;
793 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
794
795 reg = DSI_READ(dsi, DSIM_ESCMODE_REG);
796 reg &= ~DSIM_STOP_STATE_CNT_MASK;
797 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
798 DSI_WRITE(dsi, DSIM_ESCMODE_REG, reg);
799
800 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
801 DSI_WRITE(dsi, DSIM_TIMEOUT_REG, reg);
802
803 return 0;
804 }
805
806 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
807 {
808 struct videomode *vm = &dsi->vm;
809 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
810 u32 reg;
811
812 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
813 reg = DSIM_CMD_ALLOW(0xf)
814 | DSIM_STABLE_VFP(vm->vfront_porch)
815 | DSIM_MAIN_VBP(vm->vback_porch);
816 DSI_WRITE(dsi, DSIM_MVPORCH_REG, reg);
817
818 reg = DSIM_MAIN_HFP(vm->hfront_porch)
819 | DSIM_MAIN_HBP(vm->hback_porch);
820 DSI_WRITE(dsi, DSIM_MHPORCH_REG, reg);
821
822 reg = DSIM_MAIN_VSA(vm->vsync_len)
823 | DSIM_MAIN_HSA(vm->hsync_len);
824 DSI_WRITE(dsi, DSIM_MSYNC_REG, reg);
825 }
826 reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) |
827 DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol);
828
829 DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg);
830
831 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
832 }
833
834 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
835 {
836 u32 reg;
837
838 reg = DSI_READ(dsi, DSIM_MDRESOL_REG);
839 if (enable)
840 reg |= DSIM_MAIN_STAND_BY;
841 else
842 reg &= ~DSIM_MAIN_STAND_BY;
843 DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg);
844 }
845
846 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
847 {
848 int timeout = 2000;
849
850 do {
851 u32 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG);
852
853 if (!(reg & DSIM_SFR_HEADER_FULL))
854 return 0;
855
856 if (!cond_resched())
857 usleep_range(950, 1050);
858 } while (--timeout);
859
860 return -ETIMEDOUT;
861 }
862
863 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
864 {
865 u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG);
866
867 if (lpm)
868 v |= DSIM_CMD_LPDT_LP;
869 else
870 v &= ~DSIM_CMD_LPDT_LP;
871
872 DSI_WRITE(dsi, DSIM_ESCMODE_REG, v);
873 }
874
875 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
876 {
877 u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG);
878 v |= DSIM_FORCE_BTA;
879 DSI_WRITE(dsi, DSIM_ESCMODE_REG, v);
880 }
881
882 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
883 struct exynos_dsi_transfer *xfer)
884 {
885 struct device *dev = dsi->dev;
886 const u8 *payload = xfer->tx_payload + xfer->tx_done;
887 u16 length = xfer->tx_len - xfer->tx_done;
888 bool first = !xfer->tx_done;
889 u32 reg;
890
891 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
892 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
893
894 if (length > DSI_TX_FIFO_SIZE)
895 length = DSI_TX_FIFO_SIZE;
896
897 xfer->tx_done += length;
898
899 /* Send payload */
900 while (length >= 4) {
901 reg = (payload[3] << 24) | (payload[2] << 16)
902 | (payload[1] << 8) | payload[0];
903 DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg);
904 payload += 4;
905 length -= 4;
906 }
907
908 reg = 0;
909 switch (length) {
910 case 3:
911 reg |= payload[2] << 16;
912 /* Fall through */
913 case 2:
914 reg |= payload[1] << 8;
915 /* Fall through */
916 case 1:
917 reg |= payload[0];
918 DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg);
919 break;
920 case 0:
921 /* Do nothing */
922 break;
923 }
924
925 /* Send packet header */
926 if (!first)
927 return;
928
929 reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id;
930 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
931 dev_err(dev, "waiting for header FIFO timed out\n");
932 return;
933 }
934
935 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
936 dsi->state & DSIM_STATE_CMD_LPM)) {
937 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
938 dsi->state ^= DSIM_STATE_CMD_LPM;
939 }
940
941 DSI_WRITE(dsi, DSIM_PKTHDR_REG, reg);
942
943 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
944 exynos_dsi_force_bta(dsi);
945 }
946
947 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
948 struct exynos_dsi_transfer *xfer)
949 {
950 u8 *payload = xfer->rx_payload + xfer->rx_done;
951 bool first = !xfer->rx_done;
952 struct device *dev = dsi->dev;
953 u16 length;
954 u32 reg;
955
956 if (first) {
957 reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
958
959 switch (reg & 0x3f) {
960 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
961 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
962 if (xfer->rx_len >= 2) {
963 payload[1] = reg >> 16;
964 ++xfer->rx_done;
965 }
966 /* Fall through */
967 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
968 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
969 payload[0] = reg >> 8;
970 ++xfer->rx_done;
971 xfer->rx_len = xfer->rx_done;
972 xfer->result = 0;
973 goto clear_fifo;
974 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
975 dev_err(dev, "DSI Error Report: 0x%04x\n",
976 (reg >> 8) & 0xffff);
977 xfer->result = 0;
978 goto clear_fifo;
979 }
980
981 length = (reg >> 8) & 0xffff;
982 if (length > xfer->rx_len) {
983 dev_err(dev,
984 "response too long (%u > %u bytes), stripping\n",
985 xfer->rx_len, length);
986 length = xfer->rx_len;
987 } else if (length < xfer->rx_len)
988 xfer->rx_len = length;
989 }
990
991 length = xfer->rx_len - xfer->rx_done;
992 xfer->rx_done += length;
993
994 /* Receive payload */
995 while (length >= 4) {
996 reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
997 payload[0] = (reg >> 0) & 0xff;
998 payload[1] = (reg >> 8) & 0xff;
999 payload[2] = (reg >> 16) & 0xff;
1000 payload[3] = (reg >> 24) & 0xff;
1001 payload += 4;
1002 length -= 4;
1003 }
1004
1005 if (length) {
1006 reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
1007 switch (length) {
1008 case 3:
1009 payload[2] = (reg >> 16) & 0xff;
1010 /* Fall through */
1011 case 2:
1012 payload[1] = (reg >> 8) & 0xff;
1013 /* Fall through */
1014 case 1:
1015 payload[0] = reg & 0xff;
1016 }
1017 }
1018
1019 if (xfer->rx_done == xfer->rx_len)
1020 xfer->result = 0;
1021
1022 clear_fifo:
1023 length = DSI_RX_FIFO_SIZE / 4;
1024 do {
1025 reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
1026 if (reg == DSI_RX_FIFO_EMPTY)
1027 break;
1028 } while (--length);
1029 }
1030
1031 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
1032 {
1033 unsigned long flags;
1034 struct exynos_dsi_transfer *xfer;
1035 bool start = false;
1036
1037 again:
1038 spin_lock_irqsave(&dsi->transfer_lock, flags);
1039
1040 if (list_empty(&dsi->transfer_list)) {
1041 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1042 return;
1043 }
1044
1045 xfer = list_first_entry(&dsi->transfer_list,
1046 struct exynos_dsi_transfer, list);
1047
1048 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1049
1050 if (xfer->tx_len && xfer->tx_done == xfer->tx_len)
1051 /* waiting for RX */
1052 return;
1053
1054 exynos_dsi_send_to_fifo(dsi, xfer);
1055
1056 if (xfer->tx_len || xfer->rx_len)
1057 return;
1058
1059 xfer->result = 0;
1060 complete(&xfer->completed);
1061
1062 spin_lock_irqsave(&dsi->transfer_lock, flags);
1063
1064 list_del_init(&xfer->list);
1065 start = !list_empty(&dsi->transfer_list);
1066
1067 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1068
1069 if (start)
1070 goto again;
1071 }
1072
1073 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
1074 {
1075 struct exynos_dsi_transfer *xfer;
1076 unsigned long flags;
1077 bool start = true;
1078
1079 spin_lock_irqsave(&dsi->transfer_lock, flags);
1080
1081 if (list_empty(&dsi->transfer_list)) {
1082 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1083 return false;
1084 }
1085
1086 xfer = list_first_entry(&dsi->transfer_list,
1087 struct exynos_dsi_transfer, list);
1088
1089 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1090
1091 dev_dbg(dsi->dev,
1092 "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n",
1093 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
1094
1095 if (xfer->tx_done != xfer->tx_len)
1096 return true;
1097
1098 if (xfer->rx_done != xfer->rx_len)
1099 exynos_dsi_read_from_fifo(dsi, xfer);
1100
1101 if (xfer->rx_done != xfer->rx_len)
1102 return true;
1103
1104 spin_lock_irqsave(&dsi->transfer_lock, flags);
1105
1106 list_del_init(&xfer->list);
1107 start = !list_empty(&dsi->transfer_list);
1108
1109 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1110
1111 if (!xfer->rx_len)
1112 xfer->result = 0;
1113 complete(&xfer->completed);
1114
1115 return start;
1116 }
1117
1118 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1119 struct exynos_dsi_transfer *xfer)
1120 {
1121 unsigned long flags;
1122 bool start;
1123
1124 spin_lock_irqsave(&dsi->transfer_lock, flags);
1125
1126 if (!list_empty(&dsi->transfer_list) &&
1127 xfer == list_first_entry(&dsi->transfer_list,
1128 struct exynos_dsi_transfer, list)) {
1129 list_del_init(&xfer->list);
1130 start = !list_empty(&dsi->transfer_list);
1131 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1132 if (start)
1133 exynos_dsi_transfer_start(dsi);
1134 return;
1135 }
1136
1137 list_del_init(&xfer->list);
1138
1139 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1140 }
1141
1142 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1143 struct exynos_dsi_transfer *xfer)
1144 {
1145 unsigned long flags;
1146 bool stopped;
1147
1148 xfer->tx_done = 0;
1149 xfer->rx_done = 0;
1150 xfer->result = -ETIMEDOUT;
1151 init_completion(&xfer->completed);
1152
1153 spin_lock_irqsave(&dsi->transfer_lock, flags);
1154
1155 stopped = list_empty(&dsi->transfer_list);
1156 list_add_tail(&xfer->list, &dsi->transfer_list);
1157
1158 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1159
1160 if (stopped)
1161 exynos_dsi_transfer_start(dsi);
1162
1163 wait_for_completion_timeout(&xfer->completed,
1164 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1165 if (xfer->result == -ETIMEDOUT) {
1166 exynos_dsi_remove_transfer(dsi, xfer);
1167 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data,
1168 xfer->tx_len, xfer->tx_payload);
1169 return -ETIMEDOUT;
1170 }
1171
1172 /* Also covers hardware timeout condition */
1173 return xfer->result;
1174 }
1175
1176 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1177 {
1178 struct exynos_dsi *dsi = dev_id;
1179 u32 status;
1180
1181 status = DSI_READ(dsi, DSIM_INTSRC_REG);
1182 if (!status) {
1183 static unsigned long int j;
1184 if (printk_timed_ratelimit(&j, 500))
1185 dev_warn(dsi->dev, "spurious interrupt\n");
1186 return IRQ_HANDLED;
1187 }
1188 DSI_WRITE(dsi, DSIM_INTSRC_REG, status);
1189
1190 if (status & DSIM_INT_SW_RST_RELEASE) {
1191 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY);
1192 DSI_WRITE(dsi, DSIM_INTMSK_REG, mask);
1193 complete(&dsi->completed);
1194 return IRQ_HANDLED;
1195 }
1196
1197 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY)))
1198 return IRQ_HANDLED;
1199
1200 if (exynos_dsi_transfer_finish(dsi))
1201 exynos_dsi_transfer_start(dsi);
1202
1203 return IRQ_HANDLED;
1204 }
1205
1206 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1207 {
1208 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1209 struct drm_encoder *encoder = dsi->display.encoder;
1210
1211 if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
1212 exynos_drm_crtc_te_handler(encoder->crtc);
1213
1214 return IRQ_HANDLED;
1215 }
1216
1217 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1218 {
1219 enable_irq(dsi->irq);
1220
1221 if (gpio_is_valid(dsi->te_gpio))
1222 enable_irq(gpio_to_irq(dsi->te_gpio));
1223 }
1224
1225 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1226 {
1227 if (gpio_is_valid(dsi->te_gpio))
1228 disable_irq(gpio_to_irq(dsi->te_gpio));
1229
1230 disable_irq(dsi->irq);
1231 }
1232
1233 static int exynos_dsi_init(struct exynos_dsi *dsi)
1234 {
1235 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1236
1237 exynos_dsi_reset(dsi);
1238 exynos_dsi_enable_irq(dsi);
1239 exynos_dsi_enable_clock(dsi);
1240 if (driver_data->wait_for_reset)
1241 exynos_dsi_wait_for_reset(dsi);
1242 exynos_dsi_set_phy_ctrl(dsi);
1243 exynos_dsi_init_link(dsi);
1244
1245 return 0;
1246 }
1247
1248 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
1249 {
1250 int ret;
1251 int te_gpio_irq;
1252
1253 dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
1254 if (!gpio_is_valid(dsi->te_gpio)) {
1255 dev_err(dsi->dev, "no te-gpios specified\n");
1256 ret = dsi->te_gpio;
1257 goto out;
1258 }
1259
1260 ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio");
1261 if (ret) {
1262 dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1263 goto out;
1264 }
1265
1266 te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1267
1268 irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
1269 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1270 IRQF_TRIGGER_RISING, "TE", dsi);
1271 if (ret) {
1272 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1273 gpio_free(dsi->te_gpio);
1274 goto out;
1275 }
1276
1277 out:
1278 return ret;
1279 }
1280
1281 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1282 {
1283 if (gpio_is_valid(dsi->te_gpio)) {
1284 free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1285 gpio_free(dsi->te_gpio);
1286 dsi->te_gpio = -ENOENT;
1287 }
1288 }
1289
1290 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1291 struct mipi_dsi_device *device)
1292 {
1293 struct exynos_dsi *dsi = host_to_dsi(host);
1294
1295 dsi->lanes = device->lanes;
1296 dsi->format = device->format;
1297 dsi->mode_flags = device->mode_flags;
1298 dsi->panel_node = device->dev.of_node;
1299
1300 /*
1301 * This is a temporary solution and should be made by more generic way.
1302 *
1303 * If attached panel device is for command mode one, dsi should register
1304 * TE interrupt handler.
1305 */
1306 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1307 int ret = exynos_dsi_register_te_irq(dsi);
1308
1309 if (ret)
1310 return ret;
1311 }
1312
1313 if (dsi->connector.dev)
1314 drm_helper_hpd_irq_event(dsi->connector.dev);
1315
1316 return 0;
1317 }
1318
1319 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1320 struct mipi_dsi_device *device)
1321 {
1322 struct exynos_dsi *dsi = host_to_dsi(host);
1323
1324 exynos_dsi_unregister_te_irq(dsi);
1325
1326 dsi->panel_node = NULL;
1327
1328 if (dsi->connector.dev)
1329 drm_helper_hpd_irq_event(dsi->connector.dev);
1330
1331 return 0;
1332 }
1333
1334 /* distinguish between short and long DSI packet types */
1335 static bool exynos_dsi_is_short_dsi_type(u8 type)
1336 {
1337 return (type & 0x0f) <= 8;
1338 }
1339
1340 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1341 const struct mipi_dsi_msg *msg)
1342 {
1343 struct exynos_dsi *dsi = host_to_dsi(host);
1344 struct exynos_dsi_transfer xfer;
1345 int ret;
1346
1347 if (!(dsi->state & DSIM_STATE_ENABLED))
1348 return -EINVAL;
1349
1350 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1351 ret = exynos_dsi_init(dsi);
1352 if (ret)
1353 return ret;
1354 dsi->state |= DSIM_STATE_INITIALIZED;
1355 }
1356
1357 if (msg->tx_len == 0)
1358 return -EINVAL;
1359
1360 xfer.data_id = msg->type | (msg->channel << 6);
1361
1362 if (exynos_dsi_is_short_dsi_type(msg->type)) {
1363 const char *tx_buf = msg->tx_buf;
1364
1365 if (msg->tx_len > 2)
1366 return -EINVAL;
1367 xfer.tx_len = 0;
1368 xfer.data[0] = tx_buf[0];
1369 xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0;
1370 } else {
1371 xfer.tx_len = msg->tx_len;
1372 xfer.data[0] = msg->tx_len & 0xff;
1373 xfer.data[1] = msg->tx_len >> 8;
1374 xfer.tx_payload = msg->tx_buf;
1375 }
1376
1377 xfer.rx_len = msg->rx_len;
1378 xfer.rx_payload = msg->rx_buf;
1379 xfer.flags = msg->flags;
1380
1381 ret = exynos_dsi_transfer(dsi, &xfer);
1382 return (ret < 0) ? ret : xfer.rx_done;
1383 }
1384
1385 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1386 .attach = exynos_dsi_host_attach,
1387 .detach = exynos_dsi_host_detach,
1388 .transfer = exynos_dsi_host_transfer,
1389 };
1390
1391 static int exynos_dsi_poweron(struct exynos_dsi *dsi)
1392 {
1393 int ret;
1394
1395 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1396 if (ret < 0) {
1397 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1398 return ret;
1399 }
1400
1401 ret = clk_prepare_enable(dsi->bus_clk);
1402 if (ret < 0) {
1403 dev_err(dsi->dev, "cannot enable bus clock %d\n", ret);
1404 goto err_bus_clk;
1405 }
1406
1407 ret = clk_prepare_enable(dsi->sclk_clk);
1408 if (ret < 0) {
1409 dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
1410 goto err_sclk_clk;
1411 }
1412
1413 ret = phy_power_on(dsi->phy);
1414 if (ret < 0) {
1415 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1416 goto err_phy;
1417 }
1418
1419 return 0;
1420
1421 err_phy:
1422 clk_disable_unprepare(dsi->sclk_clk);
1423 err_sclk_clk:
1424 clk_disable_unprepare(dsi->bus_clk);
1425 err_bus_clk:
1426 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1427
1428 return ret;
1429 }
1430
1431 static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
1432 {
1433 int ret;
1434
1435 usleep_range(10000, 20000);
1436
1437 if (dsi->state & DSIM_STATE_INITIALIZED) {
1438 dsi->state &= ~DSIM_STATE_INITIALIZED;
1439
1440 exynos_dsi_disable_clock(dsi);
1441
1442 exynos_dsi_disable_irq(dsi);
1443 }
1444
1445 dsi->state &= ~DSIM_STATE_CMD_LPM;
1446
1447 phy_power_off(dsi->phy);
1448
1449 clk_disable_unprepare(dsi->sclk_clk);
1450 clk_disable_unprepare(dsi->bus_clk);
1451
1452 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1453 if (ret < 0)
1454 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1455 }
1456
1457 static int exynos_dsi_enable(struct exynos_dsi *dsi)
1458 {
1459 int ret;
1460
1461 if (dsi->state & DSIM_STATE_ENABLED)
1462 return 0;
1463
1464 ret = exynos_dsi_poweron(dsi);
1465 if (ret < 0)
1466 return ret;
1467
1468 dsi->state |= DSIM_STATE_ENABLED;
1469
1470 ret = drm_panel_prepare(dsi->panel);
1471 if (ret < 0) {
1472 dsi->state &= ~DSIM_STATE_ENABLED;
1473 exynos_dsi_poweroff(dsi);
1474 return ret;
1475 }
1476
1477 exynos_dsi_set_display_mode(dsi);
1478 exynos_dsi_set_display_enable(dsi, true);
1479
1480 ret = drm_panel_enable(dsi->panel);
1481 if (ret < 0) {
1482 dsi->state &= ~DSIM_STATE_ENABLED;
1483 exynos_dsi_set_display_enable(dsi, false);
1484 drm_panel_unprepare(dsi->panel);
1485 exynos_dsi_poweroff(dsi);
1486 return ret;
1487 }
1488
1489 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1490
1491 return 0;
1492 }
1493
1494 static void exynos_dsi_disable(struct exynos_dsi *dsi)
1495 {
1496 if (!(dsi->state & DSIM_STATE_ENABLED))
1497 return;
1498
1499 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1500
1501 drm_panel_disable(dsi->panel);
1502 exynos_dsi_set_display_enable(dsi, false);
1503 drm_panel_unprepare(dsi->panel);
1504
1505 dsi->state &= ~DSIM_STATE_ENABLED;
1506
1507 exynos_dsi_poweroff(dsi);
1508 }
1509
1510 static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode)
1511 {
1512 struct exynos_dsi *dsi = display_to_dsi(display);
1513
1514 if (dsi->panel) {
1515 switch (mode) {
1516 case DRM_MODE_DPMS_ON:
1517 exynos_dsi_enable(dsi);
1518 break;
1519 case DRM_MODE_DPMS_STANDBY:
1520 case DRM_MODE_DPMS_SUSPEND:
1521 case DRM_MODE_DPMS_OFF:
1522 exynos_dsi_disable(dsi);
1523 break;
1524 default:
1525 break;
1526 }
1527 }
1528 }
1529
1530 static enum drm_connector_status
1531 exynos_dsi_detect(struct drm_connector *connector, bool force)
1532 {
1533 struct exynos_dsi *dsi = connector_to_dsi(connector);
1534
1535 if (!dsi->panel) {
1536 dsi->panel = of_drm_find_panel(dsi->panel_node);
1537 if (dsi->panel)
1538 drm_panel_attach(dsi->panel, &dsi->connector);
1539 } else if (!dsi->panel_node) {
1540 struct exynos_drm_display *display;
1541
1542 display = platform_get_drvdata(to_platform_device(dsi->dev));
1543 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1544 drm_panel_detach(dsi->panel);
1545 dsi->panel = NULL;
1546 }
1547
1548 if (dsi->panel)
1549 return connector_status_connected;
1550
1551 return connector_status_disconnected;
1552 }
1553
1554 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1555 {
1556 drm_connector_unregister(connector);
1557 drm_connector_cleanup(connector);
1558 connector->dev = NULL;
1559 }
1560
1561 static struct drm_connector_funcs exynos_dsi_connector_funcs = {
1562 .dpms = drm_atomic_helper_connector_dpms,
1563 .detect = exynos_dsi_detect,
1564 .fill_modes = drm_helper_probe_single_connector_modes,
1565 .destroy = exynos_dsi_connector_destroy,
1566 .reset = drm_atomic_helper_connector_reset,
1567 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1568 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1569 };
1570
1571 static int exynos_dsi_get_modes(struct drm_connector *connector)
1572 {
1573 struct exynos_dsi *dsi = connector_to_dsi(connector);
1574
1575 if (dsi->panel)
1576 return dsi->panel->funcs->get_modes(dsi->panel);
1577
1578 return 0;
1579 }
1580
1581 static struct drm_encoder *
1582 exynos_dsi_best_encoder(struct drm_connector *connector)
1583 {
1584 struct exynos_dsi *dsi = connector_to_dsi(connector);
1585
1586 return dsi->display.encoder;
1587 }
1588
1589 static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1590 .get_modes = exynos_dsi_get_modes,
1591 .best_encoder = exynos_dsi_best_encoder,
1592 };
1593
1594 static int exynos_dsi_create_connector(struct exynos_drm_display *display,
1595 struct drm_encoder *encoder)
1596 {
1597 struct exynos_dsi *dsi = display_to_dsi(display);
1598 struct drm_connector *connector = &dsi->connector;
1599 int ret;
1600
1601 connector->polled = DRM_CONNECTOR_POLL_HPD;
1602
1603 ret = drm_connector_init(encoder->dev, connector,
1604 &exynos_dsi_connector_funcs,
1605 DRM_MODE_CONNECTOR_DSI);
1606 if (ret) {
1607 DRM_ERROR("Failed to initialize connector with drm\n");
1608 return ret;
1609 }
1610
1611 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1612 drm_connector_register(connector);
1613 drm_mode_connector_attach_encoder(connector, encoder);
1614
1615 return 0;
1616 }
1617
1618 static void exynos_dsi_mode_set(struct exynos_drm_display *display,
1619 struct drm_display_mode *mode)
1620 {
1621 struct exynos_dsi *dsi = display_to_dsi(display);
1622 struct videomode *vm = &dsi->vm;
1623
1624 vm->hactive = mode->hdisplay;
1625 vm->vactive = mode->vdisplay;
1626 vm->vfront_porch = mode->vsync_start - mode->vdisplay;
1627 vm->vback_porch = mode->vtotal - mode->vsync_end;
1628 vm->vsync_len = mode->vsync_end - mode->vsync_start;
1629 vm->hfront_porch = mode->hsync_start - mode->hdisplay;
1630 vm->hback_porch = mode->htotal - mode->hsync_end;
1631 vm->hsync_len = mode->hsync_end - mode->hsync_start;
1632 }
1633
1634 static struct exynos_drm_display_ops exynos_dsi_display_ops = {
1635 .create_connector = exynos_dsi_create_connector,
1636 .mode_set = exynos_dsi_mode_set,
1637 .dpms = exynos_dsi_dpms
1638 };
1639
1640 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1641
1642 /* of_* functions will be removed after merge of of_graph patches */
1643 static struct device_node *
1644 of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg)
1645 {
1646 struct device_node *np;
1647
1648 for_each_child_of_node(parent, np) {
1649 u32 r;
1650
1651 if (!np->name || of_node_cmp(np->name, name))
1652 continue;
1653
1654 if (of_property_read_u32(np, "reg", &r) < 0)
1655 r = 0;
1656
1657 if (reg == r)
1658 break;
1659 }
1660
1661 return np;
1662 }
1663
1664 static struct device_node *of_graph_get_port_by_reg(struct device_node *parent,
1665 u32 reg)
1666 {
1667 struct device_node *ports, *port;
1668
1669 ports = of_get_child_by_name(parent, "ports");
1670 if (ports)
1671 parent = ports;
1672
1673 port = of_get_child_by_name_reg(parent, "port", reg);
1674
1675 of_node_put(ports);
1676
1677 return port;
1678 }
1679
1680 static struct device_node *
1681 of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg)
1682 {
1683 return of_get_child_by_name_reg(port, "endpoint", reg);
1684 }
1685
1686 static int exynos_dsi_of_read_u32(const struct device_node *np,
1687 const char *propname, u32 *out_value)
1688 {
1689 int ret = of_property_read_u32(np, propname, out_value);
1690
1691 if (ret < 0)
1692 pr_err("%s: failed to get '%s' property\n", np->full_name,
1693 propname);
1694
1695 return ret;
1696 }
1697
1698 enum {
1699 DSI_PORT_IN,
1700 DSI_PORT_OUT
1701 };
1702
1703 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1704 {
1705 struct device *dev = dsi->dev;
1706 struct device_node *node = dev->of_node;
1707 struct device_node *port, *ep;
1708 int ret;
1709
1710 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1711 &dsi->pll_clk_rate);
1712 if (ret < 0)
1713 return ret;
1714
1715 port = of_graph_get_port_by_reg(node, DSI_PORT_OUT);
1716 if (!port) {
1717 dev_err(dev, "no output port specified\n");
1718 return -EINVAL;
1719 }
1720
1721 ep = of_graph_get_endpoint_by_reg(port, 0);
1722 of_node_put(port);
1723 if (!ep) {
1724 dev_err(dev, "no endpoint specified in output port\n");
1725 return -EINVAL;
1726 }
1727
1728 ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1729 &dsi->burst_clk_rate);
1730 if (ret < 0)
1731 goto end;
1732
1733 ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1734 &dsi->esc_clk_rate);
1735
1736 end:
1737 of_node_put(ep);
1738
1739 return ret;
1740 }
1741
1742 static int exynos_dsi_bind(struct device *dev, struct device *master,
1743 void *data)
1744 {
1745 struct exynos_drm_display *display = dev_get_drvdata(dev);
1746 struct exynos_dsi *dsi = display_to_dsi(display);
1747 struct drm_device *drm_dev = data;
1748 int ret;
1749
1750 ret = exynos_drm_create_enc_conn(drm_dev, display);
1751 if (ret) {
1752 DRM_ERROR("Encoder create [%d] failed with %d\n",
1753 display->type, ret);
1754 return ret;
1755 }
1756
1757 return mipi_dsi_host_register(&dsi->dsi_host);
1758 }
1759
1760 static void exynos_dsi_unbind(struct device *dev, struct device *master,
1761 void *data)
1762 {
1763 struct exynos_drm_display *display = dev_get_drvdata(dev);
1764 struct exynos_dsi *dsi = display_to_dsi(display);
1765
1766 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1767
1768 mipi_dsi_host_unregister(&dsi->dsi_host);
1769 }
1770
1771 static const struct component_ops exynos_dsi_component_ops = {
1772 .bind = exynos_dsi_bind,
1773 .unbind = exynos_dsi_unbind,
1774 };
1775
1776 static int exynos_dsi_probe(struct platform_device *pdev)
1777 {
1778 struct device *dev = &pdev->dev;
1779 struct resource *res;
1780 struct exynos_dsi *dsi;
1781 int ret;
1782
1783 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1784 if (!dsi)
1785 return -ENOMEM;
1786
1787 dsi->display.type = EXYNOS_DISPLAY_TYPE_LCD;
1788 dsi->display.ops = &exynos_dsi_display_ops;
1789
1790 /* To be checked as invalid one */
1791 dsi->te_gpio = -ENOENT;
1792
1793 init_completion(&dsi->completed);
1794 spin_lock_init(&dsi->transfer_lock);
1795 INIT_LIST_HEAD(&dsi->transfer_list);
1796
1797 dsi->dsi_host.ops = &exynos_dsi_ops;
1798 dsi->dsi_host.dev = dev;
1799
1800 dsi->dev = dev;
1801 dsi->driver_data = exynos_dsi_get_driver_data(pdev);
1802
1803 ret = exynos_dsi_parse_dt(dsi);
1804 if (ret)
1805 return ret;
1806
1807 dsi->supplies[0].supply = "vddcore";
1808 dsi->supplies[1].supply = "vddio";
1809 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1810 dsi->supplies);
1811 if (ret) {
1812 dev_info(dev, "failed to get regulators: %d\n", ret);
1813 return -EPROBE_DEFER;
1814 }
1815
1816 dsi->sclk_clk = devm_clk_get(dev, "sclk_mipi");
1817 if (IS_ERR(dsi->sclk_clk)) {
1818 dsi->sclk_clk = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
1819 if (IS_ERR(dsi->sclk_clk)) {
1820 dev_info(dev, "failed to get dsi sclk clock\n");
1821 eturn PTR_ERR(dsi->sclk_clk);
1822 }
1823 }
1824
1825 dsi->bus_clk = devm_clk_get(dev, "bus_clk");
1826 if (IS_ERR(dsi->bus_clk)) {
1827 dev_info(dev, "failed to get dsi bus clock\n");
1828 return PTR_ERR(dsi->bus_clk);
1829 }
1830
1831 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1832 dsi->reg_base = devm_ioremap_resource(dev, res);
1833 if (IS_ERR(dsi->reg_base)) {
1834 dev_err(dev, "failed to remap io region\n");
1835 return PTR_ERR(dsi->reg_base);
1836 }
1837
1838 dsi->phy = devm_phy_get(dev, "dsim");
1839 if (IS_ERR(dsi->phy)) {
1840 dev_info(dev, "failed to get dsim phy\n");
1841 return PTR_ERR(dsi->phy);
1842 }
1843
1844 dsi->irq = platform_get_irq(pdev, 0);
1845 if (dsi->irq < 0) {
1846 dev_err(dev, "failed to request dsi irq resource\n");
1847 return dsi->irq;
1848 }
1849
1850 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1851 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1852 exynos_dsi_irq, IRQF_ONESHOT,
1853 dev_name(dev), dsi);
1854 if (ret) {
1855 dev_err(dev, "failed to request dsi irq\n");
1856 return ret;
1857 }
1858
1859 platform_set_drvdata(pdev, &dsi->display);
1860
1861 return component_add(dev, &exynos_dsi_component_ops);
1862 }
1863
1864 static int exynos_dsi_remove(struct platform_device *pdev)
1865 {
1866 component_del(&pdev->dev, &exynos_dsi_component_ops);
1867
1868 return 0;
1869 }
1870
1871 struct platform_driver dsi_driver = {
1872 .probe = exynos_dsi_probe,
1873 .remove = exynos_dsi_remove,
1874 .driver = {
1875 .name = "exynos-dsi",
1876 .owner = THIS_MODULE,
1877 .of_match_table = exynos_dsi_of_match,
1878 },
1879 };
1880
1881 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1882 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1883 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1884 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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