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[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_dsi.c
1 /*
2 * Samsung SoC MIPI DSI Master driver.
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
5 *
6 * Contacts: Tomasz Figa <t.figa@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <drm/drmP.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_mipi_dsi.h>
16 #include <drm/drm_panel.h>
17 #include <drm/drm_atomic_helper.h>
18
19 #include <linux/clk.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/irq.h>
22 #include <linux/of_device.h>
23 #include <linux/of_gpio.h>
24 #include <linux/phy/phy.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/component.h>
27
28 #include <video/mipi_display.h>
29 #include <video/videomode.h>
30
31 #include "exynos_drm_crtc.h"
32 #include "exynos_drm_drv.h"
33
34 /* returns true iff both arguments logically differs */
35 #define NEQV(a, b) (!(a) ^ !(b))
36
37 #define DSIM_STATUS_REG 0x0 /* Status register */
38 #define DSIM_SWRST_REG 0x4 /* Software reset register */
39 #define DSIM_CLKCTRL_REG 0x8 /* Clock control register */
40 #define DSIM_TIMEOUT_REG 0xc /* Time out register */
41 #define DSIM_CONFIG_REG 0x10 /* Configuration register */
42 #define DSIM_ESCMODE_REG 0x14 /* Escape mode register */
43
44 /* Main display image resolution register */
45 #define DSIM_MDRESOL_REG 0x18
46 #define DSIM_MVPORCH_REG 0x1c /* Main display Vporch register */
47 #define DSIM_MHPORCH_REG 0x20 /* Main display Hporch register */
48 #define DSIM_MSYNC_REG 0x24 /* Main display sync area register */
49
50 /* Sub display image resolution register */
51 #define DSIM_SDRESOL_REG 0x28
52 #define DSIM_INTSRC_REG 0x2c /* Interrupt source register */
53 #define DSIM_INTMSK_REG 0x30 /* Interrupt mask register */
54 #define DSIM_PKTHDR_REG 0x34 /* Packet Header FIFO register */
55 #define DSIM_PAYLOAD_REG 0x38 /* Payload FIFO register */
56 #define DSIM_RXFIFO_REG 0x3c /* Read FIFO register */
57 #define DSIM_FIFOTHLD_REG 0x40 /* FIFO threshold level register */
58 #define DSIM_FIFOCTRL_REG 0x44 /* FIFO status and control register */
59
60 /* FIFO memory AC characteristic register */
61 #define DSIM_PLLCTRL_REG 0x4c /* PLL control register */
62 #define DSIM_PHYACCHR_REG 0x54 /* D-PHY AC characteristic register */
63 #define DSIM_PHYACCHR1_REG 0x58 /* D-PHY AC characteristic register1 */
64 #define DSIM_PHYCTRL_REG 0x5c
65 #define DSIM_PHYTIMING_REG 0x64
66 #define DSIM_PHYTIMING1_REG 0x68
67 #define DSIM_PHYTIMING2_REG 0x6c
68
69 /* DSIM_STATUS */
70 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
71 #define DSIM_STOP_STATE_CLK (1 << 8)
72 #define DSIM_TX_READY_HS_CLK (1 << 10)
73 #define DSIM_PLL_STABLE (1 << 31)
74
75 /* DSIM_SWRST */
76 #define DSIM_FUNCRST (1 << 16)
77 #define DSIM_SWRST (1 << 0)
78
79 /* DSIM_TIMEOUT */
80 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
81 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
82
83 /* DSIM_CLKCTRL */
84 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
85 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
86 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
87 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
88 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
89 #define DSIM_BYTE_CLKEN (1 << 24)
90 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
91 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
92 #define DSIM_PLL_BYPASS (1 << 27)
93 #define DSIM_ESC_CLKEN (1 << 28)
94 #define DSIM_TX_REQUEST_HSCLK (1 << 31)
95
96 /* DSIM_CONFIG */
97 #define DSIM_LANE_EN_CLK (1 << 0)
98 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
99 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
100 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
101 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
102 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
103 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
104 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
105 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
106 #define DSIM_SUB_VC (((x) & 0x3) << 16)
107 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
108 #define DSIM_HSA_MODE (1 << 20)
109 #define DSIM_HBP_MODE (1 << 21)
110 #define DSIM_HFP_MODE (1 << 22)
111 #define DSIM_HSE_MODE (1 << 23)
112 #define DSIM_AUTO_MODE (1 << 24)
113 #define DSIM_VIDEO_MODE (1 << 25)
114 #define DSIM_BURST_MODE (1 << 26)
115 #define DSIM_SYNC_INFORM (1 << 27)
116 #define DSIM_EOT_DISABLE (1 << 28)
117 #define DSIM_MFLUSH_VS (1 << 29)
118 /* This flag is valid only for exynos3250/3472/4415/5260/5430 */
119 #define DSIM_CLKLANE_STOP (1 << 30)
120
121 /* DSIM_ESCMODE */
122 #define DSIM_TX_TRIGGER_RST (1 << 4)
123 #define DSIM_TX_LPDT_LP (1 << 6)
124 #define DSIM_CMD_LPDT_LP (1 << 7)
125 #define DSIM_FORCE_BTA (1 << 16)
126 #define DSIM_FORCE_STOP_STATE (1 << 20)
127 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
128 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
129
130 /* DSIM_MDRESOL */
131 #define DSIM_MAIN_STAND_BY (1 << 31)
132 #define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
133 #define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
134
135 /* DSIM_MVPORCH */
136 #define DSIM_CMD_ALLOW(x) ((x) << 28)
137 #define DSIM_STABLE_VFP(x) ((x) << 16)
138 #define DSIM_MAIN_VBP(x) ((x) << 0)
139 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
140 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
141 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
142
143 /* DSIM_MHPORCH */
144 #define DSIM_MAIN_HFP(x) ((x) << 16)
145 #define DSIM_MAIN_HBP(x) ((x) << 0)
146 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
147 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
148
149 /* DSIM_MSYNC */
150 #define DSIM_MAIN_VSA(x) ((x) << 22)
151 #define DSIM_MAIN_HSA(x) ((x) << 0)
152 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
153 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
154
155 /* DSIM_SDRESOL */
156 #define DSIM_SUB_STANDY(x) ((x) << 31)
157 #define DSIM_SUB_VRESOL(x) ((x) << 16)
158 #define DSIM_SUB_HRESOL(x) ((x) << 0)
159 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
160 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
161 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
162
163 /* DSIM_INTSRC */
164 #define DSIM_INT_PLL_STABLE (1 << 31)
165 #define DSIM_INT_SW_RST_RELEASE (1 << 30)
166 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
167 #define DSIM_INT_BTA (1 << 25)
168 #define DSIM_INT_FRAME_DONE (1 << 24)
169 #define DSIM_INT_RX_TIMEOUT (1 << 21)
170 #define DSIM_INT_BTA_TIMEOUT (1 << 20)
171 #define DSIM_INT_RX_DONE (1 << 18)
172 #define DSIM_INT_RX_TE (1 << 17)
173 #define DSIM_INT_RX_ACK (1 << 16)
174 #define DSIM_INT_RX_ECC_ERR (1 << 15)
175 #define DSIM_INT_RX_CRC_ERR (1 << 14)
176
177 /* DSIM_FIFOCTRL */
178 #define DSIM_RX_DATA_FULL (1 << 25)
179 #define DSIM_RX_DATA_EMPTY (1 << 24)
180 #define DSIM_SFR_HEADER_FULL (1 << 23)
181 #define DSIM_SFR_HEADER_EMPTY (1 << 22)
182 #define DSIM_SFR_PAYLOAD_FULL (1 << 21)
183 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
184 #define DSIM_I80_HEADER_FULL (1 << 19)
185 #define DSIM_I80_HEADER_EMPTY (1 << 18)
186 #define DSIM_I80_PAYLOAD_FULL (1 << 17)
187 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
188 #define DSIM_SD_HEADER_FULL (1 << 15)
189 #define DSIM_SD_HEADER_EMPTY (1 << 14)
190 #define DSIM_SD_PAYLOAD_FULL (1 << 13)
191 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
192 #define DSIM_MD_HEADER_FULL (1 << 11)
193 #define DSIM_MD_HEADER_EMPTY (1 << 10)
194 #define DSIM_MD_PAYLOAD_FULL (1 << 9)
195 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
196 #define DSIM_RX_FIFO (1 << 4)
197 #define DSIM_SFR_FIFO (1 << 3)
198 #define DSIM_I80_FIFO (1 << 2)
199 #define DSIM_SD_FIFO (1 << 1)
200 #define DSIM_MD_FIFO (1 << 0)
201
202 /* DSIM_PHYACCHR */
203 #define DSIM_AFC_EN (1 << 14)
204 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
205
206 /* DSIM_PLLCTRL */
207 #define DSIM_FREQ_BAND(x) ((x) << 24)
208 #define DSIM_PLL_EN (1 << 23)
209 #define DSIM_PLL_P(x) ((x) << 13)
210 #define DSIM_PLL_M(x) ((x) << 4)
211 #define DSIM_PLL_S(x) ((x) << 1)
212
213 /* DSIM_PHYCTRL */
214 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
215
216 /* DSIM_PHYTIMING */
217 #define DSIM_PHYTIMING_LPX(x) ((x) << 8)
218 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
219
220 /* DSIM_PHYTIMING1 */
221 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
222 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
223 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
224 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
225
226 /* DSIM_PHYTIMING2 */
227 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
228 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
229 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
230
231 #define DSI_MAX_BUS_WIDTH 4
232 #define DSI_NUM_VIRTUAL_CHANNELS 4
233 #define DSI_TX_FIFO_SIZE 2048
234 #define DSI_RX_FIFO_SIZE 256
235 #define DSI_XFER_TIMEOUT_MS 100
236 #define DSI_RX_FIFO_EMPTY 0x30800002
237
238 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
239
240 enum exynos_dsi_transfer_type {
241 EXYNOS_DSI_TX,
242 EXYNOS_DSI_RX,
243 };
244
245 struct exynos_dsi_transfer {
246 struct list_head list;
247 struct completion completed;
248 int result;
249 u8 data_id;
250 u8 data[2];
251 u16 flags;
252
253 const u8 *tx_payload;
254 u16 tx_len;
255 u16 tx_done;
256
257 u8 *rx_payload;
258 u16 rx_len;
259 u16 rx_done;
260 };
261
262 #define DSIM_STATE_ENABLED BIT(0)
263 #define DSIM_STATE_INITIALIZED BIT(1)
264 #define DSIM_STATE_CMD_LPM BIT(2)
265 #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
266
267 struct exynos_dsi_driver_data {
268 unsigned int plltmr_reg;
269
270 unsigned int has_freqband:1;
271 unsigned int has_clklane_stop:1;
272 };
273
274 struct exynos_dsi {
275 struct exynos_drm_display display;
276 struct mipi_dsi_host dsi_host;
277 struct drm_connector connector;
278 struct device_node *panel_node;
279 struct drm_panel *panel;
280 struct device *dev;
281
282 void __iomem *reg_base;
283 struct phy *phy;
284 struct clk *sclk_clk;
285 struct clk *bus_clk;
286 struct regulator_bulk_data supplies[2];
287 int irq;
288 int te_gpio;
289
290 u32 pll_clk_rate;
291 u32 burst_clk_rate;
292 u32 esc_clk_rate;
293 u32 lanes;
294 u32 mode_flags;
295 u32 format;
296 struct videomode vm;
297
298 int state;
299 struct drm_property *brightness;
300 struct completion completed;
301
302 spinlock_t transfer_lock; /* protects transfer_list */
303 struct list_head transfer_list;
304
305 struct exynos_dsi_driver_data *driver_data;
306 };
307
308 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
309 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
310
311 static inline struct exynos_dsi *display_to_dsi(struct exynos_drm_display *d)
312 {
313 return container_of(d, struct exynos_dsi, display);
314 }
315
316 static struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
317 .plltmr_reg = 0x50,
318 .has_freqband = 1,
319 .has_clklane_stop = 1,
320 };
321
322 static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
323 .plltmr_reg = 0x50,
324 .has_freqband = 1,
325 .has_clklane_stop = 1,
326 };
327
328 static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
329 .plltmr_reg = 0x58,
330 .has_clklane_stop = 1,
331 };
332
333 static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
334 .plltmr_reg = 0x58,
335 };
336
337 static struct of_device_id exynos_dsi_of_match[] = {
338 { .compatible = "samsung,exynos3250-mipi-dsi",
339 .data = &exynos3_dsi_driver_data },
340 { .compatible = "samsung,exynos4210-mipi-dsi",
341 .data = &exynos4_dsi_driver_data },
342 { .compatible = "samsung,exynos4415-mipi-dsi",
343 .data = &exynos4415_dsi_driver_data },
344 { .compatible = "samsung,exynos5410-mipi-dsi",
345 .data = &exynos5_dsi_driver_data },
346 { }
347 };
348
349 static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
350 struct platform_device *pdev)
351 {
352 const struct of_device_id *of_id =
353 of_match_device(exynos_dsi_of_match, &pdev->dev);
354
355 return (struct exynos_dsi_driver_data *)of_id->data;
356 }
357
358 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
359 {
360 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
361 return;
362
363 dev_err(dsi->dev, "timeout waiting for reset\n");
364 }
365
366 static void exynos_dsi_reset(struct exynos_dsi *dsi)
367 {
368 reinit_completion(&dsi->completed);
369 writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);
370 }
371
372 #ifndef MHZ
373 #define MHZ (1000*1000)
374 #endif
375
376 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
377 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
378 {
379 unsigned long best_freq = 0;
380 u32 min_delta = 0xffffffff;
381 u8 p_min, p_max;
382 u8 _p, uninitialized_var(best_p);
383 u16 _m, uninitialized_var(best_m);
384 u8 _s, uninitialized_var(best_s);
385
386 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
387 p_max = fin / (6 * MHZ);
388
389 for (_p = p_min; _p <= p_max; ++_p) {
390 for (_s = 0; _s <= 5; ++_s) {
391 u64 tmp;
392 u32 delta;
393
394 tmp = (u64)fout * (_p << _s);
395 do_div(tmp, fin);
396 _m = tmp;
397 if (_m < 41 || _m > 125)
398 continue;
399
400 tmp = (u64)_m * fin;
401 do_div(tmp, _p);
402 if (tmp < 500 * MHZ || tmp > 1000 * MHZ)
403 continue;
404
405 tmp = (u64)_m * fin;
406 do_div(tmp, _p << _s);
407
408 delta = abs(fout - tmp);
409 if (delta < min_delta) {
410 best_p = _p;
411 best_m = _m;
412 best_s = _s;
413 min_delta = delta;
414 best_freq = tmp;
415 }
416 }
417 }
418
419 if (best_freq) {
420 *p = best_p;
421 *m = best_m;
422 *s = best_s;
423 }
424
425 return best_freq;
426 }
427
428 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
429 unsigned long freq)
430 {
431 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
432 unsigned long fin, fout;
433 int timeout;
434 u8 p, s;
435 u16 m;
436 u32 reg;
437
438 fin = dsi->pll_clk_rate;
439 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
440 if (!fout) {
441 dev_err(dsi->dev,
442 "failed to find PLL PMS for requested frequency\n");
443 return 0;
444 }
445 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
446
447 writel(500, dsi->reg_base + driver_data->plltmr_reg);
448
449 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
450
451 if (driver_data->has_freqband) {
452 static const unsigned long freq_bands[] = {
453 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
454 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
455 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
456 770 * MHZ, 870 * MHZ, 950 * MHZ,
457 };
458 int band;
459
460 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
461 if (fout < freq_bands[band])
462 break;
463
464 dev_dbg(dsi->dev, "band %d\n", band);
465
466 reg |= DSIM_FREQ_BAND(band);
467 }
468
469 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
470
471 timeout = 1000;
472 do {
473 if (timeout-- == 0) {
474 dev_err(dsi->dev, "PLL failed to stabilize\n");
475 return 0;
476 }
477 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
478 } while ((reg & DSIM_PLL_STABLE) == 0);
479
480 return fout;
481 }
482
483 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
484 {
485 unsigned long hs_clk, byte_clk, esc_clk;
486 unsigned long esc_div;
487 u32 reg;
488
489 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
490 if (!hs_clk) {
491 dev_err(dsi->dev, "failed to configure DSI PLL\n");
492 return -EFAULT;
493 }
494
495 byte_clk = hs_clk / 8;
496 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
497 esc_clk = byte_clk / esc_div;
498
499 if (esc_clk > 20 * MHZ) {
500 ++esc_div;
501 esc_clk = byte_clk / esc_div;
502 }
503
504 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
505 hs_clk, byte_clk, esc_clk);
506
507 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
508 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
509 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
510 | DSIM_BYTE_CLK_SRC_MASK);
511 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
512 | DSIM_ESC_PRESCALER(esc_div)
513 | DSIM_LANE_ESC_CLK_EN_CLK
514 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
515 | DSIM_BYTE_CLK_SRC(0)
516 | DSIM_TX_REQUEST_HSCLK;
517 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
518
519 return 0;
520 }
521
522 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
523 {
524 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
525 u32 reg;
526
527 if (driver_data->has_freqband)
528 return;
529
530 /* B D-PHY: D-PHY Master & Slave Analog Block control */
531 reg = DSIM_PHYCTRL_ULPS_EXIT(0x0af);
532 writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG);
533
534 /*
535 * T LPX: Transmitted length of any Low-Power state period
536 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
537 * burst
538 */
539 reg = DSIM_PHYTIMING_LPX(0x06) | DSIM_PHYTIMING_HS_EXIT(0x0b);
540 writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG);
541
542 /*
543 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
544 * Line state immediately before the HS-0 Line state starting the
545 * HS transmission
546 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
547 * transmitting the Clock.
548 * T CLK_POST: Time that the transmitter continues to send HS clock
549 * after the last associated Data Lane has transitioned to LP Mode
550 * Interval is defined as the period from the end of T HS-TRAIL to
551 * the beginning of T CLK-TRAIL
552 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
553 * the last payload clock bit of a HS transmission burst
554 */
555 reg = DSIM_PHYTIMING1_CLK_PREPARE(0x07) |
556 DSIM_PHYTIMING1_CLK_ZERO(0x27) |
557 DSIM_PHYTIMING1_CLK_POST(0x0d) |
558 DSIM_PHYTIMING1_CLK_TRAIL(0x08);
559 writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG);
560
561 /*
562 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
563 * Line state immediately before the HS-0 Line state starting the
564 * HS transmission
565 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
566 * transmitting the Sync sequence.
567 * T HS-TRAIL: Time that the transmitter drives the flipped differential
568 * state after last payload data bit of a HS transmission burst
569 */
570 reg = DSIM_PHYTIMING2_HS_PREPARE(0x09) | DSIM_PHYTIMING2_HS_ZERO(0x0d) |
571 DSIM_PHYTIMING2_HS_TRAIL(0x0b);
572 writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG);
573 }
574
575 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
576 {
577 u32 reg;
578
579 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
580 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
581 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
582 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
583
584 reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG);
585 reg &= ~DSIM_PLL_EN;
586 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
587 }
588
589 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
590 {
591 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
592 int timeout;
593 u32 reg;
594 u32 lanes_mask;
595
596 /* Initialize FIFO pointers */
597 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
598 reg &= ~0x1f;
599 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
600
601 usleep_range(9000, 11000);
602
603 reg |= 0x1f;
604 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
605
606 usleep_range(9000, 11000);
607
608 /* DSI configuration */
609 reg = 0;
610
611 /*
612 * The first bit of mode_flags specifies display configuration.
613 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
614 * mode, otherwise it will support command mode.
615 */
616 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
617 reg |= DSIM_VIDEO_MODE;
618
619 /*
620 * The user manual describes that following bits are ignored in
621 * command mode.
622 */
623 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
624 reg |= DSIM_MFLUSH_VS;
625 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
626 reg |= DSIM_SYNC_INFORM;
627 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
628 reg |= DSIM_BURST_MODE;
629 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
630 reg |= DSIM_AUTO_MODE;
631 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
632 reg |= DSIM_HSE_MODE;
633 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
634 reg |= DSIM_HFP_MODE;
635 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
636 reg |= DSIM_HBP_MODE;
637 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
638 reg |= DSIM_HSA_MODE;
639 }
640
641 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
642 reg |= DSIM_EOT_DISABLE;
643
644 switch (dsi->format) {
645 case MIPI_DSI_FMT_RGB888:
646 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
647 break;
648 case MIPI_DSI_FMT_RGB666:
649 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
650 break;
651 case MIPI_DSI_FMT_RGB666_PACKED:
652 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
653 break;
654 case MIPI_DSI_FMT_RGB565:
655 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
656 break;
657 default:
658 dev_err(dsi->dev, "invalid pixel format\n");
659 return -EINVAL;
660 }
661
662 reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1);
663
664 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
665
666 reg |= DSIM_LANE_EN_CLK;
667 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
668
669 lanes_mask = BIT(dsi->lanes) - 1;
670 reg |= DSIM_LANE_EN(lanes_mask);
671 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
672
673 /*
674 * Use non-continuous clock mode if the periparal wants and
675 * host controller supports
676 *
677 * In non-continous clock mode, host controller will turn off
678 * the HS clock between high-speed transmissions to reduce
679 * power consumption.
680 */
681 if (driver_data->has_clklane_stop &&
682 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
683 reg |= DSIM_CLKLANE_STOP;
684 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
685 }
686
687 /* Check clock and data lane state are stop state */
688 timeout = 100;
689 do {
690 if (timeout-- == 0) {
691 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
692 return -EFAULT;
693 }
694
695 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
696 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
697 != DSIM_STOP_STATE_DAT(lanes_mask))
698 continue;
699 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
700
701 reg = readl(dsi->reg_base + DSIM_ESCMODE_REG);
702 reg &= ~DSIM_STOP_STATE_CNT_MASK;
703 reg |= DSIM_STOP_STATE_CNT(0xf);
704 writel(reg, dsi->reg_base + DSIM_ESCMODE_REG);
705
706 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
707 writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG);
708
709 return 0;
710 }
711
712 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
713 {
714 struct videomode *vm = &dsi->vm;
715 u32 reg;
716
717 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
718 reg = DSIM_CMD_ALLOW(0xf)
719 | DSIM_STABLE_VFP(vm->vfront_porch)
720 | DSIM_MAIN_VBP(vm->vback_porch);
721 writel(reg, dsi->reg_base + DSIM_MVPORCH_REG);
722
723 reg = DSIM_MAIN_HFP(vm->hfront_porch)
724 | DSIM_MAIN_HBP(vm->hback_porch);
725 writel(reg, dsi->reg_base + DSIM_MHPORCH_REG);
726
727 reg = DSIM_MAIN_VSA(vm->vsync_len)
728 | DSIM_MAIN_HSA(vm->hsync_len);
729 writel(reg, dsi->reg_base + DSIM_MSYNC_REG);
730 }
731
732 reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive);
733 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
734
735 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
736 }
737
738 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
739 {
740 u32 reg;
741
742 reg = readl(dsi->reg_base + DSIM_MDRESOL_REG);
743 if (enable)
744 reg |= DSIM_MAIN_STAND_BY;
745 else
746 reg &= ~DSIM_MAIN_STAND_BY;
747 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
748 }
749
750 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
751 {
752 int timeout = 2000;
753
754 do {
755 u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
756
757 if (!(reg & DSIM_SFR_HEADER_FULL))
758 return 0;
759
760 if (!cond_resched())
761 usleep_range(950, 1050);
762 } while (--timeout);
763
764 return -ETIMEDOUT;
765 }
766
767 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
768 {
769 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
770
771 if (lpm)
772 v |= DSIM_CMD_LPDT_LP;
773 else
774 v &= ~DSIM_CMD_LPDT_LP;
775
776 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
777 }
778
779 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
780 {
781 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
782
783 v |= DSIM_FORCE_BTA;
784 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
785 }
786
787 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
788 struct exynos_dsi_transfer *xfer)
789 {
790 struct device *dev = dsi->dev;
791 const u8 *payload = xfer->tx_payload + xfer->tx_done;
792 u16 length = xfer->tx_len - xfer->tx_done;
793 bool first = !xfer->tx_done;
794 u32 reg;
795
796 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
797 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
798
799 if (length > DSI_TX_FIFO_SIZE)
800 length = DSI_TX_FIFO_SIZE;
801
802 xfer->tx_done += length;
803
804 /* Send payload */
805 while (length >= 4) {
806 reg = (payload[3] << 24) | (payload[2] << 16)
807 | (payload[1] << 8) | payload[0];
808 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
809 payload += 4;
810 length -= 4;
811 }
812
813 reg = 0;
814 switch (length) {
815 case 3:
816 reg |= payload[2] << 16;
817 /* Fall through */
818 case 2:
819 reg |= payload[1] << 8;
820 /* Fall through */
821 case 1:
822 reg |= payload[0];
823 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
824 break;
825 case 0:
826 /* Do nothing */
827 break;
828 }
829
830 /* Send packet header */
831 if (!first)
832 return;
833
834 reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id;
835 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
836 dev_err(dev, "waiting for header FIFO timed out\n");
837 return;
838 }
839
840 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
841 dsi->state & DSIM_STATE_CMD_LPM)) {
842 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
843 dsi->state ^= DSIM_STATE_CMD_LPM;
844 }
845
846 writel(reg, dsi->reg_base + DSIM_PKTHDR_REG);
847
848 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
849 exynos_dsi_force_bta(dsi);
850 }
851
852 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
853 struct exynos_dsi_transfer *xfer)
854 {
855 u8 *payload = xfer->rx_payload + xfer->rx_done;
856 bool first = !xfer->rx_done;
857 struct device *dev = dsi->dev;
858 u16 length;
859 u32 reg;
860
861 if (first) {
862 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
863
864 switch (reg & 0x3f) {
865 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
866 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
867 if (xfer->rx_len >= 2) {
868 payload[1] = reg >> 16;
869 ++xfer->rx_done;
870 }
871 /* Fall through */
872 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
873 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
874 payload[0] = reg >> 8;
875 ++xfer->rx_done;
876 xfer->rx_len = xfer->rx_done;
877 xfer->result = 0;
878 goto clear_fifo;
879 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
880 dev_err(dev, "DSI Error Report: 0x%04x\n",
881 (reg >> 8) & 0xffff);
882 xfer->result = 0;
883 goto clear_fifo;
884 }
885
886 length = (reg >> 8) & 0xffff;
887 if (length > xfer->rx_len) {
888 dev_err(dev,
889 "response too long (%u > %u bytes), stripping\n",
890 xfer->rx_len, length);
891 length = xfer->rx_len;
892 } else if (length < xfer->rx_len)
893 xfer->rx_len = length;
894 }
895
896 length = xfer->rx_len - xfer->rx_done;
897 xfer->rx_done += length;
898
899 /* Receive payload */
900 while (length >= 4) {
901 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
902 payload[0] = (reg >> 0) & 0xff;
903 payload[1] = (reg >> 8) & 0xff;
904 payload[2] = (reg >> 16) & 0xff;
905 payload[3] = (reg >> 24) & 0xff;
906 payload += 4;
907 length -= 4;
908 }
909
910 if (length) {
911 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
912 switch (length) {
913 case 3:
914 payload[2] = (reg >> 16) & 0xff;
915 /* Fall through */
916 case 2:
917 payload[1] = (reg >> 8) & 0xff;
918 /* Fall through */
919 case 1:
920 payload[0] = reg & 0xff;
921 }
922 }
923
924 if (xfer->rx_done == xfer->rx_len)
925 xfer->result = 0;
926
927 clear_fifo:
928 length = DSI_RX_FIFO_SIZE / 4;
929 do {
930 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
931 if (reg == DSI_RX_FIFO_EMPTY)
932 break;
933 } while (--length);
934 }
935
936 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
937 {
938 unsigned long flags;
939 struct exynos_dsi_transfer *xfer;
940 bool start = false;
941
942 again:
943 spin_lock_irqsave(&dsi->transfer_lock, flags);
944
945 if (list_empty(&dsi->transfer_list)) {
946 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
947 return;
948 }
949
950 xfer = list_first_entry(&dsi->transfer_list,
951 struct exynos_dsi_transfer, list);
952
953 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
954
955 if (xfer->tx_len && xfer->tx_done == xfer->tx_len)
956 /* waiting for RX */
957 return;
958
959 exynos_dsi_send_to_fifo(dsi, xfer);
960
961 if (xfer->tx_len || xfer->rx_len)
962 return;
963
964 xfer->result = 0;
965 complete(&xfer->completed);
966
967 spin_lock_irqsave(&dsi->transfer_lock, flags);
968
969 list_del_init(&xfer->list);
970 start = !list_empty(&dsi->transfer_list);
971
972 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
973
974 if (start)
975 goto again;
976 }
977
978 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
979 {
980 struct exynos_dsi_transfer *xfer;
981 unsigned long flags;
982 bool start = true;
983
984 spin_lock_irqsave(&dsi->transfer_lock, flags);
985
986 if (list_empty(&dsi->transfer_list)) {
987 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
988 return false;
989 }
990
991 xfer = list_first_entry(&dsi->transfer_list,
992 struct exynos_dsi_transfer, list);
993
994 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
995
996 dev_dbg(dsi->dev,
997 "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n",
998 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
999
1000 if (xfer->tx_done != xfer->tx_len)
1001 return true;
1002
1003 if (xfer->rx_done != xfer->rx_len)
1004 exynos_dsi_read_from_fifo(dsi, xfer);
1005
1006 if (xfer->rx_done != xfer->rx_len)
1007 return true;
1008
1009 spin_lock_irqsave(&dsi->transfer_lock, flags);
1010
1011 list_del_init(&xfer->list);
1012 start = !list_empty(&dsi->transfer_list);
1013
1014 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1015
1016 if (!xfer->rx_len)
1017 xfer->result = 0;
1018 complete(&xfer->completed);
1019
1020 return start;
1021 }
1022
1023 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1024 struct exynos_dsi_transfer *xfer)
1025 {
1026 unsigned long flags;
1027 bool start;
1028
1029 spin_lock_irqsave(&dsi->transfer_lock, flags);
1030
1031 if (!list_empty(&dsi->transfer_list) &&
1032 xfer == list_first_entry(&dsi->transfer_list,
1033 struct exynos_dsi_transfer, list)) {
1034 list_del_init(&xfer->list);
1035 start = !list_empty(&dsi->transfer_list);
1036 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1037 if (start)
1038 exynos_dsi_transfer_start(dsi);
1039 return;
1040 }
1041
1042 list_del_init(&xfer->list);
1043
1044 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1045 }
1046
1047 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1048 struct exynos_dsi_transfer *xfer)
1049 {
1050 unsigned long flags;
1051 bool stopped;
1052
1053 xfer->tx_done = 0;
1054 xfer->rx_done = 0;
1055 xfer->result = -ETIMEDOUT;
1056 init_completion(&xfer->completed);
1057
1058 spin_lock_irqsave(&dsi->transfer_lock, flags);
1059
1060 stopped = list_empty(&dsi->transfer_list);
1061 list_add_tail(&xfer->list, &dsi->transfer_list);
1062
1063 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1064
1065 if (stopped)
1066 exynos_dsi_transfer_start(dsi);
1067
1068 wait_for_completion_timeout(&xfer->completed,
1069 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1070 if (xfer->result == -ETIMEDOUT) {
1071 exynos_dsi_remove_transfer(dsi, xfer);
1072 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data,
1073 xfer->tx_len, xfer->tx_payload);
1074 return -ETIMEDOUT;
1075 }
1076
1077 /* Also covers hardware timeout condition */
1078 return xfer->result;
1079 }
1080
1081 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1082 {
1083 struct exynos_dsi *dsi = dev_id;
1084 u32 status;
1085
1086 status = readl(dsi->reg_base + DSIM_INTSRC_REG);
1087 if (!status) {
1088 static unsigned long int j;
1089 if (printk_timed_ratelimit(&j, 500))
1090 dev_warn(dsi->dev, "spurious interrupt\n");
1091 return IRQ_HANDLED;
1092 }
1093 writel(status, dsi->reg_base + DSIM_INTSRC_REG);
1094
1095 if (status & DSIM_INT_SW_RST_RELEASE) {
1096 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY);
1097 writel(mask, dsi->reg_base + DSIM_INTMSK_REG);
1098 complete(&dsi->completed);
1099 return IRQ_HANDLED;
1100 }
1101
1102 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY)))
1103 return IRQ_HANDLED;
1104
1105 if (exynos_dsi_transfer_finish(dsi))
1106 exynos_dsi_transfer_start(dsi);
1107
1108 return IRQ_HANDLED;
1109 }
1110
1111 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1112 {
1113 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1114 struct drm_encoder *encoder = dsi->display.encoder;
1115
1116 if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
1117 exynos_drm_crtc_te_handler(encoder->crtc);
1118
1119 return IRQ_HANDLED;
1120 }
1121
1122 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1123 {
1124 enable_irq(dsi->irq);
1125
1126 if (gpio_is_valid(dsi->te_gpio))
1127 enable_irq(gpio_to_irq(dsi->te_gpio));
1128 }
1129
1130 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1131 {
1132 if (gpio_is_valid(dsi->te_gpio))
1133 disable_irq(gpio_to_irq(dsi->te_gpio));
1134
1135 disable_irq(dsi->irq);
1136 }
1137
1138 static int exynos_dsi_init(struct exynos_dsi *dsi)
1139 {
1140 exynos_dsi_reset(dsi);
1141 exynos_dsi_enable_irq(dsi);
1142 exynos_dsi_enable_clock(dsi);
1143 exynos_dsi_wait_for_reset(dsi);
1144 exynos_dsi_set_phy_ctrl(dsi);
1145 exynos_dsi_init_link(dsi);
1146
1147 return 0;
1148 }
1149
1150 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
1151 {
1152 int ret;
1153 int te_gpio_irq;
1154
1155 dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
1156 if (!gpio_is_valid(dsi->te_gpio)) {
1157 dev_err(dsi->dev, "no te-gpios specified\n");
1158 ret = dsi->te_gpio;
1159 goto out;
1160 }
1161
1162 ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio");
1163 if (ret) {
1164 dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1165 goto out;
1166 }
1167
1168 te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1169
1170 irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
1171 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1172 IRQF_TRIGGER_RISING, "TE", dsi);
1173 if (ret) {
1174 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1175 gpio_free(dsi->te_gpio);
1176 goto out;
1177 }
1178
1179 out:
1180 return ret;
1181 }
1182
1183 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1184 {
1185 if (gpio_is_valid(dsi->te_gpio)) {
1186 free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1187 gpio_free(dsi->te_gpio);
1188 dsi->te_gpio = -ENOENT;
1189 }
1190 }
1191
1192 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1193 struct mipi_dsi_device *device)
1194 {
1195 struct exynos_dsi *dsi = host_to_dsi(host);
1196
1197 dsi->lanes = device->lanes;
1198 dsi->format = device->format;
1199 dsi->mode_flags = device->mode_flags;
1200 dsi->panel_node = device->dev.of_node;
1201
1202 /*
1203 * This is a temporary solution and should be made by more generic way.
1204 *
1205 * If attached panel device is for command mode one, dsi should register
1206 * TE interrupt handler.
1207 */
1208 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1209 int ret = exynos_dsi_register_te_irq(dsi);
1210
1211 if (ret)
1212 return ret;
1213 }
1214
1215 if (dsi->connector.dev)
1216 drm_helper_hpd_irq_event(dsi->connector.dev);
1217
1218 return 0;
1219 }
1220
1221 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1222 struct mipi_dsi_device *device)
1223 {
1224 struct exynos_dsi *dsi = host_to_dsi(host);
1225
1226 exynos_dsi_unregister_te_irq(dsi);
1227
1228 dsi->panel_node = NULL;
1229
1230 if (dsi->connector.dev)
1231 drm_helper_hpd_irq_event(dsi->connector.dev);
1232
1233 return 0;
1234 }
1235
1236 /* distinguish between short and long DSI packet types */
1237 static bool exynos_dsi_is_short_dsi_type(u8 type)
1238 {
1239 return (type & 0x0f) <= 8;
1240 }
1241
1242 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1243 const struct mipi_dsi_msg *msg)
1244 {
1245 struct exynos_dsi *dsi = host_to_dsi(host);
1246 struct exynos_dsi_transfer xfer;
1247 int ret;
1248
1249 if (!(dsi->state & DSIM_STATE_ENABLED))
1250 return -EINVAL;
1251
1252 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1253 ret = exynos_dsi_init(dsi);
1254 if (ret)
1255 return ret;
1256 dsi->state |= DSIM_STATE_INITIALIZED;
1257 }
1258
1259 if (msg->tx_len == 0)
1260 return -EINVAL;
1261
1262 xfer.data_id = msg->type | (msg->channel << 6);
1263
1264 if (exynos_dsi_is_short_dsi_type(msg->type)) {
1265 const char *tx_buf = msg->tx_buf;
1266
1267 if (msg->tx_len > 2)
1268 return -EINVAL;
1269 xfer.tx_len = 0;
1270 xfer.data[0] = tx_buf[0];
1271 xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0;
1272 } else {
1273 xfer.tx_len = msg->tx_len;
1274 xfer.data[0] = msg->tx_len & 0xff;
1275 xfer.data[1] = msg->tx_len >> 8;
1276 xfer.tx_payload = msg->tx_buf;
1277 }
1278
1279 xfer.rx_len = msg->rx_len;
1280 xfer.rx_payload = msg->rx_buf;
1281 xfer.flags = msg->flags;
1282
1283 ret = exynos_dsi_transfer(dsi, &xfer);
1284 return (ret < 0) ? ret : xfer.rx_done;
1285 }
1286
1287 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1288 .attach = exynos_dsi_host_attach,
1289 .detach = exynos_dsi_host_detach,
1290 .transfer = exynos_dsi_host_transfer,
1291 };
1292
1293 static int exynos_dsi_poweron(struct exynos_dsi *dsi)
1294 {
1295 int ret;
1296
1297 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1298 if (ret < 0) {
1299 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1300 return ret;
1301 }
1302
1303 ret = clk_prepare_enable(dsi->bus_clk);
1304 if (ret < 0) {
1305 dev_err(dsi->dev, "cannot enable bus clock %d\n", ret);
1306 goto err_bus_clk;
1307 }
1308
1309 ret = clk_prepare_enable(dsi->sclk_clk);
1310 if (ret < 0) {
1311 dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
1312 goto err_sclk_clk;
1313 }
1314
1315 ret = phy_power_on(dsi->phy);
1316 if (ret < 0) {
1317 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1318 goto err_phy;
1319 }
1320
1321 return 0;
1322
1323 err_phy:
1324 clk_disable_unprepare(dsi->sclk_clk);
1325 err_sclk_clk:
1326 clk_disable_unprepare(dsi->bus_clk);
1327 err_bus_clk:
1328 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1329
1330 return ret;
1331 }
1332
1333 static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
1334 {
1335 int ret;
1336
1337 usleep_range(10000, 20000);
1338
1339 if (dsi->state & DSIM_STATE_INITIALIZED) {
1340 dsi->state &= ~DSIM_STATE_INITIALIZED;
1341
1342 exynos_dsi_disable_clock(dsi);
1343
1344 exynos_dsi_disable_irq(dsi);
1345 }
1346
1347 dsi->state &= ~DSIM_STATE_CMD_LPM;
1348
1349 phy_power_off(dsi->phy);
1350
1351 clk_disable_unprepare(dsi->sclk_clk);
1352 clk_disable_unprepare(dsi->bus_clk);
1353
1354 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1355 if (ret < 0)
1356 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1357 }
1358
1359 static int exynos_dsi_enable(struct exynos_dsi *dsi)
1360 {
1361 int ret;
1362
1363 if (dsi->state & DSIM_STATE_ENABLED)
1364 return 0;
1365
1366 ret = exynos_dsi_poweron(dsi);
1367 if (ret < 0)
1368 return ret;
1369
1370 dsi->state |= DSIM_STATE_ENABLED;
1371
1372 ret = drm_panel_prepare(dsi->panel);
1373 if (ret < 0) {
1374 dsi->state &= ~DSIM_STATE_ENABLED;
1375 exynos_dsi_poweroff(dsi);
1376 return ret;
1377 }
1378
1379 exynos_dsi_set_display_mode(dsi);
1380 exynos_dsi_set_display_enable(dsi, true);
1381
1382 ret = drm_panel_enable(dsi->panel);
1383 if (ret < 0) {
1384 dsi->state &= ~DSIM_STATE_ENABLED;
1385 exynos_dsi_set_display_enable(dsi, false);
1386 drm_panel_unprepare(dsi->panel);
1387 exynos_dsi_poweroff(dsi);
1388 return ret;
1389 }
1390
1391 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1392
1393 return 0;
1394 }
1395
1396 static void exynos_dsi_disable(struct exynos_dsi *dsi)
1397 {
1398 if (!(dsi->state & DSIM_STATE_ENABLED))
1399 return;
1400
1401 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1402
1403 drm_panel_disable(dsi->panel);
1404 exynos_dsi_set_display_enable(dsi, false);
1405 drm_panel_unprepare(dsi->panel);
1406
1407 dsi->state &= ~DSIM_STATE_ENABLED;
1408
1409 exynos_dsi_poweroff(dsi);
1410 }
1411
1412 static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode)
1413 {
1414 struct exynos_dsi *dsi = display_to_dsi(display);
1415
1416 if (dsi->panel) {
1417 switch (mode) {
1418 case DRM_MODE_DPMS_ON:
1419 exynos_dsi_enable(dsi);
1420 break;
1421 case DRM_MODE_DPMS_STANDBY:
1422 case DRM_MODE_DPMS_SUSPEND:
1423 case DRM_MODE_DPMS_OFF:
1424 exynos_dsi_disable(dsi);
1425 break;
1426 default:
1427 break;
1428 }
1429 }
1430 }
1431
1432 static enum drm_connector_status
1433 exynos_dsi_detect(struct drm_connector *connector, bool force)
1434 {
1435 struct exynos_dsi *dsi = connector_to_dsi(connector);
1436
1437 if (!dsi->panel) {
1438 dsi->panel = of_drm_find_panel(dsi->panel_node);
1439 if (dsi->panel)
1440 drm_panel_attach(dsi->panel, &dsi->connector);
1441 } else if (!dsi->panel_node) {
1442 struct exynos_drm_display *display;
1443
1444 display = platform_get_drvdata(to_platform_device(dsi->dev));
1445 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1446 drm_panel_detach(dsi->panel);
1447 dsi->panel = NULL;
1448 }
1449
1450 if (dsi->panel)
1451 return connector_status_connected;
1452
1453 return connector_status_disconnected;
1454 }
1455
1456 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1457 {
1458 drm_connector_unregister(connector);
1459 drm_connector_cleanup(connector);
1460 connector->dev = NULL;
1461 }
1462
1463 static struct drm_connector_funcs exynos_dsi_connector_funcs = {
1464 .dpms = drm_atomic_helper_connector_dpms,
1465 .detect = exynos_dsi_detect,
1466 .fill_modes = drm_helper_probe_single_connector_modes,
1467 .destroy = exynos_dsi_connector_destroy,
1468 .reset = drm_atomic_helper_connector_reset,
1469 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1470 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1471 };
1472
1473 static int exynos_dsi_get_modes(struct drm_connector *connector)
1474 {
1475 struct exynos_dsi *dsi = connector_to_dsi(connector);
1476
1477 if (dsi->panel)
1478 return dsi->panel->funcs->get_modes(dsi->panel);
1479
1480 return 0;
1481 }
1482
1483 static struct drm_encoder *
1484 exynos_dsi_best_encoder(struct drm_connector *connector)
1485 {
1486 struct exynos_dsi *dsi = connector_to_dsi(connector);
1487
1488 return dsi->display.encoder;
1489 }
1490
1491 static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1492 .get_modes = exynos_dsi_get_modes,
1493 .best_encoder = exynos_dsi_best_encoder,
1494 };
1495
1496 static int exynos_dsi_create_connector(struct exynos_drm_display *display,
1497 struct drm_encoder *encoder)
1498 {
1499 struct exynos_dsi *dsi = display_to_dsi(display);
1500 struct drm_connector *connector = &dsi->connector;
1501 int ret;
1502
1503 connector->polled = DRM_CONNECTOR_POLL_HPD;
1504
1505 ret = drm_connector_init(encoder->dev, connector,
1506 &exynos_dsi_connector_funcs,
1507 DRM_MODE_CONNECTOR_DSI);
1508 if (ret) {
1509 DRM_ERROR("Failed to initialize connector with drm\n");
1510 return ret;
1511 }
1512
1513 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1514 drm_connector_register(connector);
1515 drm_mode_connector_attach_encoder(connector, encoder);
1516
1517 return 0;
1518 }
1519
1520 static void exynos_dsi_mode_set(struct exynos_drm_display *display,
1521 struct drm_display_mode *mode)
1522 {
1523 struct exynos_dsi *dsi = display_to_dsi(display);
1524 struct videomode *vm = &dsi->vm;
1525
1526 vm->hactive = mode->hdisplay;
1527 vm->vactive = mode->vdisplay;
1528 vm->vfront_porch = mode->vsync_start - mode->vdisplay;
1529 vm->vback_porch = mode->vtotal - mode->vsync_end;
1530 vm->vsync_len = mode->vsync_end - mode->vsync_start;
1531 vm->hfront_porch = mode->hsync_start - mode->hdisplay;
1532 vm->hback_porch = mode->htotal - mode->hsync_end;
1533 vm->hsync_len = mode->hsync_end - mode->hsync_start;
1534 }
1535
1536 static struct exynos_drm_display_ops exynos_dsi_display_ops = {
1537 .create_connector = exynos_dsi_create_connector,
1538 .mode_set = exynos_dsi_mode_set,
1539 .dpms = exynos_dsi_dpms
1540 };
1541
1542 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1543
1544 /* of_* functions will be removed after merge of of_graph patches */
1545 static struct device_node *
1546 of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg)
1547 {
1548 struct device_node *np;
1549
1550 for_each_child_of_node(parent, np) {
1551 u32 r;
1552
1553 if (!np->name || of_node_cmp(np->name, name))
1554 continue;
1555
1556 if (of_property_read_u32(np, "reg", &r) < 0)
1557 r = 0;
1558
1559 if (reg == r)
1560 break;
1561 }
1562
1563 return np;
1564 }
1565
1566 static struct device_node *of_graph_get_port_by_reg(struct device_node *parent,
1567 u32 reg)
1568 {
1569 struct device_node *ports, *port;
1570
1571 ports = of_get_child_by_name(parent, "ports");
1572 if (ports)
1573 parent = ports;
1574
1575 port = of_get_child_by_name_reg(parent, "port", reg);
1576
1577 of_node_put(ports);
1578
1579 return port;
1580 }
1581
1582 static struct device_node *
1583 of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg)
1584 {
1585 return of_get_child_by_name_reg(port, "endpoint", reg);
1586 }
1587
1588 static int exynos_dsi_of_read_u32(const struct device_node *np,
1589 const char *propname, u32 *out_value)
1590 {
1591 int ret = of_property_read_u32(np, propname, out_value);
1592
1593 if (ret < 0)
1594 pr_err("%s: failed to get '%s' property\n", np->full_name,
1595 propname);
1596
1597 return ret;
1598 }
1599
1600 enum {
1601 DSI_PORT_IN,
1602 DSI_PORT_OUT
1603 };
1604
1605 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1606 {
1607 struct device *dev = dsi->dev;
1608 struct device_node *node = dev->of_node;
1609 struct device_node *port, *ep;
1610 int ret;
1611
1612 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1613 &dsi->pll_clk_rate);
1614 if (ret < 0)
1615 return ret;
1616
1617 port = of_graph_get_port_by_reg(node, DSI_PORT_OUT);
1618 if (!port) {
1619 dev_err(dev, "no output port specified\n");
1620 return -EINVAL;
1621 }
1622
1623 ep = of_graph_get_endpoint_by_reg(port, 0);
1624 of_node_put(port);
1625 if (!ep) {
1626 dev_err(dev, "no endpoint specified in output port\n");
1627 return -EINVAL;
1628 }
1629
1630 ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1631 &dsi->burst_clk_rate);
1632 if (ret < 0)
1633 goto end;
1634
1635 ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1636 &dsi->esc_clk_rate);
1637
1638 end:
1639 of_node_put(ep);
1640
1641 return ret;
1642 }
1643
1644 static int exynos_dsi_bind(struct device *dev, struct device *master,
1645 void *data)
1646 {
1647 struct exynos_drm_display *display = dev_get_drvdata(dev);
1648 struct exynos_dsi *dsi = display_to_dsi(display);
1649 struct drm_device *drm_dev = data;
1650 int ret;
1651
1652 ret = exynos_drm_create_enc_conn(drm_dev, display);
1653 if (ret) {
1654 DRM_ERROR("Encoder create [%d] failed with %d\n",
1655 display->type, ret);
1656 return ret;
1657 }
1658
1659 return mipi_dsi_host_register(&dsi->dsi_host);
1660 }
1661
1662 static void exynos_dsi_unbind(struct device *dev, struct device *master,
1663 void *data)
1664 {
1665 struct exynos_drm_display *display = dev_get_drvdata(dev);
1666 struct exynos_dsi *dsi = display_to_dsi(display);
1667
1668 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1669
1670 mipi_dsi_host_unregister(&dsi->dsi_host);
1671 }
1672
1673 static const struct component_ops exynos_dsi_component_ops = {
1674 .bind = exynos_dsi_bind,
1675 .unbind = exynos_dsi_unbind,
1676 };
1677
1678 static int exynos_dsi_probe(struct platform_device *pdev)
1679 {
1680 struct device *dev = &pdev->dev;
1681 struct resource *res;
1682 struct exynos_dsi *dsi;
1683 int ret;
1684
1685 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1686 if (!dsi)
1687 return -ENOMEM;
1688
1689 dsi->display.type = EXYNOS_DISPLAY_TYPE_LCD;
1690 dsi->display.ops = &exynos_dsi_display_ops;
1691
1692 /* To be checked as invalid one */
1693 dsi->te_gpio = -ENOENT;
1694
1695 init_completion(&dsi->completed);
1696 spin_lock_init(&dsi->transfer_lock);
1697 INIT_LIST_HEAD(&dsi->transfer_list);
1698
1699 dsi->dsi_host.ops = &exynos_dsi_ops;
1700 dsi->dsi_host.dev = dev;
1701
1702 dsi->dev = dev;
1703 dsi->driver_data = exynos_dsi_get_driver_data(pdev);
1704
1705 ret = exynos_dsi_parse_dt(dsi);
1706 if (ret)
1707 return ret;
1708
1709 dsi->supplies[0].supply = "vddcore";
1710 dsi->supplies[1].supply = "vddio";
1711 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1712 dsi->supplies);
1713 if (ret) {
1714 dev_info(dev, "failed to get regulators: %d\n", ret);
1715 return -EPROBE_DEFER;
1716 }
1717
1718 dsi->sclk_clk = devm_clk_get(dev, "sclk_mipi");
1719 if (IS_ERR(dsi->sclk_clk)) {
1720 dsi->sclk_clk = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
1721 if (IS_ERR(dsi->sclk_clk)) {
1722 dev_info(dev, "failed to get dsi sclk clock\n");
1723 eturn PTR_ERR(dsi->sclk_clk);
1724 }
1725 }
1726
1727 dsi->bus_clk = devm_clk_get(dev, "bus_clk");
1728 if (IS_ERR(dsi->bus_clk)) {
1729 dev_info(dev, "failed to get dsi bus clock\n");
1730 return PTR_ERR(dsi->bus_clk);
1731 }
1732
1733 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1734 dsi->reg_base = devm_ioremap_resource(dev, res);
1735 if (IS_ERR(dsi->reg_base)) {
1736 dev_err(dev, "failed to remap io region\n");
1737 return PTR_ERR(dsi->reg_base);
1738 }
1739
1740 dsi->phy = devm_phy_get(dev, "dsim");
1741 if (IS_ERR(dsi->phy)) {
1742 dev_info(dev, "failed to get dsim phy\n");
1743 return PTR_ERR(dsi->phy);
1744 }
1745
1746 dsi->irq = platform_get_irq(pdev, 0);
1747 if (dsi->irq < 0) {
1748 dev_err(dev, "failed to request dsi irq resource\n");
1749 return dsi->irq;
1750 }
1751
1752 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1753 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1754 exynos_dsi_irq, IRQF_ONESHOT,
1755 dev_name(dev), dsi);
1756 if (ret) {
1757 dev_err(dev, "failed to request dsi irq\n");
1758 return ret;
1759 }
1760
1761 platform_set_drvdata(pdev, &dsi->display);
1762
1763 return component_add(dev, &exynos_dsi_component_ops);
1764 }
1765
1766 static int exynos_dsi_remove(struct platform_device *pdev)
1767 {
1768 component_del(&pdev->dev, &exynos_dsi_component_ops);
1769
1770 return 0;
1771 }
1772
1773 struct platform_driver dsi_driver = {
1774 .probe = exynos_dsi_probe,
1775 .remove = exynos_dsi_remove,
1776 .driver = {
1777 .name = "exynos-dsi",
1778 .owner = THIS_MODULE,
1779 .of_match_table = exynos_dsi_of_match,
1780 },
1781 };
1782
1783 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1784 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1785 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1786 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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