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drm/exynos: dsi: add support for Exynos5433
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_dsi.c
1 /*
2 * Samsung SoC MIPI DSI Master driver.
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
5 *
6 * Contacts: Tomasz Figa <t.figa@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <drm/drmP.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_mipi_dsi.h>
16 #include <drm/drm_panel.h>
17 #include <drm/drm_atomic_helper.h>
18
19 #include <linux/clk.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/irq.h>
22 #include <linux/of_device.h>
23 #include <linux/of_gpio.h>
24 #include <linux/phy/phy.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/component.h>
27
28 #include <video/mipi_display.h>
29 #include <video/videomode.h>
30
31 #include "exynos_drm_crtc.h"
32 #include "exynos_drm_drv.h"
33
34 /* returns true iff both arguments logically differs */
35 #define NEQV(a, b) (!(a) ^ !(b))
36
37 /* DSIM_STATUS */
38 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
39 #define DSIM_STOP_STATE_CLK (1 << 8)
40 #define DSIM_TX_READY_HS_CLK (1 << 10)
41 #define DSIM_PLL_STABLE (1 << 31)
42
43 /* DSIM_SWRST */
44 #define DSIM_FUNCRST (1 << 16)
45 #define DSIM_SWRST (1 << 0)
46
47 /* DSIM_TIMEOUT */
48 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
49 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
50
51 /* DSIM_CLKCTRL */
52 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
53 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
54 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
55 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
56 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
57 #define DSIM_BYTE_CLKEN (1 << 24)
58 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
59 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
60 #define DSIM_PLL_BYPASS (1 << 27)
61 #define DSIM_ESC_CLKEN (1 << 28)
62 #define DSIM_TX_REQUEST_HSCLK (1 << 31)
63
64 /* DSIM_CONFIG */
65 #define DSIM_LANE_EN_CLK (1 << 0)
66 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
67 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
68 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
69 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
70 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
71 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
72 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
73 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
74 #define DSIM_SUB_VC (((x) & 0x3) << 16)
75 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
76 #define DSIM_HSA_MODE (1 << 20)
77 #define DSIM_HBP_MODE (1 << 21)
78 #define DSIM_HFP_MODE (1 << 22)
79 #define DSIM_HSE_MODE (1 << 23)
80 #define DSIM_AUTO_MODE (1 << 24)
81 #define DSIM_VIDEO_MODE (1 << 25)
82 #define DSIM_BURST_MODE (1 << 26)
83 #define DSIM_SYNC_INFORM (1 << 27)
84 #define DSIM_EOT_DISABLE (1 << 28)
85 #define DSIM_MFLUSH_VS (1 << 29)
86 /* This flag is valid only for exynos3250/3472/4415/5260/5430 */
87 #define DSIM_CLKLANE_STOP (1 << 30)
88
89 /* DSIM_ESCMODE */
90 #define DSIM_TX_TRIGGER_RST (1 << 4)
91 #define DSIM_TX_LPDT_LP (1 << 6)
92 #define DSIM_CMD_LPDT_LP (1 << 7)
93 #define DSIM_FORCE_BTA (1 << 16)
94 #define DSIM_FORCE_STOP_STATE (1 << 20)
95 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
96 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
97
98 /* DSIM_MDRESOL */
99 #define DSIM_MAIN_STAND_BY (1 << 31)
100 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
101 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
102
103 /* DSIM_MVPORCH */
104 #define DSIM_CMD_ALLOW(x) ((x) << 28)
105 #define DSIM_STABLE_VFP(x) ((x) << 16)
106 #define DSIM_MAIN_VBP(x) ((x) << 0)
107 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
108 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
109 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
110
111 /* DSIM_MHPORCH */
112 #define DSIM_MAIN_HFP(x) ((x) << 16)
113 #define DSIM_MAIN_HBP(x) ((x) << 0)
114 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
115 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
116
117 /* DSIM_MSYNC */
118 #define DSIM_MAIN_VSA(x) ((x) << 22)
119 #define DSIM_MAIN_HSA(x) ((x) << 0)
120 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
121 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
122
123 /* DSIM_SDRESOL */
124 #define DSIM_SUB_STANDY(x) ((x) << 31)
125 #define DSIM_SUB_VRESOL(x) ((x) << 16)
126 #define DSIM_SUB_HRESOL(x) ((x) << 0)
127 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
128 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
129 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
130
131 /* DSIM_INTSRC */
132 #define DSIM_INT_PLL_STABLE (1 << 31)
133 #define DSIM_INT_SW_RST_RELEASE (1 << 30)
134 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
135 #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28)
136 #define DSIM_INT_BTA (1 << 25)
137 #define DSIM_INT_FRAME_DONE (1 << 24)
138 #define DSIM_INT_RX_TIMEOUT (1 << 21)
139 #define DSIM_INT_BTA_TIMEOUT (1 << 20)
140 #define DSIM_INT_RX_DONE (1 << 18)
141 #define DSIM_INT_RX_TE (1 << 17)
142 #define DSIM_INT_RX_ACK (1 << 16)
143 #define DSIM_INT_RX_ECC_ERR (1 << 15)
144 #define DSIM_INT_RX_CRC_ERR (1 << 14)
145
146 /* DSIM_FIFOCTRL */
147 #define DSIM_RX_DATA_FULL (1 << 25)
148 #define DSIM_RX_DATA_EMPTY (1 << 24)
149 #define DSIM_SFR_HEADER_FULL (1 << 23)
150 #define DSIM_SFR_HEADER_EMPTY (1 << 22)
151 #define DSIM_SFR_PAYLOAD_FULL (1 << 21)
152 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
153 #define DSIM_I80_HEADER_FULL (1 << 19)
154 #define DSIM_I80_HEADER_EMPTY (1 << 18)
155 #define DSIM_I80_PAYLOAD_FULL (1 << 17)
156 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
157 #define DSIM_SD_HEADER_FULL (1 << 15)
158 #define DSIM_SD_HEADER_EMPTY (1 << 14)
159 #define DSIM_SD_PAYLOAD_FULL (1 << 13)
160 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
161 #define DSIM_MD_HEADER_FULL (1 << 11)
162 #define DSIM_MD_HEADER_EMPTY (1 << 10)
163 #define DSIM_MD_PAYLOAD_FULL (1 << 9)
164 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
165 #define DSIM_RX_FIFO (1 << 4)
166 #define DSIM_SFR_FIFO (1 << 3)
167 #define DSIM_I80_FIFO (1 << 2)
168 #define DSIM_SD_FIFO (1 << 1)
169 #define DSIM_MD_FIFO (1 << 0)
170
171 /* DSIM_PHYACCHR */
172 #define DSIM_AFC_EN (1 << 14)
173 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
174
175 /* DSIM_PLLCTRL */
176 #define DSIM_FREQ_BAND(x) ((x) << 24)
177 #define DSIM_PLL_EN (1 << 23)
178 #define DSIM_PLL_P(x) ((x) << 13)
179 #define DSIM_PLL_M(x) ((x) << 4)
180 #define DSIM_PLL_S(x) ((x) << 1)
181
182 /* DSIM_PHYCTRL */
183 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
184 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30)
185 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14)
186
187 /* DSIM_PHYTIMING */
188 #define DSIM_PHYTIMING_LPX(x) ((x) << 8)
189 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
190
191 /* DSIM_PHYTIMING1 */
192 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
193 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
194 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
195 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
196
197 /* DSIM_PHYTIMING2 */
198 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
199 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
200 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
201
202 #define DSI_MAX_BUS_WIDTH 4
203 #define DSI_NUM_VIRTUAL_CHANNELS 4
204 #define DSI_TX_FIFO_SIZE 2048
205 #define DSI_RX_FIFO_SIZE 256
206 #define DSI_XFER_TIMEOUT_MS 100
207 #define DSI_RX_FIFO_EMPTY 0x30800002
208
209 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
210
211 #define REG_ADDR(dsi, reg_idx) ((dsi)->reg_base + \
212 dsi->driver_data->reg_ofs[(reg_idx)])
213 #define DSI_WRITE(dsi, reg_idx, val) writel((val), \
214 REG_ADDR((dsi), (reg_idx)))
215 #define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx)))
216
217 static char *clk_names[5] = { "bus_clk", "sclk_mipi",
218 "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
219 "sclk_rgb_vclk_to_dsim0" };
220
221 enum exynos_dsi_transfer_type {
222 EXYNOS_DSI_TX,
223 EXYNOS_DSI_RX,
224 };
225
226 struct exynos_dsi_transfer {
227 struct list_head list;
228 struct completion completed;
229 int result;
230 u8 data_id;
231 u8 data[2];
232 u16 flags;
233
234 const u8 *tx_payload;
235 u16 tx_len;
236 u16 tx_done;
237
238 u8 *rx_payload;
239 u16 rx_len;
240 u16 rx_done;
241 };
242
243 #define DSIM_STATE_ENABLED BIT(0)
244 #define DSIM_STATE_INITIALIZED BIT(1)
245 #define DSIM_STATE_CMD_LPM BIT(2)
246 #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
247
248 struct exynos_dsi_driver_data {
249 unsigned int *reg_ofs;
250 unsigned int plltmr_reg;
251 unsigned int has_freqband:1;
252 unsigned int has_clklane_stop:1;
253 unsigned int num_clks;
254 unsigned int max_freq;
255 unsigned int wait_for_reset;
256 unsigned int num_bits_resol;
257 unsigned int *reg_values;
258 };
259
260 struct exynos_dsi {
261 struct exynos_drm_display display;
262 struct mipi_dsi_host dsi_host;
263 struct drm_connector connector;
264 struct device_node *panel_node;
265 struct drm_panel *panel;
266 struct device *dev;
267
268 void __iomem *reg_base;
269 struct phy *phy;
270 struct clk **clks;
271 struct regulator_bulk_data supplies[2];
272 int irq;
273 int te_gpio;
274
275 u32 pll_clk_rate;
276 u32 burst_clk_rate;
277 u32 esc_clk_rate;
278 u32 lanes;
279 u32 mode_flags;
280 u32 format;
281 struct videomode vm;
282
283 int state;
284 struct drm_property *brightness;
285 struct completion completed;
286
287 spinlock_t transfer_lock; /* protects transfer_list */
288 struct list_head transfer_list;
289
290 struct exynos_dsi_driver_data *driver_data;
291 };
292
293 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
294 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
295
296 static inline struct exynos_dsi *display_to_dsi(struct exynos_drm_display *d)
297 {
298 return container_of(d, struct exynos_dsi, display);
299 }
300
301 enum reg_idx {
302 DSIM_STATUS_REG, /* Status register */
303 DSIM_SWRST_REG, /* Software reset register */
304 DSIM_CLKCTRL_REG, /* Clock control register */
305 DSIM_TIMEOUT_REG, /* Time out register */
306 DSIM_CONFIG_REG, /* Configuration register */
307 DSIM_ESCMODE_REG, /* Escape mode register */
308 DSIM_MDRESOL_REG,
309 DSIM_MVPORCH_REG, /* Main display Vporch register */
310 DSIM_MHPORCH_REG, /* Main display Hporch register */
311 DSIM_MSYNC_REG, /* Main display sync area register */
312 DSIM_INTSRC_REG, /* Interrupt source register */
313 DSIM_INTMSK_REG, /* Interrupt mask register */
314 DSIM_PKTHDR_REG, /* Packet Header FIFO register */
315 DSIM_PAYLOAD_REG, /* Payload FIFO register */
316 DSIM_RXFIFO_REG, /* Read FIFO register */
317 DSIM_FIFOCTRL_REG, /* FIFO status and control register */
318 DSIM_PLLCTRL_REG, /* PLL control register */
319 DSIM_PHYCTRL_REG,
320 DSIM_PHYTIMING_REG,
321 DSIM_PHYTIMING1_REG,
322 DSIM_PHYTIMING2_REG,
323 NUM_REGS
324 };
325 static unsigned int exynos_reg_ofs[] = {
326 [DSIM_STATUS_REG] = 0x00,
327 [DSIM_SWRST_REG] = 0x04,
328 [DSIM_CLKCTRL_REG] = 0x08,
329 [DSIM_TIMEOUT_REG] = 0x0c,
330 [DSIM_CONFIG_REG] = 0x10,
331 [DSIM_ESCMODE_REG] = 0x14,
332 [DSIM_MDRESOL_REG] = 0x18,
333 [DSIM_MVPORCH_REG] = 0x1c,
334 [DSIM_MHPORCH_REG] = 0x20,
335 [DSIM_MSYNC_REG] = 0x24,
336 [DSIM_INTSRC_REG] = 0x2c,
337 [DSIM_INTMSK_REG] = 0x30,
338 [DSIM_PKTHDR_REG] = 0x34,
339 [DSIM_PAYLOAD_REG] = 0x38,
340 [DSIM_RXFIFO_REG] = 0x3c,
341 [DSIM_FIFOCTRL_REG] = 0x44,
342 [DSIM_PLLCTRL_REG] = 0x4c,
343 [DSIM_PHYCTRL_REG] = 0x5c,
344 [DSIM_PHYTIMING_REG] = 0x64,
345 [DSIM_PHYTIMING1_REG] = 0x68,
346 [DSIM_PHYTIMING2_REG] = 0x6c,
347 };
348
349 static unsigned int exynos5433_reg_ofs[] = {
350 [DSIM_STATUS_REG] = 0x04,
351 [DSIM_SWRST_REG] = 0x0C,
352 [DSIM_CLKCTRL_REG] = 0x10,
353 [DSIM_TIMEOUT_REG] = 0x14,
354 [DSIM_CONFIG_REG] = 0x18,
355 [DSIM_ESCMODE_REG] = 0x1C,
356 [DSIM_MDRESOL_REG] = 0x20,
357 [DSIM_MVPORCH_REG] = 0x24,
358 [DSIM_MHPORCH_REG] = 0x28,
359 [DSIM_MSYNC_REG] = 0x2C,
360 [DSIM_INTSRC_REG] = 0x34,
361 [DSIM_INTMSK_REG] = 0x38,
362 [DSIM_PKTHDR_REG] = 0x3C,
363 [DSIM_PAYLOAD_REG] = 0x40,
364 [DSIM_RXFIFO_REG] = 0x44,
365 [DSIM_FIFOCTRL_REG] = 0x4C,
366 [DSIM_PLLCTRL_REG] = 0x94,
367 [DSIM_PHYCTRL_REG] = 0xA4,
368 [DSIM_PHYTIMING_REG] = 0xB4,
369 [DSIM_PHYTIMING1_REG] = 0xB8,
370 [DSIM_PHYTIMING2_REG] = 0xBC,
371 };
372
373 enum reg_value_idx {
374 RESET_TYPE,
375 PLL_TIMER,
376 STOP_STATE_CNT,
377 PHYCTRL_ULPS_EXIT,
378 PHYCTRL_VREG_LP,
379 PHYCTRL_SLEW_UP,
380 PHYTIMING_LPX,
381 PHYTIMING_HS_EXIT,
382 PHYTIMING_CLK_PREPARE,
383 PHYTIMING_CLK_ZERO,
384 PHYTIMING_CLK_POST,
385 PHYTIMING_CLK_TRAIL,
386 PHYTIMING_HS_PREPARE,
387 PHYTIMING_HS_ZERO,
388 PHYTIMING_HS_TRAIL
389 };
390
391 static unsigned int reg_values[] = {
392 [RESET_TYPE] = DSIM_SWRST,
393 [PLL_TIMER] = 500,
394 [STOP_STATE_CNT] = 0xf,
395 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
396 [PHYCTRL_VREG_LP] = 0,
397 [PHYCTRL_SLEW_UP] = 0,
398 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
399 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
400 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
401 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
402 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
403 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
404 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
405 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
406 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
407 };
408
409 static unsigned int exynos5433_reg_values[] = {
410 [RESET_TYPE] = DSIM_FUNCRST,
411 [PLL_TIMER] = 22200,
412 [STOP_STATE_CNT] = 0xa,
413 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
414 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
415 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
416 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
417 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
418 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
419 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
420 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
421 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
422 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
423 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
424 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
425 };
426
427 static struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
428 .reg_ofs = exynos_reg_ofs,
429 .plltmr_reg = 0x50,
430 .has_freqband = 1,
431 .has_clklane_stop = 1,
432 .num_clks = 2,
433 .max_freq = 1000,
434 .wait_for_reset = 1,
435 .num_bits_resol = 11,
436 .reg_values = reg_values,
437 };
438
439 static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
440 .reg_ofs = exynos_reg_ofs,
441 .plltmr_reg = 0x50,
442 .has_freqband = 1,
443 .has_clklane_stop = 1,
444 .num_clks = 2,
445 .max_freq = 1000,
446 .wait_for_reset = 1,
447 .num_bits_resol = 11,
448 .reg_values = reg_values,
449 };
450
451 static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
452 .reg_ofs = exynos_reg_ofs,
453 .plltmr_reg = 0x58,
454 .has_clklane_stop = 1,
455 .num_clks = 2,
456 .max_freq = 1000,
457 .wait_for_reset = 1,
458 .num_bits_resol = 11,
459 .reg_values = reg_values,
460 };
461
462 static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
463 .reg_ofs = exynos_reg_ofs,
464 .plltmr_reg = 0x58,
465 .num_clks = 2,
466 .max_freq = 1000,
467 .wait_for_reset = 1,
468 .num_bits_resol = 11,
469 .reg_values = reg_values,
470 };
471
472 static struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
473 .reg_ofs = exynos5433_reg_ofs,
474 .plltmr_reg = 0xa0,
475 .has_clklane_stop = 1,
476 .num_clks = 5,
477 .max_freq = 1500,
478 .wait_for_reset = 0,
479 .num_bits_resol = 12,
480 .reg_values = exynos5433_reg_values,
481 };
482
483 static struct of_device_id exynos_dsi_of_match[] = {
484 { .compatible = "samsung,exynos3250-mipi-dsi",
485 .data = &exynos3_dsi_driver_data },
486 { .compatible = "samsung,exynos4210-mipi-dsi",
487 .data = &exynos4_dsi_driver_data },
488 { .compatible = "samsung,exynos4415-mipi-dsi",
489 .data = &exynos4415_dsi_driver_data },
490 { .compatible = "samsung,exynos5410-mipi-dsi",
491 .data = &exynos5_dsi_driver_data },
492 { .compatible = "samsung,exynos5433-mipi-dsi",
493 .data = &exynos5433_dsi_driver_data },
494 { }
495 };
496
497 static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
498 struct platform_device *pdev)
499 {
500 const struct of_device_id *of_id =
501 of_match_device(exynos_dsi_of_match, &pdev->dev);
502
503 return (struct exynos_dsi_driver_data *)of_id->data;
504 }
505
506 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
507 {
508 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
509 return;
510
511 dev_err(dsi->dev, "timeout waiting for reset\n");
512 }
513
514 static void exynos_dsi_reset(struct exynos_dsi *dsi)
515 {
516 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
517
518 reinit_completion(&dsi->completed);
519 DSI_WRITE(dsi, DSIM_SWRST_REG, driver_data->reg_values[RESET_TYPE]);
520 }
521
522 #ifndef MHZ
523 #define MHZ (1000*1000)
524 #endif
525
526 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
527 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
528 {
529 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
530 unsigned long best_freq = 0;
531 u32 min_delta = 0xffffffff;
532 u8 p_min, p_max;
533 u8 _p, uninitialized_var(best_p);
534 u16 _m, uninitialized_var(best_m);
535 u8 _s, uninitialized_var(best_s);
536
537 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
538 p_max = fin / (6 * MHZ);
539
540 for (_p = p_min; _p <= p_max; ++_p) {
541 for (_s = 0; _s <= 5; ++_s) {
542 u64 tmp;
543 u32 delta;
544
545 tmp = (u64)fout * (_p << _s);
546 do_div(tmp, fin);
547 _m = tmp;
548 if (_m < 41 || _m > 125)
549 continue;
550
551 tmp = (u64)_m * fin;
552 do_div(tmp, _p);
553 if (tmp < 500 * MHZ ||
554 tmp > driver_data->max_freq * MHZ)
555 continue;
556
557 tmp = (u64)_m * fin;
558 do_div(tmp, _p << _s);
559
560 delta = abs(fout - tmp);
561 if (delta < min_delta) {
562 best_p = _p;
563 best_m = _m;
564 best_s = _s;
565 min_delta = delta;
566 best_freq = tmp;
567 }
568 }
569 }
570
571 if (best_freq) {
572 *p = best_p;
573 *m = best_m;
574 *s = best_s;
575 }
576
577 return best_freq;
578 }
579
580 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
581 unsigned long freq)
582 {
583 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
584 unsigned long fin, fout;
585 int timeout;
586 u8 p, s;
587 u16 m;
588 u32 reg;
589
590 fin = dsi->pll_clk_rate;
591 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
592 if (!fout) {
593 dev_err(dsi->dev,
594 "failed to find PLL PMS for requested frequency\n");
595 return 0;
596 }
597 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
598
599 writel(driver_data->reg_values[PLL_TIMER],
600 dsi->reg_base + driver_data->plltmr_reg);
601
602 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
603
604 if (driver_data->has_freqband) {
605 static const unsigned long freq_bands[] = {
606 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
607 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
608 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
609 770 * MHZ, 870 * MHZ, 950 * MHZ,
610 };
611 int band;
612
613 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
614 if (fout < freq_bands[band])
615 break;
616
617 dev_dbg(dsi->dev, "band %d\n", band);
618
619 reg |= DSIM_FREQ_BAND(band);
620 }
621
622 DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg);
623
624 timeout = 1000;
625 do {
626 if (timeout-- == 0) {
627 dev_err(dsi->dev, "PLL failed to stabilize\n");
628 return 0;
629 }
630 reg = DSI_READ(dsi, DSIM_STATUS_REG);
631 } while ((reg & DSIM_PLL_STABLE) == 0);
632
633 return fout;
634 }
635
636 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
637 {
638 unsigned long hs_clk, byte_clk, esc_clk;
639 unsigned long esc_div;
640 u32 reg;
641
642 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
643 if (!hs_clk) {
644 dev_err(dsi->dev, "failed to configure DSI PLL\n");
645 return -EFAULT;
646 }
647
648 byte_clk = hs_clk / 8;
649 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
650 esc_clk = byte_clk / esc_div;
651
652 if (esc_clk > 20 * MHZ) {
653 ++esc_div;
654 esc_clk = byte_clk / esc_div;
655 }
656
657 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
658 hs_clk, byte_clk, esc_clk);
659
660 reg = DSI_READ(dsi, DSIM_CLKCTRL_REG);
661 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
662 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
663 | DSIM_BYTE_CLK_SRC_MASK);
664 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
665 | DSIM_ESC_PRESCALER(esc_div)
666 | DSIM_LANE_ESC_CLK_EN_CLK
667 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
668 | DSIM_BYTE_CLK_SRC(0)
669 | DSIM_TX_REQUEST_HSCLK;
670 DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg);
671
672 return 0;
673 }
674
675 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
676 {
677 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
678 unsigned int *reg_values = driver_data->reg_values;
679 u32 reg;
680
681 if (driver_data->has_freqband)
682 return;
683
684 /* B D-PHY: D-PHY Master & Slave Analog Block control */
685 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
686 reg_values[PHYCTRL_SLEW_UP];
687 DSI_WRITE(dsi, DSIM_PHYCTRL_REG, reg);
688
689 /*
690 * T LPX: Transmitted length of any Low-Power state period
691 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
692 * burst
693 */
694 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
695 DSI_WRITE(dsi, DSIM_PHYTIMING_REG, reg);
696
697 /*
698 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
699 * Line state immediately before the HS-0 Line state starting the
700 * HS transmission
701 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
702 * transmitting the Clock.
703 * T CLK_POST: Time that the transmitter continues to send HS clock
704 * after the last associated Data Lane has transitioned to LP Mode
705 * Interval is defined as the period from the end of T HS-TRAIL to
706 * the beginning of T CLK-TRAIL
707 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
708 * the last payload clock bit of a HS transmission burst
709 */
710 reg = reg_values[PHYTIMING_CLK_PREPARE] |
711 reg_values[PHYTIMING_CLK_ZERO] |
712 reg_values[PHYTIMING_CLK_POST] |
713 reg_values[PHYTIMING_CLK_TRAIL];
714
715 DSI_WRITE(dsi, DSIM_PHYTIMING1_REG, reg);
716
717 /*
718 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
719 * Line state immediately before the HS-0 Line state starting the
720 * HS transmission
721 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
722 * transmitting the Sync sequence.
723 * T HS-TRAIL: Time that the transmitter drives the flipped differential
724 * state after last payload data bit of a HS transmission burst
725 */
726 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
727 reg_values[PHYTIMING_HS_TRAIL];
728 DSI_WRITE(dsi, DSIM_PHYTIMING2_REG, reg);
729 }
730
731 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
732 {
733 u32 reg;
734
735 reg = DSI_READ(dsi, DSIM_CLKCTRL_REG);
736 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
737 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
738 DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg);
739
740 reg = DSI_READ(dsi, DSIM_PLLCTRL_REG);
741 reg &= ~DSIM_PLL_EN;
742 DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg);
743 }
744
745 static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
746 {
747 u32 reg = DSI_READ(dsi, DSIM_CONFIG_REG);
748 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
749 DSIM_LANE_EN(lane));
750 DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
751 }
752
753 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
754 {
755 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
756 int timeout;
757 u32 reg;
758 u32 lanes_mask;
759
760 /* Initialize FIFO pointers */
761 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG);
762 reg &= ~0x1f;
763 DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg);
764
765 usleep_range(9000, 11000);
766
767 reg |= 0x1f;
768 DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg);
769 usleep_range(9000, 11000);
770
771 /* DSI configuration */
772 reg = 0;
773
774 /*
775 * The first bit of mode_flags specifies display configuration.
776 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
777 * mode, otherwise it will support command mode.
778 */
779 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
780 reg |= DSIM_VIDEO_MODE;
781
782 /*
783 * The user manual describes that following bits are ignored in
784 * command mode.
785 */
786 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
787 reg |= DSIM_MFLUSH_VS;
788 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
789 reg |= DSIM_SYNC_INFORM;
790 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
791 reg |= DSIM_BURST_MODE;
792 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
793 reg |= DSIM_AUTO_MODE;
794 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
795 reg |= DSIM_HSE_MODE;
796 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
797 reg |= DSIM_HFP_MODE;
798 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
799 reg |= DSIM_HBP_MODE;
800 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
801 reg |= DSIM_HSA_MODE;
802 }
803
804 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
805 reg |= DSIM_EOT_DISABLE;
806
807 switch (dsi->format) {
808 case MIPI_DSI_FMT_RGB888:
809 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
810 break;
811 case MIPI_DSI_FMT_RGB666:
812 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
813 break;
814 case MIPI_DSI_FMT_RGB666_PACKED:
815 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
816 break;
817 case MIPI_DSI_FMT_RGB565:
818 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
819 break;
820 default:
821 dev_err(dsi->dev, "invalid pixel format\n");
822 return -EINVAL;
823 }
824
825 /*
826 * Use non-continuous clock mode if the periparal wants and
827 * host controller supports
828 *
829 * In non-continous clock mode, host controller will turn off
830 * the HS clock between high-speed transmissions to reduce
831 * power consumption.
832 */
833 if (driver_data->has_clklane_stop &&
834 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
835 reg |= DSIM_CLKLANE_STOP;
836 }
837 DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
838
839 lanes_mask = BIT(dsi->lanes) - 1;
840 exynos_dsi_enable_lane(dsi, lanes_mask);
841
842 /* Check clock and data lane state are stop state */
843 timeout = 100;
844 do {
845 if (timeout-- == 0) {
846 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
847 return -EFAULT;
848 }
849
850 reg = DSI_READ(dsi, DSIM_STATUS_REG);
851 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
852 != DSIM_STOP_STATE_DAT(lanes_mask))
853 continue;
854 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
855
856 reg = DSI_READ(dsi, DSIM_ESCMODE_REG);
857 reg &= ~DSIM_STOP_STATE_CNT_MASK;
858 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
859 DSI_WRITE(dsi, DSIM_ESCMODE_REG, reg);
860
861 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
862 DSI_WRITE(dsi, DSIM_TIMEOUT_REG, reg);
863
864 return 0;
865 }
866
867 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
868 {
869 struct videomode *vm = &dsi->vm;
870 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
871 u32 reg;
872
873 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
874 reg = DSIM_CMD_ALLOW(0xf)
875 | DSIM_STABLE_VFP(vm->vfront_porch)
876 | DSIM_MAIN_VBP(vm->vback_porch);
877 DSI_WRITE(dsi, DSIM_MVPORCH_REG, reg);
878
879 reg = DSIM_MAIN_HFP(vm->hfront_porch)
880 | DSIM_MAIN_HBP(vm->hback_porch);
881 DSI_WRITE(dsi, DSIM_MHPORCH_REG, reg);
882
883 reg = DSIM_MAIN_VSA(vm->vsync_len)
884 | DSIM_MAIN_HSA(vm->hsync_len);
885 DSI_WRITE(dsi, DSIM_MSYNC_REG, reg);
886 }
887 reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) |
888 DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol);
889
890 DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg);
891
892 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
893 }
894
895 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
896 {
897 u32 reg;
898
899 reg = DSI_READ(dsi, DSIM_MDRESOL_REG);
900 if (enable)
901 reg |= DSIM_MAIN_STAND_BY;
902 else
903 reg &= ~DSIM_MAIN_STAND_BY;
904 DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg);
905 }
906
907 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
908 {
909 int timeout = 2000;
910
911 do {
912 u32 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG);
913
914 if (!(reg & DSIM_SFR_HEADER_FULL))
915 return 0;
916
917 if (!cond_resched())
918 usleep_range(950, 1050);
919 } while (--timeout);
920
921 return -ETIMEDOUT;
922 }
923
924 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
925 {
926 u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG);
927
928 if (lpm)
929 v |= DSIM_CMD_LPDT_LP;
930 else
931 v &= ~DSIM_CMD_LPDT_LP;
932
933 DSI_WRITE(dsi, DSIM_ESCMODE_REG, v);
934 }
935
936 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
937 {
938 u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG);
939 v |= DSIM_FORCE_BTA;
940 DSI_WRITE(dsi, DSIM_ESCMODE_REG, v);
941 }
942
943 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
944 struct exynos_dsi_transfer *xfer)
945 {
946 struct device *dev = dsi->dev;
947 const u8 *payload = xfer->tx_payload + xfer->tx_done;
948 u16 length = xfer->tx_len - xfer->tx_done;
949 bool first = !xfer->tx_done;
950 u32 reg;
951
952 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
953 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
954
955 if (length > DSI_TX_FIFO_SIZE)
956 length = DSI_TX_FIFO_SIZE;
957
958 xfer->tx_done += length;
959
960 /* Send payload */
961 while (length >= 4) {
962 reg = (payload[3] << 24) | (payload[2] << 16)
963 | (payload[1] << 8) | payload[0];
964 DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg);
965 payload += 4;
966 length -= 4;
967 }
968
969 reg = 0;
970 switch (length) {
971 case 3:
972 reg |= payload[2] << 16;
973 /* Fall through */
974 case 2:
975 reg |= payload[1] << 8;
976 /* Fall through */
977 case 1:
978 reg |= payload[0];
979 DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg);
980 break;
981 case 0:
982 /* Do nothing */
983 break;
984 }
985
986 /* Send packet header */
987 if (!first)
988 return;
989
990 reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id;
991 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
992 dev_err(dev, "waiting for header FIFO timed out\n");
993 return;
994 }
995
996 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
997 dsi->state & DSIM_STATE_CMD_LPM)) {
998 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
999 dsi->state ^= DSIM_STATE_CMD_LPM;
1000 }
1001
1002 DSI_WRITE(dsi, DSIM_PKTHDR_REG, reg);
1003
1004 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1005 exynos_dsi_force_bta(dsi);
1006 }
1007
1008 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
1009 struct exynos_dsi_transfer *xfer)
1010 {
1011 u8 *payload = xfer->rx_payload + xfer->rx_done;
1012 bool first = !xfer->rx_done;
1013 struct device *dev = dsi->dev;
1014 u16 length;
1015 u32 reg;
1016
1017 if (first) {
1018 reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
1019
1020 switch (reg & 0x3f) {
1021 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1022 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1023 if (xfer->rx_len >= 2) {
1024 payload[1] = reg >> 16;
1025 ++xfer->rx_done;
1026 }
1027 /* Fall through */
1028 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1029 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1030 payload[0] = reg >> 8;
1031 ++xfer->rx_done;
1032 xfer->rx_len = xfer->rx_done;
1033 xfer->result = 0;
1034 goto clear_fifo;
1035 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1036 dev_err(dev, "DSI Error Report: 0x%04x\n",
1037 (reg >> 8) & 0xffff);
1038 xfer->result = 0;
1039 goto clear_fifo;
1040 }
1041
1042 length = (reg >> 8) & 0xffff;
1043 if (length > xfer->rx_len) {
1044 dev_err(dev,
1045 "response too long (%u > %u bytes), stripping\n",
1046 xfer->rx_len, length);
1047 length = xfer->rx_len;
1048 } else if (length < xfer->rx_len)
1049 xfer->rx_len = length;
1050 }
1051
1052 length = xfer->rx_len - xfer->rx_done;
1053 xfer->rx_done += length;
1054
1055 /* Receive payload */
1056 while (length >= 4) {
1057 reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
1058 payload[0] = (reg >> 0) & 0xff;
1059 payload[1] = (reg >> 8) & 0xff;
1060 payload[2] = (reg >> 16) & 0xff;
1061 payload[3] = (reg >> 24) & 0xff;
1062 payload += 4;
1063 length -= 4;
1064 }
1065
1066 if (length) {
1067 reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
1068 switch (length) {
1069 case 3:
1070 payload[2] = (reg >> 16) & 0xff;
1071 /* Fall through */
1072 case 2:
1073 payload[1] = (reg >> 8) & 0xff;
1074 /* Fall through */
1075 case 1:
1076 payload[0] = reg & 0xff;
1077 }
1078 }
1079
1080 if (xfer->rx_done == xfer->rx_len)
1081 xfer->result = 0;
1082
1083 clear_fifo:
1084 length = DSI_RX_FIFO_SIZE / 4;
1085 do {
1086 reg = DSI_READ(dsi, DSIM_RXFIFO_REG);
1087 if (reg == DSI_RX_FIFO_EMPTY)
1088 break;
1089 } while (--length);
1090 }
1091
1092 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
1093 {
1094 unsigned long flags;
1095 struct exynos_dsi_transfer *xfer;
1096 bool start = false;
1097
1098 again:
1099 spin_lock_irqsave(&dsi->transfer_lock, flags);
1100
1101 if (list_empty(&dsi->transfer_list)) {
1102 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1103 return;
1104 }
1105
1106 xfer = list_first_entry(&dsi->transfer_list,
1107 struct exynos_dsi_transfer, list);
1108
1109 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1110
1111 if (xfer->tx_len && xfer->tx_done == xfer->tx_len)
1112 /* waiting for RX */
1113 return;
1114
1115 exynos_dsi_send_to_fifo(dsi, xfer);
1116
1117 if (xfer->tx_len || xfer->rx_len)
1118 return;
1119
1120 xfer->result = 0;
1121 complete(&xfer->completed);
1122
1123 spin_lock_irqsave(&dsi->transfer_lock, flags);
1124
1125 list_del_init(&xfer->list);
1126 start = !list_empty(&dsi->transfer_list);
1127
1128 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1129
1130 if (start)
1131 goto again;
1132 }
1133
1134 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
1135 {
1136 struct exynos_dsi_transfer *xfer;
1137 unsigned long flags;
1138 bool start = true;
1139
1140 spin_lock_irqsave(&dsi->transfer_lock, flags);
1141
1142 if (list_empty(&dsi->transfer_list)) {
1143 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1144 return false;
1145 }
1146
1147 xfer = list_first_entry(&dsi->transfer_list,
1148 struct exynos_dsi_transfer, list);
1149
1150 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1151
1152 dev_dbg(dsi->dev,
1153 "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n",
1154 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
1155
1156 if (xfer->tx_done != xfer->tx_len)
1157 return true;
1158
1159 if (xfer->rx_done != xfer->rx_len)
1160 exynos_dsi_read_from_fifo(dsi, xfer);
1161
1162 if (xfer->rx_done != xfer->rx_len)
1163 return true;
1164
1165 spin_lock_irqsave(&dsi->transfer_lock, flags);
1166
1167 list_del_init(&xfer->list);
1168 start = !list_empty(&dsi->transfer_list);
1169
1170 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1171
1172 if (!xfer->rx_len)
1173 xfer->result = 0;
1174 complete(&xfer->completed);
1175
1176 return start;
1177 }
1178
1179 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1180 struct exynos_dsi_transfer *xfer)
1181 {
1182 unsigned long flags;
1183 bool start;
1184
1185 spin_lock_irqsave(&dsi->transfer_lock, flags);
1186
1187 if (!list_empty(&dsi->transfer_list) &&
1188 xfer == list_first_entry(&dsi->transfer_list,
1189 struct exynos_dsi_transfer, list)) {
1190 list_del_init(&xfer->list);
1191 start = !list_empty(&dsi->transfer_list);
1192 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1193 if (start)
1194 exynos_dsi_transfer_start(dsi);
1195 return;
1196 }
1197
1198 list_del_init(&xfer->list);
1199
1200 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1201 }
1202
1203 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1204 struct exynos_dsi_transfer *xfer)
1205 {
1206 unsigned long flags;
1207 bool stopped;
1208
1209 xfer->tx_done = 0;
1210 xfer->rx_done = 0;
1211 xfer->result = -ETIMEDOUT;
1212 init_completion(&xfer->completed);
1213
1214 spin_lock_irqsave(&dsi->transfer_lock, flags);
1215
1216 stopped = list_empty(&dsi->transfer_list);
1217 list_add_tail(&xfer->list, &dsi->transfer_list);
1218
1219 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1220
1221 if (stopped)
1222 exynos_dsi_transfer_start(dsi);
1223
1224 wait_for_completion_timeout(&xfer->completed,
1225 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1226 if (xfer->result == -ETIMEDOUT) {
1227 exynos_dsi_remove_transfer(dsi, xfer);
1228 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data,
1229 xfer->tx_len, xfer->tx_payload);
1230 return -ETIMEDOUT;
1231 }
1232
1233 /* Also covers hardware timeout condition */
1234 return xfer->result;
1235 }
1236
1237 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1238 {
1239 struct exynos_dsi *dsi = dev_id;
1240 u32 status;
1241
1242 status = DSI_READ(dsi, DSIM_INTSRC_REG);
1243 if (!status) {
1244 static unsigned long int j;
1245 if (printk_timed_ratelimit(&j, 500))
1246 dev_warn(dsi->dev, "spurious interrupt\n");
1247 return IRQ_HANDLED;
1248 }
1249 DSI_WRITE(dsi, DSIM_INTSRC_REG, status);
1250
1251 if (status & DSIM_INT_SW_RST_RELEASE) {
1252 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1253 DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE |
1254 DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE);
1255 DSI_WRITE(dsi, DSIM_INTMSK_REG, mask);
1256 complete(&dsi->completed);
1257 return IRQ_HANDLED;
1258 }
1259
1260 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1261 DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE)))
1262 return IRQ_HANDLED;
1263
1264 if (exynos_dsi_transfer_finish(dsi))
1265 exynos_dsi_transfer_start(dsi);
1266
1267 return IRQ_HANDLED;
1268 }
1269
1270 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1271 {
1272 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1273 struct drm_encoder *encoder = dsi->display.encoder;
1274
1275 if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
1276 exynos_drm_crtc_te_handler(encoder->crtc);
1277
1278 return IRQ_HANDLED;
1279 }
1280
1281 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1282 {
1283 enable_irq(dsi->irq);
1284
1285 if (gpio_is_valid(dsi->te_gpio))
1286 enable_irq(gpio_to_irq(dsi->te_gpio));
1287 }
1288
1289 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1290 {
1291 if (gpio_is_valid(dsi->te_gpio))
1292 disable_irq(gpio_to_irq(dsi->te_gpio));
1293
1294 disable_irq(dsi->irq);
1295 }
1296
1297 static int exynos_dsi_init(struct exynos_dsi *dsi)
1298 {
1299 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1300
1301 exynos_dsi_reset(dsi);
1302 exynos_dsi_enable_irq(dsi);
1303
1304 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1305 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
1306
1307 exynos_dsi_enable_clock(dsi);
1308 if (driver_data->wait_for_reset)
1309 exynos_dsi_wait_for_reset(dsi);
1310 exynos_dsi_set_phy_ctrl(dsi);
1311 exynos_dsi_init_link(dsi);
1312
1313 return 0;
1314 }
1315
1316 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
1317 {
1318 int ret;
1319 int te_gpio_irq;
1320
1321 dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
1322 if (!gpio_is_valid(dsi->te_gpio)) {
1323 dev_err(dsi->dev, "no te-gpios specified\n");
1324 ret = dsi->te_gpio;
1325 goto out;
1326 }
1327
1328 ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio");
1329 if (ret) {
1330 dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1331 goto out;
1332 }
1333
1334 te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1335
1336 irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
1337 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1338 IRQF_TRIGGER_RISING, "TE", dsi);
1339 if (ret) {
1340 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1341 gpio_free(dsi->te_gpio);
1342 goto out;
1343 }
1344
1345 out:
1346 return ret;
1347 }
1348
1349 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1350 {
1351 if (gpio_is_valid(dsi->te_gpio)) {
1352 free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1353 gpio_free(dsi->te_gpio);
1354 dsi->te_gpio = -ENOENT;
1355 }
1356 }
1357
1358 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1359 struct mipi_dsi_device *device)
1360 {
1361 struct exynos_dsi *dsi = host_to_dsi(host);
1362
1363 dsi->lanes = device->lanes;
1364 dsi->format = device->format;
1365 dsi->mode_flags = device->mode_flags;
1366 dsi->panel_node = device->dev.of_node;
1367
1368 /*
1369 * This is a temporary solution and should be made by more generic way.
1370 *
1371 * If attached panel device is for command mode one, dsi should register
1372 * TE interrupt handler.
1373 */
1374 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1375 int ret = exynos_dsi_register_te_irq(dsi);
1376
1377 if (ret)
1378 return ret;
1379 }
1380
1381 if (dsi->connector.dev)
1382 drm_helper_hpd_irq_event(dsi->connector.dev);
1383
1384 return 0;
1385 }
1386
1387 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1388 struct mipi_dsi_device *device)
1389 {
1390 struct exynos_dsi *dsi = host_to_dsi(host);
1391
1392 exynos_dsi_unregister_te_irq(dsi);
1393
1394 dsi->panel_node = NULL;
1395
1396 if (dsi->connector.dev)
1397 drm_helper_hpd_irq_event(dsi->connector.dev);
1398
1399 return 0;
1400 }
1401
1402 /* distinguish between short and long DSI packet types */
1403 static bool exynos_dsi_is_short_dsi_type(u8 type)
1404 {
1405 return (type & 0x0f) <= 8;
1406 }
1407
1408 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1409 const struct mipi_dsi_msg *msg)
1410 {
1411 struct exynos_dsi *dsi = host_to_dsi(host);
1412 struct exynos_dsi_transfer xfer;
1413 int ret;
1414
1415 if (!(dsi->state & DSIM_STATE_ENABLED))
1416 return -EINVAL;
1417
1418 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1419 ret = exynos_dsi_init(dsi);
1420 if (ret)
1421 return ret;
1422 dsi->state |= DSIM_STATE_INITIALIZED;
1423 }
1424
1425 if (msg->tx_len == 0)
1426 return -EINVAL;
1427
1428 xfer.data_id = msg->type | (msg->channel << 6);
1429
1430 if (exynos_dsi_is_short_dsi_type(msg->type)) {
1431 const char *tx_buf = msg->tx_buf;
1432
1433 if (msg->tx_len > 2)
1434 return -EINVAL;
1435 xfer.tx_len = 0;
1436 xfer.data[0] = tx_buf[0];
1437 xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0;
1438 } else {
1439 xfer.tx_len = msg->tx_len;
1440 xfer.data[0] = msg->tx_len & 0xff;
1441 xfer.data[1] = msg->tx_len >> 8;
1442 xfer.tx_payload = msg->tx_buf;
1443 }
1444
1445 xfer.rx_len = msg->rx_len;
1446 xfer.rx_payload = msg->rx_buf;
1447 xfer.flags = msg->flags;
1448
1449 ret = exynos_dsi_transfer(dsi, &xfer);
1450 return (ret < 0) ? ret : xfer.rx_done;
1451 }
1452
1453 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1454 .attach = exynos_dsi_host_attach,
1455 .detach = exynos_dsi_host_detach,
1456 .transfer = exynos_dsi_host_transfer,
1457 };
1458
1459 static int exynos_dsi_poweron(struct exynos_dsi *dsi)
1460 {
1461 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1462 int ret, i;
1463
1464 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1465 if (ret < 0) {
1466 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1467 return ret;
1468 }
1469
1470 for (i = 0; i < driver_data->num_clks; i++) {
1471 ret = clk_prepare_enable(dsi->clks[i]);
1472 if (ret < 0)
1473 goto err_clk;
1474 }
1475
1476 ret = phy_power_on(dsi->phy);
1477 if (ret < 0) {
1478 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1479 goto err_clk;
1480 }
1481
1482 return 0;
1483
1484 err_clk:
1485 while (--i > -1)
1486 clk_disable_unprepare(dsi->clks[i]);
1487 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1488
1489 return ret;
1490 }
1491
1492 static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
1493 {
1494 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1495 int ret, i;
1496
1497 usleep_range(10000, 20000);
1498
1499 if (dsi->state & DSIM_STATE_INITIALIZED) {
1500 dsi->state &= ~DSIM_STATE_INITIALIZED;
1501
1502 exynos_dsi_disable_clock(dsi);
1503
1504 exynos_dsi_disable_irq(dsi);
1505 }
1506
1507 dsi->state &= ~DSIM_STATE_CMD_LPM;
1508
1509 phy_power_off(dsi->phy);
1510
1511 for (i = driver_data->num_clks - 1; i > -1; i--)
1512 clk_disable_unprepare(dsi->clks[i]);
1513
1514 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1515 if (ret < 0)
1516 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1517 }
1518
1519 static int exynos_dsi_enable(struct exynos_dsi *dsi)
1520 {
1521 int ret;
1522
1523 if (dsi->state & DSIM_STATE_ENABLED)
1524 return 0;
1525
1526 ret = exynos_dsi_poweron(dsi);
1527 if (ret < 0)
1528 return ret;
1529
1530 dsi->state |= DSIM_STATE_ENABLED;
1531
1532 ret = drm_panel_prepare(dsi->panel);
1533 if (ret < 0) {
1534 dsi->state &= ~DSIM_STATE_ENABLED;
1535 exynos_dsi_poweroff(dsi);
1536 return ret;
1537 }
1538
1539 exynos_dsi_set_display_mode(dsi);
1540 exynos_dsi_set_display_enable(dsi, true);
1541
1542 ret = drm_panel_enable(dsi->panel);
1543 if (ret < 0) {
1544 dsi->state &= ~DSIM_STATE_ENABLED;
1545 exynos_dsi_set_display_enable(dsi, false);
1546 drm_panel_unprepare(dsi->panel);
1547 exynos_dsi_poweroff(dsi);
1548 return ret;
1549 }
1550
1551 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1552
1553 return 0;
1554 }
1555
1556 static void exynos_dsi_disable(struct exynos_dsi *dsi)
1557 {
1558 if (!(dsi->state & DSIM_STATE_ENABLED))
1559 return;
1560
1561 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1562
1563 drm_panel_disable(dsi->panel);
1564 exynos_dsi_set_display_enable(dsi, false);
1565 drm_panel_unprepare(dsi->panel);
1566
1567 dsi->state &= ~DSIM_STATE_ENABLED;
1568
1569 exynos_dsi_poweroff(dsi);
1570 }
1571
1572 static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode)
1573 {
1574 struct exynos_dsi *dsi = display_to_dsi(display);
1575
1576 if (dsi->panel) {
1577 switch (mode) {
1578 case DRM_MODE_DPMS_ON:
1579 exynos_dsi_enable(dsi);
1580 break;
1581 case DRM_MODE_DPMS_STANDBY:
1582 case DRM_MODE_DPMS_SUSPEND:
1583 case DRM_MODE_DPMS_OFF:
1584 exynos_dsi_disable(dsi);
1585 break;
1586 default:
1587 break;
1588 }
1589 }
1590 }
1591
1592 static enum drm_connector_status
1593 exynos_dsi_detect(struct drm_connector *connector, bool force)
1594 {
1595 struct exynos_dsi *dsi = connector_to_dsi(connector);
1596
1597 if (!dsi->panel) {
1598 dsi->panel = of_drm_find_panel(dsi->panel_node);
1599 if (dsi->panel)
1600 drm_panel_attach(dsi->panel, &dsi->connector);
1601 } else if (!dsi->panel_node) {
1602 struct exynos_drm_display *display;
1603
1604 display = platform_get_drvdata(to_platform_device(dsi->dev));
1605 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1606 drm_panel_detach(dsi->panel);
1607 dsi->panel = NULL;
1608 }
1609
1610 if (dsi->panel)
1611 return connector_status_connected;
1612
1613 return connector_status_disconnected;
1614 }
1615
1616 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1617 {
1618 drm_connector_unregister(connector);
1619 drm_connector_cleanup(connector);
1620 connector->dev = NULL;
1621 }
1622
1623 static struct drm_connector_funcs exynos_dsi_connector_funcs = {
1624 .dpms = drm_atomic_helper_connector_dpms,
1625 .detect = exynos_dsi_detect,
1626 .fill_modes = drm_helper_probe_single_connector_modes,
1627 .destroy = exynos_dsi_connector_destroy,
1628 .reset = drm_atomic_helper_connector_reset,
1629 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1630 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1631 };
1632
1633 static int exynos_dsi_get_modes(struct drm_connector *connector)
1634 {
1635 struct exynos_dsi *dsi = connector_to_dsi(connector);
1636
1637 if (dsi->panel)
1638 return dsi->panel->funcs->get_modes(dsi->panel);
1639
1640 return 0;
1641 }
1642
1643 static struct drm_encoder *
1644 exynos_dsi_best_encoder(struct drm_connector *connector)
1645 {
1646 struct exynos_dsi *dsi = connector_to_dsi(connector);
1647
1648 return dsi->display.encoder;
1649 }
1650
1651 static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1652 .get_modes = exynos_dsi_get_modes,
1653 .best_encoder = exynos_dsi_best_encoder,
1654 };
1655
1656 static int exynos_dsi_create_connector(struct exynos_drm_display *display,
1657 struct drm_encoder *encoder)
1658 {
1659 struct exynos_dsi *dsi = display_to_dsi(display);
1660 struct drm_connector *connector = &dsi->connector;
1661 int ret;
1662
1663 connector->polled = DRM_CONNECTOR_POLL_HPD;
1664
1665 ret = drm_connector_init(encoder->dev, connector,
1666 &exynos_dsi_connector_funcs,
1667 DRM_MODE_CONNECTOR_DSI);
1668 if (ret) {
1669 DRM_ERROR("Failed to initialize connector with drm\n");
1670 return ret;
1671 }
1672
1673 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1674 drm_connector_register(connector);
1675 drm_mode_connector_attach_encoder(connector, encoder);
1676
1677 return 0;
1678 }
1679
1680 static void exynos_dsi_mode_set(struct exynos_drm_display *display,
1681 struct drm_display_mode *mode)
1682 {
1683 struct exynos_dsi *dsi = display_to_dsi(display);
1684 struct videomode *vm = &dsi->vm;
1685
1686 vm->hactive = mode->hdisplay;
1687 vm->vactive = mode->vdisplay;
1688 vm->vfront_porch = mode->vsync_start - mode->vdisplay;
1689 vm->vback_porch = mode->vtotal - mode->vsync_end;
1690 vm->vsync_len = mode->vsync_end - mode->vsync_start;
1691 vm->hfront_porch = mode->hsync_start - mode->hdisplay;
1692 vm->hback_porch = mode->htotal - mode->hsync_end;
1693 vm->hsync_len = mode->hsync_end - mode->hsync_start;
1694 }
1695
1696 static struct exynos_drm_display_ops exynos_dsi_display_ops = {
1697 .create_connector = exynos_dsi_create_connector,
1698 .mode_set = exynos_dsi_mode_set,
1699 .dpms = exynos_dsi_dpms
1700 };
1701
1702 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1703
1704 /* of_* functions will be removed after merge of of_graph patches */
1705 static struct device_node *
1706 of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg)
1707 {
1708 struct device_node *np;
1709
1710 for_each_child_of_node(parent, np) {
1711 u32 r;
1712
1713 if (!np->name || of_node_cmp(np->name, name))
1714 continue;
1715
1716 if (of_property_read_u32(np, "reg", &r) < 0)
1717 r = 0;
1718
1719 if (reg == r)
1720 break;
1721 }
1722
1723 return np;
1724 }
1725
1726 static struct device_node *of_graph_get_port_by_reg(struct device_node *parent,
1727 u32 reg)
1728 {
1729 struct device_node *ports, *port;
1730
1731 ports = of_get_child_by_name(parent, "ports");
1732 if (ports)
1733 parent = ports;
1734
1735 port = of_get_child_by_name_reg(parent, "port", reg);
1736
1737 of_node_put(ports);
1738
1739 return port;
1740 }
1741
1742 static struct device_node *
1743 of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg)
1744 {
1745 return of_get_child_by_name_reg(port, "endpoint", reg);
1746 }
1747
1748 static int exynos_dsi_of_read_u32(const struct device_node *np,
1749 const char *propname, u32 *out_value)
1750 {
1751 int ret = of_property_read_u32(np, propname, out_value);
1752
1753 if (ret < 0)
1754 pr_err("%s: failed to get '%s' property\n", np->full_name,
1755 propname);
1756
1757 return ret;
1758 }
1759
1760 enum {
1761 DSI_PORT_IN,
1762 DSI_PORT_OUT
1763 };
1764
1765 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1766 {
1767 struct device *dev = dsi->dev;
1768 struct device_node *node = dev->of_node;
1769 struct device_node *port, *ep;
1770 int ret;
1771
1772 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1773 &dsi->pll_clk_rate);
1774 if (ret < 0)
1775 return ret;
1776
1777 port = of_graph_get_port_by_reg(node, DSI_PORT_OUT);
1778 if (!port) {
1779 dev_err(dev, "no output port specified\n");
1780 return -EINVAL;
1781 }
1782
1783 ep = of_graph_get_endpoint_by_reg(port, 0);
1784 of_node_put(port);
1785 if (!ep) {
1786 dev_err(dev, "no endpoint specified in output port\n");
1787 return -EINVAL;
1788 }
1789
1790 ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1791 &dsi->burst_clk_rate);
1792 if (ret < 0)
1793 goto end;
1794
1795 ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1796 &dsi->esc_clk_rate);
1797
1798 end:
1799 of_node_put(ep);
1800
1801 return ret;
1802 }
1803
1804 static int exynos_dsi_bind(struct device *dev, struct device *master,
1805 void *data)
1806 {
1807 struct exynos_drm_display *display = dev_get_drvdata(dev);
1808 struct exynos_dsi *dsi = display_to_dsi(display);
1809 struct drm_device *drm_dev = data;
1810 int ret;
1811
1812 ret = exynos_drm_create_enc_conn(drm_dev, display);
1813 if (ret) {
1814 DRM_ERROR("Encoder create [%d] failed with %d\n",
1815 display->type, ret);
1816 return ret;
1817 }
1818
1819 return mipi_dsi_host_register(&dsi->dsi_host);
1820 }
1821
1822 static void exynos_dsi_unbind(struct device *dev, struct device *master,
1823 void *data)
1824 {
1825 struct exynos_drm_display *display = dev_get_drvdata(dev);
1826 struct exynos_dsi *dsi = display_to_dsi(display);
1827
1828 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1829
1830 mipi_dsi_host_unregister(&dsi->dsi_host);
1831 }
1832
1833 static const struct component_ops exynos_dsi_component_ops = {
1834 .bind = exynos_dsi_bind,
1835 .unbind = exynos_dsi_unbind,
1836 };
1837
1838 static int exynos_dsi_probe(struct platform_device *pdev)
1839 {
1840 struct device *dev = &pdev->dev;
1841 struct resource *res;
1842 struct exynos_dsi *dsi;
1843 int ret, i;
1844
1845 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1846 if (!dsi)
1847 return -ENOMEM;
1848
1849 dsi->display.type = EXYNOS_DISPLAY_TYPE_LCD;
1850 dsi->display.ops = &exynos_dsi_display_ops;
1851
1852 /* To be checked as invalid one */
1853 dsi->te_gpio = -ENOENT;
1854
1855 init_completion(&dsi->completed);
1856 spin_lock_init(&dsi->transfer_lock);
1857 INIT_LIST_HEAD(&dsi->transfer_list);
1858
1859 dsi->dsi_host.ops = &exynos_dsi_ops;
1860 dsi->dsi_host.dev = dev;
1861
1862 dsi->dev = dev;
1863 dsi->driver_data = exynos_dsi_get_driver_data(pdev);
1864
1865 ret = exynos_dsi_parse_dt(dsi);
1866 if (ret)
1867 return ret;
1868
1869 dsi->supplies[0].supply = "vddcore";
1870 dsi->supplies[1].supply = "vddio";
1871 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1872 dsi->supplies);
1873 if (ret) {
1874 dev_info(dev, "failed to get regulators: %d\n", ret);
1875 return -EPROBE_DEFER;
1876 }
1877
1878 dsi->clks = devm_kzalloc(dev,
1879 sizeof(*dsi->clks) * dsi->driver_data->num_clks,
1880 GFP_KERNEL);
1881 if (!dsi->clks)
1882 return -ENOMEM;
1883
1884 for (i = 0; i < dsi->driver_data->num_clks; i++) {
1885 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1886 if (IS_ERR(dsi->clks[i])) {
1887 if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1888 strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
1889 i--;
1890 continue;
1891 }
1892
1893 dev_info(dev, "failed to get the clock: %s\n",
1894 clk_names[i]);
1895 return PTR_ERR(dsi->clks[i]);
1896 }
1897 }
1898
1899 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1900 dsi->reg_base = devm_ioremap_resource(dev, res);
1901 if (IS_ERR(dsi->reg_base)) {
1902 dev_err(dev, "failed to remap io region\n");
1903 return PTR_ERR(dsi->reg_base);
1904 }
1905
1906 dsi->phy = devm_phy_get(dev, "dsim");
1907 if (IS_ERR(dsi->phy)) {
1908 dev_info(dev, "failed to get dsim phy\n");
1909 return PTR_ERR(dsi->phy);
1910 }
1911
1912 dsi->irq = platform_get_irq(pdev, 0);
1913 if (dsi->irq < 0) {
1914 dev_err(dev, "failed to request dsi irq resource\n");
1915 return dsi->irq;
1916 }
1917
1918 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1919 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1920 exynos_dsi_irq, IRQF_ONESHOT,
1921 dev_name(dev), dsi);
1922 if (ret) {
1923 dev_err(dev, "failed to request dsi irq\n");
1924 return ret;
1925 }
1926
1927 platform_set_drvdata(pdev, &dsi->display);
1928
1929 return component_add(dev, &exynos_dsi_component_ops);
1930 }
1931
1932 static int exynos_dsi_remove(struct platform_device *pdev)
1933 {
1934 component_del(&pdev->dev, &exynos_dsi_component_ops);
1935
1936 return 0;
1937 }
1938
1939 struct platform_driver dsi_driver = {
1940 .probe = exynos_dsi_probe,
1941 .remove = exynos_dsi_remove,
1942 .driver = {
1943 .name = "exynos-dsi",
1944 .owner = THIS_MODULE,
1945 .of_match_table = exynos_dsi_of_match,
1946 },
1947 };
1948
1949 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1950 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1951 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1952 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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